AMC23C14
SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
AMC23C14 Dual, Fast Response, Reinforced Isolated Window Comparator
With Adjustable Threshold
1 Features
3 Description
•
•
•
The AMC23C14 is a dual, isolated window
comparator with a short response time. The opendrain outputs are separated from the input circuitry
by an isolation barrier that is highly resistant to
magnetic interference. This barrier is certified to
provide reinforced galvanic isolation of up to 5 kVRMS
according to VDE 0884-17 and UL1577, and supports
a working voltage of up to 1 kVPK.
•
•
•
•
•
•
•
2 Applications
Overcurrent or overvoltage detection in:
– Motor drives
– Frequency inverters
– Solar inverters
– DC/DC converters
The AMC23C14 also supports a positive-comparator
only mode. When the voltage on the REF pin is
greater than 550 mV, the negative comparators
are disabled and only the positive comparators are
functional. The reference voltage in this mode can be
as high as 2.7 V. This mode is particularly useful for
monitoring positive voltage supplies.
The AMC23C14 is available in an 8-pin, wide-body
SOIC package and is specified over the extended
industrial temperature range of –40°C to +125°C.
Package Information(1)
PART NUMBER
AMC23C14
(1)
PACKAGE
SOIC (8)
For all available packages, see the orderable addendum at
the end of the data sheet.
Low-side supply
(2.7..5.5 V)
AMC23C14
VDD1
I
LDO
300 mV
VDD2
+
OUT2
IN
–
100 A
REF
GND1
BODY SIZE (NOM)
5.85 mm × 7.50 mm
High-side supply
(3..27 V)
RSHUNT
•
Both comparators have windows that are centered
around 0 V, meaning that the comparators trip if the
input exceeds the thresholds in a positive or negative
direction. One comparator has fixed thresholds of
±300 mV. The second comparator has adjustable
thresholds from ±20 mV to ±300 mV through a single
external resistor.
+
Reinforced Isolation
•
Wide high-side supply range: 3 V to 27 V
Low-side supply range: 2.7 V to 5.5 V
Dual window comparator:
– Window comparator 1: ±20-mV to ±300-mV
adjustable threshold
– Window comparator 2: ±300-mV fixed threshold
Supports positive-comparator mode:
– Cmp0: 600-mV to 2.7-V adjustable threshold
– Cmp2: 300-mV fixed threshold
– Cmp1 and Cmp3: Disabled
Reference for threshold adjustment: 100 μA, ±2%
Trip threshold error: ±1% (max) at 250 mV
Open-drain outputs
Propagation delay: 280 ns (typ)
High CMTI: 15 V/ns (min)
Safety-related certifications:
– 7000-VPK reinforced isolation per DIN EN IEC
60747-17 (VDE 0884-17)
– 5000-VRMS isolation for 1 minute per UL1577
Fully specified over the extended industrial
temperature range: –40°C to +125°C
–
OUT1
to MCU
to MCU
GND2
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC23C14
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SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information ...................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .......................................10
6.11 Timing Diagrams..................................................... 10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................ 12
7 Detailed Description......................................................22
7.1 Overview................................................................... 22
7.2 Functional Block Diagram......................................... 22
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................29
8 Application and Implementation.................................. 30
8.1 Application Information............................................. 30
8.2 Typical Applications ................................................. 30
8.3 Best Design Practices...............................................35
8.4 Power Supply Recommendations.............................36
8.5 Layout....................................................................... 36
9 Device and Documentation Support............................37
9.1 Documentation Support............................................ 37
9.2 Receiving Notification of Documentation Updates....37
9.3 Support Resources................................................... 37
9.4 Trademarks............................................................... 37
9.5 Electrostatic Discharge Caution................................37
9.6 Glossary....................................................................37
10 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (February 2022) to Revision A (July 2022)
Page
• Changed document status from advance information to production data ......................................................... 1
2
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5 Pin Configuration and Functions
VDD1
1
8
VDD2
IN
2
7
OUT2
REF
3
6
OUT1
GND1
4
5
GND2
Not to scale
Figure 5-1. DWV Package, 8-Pin SOIC (Top View)
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
VDD1
High-side power
2
IN
Analog input
Common analog input pin for window comparator 1 and 2.
Reference pin that defines the trip threshold for window comparator 1. The voltage
on this pin also affects the hysteresis of comparator Cmp0 as explained in the
Reference Input section. This pin is internally connected to a 100-μA current source.
Connect a resistor from REF to GND1 to define the trip threshold, and a capacitor
from REF to GND1 to filter the reference voltage. For best transient noise immunity,
place the capacitor as closely to the pin as possible. This pin can also be driven by
an external voltage source.
(1)
High-side power supply.(1)
3
REF
Analog input
4
GND1
High-side ground
High-side ground.
5
GND2
Low-side ground
Low-side ground.
6
OUT1
Digital output
Open-drain output of window comparator 1. Connect to an external pullup resistor or
leave unconnected (floating) when not used.
7
OUT2
Digital output
Open-drain output of window comparator 2. Connect to an external pullup resistor or
leave unconnected (floating) when not used.
8
VDD2
Low-side power
Low-side power supply.(1)
See the Layout section for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
Power-supply voltage
Analog input voltage
MAX
VDD1 to GND1
–0.3
30
VDD2 to GND2
–0.3
6.5
REF to GND1
–0.5
6.5
–6
5.5
IN to GND1
Digital output voltage
OUT1, OUT2 to GND2
–0.5
VDD2 + 0.5
Input current
Continuous, any pin except power-supply pins
–10
10
Temperature
(1)
Junction, TJ
150
Storage, Tstg
–65
150
UNIT
V
V
V
mA
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VVDD1
High-side power-supply voltage
VDD1 to GND1
3.0
5
27
V
VVDD2
Low-side power supply voltage
VDD2 to GND2
2.7
3.3
5.5
V
ANALOG INPUT
VIN
Input voltage
Reference voltage, window comparator mode
VREF
IN to GND1, VDD1 ≤ 4.3 V
–0.4
VDD1 – 0.3
IN to GND1, VDD1 > 4.3 V
–0.4
4
REF to GND1
20
300
Low hysteresis mode
20
450
Reference voltage, positive-comparator mode
High hysteresis mode
(Cmp0 only)
600
2700(1)
Reference voltage headroom
VDD1 – VREF
1.4
Filter capacitance on REF pin
V
mV
V
20
100
nF
DIGITAL OUTPUTS
Digital output voltage
OUT1, OUT2 to GND2
Sink current
OUT1, OUT2
GND2
VDD2
0
4
mA
V
125
°C
TEMPERATURE RANGE
TA
(1)
Specified ambient temperature
–40
25
Reference voltages (VREF) >1.6 V require VVDD1 > VVDD1,MIN to maintain minimum headroom (VVDD1 – VREF) of 1.4 V.
6.4 Thermal Information
DWV (SOIC)
THERMAL METRIC(1)
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
102.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.1
°C/W
RθJB
Junction-to-board thermal resistance
63.0
°C/W
ΨJT
Junction-to-top characterization parameter
14.3
°C/W
ΨJB
Junction-to-board characterization parameter
61.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
PD
PD1
PD2
Maximum power dissipation (both sides)
Maximum power dissipation (high-side)
Maximum power dissipation (low-side)
TEST CONDITIONS
VALUE
VDD1 = 25 V, VDD2 = 5.5 V
110
VDD1 = VDD2 = 5.5 V
34
VDD1 = VDD2 = 3.6 V
22
VDD1 = 25 V
98
VDD1 = 5.5 V
21
VDD1 = 3.6 V
14
VDD2 = 5.5 V
12
VDD2 = 3.6 V
8
UNIT
mW
mW
mW
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
Shortest pin-to-pin distance through air
≥ 8.5
mm
CPG
External creepage(1)
Shortest pin-to-pin distance across the package surface
≥ 8.5
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation
≥ 15.4
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-III
Rated mains voltage ≤ 1000 VRMS
I-II
DIN EN IEC 60747-17 (VDE
I
0884-17)(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
At AC voltage
1060
VPK
Maximum-rated isolation
working voltage
At AC voltage (sine wave)
750
VRMS
At DC voltage
1060
VDC
VIOTM
Maximum transient
isolation voltage
VTEST = VIOTM, t = 60 s (qualification test)
7070
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8500
VIMP
Maximum impulse voltage(3)
Tested in air, 1.2/50-µs waveform per IEC 62368-1
8300
VPK
VIOSM
Maximum surge
isolation voltage(4)
Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1
10000
VPK
Apparent charge(5)
qpd
CIO
Barrier capacitance,
input to output(6)
RIO
Insulation resistance,
input to output(6)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875
× VIORM, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1.5
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
55/125/21
VPK
pC
pF
Ω
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
(6)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air to determine the surge immunity of the package.
Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17,
DIN EN IEC 62368-1 (VDE 0868-1),
EN IEC 62368-1,
IEC 62368-1 Clause : 5.4.3 ; 5.4.4.4 ; 5.4.9
Recognized under 1577 component recognition
Reinforced insulation
Single protection
Certificate number: pending
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 102.8°C/W,
VDD1 = VDD2 = 5.5 V,
TJ = 150°C, TA = 25°C
220
RθJA = 102.8°C/W,
VDD1 = VDD2 = 3.6 V,
TJ = 150°C, TA = 25°C
340
RθJA = 102.8°C/W,
TJ = 150°C, TA = 25°C
1220
mW
150
°C
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side voltage and DVDDmax is the maximum controller-side
supply voltage.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3.0 V to 27 V, VDD2 = 2.7 V to 5.5 V, VREF =
20 mV to 2.7 V(1), and VIN = –400 mV to 4 V(3); typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, and VREF
= 250 mV (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Input resistance
IBIAS
Input bias current
CIN
Input capacitance
IN pin, 0 ≤ VIN ≤ 4 V
IN pin, 0 ≤ VIN ≤ 4
1
V(4)
IN pin, –400 mV ≤ VIN ≤ 0 V(5)
0.1
–310
GΩ
25
–0.5
IN pin
4
nA
pF
REFERENCE PIN
IREF
Reference current
VMSEL
Mode selection threshold(2)
REF to GND1, 20 mV < VREF ≤ 2.7 V
99
100
101
VREF rising
500
550
600
VREF falling
450
500
550
Mode selection threshold hysteresis
50
μA
mV
mV
300-mV FIXED-THRESHOLD COMPARATORS (CMP2 AND CMP3)
VIT+
Positive-going trip threshold
Cmp2
EIT+
Positive-going trip threshold error
Cmp2
VIT–
Negative-going trip threshold
Cmp2
EIT–
Negative-going trip threshold error
Cmp2
VIT–
Negative-going trip threshold
Cmp3
EIT–
Negative-going trip threshold error
Cmp3
VIT+
Positive-going trip threshold
Cmp3
EIT+
Positive-going trip threshold error
Cmp3
VHYS
Trip threshold hysteresis
Cmp2 and Cmp3, (VIT+ – VIT–)
304
–3.5
mV
3.5
300
–3.5
mV
3.5
–304
–4.5
mV
mV
4.5
–300
–4.5
mV
mV
mV
4.5
4
mV
mV
VARIABLE-THRESHOLD COMPARATORS (CMP0 AND CMP1)
VIT+
EIT+
VIT–
EIT–
Positive-going trip threshold
Positive-going trip threshold error
Negative-going trip threshold
Negative-going trip threshold error
Cmp0
EIT–
VIT+
Negative-going trip threshold
Negative-going trip threshold error
Positive-going trip threshold
EIT+
Positive-going trip threshold error
VHYS
Trip threshold hysteresis
mV
–2
2
Cmp0, (VIT+ – VREF – VHYS),
VREF = 250 mV, VHYS = 4 mV
–2
2
Cmp0, (VIT+ – VREF – VHYS),
VREF = 2 V, VHYS = 25 mV
–5
5
Cmp0
VREF
–2.5
2.5
Cmp0, (VIT– – VREF), VREF = 250 mV
–2.5
2.5
–5
5
Cmp1
mV
mV
Cmp0, (VIT– – VREF), VREF = 20 mV
Cmp0, (VIT– – VREF), VREF = 2 V
VIT–
VREF + VHYS
Cmp0, (VIT+ – VREF – VHYS),
VREF = 20 mV, VHYS = 4 mV
–VREF – VHYS
mV
mV
Cmp1, (VIT– + VREF + VHYS),
VREF = 20 mV, VHYS = 4 mV
–3
3
Cmp1, (VIT– + VREF + VHYS),
VREF = 250 mV, VHYS = 4 mV
–3
3
mV
Cmp1
–VREF
mV
Cmp1, (VIT+ + VREF), VREF = 20 mV
–3.5
3.5
Cmp1, (VIT+ + VREF), VREF = 250 mV
–3.5
3.5
Cmp0 and Cmp1, (VIT+ – VIT–), VREF ≤ 450 mV
4
mV
mV
Cmp0 only, (VIT+ – VIT–), VREF ≥ 600 mV
25
80
250
5
100
DIGITAL OUTPUTS
8
VOL
Low-level output voltage
ISINK = 4 mA
ILKG
Open-drain output leakage current
VDD2 = 5 V, VOUT = 5 V
CMTI
Common-mode transient immunity
|VIN – VREF| ≥ 4 mV, RPULLUP = 10 kΩ
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40
mV
nA
V/ns
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3.0 V to 27 V, VDD2 = 2.7 V to 5.5 V, VREF =
20 mV to 2.7 V(1), and VIN = –400 mV to 4 V(3); typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, and VREF
= 250 mV (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VDD1UV
VDD1 undervoltage detection threshold
VDD1POR
VDD1 power-on reset threshold
VDD1 rising
3
VDD1 falling
2.9
VDD1 falling
2.3
VDD2 rising
2.7
VDD2 falling
2.1
V
V
VDD2UV
VDD2 undervoltage detection threshold
IDD1
High-side supply current
3.2
4.3
mA
IDD2
Low-side supply current
1.8
2.2
mA
(1)
(2)
(3)
(4)
(5)
V
Reference voltages >1.6 V require VDD1 > VDD1MIN. See the Recommended Operating Conditions table for details.
The voltage level VREF determines if the device operates as window-comparator with positive and negative thresholds or as simple
comparator with positive thresholds only. See the Reference Input section for more details.
But not exceeding the maximum input voltage specified in the Recommended Operating Conditions table.
The typical value is measured at VIN = 0.4 V.
The typical value is measured at VIN = –400 mV.
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD2 = 3.3 V, VREF = 250 mV,
VOVERDRIVE = 10 mV, CL = 15 pF
280
410
VDD2 = 3.3 V, VREF = 2 V,
VOVERDRIVE = 50 mV, CL = 15 pF
240
370
VDD2 = 3.3 V, VREF = 250 mV,
VOVERDRIVE = 10 mV, CL = 15 pF
280
410
VDD2 = 3.3 V, VREF = 2 V,
VOVERDRIVE = 50 mV, CL = 15 pF
240
370
UNIT
OPEN-DRAIN OUTPUTS
tpH
Propagation delay time, |VIN| rising
tpL
Propagation delay time, |VIN| falling
tf
Output signal fall time
ns
ns
RPULLUP = 4.7 kΩ, CL = 15 pF
2
ns
MODE SELECTION
tHSEL
Comparator hysteresis selection deglitch
time
Cmp0, VREF rising or falling
10
µs
tDIS13
Comparator disable deglitch time
Cmp1 and Cmp3, VREF rising
10
µs
tEN13
Comparator enable deglitch time
Cmp1 and Cmp3, VREF falling
100
µs
START-UP TIMING
tLS ,STA
Low-side start-up time
VDD2 step to 2.7 V, VDD1 ≥ 3.0 V
40
µs
tHS ,STA
High-side start-up time
VDD1 step to 3.0 V, VDD2 ≥ 2.7 V
45
µs
tHS,BLK
High-side blanking time
200
µs
tHS,FLT
High-side-fault detection delay time
100
µs
6.11 Timing Diagrams
VREF + VOVERDRIVE
VOVERDRIVE
VREF
VOVERDRIVE
IN
VREF – VOVERDRIVE
tpH
tpL
OUTx
90%
50%
10%
10%
tf
Figure 6-1. Rise, Fall, and Delay Time Definition
300 mV
VREF
VIN
–VREF
–300 mV
OUT2
OUT1
Figure 6-2. Functional Timing Diagram
10
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SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
6.12 Insulation Characteristics Curves
400
1400
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
350
1200
300
1000
PS (mW)
IS (mA)
250
200
800
600
150
400
100
200
50
0
0
0
25
50
75
TA (°C)
100
125
150
0
D069
Figure 6-3. Thermal Derating Curve for Safety-Limiting Current
per VDE
25
50
75
TA (°C)
100
125
150
D070
Figure 6-4. Thermal Derating Curve for Safety-Limiting Power
per VDE
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SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
306
305
304
VIT (mV)
303
302
301
300
299
298
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
297
296
0
5
10
15
VDD1 (V)
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
20
25
30
D008a
Figure 6-6. Cmp2 Trip Threshold vs Temperature
2
2
1.5
1.5
1
1
0.5
0.5
EIT (mV)
EIT (mV)
Figure 6-5. Cmp2 Trip Threshold vs Supply Voltage
0
-0.5
0
-0.5
-1
-1
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
-1.5
-2
0
5
10
15
VDD1 (V)
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
20
25
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
-1.5
-2
-40
30
-25
-10
5
D008b
Figure 6-7. Cmp2 Trip Threshold Error vs Supply Voltage
20
35
50
65
Temperature (C)
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
80
95
110 125
D009b
Figure 6-8. Cmp2 Trip Threshold Error vs Temperature
6
5
VHYS (mV)
4
3
2
Device 1
Device 2
Device 3
1
0
-40
Figure 6-9. Cmp2 Trip Threshold Hysteresis vs Supply Voltage
12
-25
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D013
Figure 6-10. Cmp2 Trip Threshold Hysteresis vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
-296
-296
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
-297
-298
-299
-299
-300
-300
-301
-302
-302
-303
-304
-304
-305
-305
-306
5
10
15
VDD1 (V)
20
25
-306
-40
30
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
Figure 6-12. Cmp3 Trip Threshold vs Temperature
2
2
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
1.5
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
1
1
0.5
0.5
0
-0.5
-0.5
-1
-1
-1.5
-2
5
10
15
VDD1 (V)
20
25
-2
-40
30
-25
-10
5
D014b
Figure 6-13. Cmp3 Trip Threshold Error vs Supply Voltage
5
5
4
4
VHYS (mV)
6
2
20
35
50
65
Temperature (C)
80
95
110 125
D015b
Figure 6-14. Cmp3 Trip Threshold Error vs Temperature
6
3
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
0
-1.5
0
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
1.5
EIT (mV)
EIT (mV)
-25
D014a
Figure 6-11. Cmp3 Trip Threshold vs Supply Voltage
VHYS (mV)
Device 1, VIT+
Device 2, VIT+
-301
-303
0
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
-297
VIT (mV)
VIT (mV)
-298
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
3
2
Device 1
Device 2
Device 3
1
0
0
5
10
15
VDD1 (V)
20
25
30
Device 1
Device 2
Device 3
1
0
-40
-25
D018
Figure 6-15. Cmp3 Trip Threshold Hysteresis vs Supply Voltage
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D019
Figure 6-16. Cmp3 Trip Threshold Hysteresis vs Temperature
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SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
6.13 Typical Characteristics (continued)
26
26
25
25
24
24
23
23
22
22
VIT (mV)
VIT (mV)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
21
20
19
21
20
19
18
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
17
16
0
5
10
15
VDD1 (V)
18
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
20
25
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
17
16
-40
30
-25
-10
5
D020a
VREF = 20 mV
80
95
110 125
D021a
VREF = 20 mV
Figure 6-17. Cmp0 Trip Threshold vs Supply Voltage
Figure 6-18. Cmp0 Trip Threshold vs Temperature
1.5
1.5
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
1
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
1
0.5
EIT (mV)
0.5
EIT (mV)
20
35
50
65
Temperature (C)
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
0
0
-0.5
-0.5
-1
-1
-1.5
0
5
10
15
VDD1 (V)
20
25
-1.5
-40
30
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
-25
-10
5
D020d
VREF = 20 mV
20
35
50
65
Temperature (C)
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
80
95
110 125
D021d
VREF = 20 mV
Figure 6-19. Cmp0 Trip Threshold Error vs Supply Voltage
Figure 6-20. Cmp0 Trip Threshold Error vs Temperature
6
5
VHYS (mV)
4
3
2
Device 1
Device 2
Device 3
1
0
-40
-25
5
20
35
50
65
Temperature (C)
80
95
110 125
D025a
VREF = 20 mV
VREF = 20 mV
Figure 6-21. Cmp0 Trip Threshold Hysteresis vs Supply Voltage
14
-10
Figure 6-22. Cmp0 Trip Threshold Hysteresis vs Temperature
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6.13 Typical Characteristics (continued)
256
256
255
255
254
254
253
253
252
252
VIT (mV)
VIT (mV)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
251
250
249
251
250
249
248
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
247
246
0
5
10
248
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
15
VDD1 (V)
20
25
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
247
246
-40
30
-25
-10
5
D020b
VREF = 250 mV
95
110 125
D021b
Figure 6-24. Cmp0 Trip Threshold vs Temperature
2.5
2.5
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
2
1.5
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
2
1.5
1
1
0.5
0.5
EIT (mV)
EIT (mV)
80
VREF = 250 mV
Figure 6-23. Cmp0 Trip Threshold vs Supply Voltage
0
-0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
-2.5
-40
-2.5
0
5
10
15
VDD1 (V)
20
25
30
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
-25
-10
5
D020e
VREF = 250 mV
20
35
50
65
Temperature (C)
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
80
95
110 125
D021e
VREF = 250 mV
Figure 6-25. Cmp0 Trip Threshold Error vs Supply Voltage
Figure 6-26. Cmp0 Trip Threshold Error vs Temperature
6
6
5
5
4
4
VHYS (mV)
VHYS (mV)
20 35 50
65
Temperature (C)
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
3
2
3
2
Device 1
Device 2
Device 3
1
0
0
5
10
15
VDD1 (V)
20
25
30
Device 1
Device 2
Device 3
1
0
-40
-25
D024b
VREF = 250 mV
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D025b
VREF = 250 mV
Figure 6-27. Cmp0 Trip Threshold Hysteresis vs Supply Voltage
Figure 6-28. Cmp0 Trip Threshold Hysteresis vs Temperature
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SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
6.13 Typical Characteristics (continued)
2.030
2.030
2.025
2.025
2.020
2.020
2.015
2.015
2.010
2.010
VIT (mV)
VIT (mV)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
2.005
2.000
1.995
2.005
2.000
1.995
1.990
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
1.985
1.980
0
5
10
15
VDD1 (V)
1.990
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
20
25
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
1.985
1.980
-40
30
-25
-10
5
D020c
VREF = 2 V
110 125
D021c
5
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
4
3
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
4
3
2
2
1
1
EIT (mV)
EIT (mV)
95
Figure 6-30. Cmp0 Trip Threshold vs Temperature
5
0
-1
0
-1
-2
-2
-3
-3
-4
-4
-5
0
5
10
15
VDD1 (V)
20
25
-5
-40
30
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
-25
-10
5
D020f
VREF = 2 V
20
35
50
65
Temperature (C)
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
80
95
110 125
D021f
VREF = 2 V
Figure 6-31. Cmp0 Trip Threshold Error vs Supply Voltage
Figure 6-32. Cmp0 Trip Threshold Error vs Temperature
30
30
25
25
20
20
VHYS (mV)
VHYS (mV)
80
VREF = 2 V
Figure 6-29. Cmp0 Trip Threshold vs Supply Voltage
15
10
15
10
Device 1
Device 2
Device 3
5
0
0
5
10
15
VDD1 (V)
20
25
30
Device 1
Device 2
Device 3
5
0
-40
-25
D024c
VREF = 2 V
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D025c
VREF = 2 V
Figure 6-33. Cmp0 Trip Threshold Hysteresis vs Supply Voltage
16
20
35
50
65
Temperature (C)
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
Figure 6-34. Cmp0 Trip Threshold Hysteresis vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
-16
-16
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
-17
-18
-19
-19
-20
-20
-21
-22
-22
-23
-24
-24
-25
-25
-26
5
10
15
VDD1 (V)
20
25
-26
-40
30
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
-21
-23
0
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
-17
VIT (mV)
VIT (mV)
-18
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
-25
-10
5
D026a
VREF = 20 mV
20 35 50 65
Temperature (C)
80
95
110 125
D027a
VREF = 20 mV
Figure 6-35. Cmp1 Trip Threshold vs Supply Voltage
Figure 6-36. Cmp1 Trip Threshold vs Temperature
1.5
1
EIT (mV)
0.5
0
-0.5
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
-1
-1.5
0
5
10
15
VDD1 (V)
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
20
25
30
D026c
VREF = 20 mV
VREF = 20 mV
Figure 6-38. Cmp1 Trip Threshold Error vs Temperature
6
6
5
5
4
4
VHYS (mV)
VHYS (mV)
Figure 6-37. Cmp1 Trip Threshold Error vs Supply Voltage
3
2
3
2
Device 1
Device 2
Device 3
1
0
0
5
10
15
VDD1 (V)
20
25
30
Device 1
Device 2
Device 3
1
0
-40
-25
D030a
VREF = 20 mV
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D031a
VREF = 20 mV
Figure 6-39. Cmp1 Trip Threshold Hysteresis vs Supply Voltage
Figure 6-40. Cmp1 Trip Threshold Hysteresis vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
-246
-246
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
-247
-248
-249
-249
-250
-250
-251
-252
-252
-253
-254
-254
-255
-255
-256
5
10
15
VDD1 (V)
20
25
-256
-40
30
-25
-10
5
D026b
VREF = 250 mV
Figure 6-41. Cmp1 Trip Threshold vs Supply Voltage
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
1.5
95
110 125
D027b
Figure 6-42. Cmp1 Trip Threshold vs Temperature
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
Device 1, EIT−
Device 2, EIT−
Device 3, EIT−
2
1.5
1
1
0.5
0.5
EIT (mV)
EIT (mV)
80
2.5
2
0
-0.5
Device 1, EIT+
Device 2, EIT+
Device 3, EIT+
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
-2.5
0
5
10
15
VDD1 (V)
20
25
-2.5
-40
30
-25
-10
5
D026d
VREF = 250 mV
20
35
50
65
Temperature (C)
80
95
110 125
D027d
VREF = 250 mV
Figure 6-43. Cmp1 Trip Threshold Error vs Supply Voltage
Figure 6-44. Cmp1 Trip Threshold Error vs Temperature
6
6
5
5
4
4
VHYS (mV)
VHYS (mV)
20
35
50
65
Temperature (C)
VREF = 250 mV
2.5
3
2
3
2
Device 1
Device 2
Device 3
1
0
0
5
10
15
VDD1 (V)
20
25
30
Device 1
Device 2
Device 3
1
0
-40
-25
D030b
VREF = 250 mV
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D031b
VREF = 250 mV
Figure 6-45. Cmp1 Trip Threshold Hysteresis vs Supply Voltage
18
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
-251
-253
0
Device 1, VIT−
Device 2, VIT−
Device 3, VIT−
-247
VIT (mV)
VIT (mV)
-248
Device 1, VIT+
Device 2, VIT+
Device 3, VIT+
Figure 6-46. Cmp1 Trip Threshold Hysteresis vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
310
310
VINP rising
VINP falling
290
300
Propagation delay time (ns)
Propagation delay time (ns)
300
280
270
260
250
240
230
220
290
280
270
260
250
240
230
210
220
200
210
-40
0
10
20
30
40
50
60
Overdrive (mV)
70
80
90
100
VINP rising
VINP falling
-25
-10
5
D042
20 35 50
65
Temperature (C)
80
95
110 125
D059
Figure 6-48. Cmp2 Propagation Delay vs Temperature
Figure 6-47. Cmp2 Propagation Delay vs Overdrive
310
Propagation delay time (ns)
300
290
280
270
260
250
240
230
VINP falling
VINP rising
220
210
-40
-10
5
20 35 50
65
Temperature (C)
80
95
110 125
D060
Figure 6-50. Cmp3 Propagation Delay vs Temperature
Figure 6-49. Cmp3 Propagation Delay vs Overdrive
310
310
VINP rising
VINP falling
300
290
300
Propagation delay time (ns)
Propagation delay time (ns)
-25
280
270
260
250
240
230
290
280
270
260
250
240
230
220
220
210
210
-40
0
10
20
30
40
50
60
Overdrive (mV)
70
80
90
100
VINP rising
VINP falling
-25
D046a
Figure 6-51. Cmp0 Propagation Delay vs Overdrive
-10
5
20 35 50
65
Temperature (C)
80
95
110 125
D057
Figure 6-52. Cmp0 Propagation Delay vs Temperature
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SBAS945A – FEBRUARY 2022 – REVISED JULY 2022
6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
310
310
VINP falling
VINP rising
300
290
Propagation delay time (ns)
Propagation delay time (ns)
300
280
270
260
250
240
230
290
280
270
260
250
240
230
220
220
210
210
-40
0
10
20
30
40
50
60
Overdrive (mV)
70
80
90
100
VINP rising
VINP falling
-25
-10
5
D050
20 35 50
65
Temperature (C)
80
95
110 125
D058
Figure 6-54. Cmp1 Propagation Delay vs Temperature
Figure 6-53. Cmp1 Propagation Delay vs Overdrive
7
VDD1 = 3.3 V
VDD1 = 5 V
6
IIB (nA)
5
4
3
2
1
0
-0.5
0
0.5
1
1.5
2
2.5
VIN (V)
3
3.5
4
4.5
5
D001
VIN = 2 V
Figure 6-56. Input Bias Current vs Temperature
Figure 6-55. Input Bias Current vs Input Voltage
102
102
101.5
101
100.5
IREF (A)
IREF (A)
101
100
99.5
99
Device 1
Device 2
Device 3
98.5
98
10
100
1000
5000
VREF (mV)
99
Device 1
Device 2
Device 3
98
-40
-25
D007
Figure 6-57. Reference Current vs Reference Voltage
20
100
-10
5
20
35 50
65
Temperature (C)
80
95
110 125
D007b
Figure 6-58. Reference Current vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V (unless otherwise noted)
5
5
VREF = 250 mV
VREF = 2 V
4
4
3
3
IVDD1 (mA)
IVDD1 (mA)
VREF = 250 mV
VREF = 2 V
2
1
1
0
0
3
6
9
12
15
18
VDD1 (V)
21
24
27
0
-40
30
-10
5
20
35
50
65
Temperature (C)
2
2
1.8
1.8
IVDD2 (mA)
2.2
1.6
1.4
80
95
110 125
D033a
Figure 6-60. High-Side Supply Current vs Temperature
2.2
1.2
2.5
-25
D038a
Figure 6-59. High-Side Supply Current vs Supply Voltage
IVDD2 (mA)
2
1.6
1.4
3
3.5
4
4.5
VDD2 (V)
5
5.5
6
1.2
-40
-25
D040
Figure 6-61. Low-Side Supply Current vs Supply Voltage
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
D041
Figure 6-62. Low-Side Supply Current vs Temperature
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7 Detailed Description
7.1 Overview
The AMC23C14 is a dual, isolated window comparator with open-drain outputs. Window comparator 1 is
comprised of comparator Cmp0 and Cmp1 and window comparator 2 is comprised of Cmp2 and Cmp3. Cmp0
and Cmp2 compare the input voltage (VIN) against their respective positive thresholds (VIT+) and Cmp1 and
Cmp3 compare the input voltage (VIN) against their respective negative thresholds (VIT–). The respective VIT+
and VIT– thresholds are of equal magnitude but opposite signs, therefore both window comparators have
windows that are centered around 0 V. Window comparator 2 has fixed thresholds of ±300 mV. Window
comparator 1 has adjustable thresholds from ±20 mV to ±300 mV through an internally generated 100-μA
reference current and a single external resistor.
The open-drain outputs are actively pulled low when the input voltage (VIN) is outside the respective comparison
window, but are otherwise in a high-impedance state.
When the voltage on the REF pin is greater than VMSEL, the device operates in positive-comparator mode.
This mode is particularly useful for monitoring positive voltage supplies. Both negative comparators (Cmp1 and
Cmp3) are disabled and only the positive comparators (Cmp0 and Cmp2) are functional. The reference voltage
in this mode can be as high as 2.7 V.
Galvanic isolation between the high- and low-voltage side of the device is achieved by transmitting the
comparator states across a SiO2-based, reinforced capacitive isolation barrier. This isolation barrier supports
a high level of magnetic field immunity, as described in the ISO72x Digital Isolator Magnetic-Field Immunity
application report. The digital modulation scheme used in the AMC23C14 to transmit data across the isolation
barrier, and the isolation barrier characteristics itself, result in high reliability and common-mode transient
immunity.
7.2 Functional Block Diagram
Window Comparator 2
VDD1
AMC23C14
VDD2
LDO
Cmp2
Barrier
300 mV
OUT2
IN
Cmp3
GND1
RX
OUT1
Cmp1
Isolation
Cmp0
VREF
Logic
100 A
REF
TX
Logic
–300 mV
–VREF
GND2
Window Comparator 1
22
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7.3 Feature Description
7.3.1 Analog Input
The AMC23C14 has a single input that drives both window comparators. Window comparator 1 has an
adjustable threshold and window comparator 2 has a fixed threshold.
The positive comparators trip when the input voltage (VIN) rises above the respective VIT+ threshold that is
defined as the reference value plus the internal hysteresis voltage (for example, 304 mV for the fixed-threshold
comparator). The positive comparators release when VIN drops below the respective VIT– threshold that equals
the reference value (for example, 300 mV for the fixed-threshold comparator). The negative comparators trip
when VIN drops below the respective VIT– threshold that is defined as the negative reference value minus the
internal hysteresis voltage (for example, –304 mV for the fixed-threshold comparator). The negative comparators
release when VIN rises above the respective VIT+ threshold that equals the negative reference value (for
example –300 mV for the fixed-threshold comparator).
The difference between VIT+ and VIT– is referred to as the comparator hysteresis and is 4 mV for reference
voltages below 450 mV. The integrated hysteresis makes the AMC23C14 less sensitive to input noise and
provides stable operation in noisy environments without having to add external positive feedback to create
hysteresis. The hysteresis of Cmp0 increases to 25 mV for reference values (VREF) greater than 600 mV. See
the Reference Input description for more details.
Figure 7-1 shows a timing diagram of the relationship between hysteresis and switching thresholds.
VIT+
VHYS
VIT– (300 mV)
0V
VIN
VIT+ (–300 mV)
VIT–
VHYS
OUT2
VIT+
VHYS
VIT– (VREF)
0V
VIN
VIT+ (–VREF)
VIT–
VHYS
OUT1
Figure 7-1. Switching Thresholds and Hysteresis
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7.3.2 Reference Input
The voltage on the REF pin determines the trip threshold of window comparator 1. The internal precision
current source forces a 100-μA current through an external resistor connected from the REF pin to GND1. The
resulting voltage across the resistor (VREF) equals the magnitude of the positive and negative trip thresholds,
see Figure 7-1. Place a 100-nF capacitor parallel to the resistor to filter the reference voltage. This capacitor
must be charged by the 100-μA current source during power-up and the charging time may exceed the high-side
blanking time (tHS,BLK). In this case, as shown in Figure 7-2, window comparator 1 may output an incorrect
state after the high-side blanking time has expired until VREF reaches its final value. See the Power-Up and
Power-Down Behavior section for more details on power-up behavior.
VDD1
VDD2
ON
tHS,STA + tHS,BLK
VDD2
(low-side)
VDD2UV
(Hi-Z)
90%
VDD2UV
normal
operation
OUT2 normal
(open-drain) operation
(Hi-Z)
normal
operation
OUT1 normal
(open-drain) operation
(Hi-Z)
tLS,STA
OUT1
(Hi-Z)
(open-drain)
(Hi-Z)
Figure 7-9. VDD1 Turns On, Followed by VDD2
(Long Delay)
Figure 7-10. VDD2 Turns Off, Followed by VDD1
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7.3.6 VDD1 Brownout and Power-Loss Behavior
Brownout is a condition where the VDD1 supply droops below the specified operating voltage range but the
device remains functional. Power-loss is a condition where the VDD1 supply drops below a level where the
device stops being functional. Depending on the duration and the voltage level, a brownout condition may or
may not be noticeable at the output of the device. A power-loss condition is always signaled on the output of the
isolated comparator.
Figure 7-11 through Figure 7-13 show typical brownout and power-loss scenarios.
In Figure 7-11, VDD1 droops below the undervoltage detection threshold (VDD1UV) but recovers before the
high-side-fault detection delay time (tHS,FLT) expires. The brownout event has no effect on the comparator
outputs.
In Figure 7-12, VDD1 droops below the undervoltage detection threshold (VDD1UV) for more than the high-sidefault detection delay time (tHS,FLT). The brownout condition is detected as a fault and both outputs are pulled
low after a delay equal to tHS,FLT. The device resumes normal operation as soon as VDD1 recovers above the
VDD1UV threshold.
VDD1
(high-side)
VDD1UV
VDD1
(high-side)
VDD1UV
< tHS,FLT
tHS,FLT
VDD2
(low-side)
VDD2
(low-side)
ON
ON
OUT2
(open-drain)
no change on output
OUT2 normal
(open-drain) operation
OUT1
(open-drain)
no change on output
OUT1 normal
(open-drain) operation
90% fault
normal
operation
normal
operation
Figure 7-11. Output Response to a Short Brownout Figure 7-12. Output Response to a Long Brownout
Event on VDD1
Event on VDD1
In Figure 7-13, VDD1 droops below the power-on-reset (POR) threshold (VDD1POR). The power-loss condition
is detected as a fault and both outputs are pulled low after a delay equal to tHS,FLT. The device resumes normal
operation after a delay equal to tHS,STA + tHS,BLK after VDD1 recovers above the VDD1UV threshold.
VDD1
(high-side)
VDD1UV
VDD1POR
tHS,STA+ tHS,BLK
VDD2
(low-side)
ON
tHS,FLT
OUT2 normal
(open-drain) operation
90% fault
normal
operation
OUT1 normal
(open-drain) operation
90% fault
normal
operation
Figure 7-13. Output Response to a Power-Loss Event on VDD1
28
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7.4 Device Functional Modes
The AMC23C14 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
The four comparators on the high-side (Cmp0 to Cmp3) function as two independent window comparators when
the voltage on the REF pin is below the VMSEL threshold. If the voltage on the REF pin exceeds the VMSEL
threshold, the negative comparators (Cmp1 and Cmp3) are disabled, and Cmp0 and Cmp2 function as two
independent positive comparators, as described in the Reference Input section.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
With its low response time, high common-mode transient immunity (CMTI) and reinforced isolation barrier,
the AMC23C14 is designed to provide fast and reliable overcurrent and overvoltage detection for high-voltage
applications in harsh and noisy environments.
8.2 Typical Applications
8.2.1 Overcurrent and Short-Circuit Current Detection
Fast overcurrent and short-circuit current detection is a common requirement in DC/DC converter and motorcontrol applications, and can be implemented with an AMC23C14 isolated window comparator as shown in
Figure 8-1.
DC-link
Low-side supply (3..5.5 V)
R2
4.7 k
HS Gate Driver Supply (3..27 V)
R4
10
R3
4.7 k
AMC23C14
R5
10
C2
1 µF
C1
100 nF
C6
1 nF
R1
1.96 k
VDD1
VDD2
IN
OUT2
to MCU
REF
OUT1
to MCU
GND1
GND2
C5
100 nF
C3
100 nF
C4
1µF
Low-side supply (3..5.5 V)
AMC1300B
VDD2
INP
OUTP
INN
OUTN
GND1
GND2
RSHUNT
10 m
LS Gate Driver Supply
Barrier
ADC
Isoation
M
3~
VDD1
Figure 8-1. Using the AMC23C14 for Overcurrent and Short-Circuit Detection
The load current flowing through an external shunt resistor RSHUNT produces a voltage drop that is sensed
by the AMC1300B for control purposes. The same voltage is monitored by the AMC23C14 that is connected in
parallel to the current-sensing amplifier and provides a fast sensing path for positive and negative fault-current
detection. The trip threshold for overcurrent detection is set by the external resistor R1. The trip threshold for
short-circuit detection is fixed by the internal 300-mV reference. Overcurrent conditions are signaled on OUT1,
and short-circuit conditions are signaled on OUT2.
As depicted in Figure 8-1, the integrated low-dropout (LDO) regulator on the high-side allows direct connection
of the VDD1 input to a commonly used floating gate-driver supply. Alternatively, the AMC23C14 can share a
regulated supply with the AMC1300B. In that case, the VDD1 pin of the AMC23C14 connects directly to the
VDD1 pin of the AMC1300B and R4 is not needed. The fast response time and high common-mode transient
immunity (CMTI) of the AMC23C14 ensure reliable and accurate operation even in high-noise environments.
30
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8.2.1.1 Design Requirements
Table 8-1 lists the parameters for the application example in Figure 8-1.
Table 8-1. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3 V to 27 V
Low-side supply voltage
2.7 V to 5.5 V
Shunt-resistor value
10 mΩ
Linear input voltage range of the AMC1300B
±250 mV
Maximum peak motor current
±25 A
Overcurrent detection threshold
±20 A
Short-circuit current detection threshold
±30 A
8.2.1.2 Detailed Design Procedure
The value of the shunt resistor in this example is 10 mΩ, determined by the linear input voltage range of the
AMC1300B current-sensing amplifier (±250 mV) and the full-scale current of ±25 A. The short-circuit current
detection threshold of the AMC23C14 is a fixed 300-mV value and places the short-circuit current threshold at
30 A.
At the desired 20-A overcurrent detection level, the voltage drop across the shunt resistor is 10 mΩ × 20 A
= 200 mV. The positive-going trip threshold of window comparator 1 is VREF + VHYS, where VHYS is 4 mV as
specified in the Electrical Characteristics table and VREF is the voltage across R1 that is connected between
the REF and GND1 pins. R1 is calculated as (VTRIP – VHYS) / IREF = (200 mV – 4 mV) / 100 μA = 1.96 kΩ and
matches a value from the E96 series (1% accuracy).
A 10-Ω, 1-nF RC filter (R5, C6) is placed at the input of the comparator to filter the input signal and reduce
noise sensitivity. This filter adds 10 Ω × 1 nF = 10 ns of propagation delay that must be considered when
calculating the overall response time of the protection circuit. Larger filter constants are preferable to increase
noise immunity if the system can tolerate the additional delay.
Table 8-2 summarizes the key parameters of the design.
Table 8-2. Overcurrent and Short-Circuit Detection Design Example
PARAMETER
VALUE
Reference resistor value (R1)
1.96 kΩ
Reference capacitor value (C5)
100 nF
Reference voltage
196 mV
Reference voltage settling time (to 90% of final value)
470 μs
Overcurrent trip threshold (rising)
200 mV / 20.0 A
Overcurrent trip threshold (falling)
196 mV / 19.6 A
Short-circuit current trip threshold (rising)
304 mV / 30.4 A
Short-circuit current trip threshold (falling)
300 mV / 30.0 A
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8.2.2 Overvoltage and Undervoltage Detection
Industrial I/O modules are frequently powered by external field supplies with a nominal voltage of 24 V and a
tolerance of –15% to +20%. In safety-critical applications, the controller-side may need to know whether the
voltage is in the valid range for correct operation or not. Figure 8-2 shows the AMC23C14 in an application
that monitors a 24-V supply on the high-side and signals undervoltage and overvoltage conditions to the
programmable logic controller (PLC) on the low-side.
The voltage divider R5 and R6 is sized to trip the fixed internal 300-mV threshold when the power supply
exceeds the minimum valid operating voltage of 20.4 V (24 V – 15%). In a second step, R1 (connected to the
REF pin) is sized to trip the adjustable-threshold comparator when the power supply exceeds 28.8 V (24 V +
20%). The AMC23C14 is powered from the field supply and is protected against voltages greater than 30 V by a
Zener diode (Z1) and shunt resistor R4.
When the power supply is below 20.4 V, both outputs of the AMC23C14 are in a Hi-Z state. Between 20.4 V and
28.8 V, OUT1 is in a Hi-Z state and OUT2 is actively pulled low. Both outputs are pulled low, as shown in Figure
8-3, when the power supply is above 28.8 V.
Low-side supply (2.7..5.5 V)
24 V field supply
R2
R3
4.7 k 4.7 k
R4
1 k
R5
237 k
AMC23C14
+
–
R6
3.52 k
Z1
27 V
C2
1 µF
C1
100 nF
C6
1 nF
R1
4.17 k
VDD1
VDD2
IN
OUT2
to PLC
REF
OUT1
to PLC
GND1
GND2
C5
100 nF
C3
100 nF
C4
1 µF
Figure 8-2. Using the AMC23C14 for Overvoltage and Undervoltage Detection
28.8 V
28.5 V
Supply
Voltage
Valid Supply Range
20.8 V
20.5 V
OUT2
OUT1
Off
Undervoltage
Normal
Overvoltage
Normal
Undervoltage
Off
Figure 8-3. Output of the AMC23C14 in Supply Voltage Supervisor Application
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8.2.2.1 Design Requirements
Table 8-1 lists the parameters for the application example in Figure 8-2.
Table 8-3. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3 V to 27 V
Low-side supply voltage
2.7 V to 5.5 V
Field supply range
24 V, –15 % to +20%
Undervoltage detection threshold
20.4 V
Overvoltage detection threshold
28.8 V
Cross-current in resistor divider (R5, R6)
100 μA
8.2.2.2 Detailed Design Procedure
The 100-μA, cross-current requirement at nominal field-supply voltage (24 V) determines that the total
impedance of the resistor divider comprised of R5 and R6 is 240 kΩ. The impedance of the voltage divider
is dominated by R5, and therefore R5 is chosen as 237 kΩ.
At a field-supply voltage of 20.4 V, the voltage across R6 must equal the fixed-comparator threshold of 300 mV.
This value determines the voltage divider ratio and the ideal value of R6 is calculated as R6 = R5 × 300 mV /
(VTRIP – 300 mV), where VTRIP equals 20.4 V. The calculated value for R6 is 3.54 kΩ and the closest lower value
from the E192 series is 3.52 kΩ.
With R6 and R5 known, the voltage can be calculated that is present at the input of the comparator when the
field supply reaches 28.8 V, which is the upper limit of the valid operating range. This voltage is V2 = 28.8 V ×
(R6 / (R5 + R6) = 421.5 mV, and determines the value of R1. R1 is the resistor connected to the REF pin of the
AMC23C14. R1 is calculated as (V2 – VHYS) / IREF = (421.5 mV – 4 mV) / 100 μA = 4.17 kΩ. The value 4.17 kΩ
matches a value in the E192 series. The comparator hysteresis voltage (VHYS) is subtracted from V2 because
the comparator trips at VREF + VHYS, see Figure 7-1.
With R5 = 237 kΩ, R6 = 3.52 kΩ, and R1 = 4.17 kΩ, the resulting rising and falling thresholds are 20.8 V and
20.5 V for undervoltage detection and 28.8 V and 28.5 V for overvoltage detection, see Figure 8-3.
Table 8-4 summarizes the key parameters of the design.
Table 8-4. Overvoltage and Undervoltage Detection Design Example
PARAMETER
VALUE
Voltage divider, top resistor value (R5)
237 kΩ
Voltage divider, bottom resistor value (R6)
3.52 kΩ
Reference resistor value (R1)
4.17 kΩ
Reference capacitor value (C5)
100 nF
Reference voltage
417 mV
Reference voltage settling time (to 90% of final value)
960 μs
Undervoltage trip threshold (rising)
20.5 V
Undervoltage trip threshold (falling)
20.8 V
Overvoltage trip threshold (rising)
28.8 V
Overvoltage trip threshold (rising)
28.5 V
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8.2.3 Application Curves
Figure 8-4 shows the typical response of the AMC23C14 to a bipolar, triangular input waveform with an
amplitude of 720 mVPP. OUT1 switches when VIN crosses the ±250-mV level determined by the REF pin voltage
that is biased to 250 mV in this example. OUT2 switches when VIN crosses the ±300-mV level determined by
the fixed internal reference value.
Figure 8-4. Output Response of the AMC23C14 to a Triangular Input Waveform
The integrated LDO of the AMC23C14 greatly relaxes the power-supply requirements on the high-voltage side
and allows powering the device from non-regulated transformer, charge pump, and bootstrap supplies. As shown
in Figure 8-5 through Figure 8-7, the internal LDO provides a stable operating voltage to the internal circuitry,
allowing the trip thresholds to remain mostly undisturbed even at ripple voltages of 2 VPP and higher.
1.4
VDD1 = 5 V
VDD1 = 10 V
1.2
Trip Threshold Uncertainty (mV)
Trip Threshold Uncertainty (mV)
1.4
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
0
0
0
1
VDD1
2
3
Ripple Voltage (VPP)
4
5
0
D063a
Figure 8-5. Trip Threshold Sensitivity to VDD1
Ripple Voltage (Cmp0, fRIPPLE = 10 kHz)
34
VDD1 = 5 V
VDD1 = 10 V
1.2
1
2
3
VDD1 Ripple Voltage (VPP)
4
5
D063b
Figure 8-6. Trip Threshold Sensitivity to VDD1
Ripple Voltage (Cmp1, fRIPPLE = 10 kHz)
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1.4
VDD1 = 5 V
VDD1 = 10 V
1.2
Trip Threshold Uncertainty (mV)
Trip Threshold Uncertainty (mV)
1.4
1
0.8
0.6
0.4
0.2
0
0
1
2
3
VDD1 Ripple Voltage (VPP)
4
5
VDD1 = 5 V
VDD1 = 10 V
1.2
1
0.8
0.6
0.4
0.2
0
0
D063c
Figure 8-7. Trip Threshold Sensitivity to VDD1
Ripple Voltage (Cmp2, fRIPPLE = 10 kHz)
1
2
3
VDD1 Ripple Voltage (VPP)
4
5
D063d
Figure 8-8. Trip Threshold Sensitivity to VDD1
Ripple Voltage (Cmp3, fRIPPLE = 10 kHz)
8.3 Best Design Practices
Keep the connection between the low-side of the sense resistor and the GND1 pin of the AMC23C14 short
and low impedance. Any voltage drop in the ground line adds error to the voltage sensed at the input of the
comparator and leads to inaccuracies in the trip thresholds.
For best common-mode transient immunity, place the filter capacitor C5 as closely to the REF pin as possible
as illustrated in Figure 8-10. Use a low value pullup resistor (5.5 V) place a 10-Ω resistor (R4) is series with the VDD1 power supply for
additional filtering.
Low-side supply (2.7..5.5 V)
High-side supply (3..27V)
R2
4.7 k
R4
10
AMC23C14
R5
10 Ω
RSHUNT
I
C2
1 µF
R3
4.7 k
C1
100 nF
C6
1 nF
VDD1
VDD2
IN
OUT2
to MCU
REF
OUT1
to MCU
GND1
GND2
C5
R1
1.96 k 100 nF
C3
100 nF
C4
1 µF
Figure 8-9. Decoupling of the AMC23C14
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
8.5 Layout
8.5.1 Layout Guidelines
Figure 8-10 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC23C14 supply pins) and placement of the other components required by the device.
8.5.2 Layout Example
High-side
supply
R5
C4
C3
C6
IN
Low-side
supply
VDD2
C1
AMC23C14
C5
REF
R1
RSHUNT
C2
VDD1
R4
Clearance area, to be
kept free of any
conductive materials.
OUT2
to MCU
OUT1
to MCU
GND2
GND1
Top Metal
Inner or Bottom Layer Metal
Via
Figure 8-10. Recommended Layout of the AMC23C14
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
Texas Instruments, Isolation Glossary application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, AMC1300 Precision, ±250-mV Input, Reinforced Isolated Amplifier data sheet
Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: AMC23C14
37
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
AMC23C14DWV
ACTIVE
SOIC
DWV
8
64
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
MC23C14
Samples
AMC23C14DWVR
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
MC23C14
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of