AMC3306M05DWER

AMC3306M05 AMC3306M05 SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 www.ti.com AMC3306M05 High-Precision, ±50-mV Input, Reinforced Isolated Delta-Sigma Modulator With Integrated DC/DC Converter 1 Features 3 Description • The AMC3306M05 is a precision, isolated delta-sigma (ΔΣ) modulator, optimized for shunt-based current measurements. The fully integrated, isolated DC/DC converter allows single-supply operation from the low-side of the device which makes the device a unique solution for space-constrained applications. The reinforced capacitive isolation barrier is certified according to VDE V 0884-11 and UL1577 and supports a working voltage of up to 1.2 kVRMS. • • • • • • • 3.3-V or 5-V single supply with integrated DC/DC converter ±50-mV input voltage range optimized for current measurement using shunt resistors Low DC errors: – Offset error: ±50 µV (max) – Offset drift: ±0.4 µV/°C (max) – Gain error: ±0.2% (max) – Gain drift: ±35 ppm/°C (max) High CMTI: 75 kV/µs (min) System-level diagnostic features Low EMI: meets CISPR-11 and CISPR-25 standards Safety-related certifications: – 6000-VPEAK reinforced isolation per DIN VDE V 0884-11 – 4250-VRMS isolation for 1 minute per UL1577 Fully specified over the extended industrial temperature range: –40°C to +125°C The isolation barrier separates parts of the system that operate on different common-mode voltage levels and protects the low-voltage side from hazardous voltages and damage. The input of the AMC3306M05 is optimized for direct connection to a low-impedance shunt resistor or other, low-impedance voltage source with low signal levels. The excellent DC accuracy and low temperature drift supports accurate current measurments over the extended industial temperature range from –40°C to +125°C. 2 Applications • Compact, isolated shunt-based current sensing in: – Protection relays – Motor drives – Power supplies – Photovoltaic inverters By using a digital filter (such as a sinc3 filter) to decimate the bitstream, the device can achieve 16 bits of resolution with a dynamic range of 85 dB at a data rate of 78 kSPS. Device Information(1) PART NUMBER AMC3306M05 (1) PACKAGE SOIC (16) BODY SIZE (NOM) 10.30 mm × 7.50 mm For all available packages, see the orderable addendum at the end of the datasheet. Low-side supply (3.3 V or 5 V) DCDC_OUT DCDC_IN HLDO_IN I DCDC_GND Isolated Power NC RSHUNT HLDO_OUT +50 mV 0V ± 50 mV INP INN Isolated Reinforced Isolation DCDC_HGND Isolated Power DIAG LDO_OUT VDD MCU CLKIN û -ADC HGND DOUT GND AMC3306M05 Typical Application An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: AMC3306M05 1 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................4 6.4 Thermal Information ...................................................5 6.5 Power Ratings ............................................................5 6.6 Insulation Specifications ............................................ 6 6.7 Safety-Related Certifications ..................................... 7 6.8 Safety Limiting Values ................................................7 6.9 Electrical Characteristics ............................................8 6.10 Switching Characteristics .......................................10 6.11 Timing Diagrams..................................................... 10 6.12 Insulation Characteristics Curves............................11 6.13 Typical Characteristics............................................ 12 7 Detailed Description......................................................19 7.1 Overview................................................................... 19 7.2 Functional Block Diagram......................................... 19 7.3 Feature Description...................................................20 7.4 Device Functional Modes..........................................24 8 Application and Implementation.................................. 25 8.1 Application Information............................................. 25 8.2 Typical Application.................................................... 26 9 Power Supply Recommendations................................29 10 Layout...........................................................................30 10.1 Layout Guidelines................................................... 30 10.2 Layout Example...................................................... 30 11 Device and Documentation Support..........................31 11.1 Device Support........................................................31 11.2 Documentation Support.......................................... 31 11.3 Receiving Notification of Documentation Updates.. 31 11.4 Support Resources................................................. 31 11.5 Trademarks............................................................. 31 11.6 Electrostatic Discharge Caution.............................. 31 11.7 Glossary.................................................................. 31 12 Mechanical, Packaging, and Orderable Information.................................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (December 2020) to Revision A (January 2021) Page • Changed Typical Application figure.....................................................................................................................1 • Added discussion to pin 13 description regarding the output of the LDO...........................................................3 • Changed Absolute Maximum Ratings: changed max for DIAG pin from 5.5 V to 6.5 V..................................... 4 • Changed Operating common-mode input voltage (min) from -0.16 V to -0.032 V..............................................4 • Changed overvoltage category for rated mains voltage ≤ 600 V from I-IV to I-III and for rated mains voltage ≤1000 V from I-III to I-II ......................................................................................................................................6 • Changed Typical Characteristics section: deleted histograms..........................................................................12 • Changed the Isolated DC/DC Converter section: clarified that the low-side LDO is not intended for driving external loads................................................................................................................................................... 23 • Changed Differential Input Filter figure............................................................................................................. 27 • Changed What To Do and What Not To Do section......................................................................................... 28 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 5 Pin Configuration and Functions DCDC_OUT 1 16 DCDC_IN DCDC_HGND 2 15 DCDC_GND HLDO_IN 3 14 DIAG NC 4 13 LDO_OUT HLDO_OUT 5 12 VDD INP 6 11 CLKIN INN 7 10 DOUT HGND 8 9 GND Not to scale Figure 5-1. DWE Package, 16-Pin SOIC, Top View Table 5-1. Pin Functions PIN NO. NAME TYPE DESCRIPTION High-side output of the DC/DC converter; connect this pin to the HLDO_IN pin.(1) 1 DCDC_OUT Power 2 DCDC_HGND High-side power ground 3 HLDO_IN Power 4 NC — 5 HLDO_OUT Power 6 INP Analog input Noninverting analog input. Either INP or INN must have a DC current path to HGND to define the common-mode input voltage.(2) 7 INN Analog input Inverting analog input. Either INP or INN must have a DC current path to HGND to define the common-mode input voltage.(2) 8 HGND High-side signal ground High-side ground reference for the DC/DC converter; connect this pin to the HGND pin. Input of the high-side LDO; connect this pin to the DCDC_OUT pin.(1) No internal connection. Connect this pin to the high-side ground or leave unconnected (floating). Output of the high-side LDO.(1) High-side analog signal ground; connect this pin to the DCDC_HGND pin. 9 GND Low-side signal ground 10 DOUT Digital output 11 CLKIN Digital input 12 VDD Low-side power 13 LDO_OUT Power 14 DIAG Digital output Active-low, open-drain status indicator output; connect this pin to the pullup supply (for example, VDD) using a resistor or leave this pin floating if not used. 15 DCDC_GND Low-side power ground Low-side ground reference for the DC/DC converter; connect this pin to the GND pin. 16 DCDC_IN Power (1) (2) Low-side analog signal ground; connect this pin to the DCDC_GND pin. Modulator data output. Modulator clock input with internal pulldown resistor (typical value: 1.5 MΩ). Low-side power supply.(1) Output of the low-side LDO; connect this pin to the DCDC_IN pin. The output of the LDO must not be loaded by external circuitry.(1) Low-side input of the DC/DC converter; connect this pin to the LDO_OUT pin.(1) See the Power Supply Recommendations section for power-supply decoupling recommendations. See the Layout section for details. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 3 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6 Specifications 6.1 Absolute Maximum Ratings see (1) MIN Power-supply voltage VDD to GND Analog input voltage INP, INN Digital input voltage Digital output voltage Input current Temperature (1) MAX UNIT –0.3 6.5 V HGND – 6 VHLDO_OUT + 0.5 V V CLKIN GND – 0.5 VDD + 0.5 DOUT GND – 0.5 VDD + 0.5 DIAG GND – 0.5 6.5 –10 10 –65 150 Continuous, any pin except power-supply pins Junction, TJ 150 Storage, Tstg V mA °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX 3 3.3 5.5 UNIT POWER SUPPLY VDD Low-side power supply VDD to GND V ANALOG INPUT VClipping Differential input voltage before clipping output VIN = VINP – VINN VFSR Specified linear differential full-scale voltage VIN = VINP – VINN –50 50 Absolute common-mode input voltage (1) (VINP + VINN) / 2 to HGND –2 VHLDO_OUT V Operating common-mode input voltage (VINP + VINN) / 2 to HGND –0.032 0.9 V VCM ±64 mV mV DIGITAL I/O VIO Digital input / output voltage 0 fCLKIN Input clock frequency 5 20 21 40% 50% 60% Input clock duty cycle 5 MHz ≤ fCLKIN ≤ 21 MHz VDD V MHz TEMPERATURE RANGE TA (1) 4 Specified ambient temperature –40 125 °C Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.4 Thermal Information AMC3306M05 THERMAL METRIC(1) DWE (SOIC) UNIT 16 PINS Rθ JA Junction-to-ambient thermal resistance Rθ JC(top) Junction-to-case (top) thermal resistance 73.5 °C/W 31 °C/W Rθ JB Junction-to-board thermal resistance 44 °C/W ψJT Junction-to-top characterization parameter 16.7 °C/W ψJB Junction-to-board characterization parameter 42.8 °C/W Rθ JC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Power Ratings PARAMETER PD Maximum power dissipation TEST CONDITIONS VALUE VDD = 5.5 V 231 VDD = 3.6 V 151 UNIT mW Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 5 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.6 Insulation Specifications over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest pin-to-pin distance through air ≥8 mm CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥8 mm Minimum internal gap (internal clearance - capacitive signal isolation) ≥ 21 Minimum internal gap (internal clearance - transformer power isolation) ≥ 120 ≥ 600 DTI Distance through the insulation CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 Material group According to IEC 60664-1 Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-III Rated mains voltage ≤ 1000 VRMS I-II DIN VDE V 0884-11 (VDE V 0884-11): µm V I 2017-01(2) VIORM Maximum repetitive peak isolation voltage VIOWM At AC voltage (bipolar) 1700 VPK Maximum-rated isolation working voltage At AC voltage (sine wave) 1200 VRMS At DC voltage 1700 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 6000 VPK VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 7200 VPK VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50-µs waveform, VTEST = 1.6 × VIOSM = 10000 VPK (qualification) 6250 VPK Apparent charge(4) qpd Method a, after input/output safety test subgroup 2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s ≤5 Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s ≤5 Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s ≤5 ~3.5 CIO Barrier capacitance, input to output(5) VIO = 0.5 VPP at 1 MHz > 1012 Insulation resistance, input to output(5) VIO = 500 V at TA = 25°C RIO VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 VIO = 500 V at TS = 150°C > pC pF Ω 109 Pollution degree 2 Climatic category 40/125/21 UL1577 VISO (1) (2) (3) (4) (5) 6 Withstand isolation voltage VTEST = VISO = 4250 VRMS or 6000 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO, t = 1 s (100% production test) 4250 VRMS Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings must be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier are tied together, creating a two-pin device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.7 Safety-Related Certifications VDE UL Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60065 (VDE 0860): 2005-11 Recognized under 1577 component recognition and CSA component acceptance NO 5 programs Reinforced insulation Single protection Certificate number: 40040142 File number: E181974 6.8 Safety Limiting Values Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-heat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current PS Safety input, output, or total power TS Maximum safety temperature (1) TEST CONDITIONS MIN TYP MAX RθJA = 73.5°C/W, VDD = 5.5 V, TJ = 150°C, TA = 25°C 309 RθJA = 73.5°C/W, VDD = 3.6 V, TJ = 150°C, TA = 25°C 472 RθJA = 73.5°C/W, TJ = 150°C, TA = 25°C UNIT mA 1700 mW 150 °C The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature. PS = IS × VDDmax, where VDDmax is the maximum low-side voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 7 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.9 Electrical Characteristics all minimum and maximum specifications are at TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –50 mV to +50 mV, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical values are at TA = 25°C, CLKIN = 20 MHz, VDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT RIN Single-ended input resistance RIND Differential input resistance IIB Input bias current current(1) INN = HGND INP = INN = HGND; IIB = (IIBP + IIBN) / 2 –48 IIO = IIBP – IIBN; INP = INN = HGND 4.75 kΩ 4.9 kΩ –36 –28 ±10 μA IIO Input offset CIN Single-ended input capacitance INN = HGND, fIN = 310 kHz 4 nA pF CIND Differential input capacitance fIN = 310 kHz 2 pF EO Offset error(1) INN = INP = HGND, TA = 25°C –50 TCEO Offset error thermal drift(4) INN = INP = HGND –0.4 TA = 25°C ACCURACY –0.2% ±10 EG Gain error TCEG Gain error drift(5) ±0.005% DNL Differential nonlinearity Resolution: 16 bits –0.99 INL Integral nonlinearity Resolution: 16 bits –4 ±1 SNR Signal-to-noise ratio fIN = 1 kHz 77 81 SINAD Signal-to-noise + distortion fIN = 1 kHz 77 81 THD Total harmonic distortion(3) 5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz SFDR Spurious-free dynamic range fIN = 1 kHz –35 µV µV/°C 0.2% 35 –93 87 50 0.4 0.99 LSB 4 LSB dB dB –86 94 fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max –100 fIN = 10 kHz, VCM min ≤ VIN ≤ VCM max, VINP = VINN = 100 mVPP –100 ppm/°C dB dB CMRR Common-mode rejection ratio dB VDD from 3.0 V to 5.5 V, at DC –120 PSRR Power-supply rejection ratio INP = INN = HGND, VDD from 3.0 V to 5.5 V, 10 kHz, 100 mV ripple –120 IIN Input leakage current GND ≤ VIN ≤ VDD CIN Input capacitance VIH High-level input voltage 0.7 × VDD VDD + 0.3 V VIL Low-level input voltage –0.3 0.3 × VDD V CLOAD Output load capacitance 30 pF dB DIGITAL I/O 8 VOH High-level output voltage VOL Low-level output voltage CMTI Common-mode transient immunity 0 7 4 15 IOH = –20 µA VDD – 0.1 IOH = –4 mA VDD – 0.4 pF V IOL = 20 µA 0.1 IOL = 4 mA 0.4 75 Submit Document Feedback μA 135 V kV/μs Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.9 Electrical Characteristics (continued) all minimum and maximum specifications are at TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –50 mV to +50 mV, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical values are at TA = 25°C, CLKIN = 20 MHz, VDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX no external load on HLDO 26 40 1 mA external load on HLDO 28 42 4.65 UNIT POWER SUPPLY IDD Low-side supply current VDCDC_OUT DC/DC output voltage DCDC_OUT to HGND 3.1 3.5 VDCDCUV DC/DC output undervoltage detection threshold voltage VDCDC_OUT falling 2.1 2.25 VHLDO_OUT High-side LDO output voltage HLDO_OUT to HGND, up to 1 mA external load(2) 3 3.2 VHLDOUV High-side LDO output undervoltage detection threshold voltage VHLDO_OUT falling 2.4 2.6 IH High-side supply current for auxiliary circuitry Load connected from HLDO_OUT to HGND; non-switching; -40℃ ≤ TA ≤ 85℃(2) tSTART Device startup time VDD step to 3.0 V to bitstream valid (1) (2) (3) (4) (5) 0.9 mA V V 3.4 V V 1 mA 1.4 ms The typical value includes one sigma statistical variation at nominal operating conditions. High-side LDO supports external loads only up to TA = 85℃. See the Isolated DC/DC Converter section for more details. THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental. Offset error temperature drift is calculated using the box method, as described by the following equation: TCEO = (ValueMAX - ValueMIN) / TempRange Gain error temperature drift is calculated using the box method, as described by the following equation: TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 9 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.10 Switching Characteristics PARAMETER TEST CONDITIONS tH DOUT hold time after rising edge of CLKIN CLOAD = 15 pF tD Rising edge of CLKIN to DOUT valid delay tr DOUT rise time tf DOUT fall time MIN TYP MAX 3.5 UNIT ns CLOAD = 15 pF; CLKIN 50% to DOUT 10% / 90% 15 10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, CLOAD = 15 pF 2.5 6 10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V, CLOAD = 15 pF 3.2 6 10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, CLOAD = 15 pF 2.2 6 10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V,CLOAD = 15 pF 2.9 6 ns ns ns 6.11 Timing Diagrams tCLKIN tHIGH CLKIN 50% tLOW tH tD tr / tf 90% DOUT 10% Figure 6-1. Digital Interface Timing VDD tSTART CLKIN DOUT Bitstream not valid (analog settling) Valid bitstream Figure 6-2. Device Startup Timing 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.12 Insulation Characteristics Curves 500 1800 VDD = 3.6 V VDD = 5.5 V 1600 400 1400 PS (mW) IS (mA) 1200 300 200 1000 800 600 400 100 200 0 0 0 25 50 75 TA (°C) 100 125 0 150 25 50 D069 Figure 6-3. Thermal Derating Curve for Safety-Limiting Current Per VDE 75 TA (°C) 100 125 150 D070 Figure 6-4. Thermal Derating Curve for Safety-Limiting Power Per VDE 1.E+11 87.5% 1.E+10 143 Yrs 76 Yrs 1.E+09 Time to Fail (sec) 1.E+08 1.E+07 TDDB Line (< 1 ppm Fail Rate) 1.E+06 Operating Zone 1.E+05 1.E+04 VDE Safety Margin Zone 1.E+03 20 % 1.E+02 1.E+01 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 Applied Voltage (VRMS) TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1200 VRMS, operating lifetime = 76 years Figure 6-5. Reinforced Isolation Capacitor Lifetime Projection Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 11 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) -10 -30 -31 -15 -32 -33 -25 IIB (PA) IIB (PA) -20 -30 -34 -35 -36 -37 -35 -38 -40 -39 -45 -0.5 -40 -0.25 0 0.25 0.5 VCM (V) 0.75 1 1.25 3 3.5 4 4.5 5 5.5 VDD (V) D003 D004 Figure 6-7. Input Bias Current vs Supply Voltage Figure 6-6. Input Bias Current vs Common-Mode Input Voltage -30 30 -31 20 -32 10 -34 EO (PV) IIB (PA) -33 -35 -36 0 -10 -37 -38 Device 1 Device 2 Device 3 -20 -39 -40 -40 -30 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D025 Figure 6-9. Offset Error vs Input Clock Frequency 30 30 20 20 10 10 EO (PV) EO (PV) Figure 6-8. Input Bias Current vs Temperature 0 -10 0 -10 Device 1 Device 2 Device 3 -20 3 3.5 4 4.5 5 VDD (V) Device 1 Device 2 Device 3 -20 -30 5.5 -30 -40 -25 D027 Figure 6-10. Offset Error vs Supply Voltage 12 6 D005 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D026 Figure 6-11. Offset Error vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics (continued) 0.3 0.3 0.2 0.2 0.1 0.1 EG (%) EG (%) at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) 0 -0.1 0 -0.1 Device 1 Device 2 Device 3 -0.2 Device 1 Device 2 Device 3 -0.2 -0.3 -0.3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D022 3 3.5 4 4.5 5 5.5 VDD (V) Figure 6-12. Gain Error vs Input Clock Frequency D020 Figure 6-13. Gain Error vs Supply Voltage 0.3 2 1.5 0.2 1 INL (|LSB|) EG (%) 0.1 0 -0.1 0.5 0 -0.5 -1 Device 1 Device 2 Device 3 -0.2 -0.3 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 -1.5 -2 -50 110 125 -40 -30 -20 -10 D021 0 10 VIN (mV) 20 30 40 50 D028 Figure 6-15. Integral Nonlinearity vs Input Voltage Figure 6-14. Gain Error vs Temperature 2 2 Device 1 Device 2 Device 3 1.5 INL (|LSB|) INL (|LSB|) 1.5 1 1 0.5 0.5 Device 1 Device 2 Device 3 0 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D031 Figure 6-16. Integral Nonlinearity vs Input Clock Frequency 3 3.5 4 4.5 5 VDD (V) 5.5 D029 Figure 6-17. Integral Nonlinearity vs Supply Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 13 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics (continued) at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) 2 100 90 SNR and SINAD (dB) INL (|LSB|) 1.5 1 0.5 Device 1 Device 2 Device 3 0 -40 -10 5 20 35 50 65 Temperature (°C) 80 95 SNR SINAD 0 110 125 10 20 30 D030 D001 D024 40 50 60 VIN (VPP) 70 80 90 100 D032 Figure 6-19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Amplitude 85 SNR SINAD 84 SNR SINAD 84 83 SNR and SINAD (dB) 83 SNR and SINAD (dB) 60 40 -25 85 82 81 80 79 78 82 81 80 79 78 77 77 76 76 75 0.01 75 0.1 1 10 fIN (kHz) 5 6 7 8 D033 Figure 6-20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Frequency 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D036 Figure 6-21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Clock Frequency 85 85 SNR SINAD 84 SNR SINAD 84 83 SNR and SINAD (dB) 83 SNR and SINAD (dB) 70 50 Figure 6-18. Integral Nonlinearity vs Temperature 82 81 80 79 78 77 82 81 80 79 78 77 76 76 75 75 -40 3 3.5 4 4.5 VDD (V) 5 5.5 -25 D034 Figure 6-22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Supply Voltage 14 80 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D035 Figure 6-23. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics (continued) at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) -60 -60 Device 1 Device 2 Device 3 -65 -70 -70 -75 -75 THD (dB) THD (dB) -65 -80 -85 -80 -85 -90 -90 -95 -95 -100 0.01 -100 0 10 20 30 40 50 60 VIN (VPP) 70 80 90 100 0.1 1 10 fIN (kHz) D049 D052 Figure 6-25. Total Harmonic Distortion vs Input Signal Frequency Figure 6-24. Total Harmonic Distortion vs Input Signal Amplitude -60 -80 Device 1 Device 2 Device 3 -65 Device 1 Device 2 Device 3 -82 -84 -70 THD (dB) THD (dB) -86 -75 -80 -85 -88 -90 -92 -94 -90 -96 -95 -98 -100 -100 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D062 3 4.5 5 5.5 D056 Figure 6-27. Total Harmonic Distortion vs Supply Voltage 120 -60 Device 1 Device 2 Device 3 -65 110 -70 100 -75 90 SFDR (dB) THD (dB) 4 VDD (V) Figure 6-26. Total Harmonic Distortion vs Input Clock Frequency -80 -85 80 70 -90 60 -95 50 -100 -40 3.5 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Device 1 Device 2 Device 3 40 0 10 D059 Figure 6-28. Total Harmonic Distortion vs Temperature 20 30 40 50 60 VIN (VPP) 70 80 90 100 D051 Figure 6-29. Spurious-Free Dynamic Range vs Input Signal Amplitude Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 15 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics (continued) at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) 120 120 Device 1 Device 2 Device 3 110 110 105 105 100 95 85 85 80 0.1 1 10 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D064 Figure 6-31. Spurious-Free Dynamic Range vs Input Clock Frequency 120 120 Device 1 Device 2 Device 3 115 110 110 105 105 100 95 100 95 90 90 85 85 80 3 3.5 4 4.5 5 80 -40 5.5 VDD (V) 0 0 -20 -40 -40 -60 -60 Magnitude (dB) -80 -100 -120 -140 -160 -220 -240 -240 0 5 D014 Figure 6-34. Output Frequency Spectrum With a 1-kHz Input Signal 110 125 D061 -160 -200 40 95 -140 -220 35 80 -120 -180 30 20 35 50 65 Temperature (°C) -80 -200 15 20 25 Frequency (kHz) 5 -100 -180 10 -10 Figure 6-33. Spurious-Free Dynamic Range vs Temperature -20 5 -25 D058 Figure 6-32. Spurious-Free Dynamic Range vs Supply Voltage 0 Device 1 Device 2 Device 3 115 SFDR (dB) SFDR (dB) 6 D054 Figure 6-30. Spurious-Free Dynamic Range vs Input Signal Frequency Magnitude (dB) 95 90 fIN (kHz) 16 100 90 80 0.01 Device 1 Device 2 Device 3 115 SFDR (dB) SFDR (dB) 115 10 15 20 25 Frequency (kHz) 30 35 40 D015 Figure 6-35. Output Frequency Spectrum With a 10-kHz Input Signal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics (continued) at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) 0 0 OSR = 8 OSR = 256 -20 -40 PSRR (dB) CMRR (dB) -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 0.01 0.1 1 10 100 -160 0.01 1000 fCM (kHz) 0.1 D038 Figure 6-36. Common-Mode Rejection Ratio vs Input Signal Frequency 1 10 fRipple (kHz) 100 1000 D041 Figure 6-37. Power-Supply Rejection Ratio vs Ripple Frequency 30 30 28 28 26 26 IDD (mA) IDD (mA) OSR = 8 OSR = 256 -20 24 24 22 22 20 20 3 3.5 4 4.5 5 5 5.5 VDD (V) 6 7 D043 Figure 6-38. Supply Current vs Supply Voltage 8 9 10 11 12 13 14 15 16 17 18 19 20 21 fCLKIN (MHz) D045 Figure 6-39. Supply Current vs Input Clock Frequency 30 3.4 3.35 3.3 VHLDO_OUT (V) IDD (mA) 28 26 24 3.25 3.2 3.15 3.1 22 3.05 20 -40 3 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D044 Figure 6-40. Supply Current vs Temperature 3 3.5 4 4.5 VDD (V) 5 5.5 D046 Figure 6-41. High-Side LDO Output Voltage vs Supply Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 17 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 6.13 Typical Characteristics (continued) at VDD = 3.3 V, INP = –50 mV to +50 mV, INN = HGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256, 16-bit resolution (unless otherwise noted) 1.25 IH (mA) 1 0.75 0.5 0.25 0 -40 -25 -10 5 20 35 50 TA (qC) 65 80 95 110 125 D005 D048 Figure 6-42. IH Derating vs Ambient Temperature 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 7 Detailed Description 7.1 Overview The AMC3306M05 is a fully differential, precision, isolated modulator with an integrated DC/DC converter that can supply the high-side of the device from a single 3.3-V or 5-V voltage supply on the low side. The analog input pins INP and INN are connected to a fully differential amplifier that feeds the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog input signal into a digital bitstream that is transferred across the isolation barrier and separates the high-side from the low-side. The isolated data output DOUT of the converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin. The time average of this serial bitstream output is proportional to the analog input voltage. The external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The signal path is isolated by a double capacitive silicon dioxide (SiO2) insuation barrier, whereas power isolation uses an on-chip transformer separated by a thin-film polymer as the insulating material. 7.2 Functional Block Diagram DCDC_OUT DCDC_IN Resonator And Driver Rectifier DCDC_HGND HLDO_IN DIAG Diagnostics AMC3306M05 Isolation Barrier NC DCDC_GND LDO LDO_OUT LDO HLDO_OUT VDD û Modulator INN GND1 TX / RX CLKIN RX / TX INP Digital Interface DOUT GND2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 19 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 7.3 Feature Description 7.3.1 Analog Input The differential amplifier input stage of the AMC3306M05 feeds a second-order, switched-capacitor, feedforward ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input impedance of RIND. The modulator converts the analog input signal into a bitstream that is transferred across the isolation barrier, as described in the Isolation Channel Signal Transmission section. For reduced offset and offset drift, the differential amplifier is chopper-stabilized with the switching frequency set at fCLKIN / 32. As shown in Figure 7-1, the switching frequency generates a spur at 625 kHz. 0 -20 Magnitude (dB) -40 -60 -80 -100 -120 -140 -160 -180 0.1 sinc3 1 10 100 Frequency (kHz) 1000 10000 D016 filter, OSR = 2, fCLKIN = 20 MHz, fIN = 1 kHz Figure 7-1. Quantization Noise Shaping There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity and parametric performance of the device are ensured only when the analog input voltage remains within the linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the Recommended Operating Conditions table. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 7.3.2 Modulator The second-order, switched-capacitor, feed-forward ΔΣ modulator conceptualized in Figure 7-2 is implemented in the AMC3306M05 . The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V5, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input. fCLKIN V1 VIN G V2 Integrator 1 V4 V3 Integrator 2 G + DOUT 0V V5 ± DAC Figure 7-2. Block Diagram of a Second-Order Modulator The modulator shifts the quantization noise to high frequencies, as shown in Figure 7-1. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's C2000™ and Sitara™ microcontroller families offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC3306M05. Alternatively, a fieldprogrammable gate array (FPGA) or complex programmable logic device (CPLD) can be used to implement the filter. 7.3.3 Isolation Channel Signal Transmission The AMC3306M05 uses an on-off keying (OOK) modulation scheme, as shown in Figure 7-3, to transmit the modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation barrier to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the carrier used inside the AMC3306M05 is 480 MHz. The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and produces the output. The AMC3306M05 transmission channel is optimized to achieve the highest level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-frequency carrier and RX/TX buffer switching. Clock Modulator Bitstream on High-side Signal Across Isolation Barrier Recovered Sigal on Low-side Figure 7-3. OOK-Based Modulation Scheme Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 21 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 7.3.4 Digital Output A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 50 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits of resolution, that percentage ideally corresponds to code 58368. A differential input of –50 mV produces a stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with 16-bit resolution. These input voltages are also the specified linear range of the AMC3306M05. If the input voltage value exceeds this range, the output of the modulator shows nonlinear behavior as the quantization noise increases. The output of the modulator clips with a constant stream of zeros with an input less than or equal to –64 mV or with a constant stream of ones with an input greater than or equal to 64 mV. In this case, however, the AMC3306M05 generates a single 1 (if the input is at negative full-scale) or 0 (if the input is at positive full-scale) every 128 clock cycles to indicate proper device function (see the Output Behavior in Case of a Full-Scale Input section for more details). Figure 7-4 shows the input voltage versus the output modulator signal. + FS (Analog Input) Modulator Output ± FS (Analog Input) Analog Input Figure 7-4. AMC3306M05 Modulator Output vs Analog Input The density of ones in the output bitstream can be calculated using Equation 1 for any input voltage value with the exception of a full-scale input signal, as described in Output Behavior in Case of a Full-Scale Input: VIN VClipping 2 u VClipping (1) 7.3.4.1 Output Behavior in Case of a Full-Scale Input If a full-scale input signal is applied to the AMC3306M05 (that is, |VIN| ≥ VClipping), the device generates a single one or zero every 128 bits at DOUT, as shown in Figure 7-5, depending on the actual polarity of the signal being sensed. In this way, differentiating between a missing high-side supply and a full-scale input signal is possible on the system level. CLKIN DOUT VIN ” ±64 mV DOUT VIN • 64 mV 127 CLKIN cycles 127 CLKIN cycles Figure 7-5. Full-Scale Output of the AMC3306M05 7.3.4.2 Output Behavior in Case of a High-Side Supply Failure The AMC3306M05 provides a failsafe output that ensures that the output DOUT of the device is a constant bitstream of logic 0's in case the integrated DC/DC converter output voltage is below the undervoltage detection threshold. See the Diagnostic Output section for more information. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 7.3.5 Isolated DC/DC Converter The AMC3306M05 offers a fully integrated isolated DC/DC converter that includes the following components illustrated in the Functional Block Diagram section: • Low-dropout regulator (LDO) on the low-side to stabilize the supply voltage VDD that drives the low-side of the converter. This circuit does not output a constant voltage and is not intended for driving any external load. • Low-side full-bridge inverter and drivers • Laminate-based, air-core transformer for high immunity to magnetic fields • High-side full-bridge rectifier • High-side LDO to stabilize the output voltage of the DC/DC converter for high analog performance of the signal path. The high-side LDO outputs a constant voltage and can provide a limited amount of current to power external circuitry. The DC/DC converter uses a spread-spectrum clock generation technique to reduce the spectral density of the electromagnetic radiation. The resonator frequency is synchronized to the operation of the ΔΣ modulator to minimize interference with data transmission and support the high analog performance of the device. The architecture of the DC/DC converter is optimized to drive the high-side circuitry of the AMC3306M05 and can source up to IH of additional DC current for an optional auxiliary circuit such as an active filter, preamplifier, or comparator. As shown in Figure 7-6, IH is specified up to an ambient temperature of 85°C and derates linearly at higher temperatures. 1.25 IH (mA) 1 0.75 0.5 0.25 0 -40 -25 -10 5 20 35 50 TA (qC) 65 80 95 110 125 D005 D048 Figure 7-6. Derating of IH at Ambient Temperatures >85°C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 23 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 7.3.6 Diagnostic Output As shown in Figure 7-7, the open-drain DIAG pin can be monitored to confirm the device is operational, and the output data are valid. During power-up, the DIAG pin is actively held low until the high-side supply is in regulation and the modulator starts outputting data. The DIAG pin is actively pulled low if: • • The low-side does not receive data from the high-side (for example, because of a loss of power on the high-side). The modulator itself outputs a constant bitstream of logic 0's in this case, that is, the DOUT pin is permanently low. The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop below their respective undervoltage detection thresholds (brown-out). In this case, the low-side may still receive data from the high-side but the data may not be valid. However, the modulator itself outputs a constant bitstream of logic 0's in this case, meaning that the DOUT pin is permanently low. CLKIN DOUT DIAG Power-up Normal Operation High-side supply undervoltage Normal Operation Figure 7-7. DIAG and Output Under Different Operating Conditions 7.4 Device Functional Modes The AMC3306M05 is operational when VDD is applied, as specified in the Recommended Operating Conditions table. 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The low analog input voltage range, excellent accuracy, and low temperature drift make the AMC3306M05 a high performance solution for industrial applications where shunt-based current sensing in the presence of high common-mode voltage levels is required. 8.1.1 Digital Filter Usage The modulator generates a bitstream that must be processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, as shown in Equation 2, built with minimal effort and hardware, is a sinc3-type filter: H z § 1 z OSR ¨¨ 1 © 1 z · ¸¸ ¹ 3 (2) This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-order modulator. All characterization in this document is done with a sinc3 filter with an oversampling ratio (OSR) of 256 and an output word width of 16 bits, unless specified otherwise. The measured effective number of bits (ENOB) as a function of the OSR is illustrated in Figure 8-3 of the Typical Application section. A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter-order to achieve the desired output resolution and filter response time. An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for download at www.ti.com. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 25 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 8.2 Typical Application 8.2.1 Solar Inverter Application The AMC3306M05 is ideally suited for shunt-based current sensing applications where accurate current monitoring is required in the presence of high common-mode voltages. The AMC3306M05 integrates an isolated power supply for the high-voltage side and therefore makes the device particularly easy to use in applications that do not have a high-side supply readily available or where a high-side supply is referenced to a different ground potential than the signal to be measured. Figure 8-1 shows a simplified schematic of the AMC3306M05 in a solar inverter where the phase current is measured on the grid-side of an LCL filter. Although the system offers a supply for the high-side gate driver, there is a large common-mode voltage between the gate driver supply ground reference and the shunt resistor on the other side of the LCL filter. Therefore, the gate driver supply is not suitable for powering the high-side of an isolated modulator that measures the voltage across the shunt. The integrated isolated power supply of the AMC3306M05 solves that problem and enables current sensing at locations that is optimal for the system. DC+ HS Gate Driver Supply IPHASE to grid RSHUNT GND LS Gate Driver Supply DC- GND AMC3306M05 1 µF 1 nF 100 nF DCDC_OUT DCDC_HGND HLDO_IN DCDC_IN DCDC_GND 47 k DIAG to uC (optional) 100 nF NC LDO_OUT 100 nF 1 nF 10
1 nF 1 µF HLDO_OUT VDD 3.3 V / 5 V supply 10 nF INP CLKIN from uC INN DOUT to uC 10 HGND GND GND Figure 8-1. The AMC3306M05 in a Solar Inverter Application 8.2.1.1 Design Requirements Table 8-1 lists the parameters for this typical application. Table 8-1. Design Requirements 26 PARAMETER VALUE Low-side supply voltage 3.3 V or 5 V Voltage drop across RSHUNT for a linear response ±50 mV (maximum) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 8.2.1.2 Detailed Design Procedure The AMC3306M05 requires a single 3.3-V or 5-V supply on its low-side. The high-side supply is internally generated by an integrated DC/DC converter as explained in the Isolated DC/DC Converter section. The ground reference (HGND) is derived from the terminal of the shunt resistor that is connected to the negative input (INN) of the AMC3306M05. If a four-pin shunt is used, the inputs of the device are connected to the inner leads and HGND is connected to one of the outer leads. To minimize offset and improve accuracy, set the ground connection to a separate trace that connects directly to the shunt resistor rather than shorting HGND to INN directly at the input to the device. See the Layout section for more details. 8.2.1.2.1 Shunt Resistor Sizing Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured current: VSHUNT = I × RSHUNT. Consider the following two restrictions to choose the proper value of the shunt resistor, RSHUNT: • • The voltage drop caused by the nominal current range must not exceed the recommended differential input voltage range for linear response: |VSHUNT| ≤ VFSR The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes a clipping output: |VSHUNT| ≤ |VClipping| 8.2.1.2.2 Input Filter Design TI recommends placing a RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the signal path. Design the input filter such that: • • • The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency of the ΔΣ modulator (fCLKIN) The input bias current does not generate significant voltage drop across the DC impedance of the input filter The impedances measured from the analog inputs are equal For most applications the structure shown in Figure 8-2 achieves excellent performance. AMC3306M05 DCDC_OUT DCDC_HGND DCDC_IN DCDC_GND HLDO_IN RSHUNT NC 10
DIAG LDO_OUT HLDO_OUT VDD 10 nF INP CLKIN INN DOUT 10 HGND GND Figure 8-2. Differential Input Filter 8.2.1.2.3 Bitstream Filtering For modulator output bitstream filtering, a device from TI's C2000™ or Sitara™ microcontroller families is recommended. These families support up to eight channels of dedicated hardwired filter structures that significantly simplify system level design by offering two filtering paths per channel: one providing high-accuracy results for the control loop and one fast-response path for overcurrent detection. A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter-order to achieve the desired output resolution and filter response time. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 27 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 8.2.1.3 Application Curve The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. Figure 8-3 shows the ENOB of the AMC3306M05 with different oversampling ratios. By using Equation 3, this number can also be calculated from the SINAD: SINAD = 1.76 dB + 6.02 dB x ENOB (3) 16 14 ENOB (bits) 12 10 8 6 4 sinc3 sinc2 sinc1 2 0 1 10 100 OSR 1000 D013 Figure 8-3. Measured Effective Number of Bits vs Oversampling Ratio 8.2.2 What To Do and What Not To Do Do not leave the inputs of the AMC3306M05 unconnected (floating) when the device is powered up. If the device inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the operating common-mode input voltage and the output of the device is undetermined. Connect the negative input (INN) to the high-side ground (HGND), either by a hard short or through a resistive path. A DC current path between INN and HGND is required to define the input common-mode voltage. Take care not to exceed the input common-mode range as specified in the Recommended Operating Conditions table. For best accuracy, route the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting AGND to INN directly at the input to the device. See the Layout section for more details. The high-side LDO can source a limited amount of current (IH) to power external circuitry. Take care not to overload the high-side LDO and be aware of derating IH at high temperatures as explained in the Isolated DC/DC Converter section. The low-side LDO does not output a constant voltage and is not intended for powering any external circuitry. Do not connect any external load to the HLDO_OUT pin. 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 9 Power Supply Recommendations The AMC3306M05 is powered from the low-side power supply (VDD) with a nominal value of 3.3 V or 5 V. TI recommends a low-ESR decoupling capacitor of 1 nF (C8 in Figure 9-1) placed as close as possible to the VDD pin, followed by a 1-µF capacitor (C9) to filter this power-supply path. The low-side of the DC/DC converter is decoupled with a low-ESR, 100-nF capacitor (C4) positioned close to the device between the DCDC_IN and DCDC_GND pins. Use a 1-µF capacitor (C2) to decouple the high-side in addition to a low-ESR, 1-nF capacitor (C3) placed as close as possible to the device and connected to the DCDC_OUT and DCDC_HGND pins. For the high-side LDO, use low-ESR capacitors of 1-nF (C6), placed as close as possible to the AMC3306M05, followed by a 100-nF decoupling capacitor (C5). The ground reference for the high-side (HGND) is derived from the terminal of the shunt resistor that is connected to the negative input (INN) of the device. For best DC accuracy, use a separate trace to make this connection instead of shorting HGND to INN directly at the device input. The high-side DC/DC ground terminal (DCDC_HGND) is shorted to HGND directly at the device pins. AMC3306M05 C2 C3 1 µF 1 nF DCDC_OUT DCDC_HGND C4 100 nF DCDC_IN DCDC_GND R1 47 k C1 100 nF HLDO_IN I RSHUNT C5 C6 100 nF 1 nF R2 10
C10 10 nF NC HLDO_OUT DIAG LDO_OUT to uC (optional) C8 C9 1 nF 1 µF VDD 3.3 V / 5 V supply INP CLKIN from uC INN DOUT to uC R4 10 HGND GND Figure 9-1. Decoupling the AMC3306M05 Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they experience in the application. MLCC capacitors typically exhibit only a fraction of their nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves that greatly simplify component selection. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 29 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 Table 9-1 lists components suitable for use with the AMC3306M05. This list is not exhaustive. Other components may exist that are equally suitable (or better), however these listed components have been validated during the development of the AMC3306M05. Table 9-1. Recommended External Components DESCRIPTION PART NUMBER MANUFACTURER SIZE (EIA, L x W) VDD C8 1 nF ± 10%, X7R, 50 V 12065C102KAT2A AVX 1206, 3.2 mm x 1.6 mm C9 1 µF ± 10%, X7R, 25 V 12063C105KAT2A AVX 1206, 3.2 mm x 1.6 mm DC/DC CONVERTER C4 100 nF ± 10%, X7R, 50 V C0603C104K5RACAUTO Kemet 0603, 1.6 mm x 0.8 mm C3 1 nF ± 10%, X7R, 50 V C0603C102K5RACTU Kemet 0603, 1.6 mm x 0.8 mm C2 1 µF ± 10%, X7R, 25 V CGA3E1X7R1E105K080AC TDK 0603, 1.6 mm x 0.8 mm C1 100 nF ± 10%, X7R, 50 V C0603C104K5RACAUTO Kemet 0603, 1.6 mm x 0.8 mm C5 100 nF ± 5%, NP0, 50 V C3216NP01H104J160AA TDK 1206, 3.2 mm x 1.6 mm C6 1 nF ± 10%, X7R, 50 V 12065C102KAT2A AVX 1206, 3.2 mm x 1.6 mm HLDO 10 Layout 10.1 Layout Guidelines Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as possible to the AMC3306M05 supply pins) and placement of the other components required by the device. For best performance, place the shunt resistor close to the INP and INN inputs of the AMC3306M05 and keep the layout of both connections symmetrical. This layout is used on the AMC3306M05 EVM and supports CISPR-11 compliant electromagnetic radiation levels. 10.2 Layout Example C4 C3 DIAG To MCU I/O (optional) R1 C1 C2 Clearance area, to be kept free of any conductive materials. C9 C8 R4 C6 INN C5 VDD R2 C10 RSHUNT AMC3306M05 INP CLKIN DOUT 3.3-V or 5-V supply From Clock Source (MCU) To Digital Filter (MCU) GND HGND Top Metal Inner or Bottom Layer Metal Via Figure 10-1. Recommended Layout of the AMC3306M05 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 AMC3306M05 www.ti.com SBASA82A – DECEMBER 2020 – REVISED APRIL 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature 11.1.1.1 Isolation Glossary See the Isolation Glossary 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • Texas Instruments, Isolation Glossary application report • Texas Instruments, Semiconductor and IC Package Thermal Metrics application report • Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report • Texas Instruments, Delta Sigma Modulator Filter Calculator design tool 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks C2000™, Sitara™, and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: AMC3306M05 31 PACKAGE OPTION ADDENDUM www.ti.com 4-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) AMC3306M05DWE ACTIVE SOIC DWE 16 40 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AMC3306M05 AMC3306M05DWER ACTIVE SOIC DWE 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 AMC3306M05 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of