AMC3330
AMC3330
SBASA34A – JUNE 2020 – REVISED OCTOBER
2020
SBASA34A – JUNE 2020 – REVISED OCTOBER 2020
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AMC3330 Precision, ±1-V Input, Reinforced Isolated Amplifier
With Integrated DC/DC Converter
1 Features
3 Description
•
The AMC3330 is a precision, isolated amplifier with a
fully integrated, isolated DC/DC converter that allows
single-supply operation from the low-side of the
device. The reinforced capacitive isolation barrier is
certified according to VDE V 0884-11 and UL1577
and separates sections of the system that operate on
different common-mode voltage levels and protects
low-voltage domains from damage.
•
•
•
•
•
•
•
3.3-V or 5-V single supply operation with
integrated DC/DC converter
±1-V input voltage range optimized for voltage
measurements with high input impedance
Fixed gain: 2.0
Low DC errors:
– Gain error: ±0.2% (max)
– Gain drift: ±45 ppm/°C (max)
– Offset error: ±0.3 mV (max)
– Offset drift: ±4 µV/°C (max)
– Nonlinearity: ±0.02% (max)
High CMTI: 85 kV/µs (min)
System-level diagnostic features
Safety-related certifications:
– 6000-VPK reinforced isolation per DIN VDE V
0884-11 (VDE V 0884-11): 2017-01
– 4250-VRMS isolation for 1 minute per UL1577
Meets CISPR-11 and CISPR-25 EMI standards
2 Applications
•
The input of the AMC3330 is optimized for direct
connection to high-impedance, voltage-signal sources
such as a resistor-divider network to sense highvoltage signals. The integrated isolated DC/DC
converter allows measurement of non-groundreferenced signals and makes the device a unique
solution for noisy, space-constrained applications.
The excellent performance of the device supports
accurate voltage monitoring and control. The
integrated DC/DC converter fault-detection and
diagnostic output pin of the AMC3330 simplify
system-level design and diagnostics.
The AMC3330 is specified over the temperature
range of –40°C to +125°C.
Isolated voltage sensing in:
– Motor drives
– Photovoltaic inverters
– Power delivery systems
– Electricity meters
– Protection relays
Device Information (1)
PART NUMBER
AMC3330
(1)
DCDC_OUT
BODY SIZE (NOM)
10.30 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
DCDC_IN
DCDC_HGND
DCDC_GND
Isolated
Power
Isolated
Power
Reinforced Isolation
HLDO_IN
PACKAGE
SOIC (16)
NC
HLDO_OUT
DIAG
To MCU (optional)
LDO_OUT
3.3 V / 5 V
VDD
INP
OUTP
INN
OUTN
ADS8363
16-Bit ADC
HGND
AMC3330
GND
GND
Application Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
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property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Power Ratings ............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .........................................9
6.11 Timing Diagram......................................................... 9
6.12 Insulation Characteristics Curves........................... 10
6.13 Typical Characteristics............................................ 11
7 Detailed Description......................................................17
7.1 Overview................................................................... 17
7.2 Functional Block Diagram......................................... 17
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................21
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
8.3 What to Do and What Not to Do............................... 24
9 Power Supply Recommendations................................25
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 Documentation Support.......................................... 28
11.3 Receiving Notification of Documentation Updates.. 28
11.4 Support Resources................................................. 28
11.5 Trademarks............................................................. 28
11.6 Electrostatic Discharge Caution.............................. 28
11.7 Glossary.................................................................. 28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2020) to Revision A (October 2020)
Page
• Changed document status from advance information to production data.......................................................... 1
2
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5 Pin Configuration and Functions
DCDC_OUT
1
16
DCDC_IN
DCDC_HGND
2
15
DCDC_GND
HLDO_IN
3
14
DIAG
NC
4
13
LDO_OUT
HLDO_OUT
5
12
VDD
INP
6
11
OUTP
INN
7
10
OUTN
HGND
8
9
GND
Not to scale
Figure 5-1. DWE Package, 16-Pin SOIC, Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE
High-side output of the isolated DC/DC converter; connect this pin to the HLDO_IN pin.(1)
1
DCDC_OUT
2
DCDC_HGND
3
HLDO_IN
Power
Input of the high-side low-dropout (LDO) regulator; connect this pin to the DCDC_OUT pin.(1)
4
NC
—
No internal connection. Connect this pin to the high-side ground or leave this pin unconnected
(floating).
5
HLDO_OUT
Power
6
INP
Analog Input
Noninverting analog input.
Analog Input
Inverting analog input. Connect this pin to HGND.
7
INN
8
HGND
Power
DESCRIPTION
Power Ground High-side ground reference for the isolated DC/DC converter; connect this pin to the HGND pin.
Output of the high-side LDO.(1)
Signal Ground High-side analog ground; connect this pin to the DCDC_HGND pin.
9
GND
10
OUTN
Analog Output Inverting analog output.
11
OUTP
Analog Output Noninverting analog output.
12
VDD
Power
Low-side power supply.(1)
13
LDO_OUT
Power
Output of the low-side LDO; connect this pin to the DCDC_IN pin.(1)
14
DIAG
Digital Output
15
DCDC_GND
16
DCDC_IN
(1)
Signal Ground Low-side analog ground; connect this pin to the DCDC_GND pin.
Active-low, open-drain status indicator output; connect this pin to the pullup supply (for example,
VDD) using a resistor or leave this pin floating if not used.
Power Ground Low-side ground reference for the isolated DC/DC converter; connect this pin to the GND pin.
Power
Low-side input of the isolated DC/DC converter; connect this pin to the LDO_OUT pin.(1)
See the Power Supply Recommendations section for power-supply decouplng recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
MAX
UNIT
Power-supply voltage
VDD to GND
–0.3
6.5
V
Analog input voltage
INP, INN
HGND – 6
VHLDOout + 0.5
V
Analog output voltage
OUTP, OUTN
GND – 0.5
VDD + 0.5
V
Digital output voltage
DIAG
GND – 0.5
5.5
V
Input current
Continuous, any pin except power-supply pins
10
mA
Temperature
(1)
–10
Junction, TJ
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC
Electrostatic discharge
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
3.0
3.3
5.5
UNIT
POWER SUPPLY
VDD
Low-side supply voltage
VDD to GND
V
ANALOG INPUT
VClipping
Differential input voltage before clipping output
VIN = VINP – VINN
VFSR
Specified linear differential full-scale voltage
VIN = VINP – VINN
–1
1
V
(VINP + VINN) / 2 to HGND
–2
3
V
(VINP + VINN) / 2 to HGND,
VINP = VINN
–1.4
1.6
(VINP + VINN) / 2 to HGND,
|VINP – VINN| = 1.0 V (2)
–0.925
0.725
(VINP + VINN) / 2 to HGND,
|VINP – VINN| = 1.25 V
–0.8
0.6
0
VDD
V
125
°C
Absolute common-mode input
VCM
voltage(1)
Operating common-mode input voltage
±1.25
V
V
DIGITAL OUTPUT
Pull-up supply-voltage for DIAG pin
TEMPERATURE RANGE
TA
(1)
(2)
4
Operating ambient temperature
–40
25
Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
Linear response.
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6.4 Thermal Information
AMC3330
THERMAL
METRIC(1)
UNIT
DWE (SOIC)
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
44
°C/W
ψJT
Junction-to-top characterization parameter
16.7
°C/W
ψJB
Junction-to-board characterization parameter
42.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
73.5
°C/W
31
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation
TEST CONDITIONS
MIN
TYP
MAX
VDD = 5.5 V
236.5
VDD = 3.6 V
155
UNIT
mW
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
Shortest pin-to-pin distance through air
≥8
mm
CPG
External creepage(1)
Shortest pin-to-pin distance across the package surface
≥8
mm
Minimum internal gap (internal clearance - capacitive signal
isolation)
≥ 21
Minimum internal gap (internal clearance - transformer power
isolation)
≥ 120
≥ 600
DTI
Distance through the insulation
CTI
µm
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN VDE V 0884-11 (VDE V 0884-11):
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum-rated isolation
working voltage
V
I
2017-01(2)
At AC voltage (bipolar)
1700
VPK
At AC voltage (sine wave); time-dependent dielectric
breakdown (TDDB) test
1200
VRMS
At DC voltage
1700
VDC
VTEST = VIOTM, t = 60 s (qualification test)
6000
VPK
VIOTM
Maximum transient
isolation voltage
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
7200
VPK
VIOSM
Maximum surge
isolation voltage(3)
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
6250
VPK
Apparent charge(4)
qpd
CIO
Barrier capacitance,
input to output(5)
RIO
Insulation resistance,
input to output(5)
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test),
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~3.5
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO, t = 1 s (100% production test)
4250
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings must be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11):
2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 73.5°C/W, VDD = 5.5 V,
TJ = 150°C, TA = 25°C
309
RθJA = 73.5°C/W, VDD = 3.6 V,
TJ = 150°C, TA = 25°C
472
RθJA = 73.5°C/W,
TJ = 150°C, TA = 25°C
UNIT
mA
1700
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum low-side voltage.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –1 V to +1 V, and INN
= HGND = 0 V; typical specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Single-ended input resistance
RIND
Differential input resistance
IIB
Input bias current
TCIIB
Input bias current drift
INN = HGND
INP = INN = HGND, IIB = (IIBP + I
IBN) / 2
0.1
0.8
0.1
1.2
–10
2.5
GΩ
10
–14
IIO
Input offset current
IIO = IINP – IINN; INP = INN = HGND
CIN
Single-ended input capacitance
INN = HGND, fIN = 310 kHz
–10
-0.8
2
CIND
Differential input capacitance
fIN = 310 kHz
2
nA
pA/°C
10
nA
pF
ANALOG OUTPUT
Nominal gain
2
VCMout
Common-mode output voltage
VCLIPout
Clipping differential output voltage
VOUT = (VOUTP – VOUTN);
|VIN| = |VINP – VINN| > VClipping
±2.49
VFailsafe
Fail-safe differential output voltage
V+ = (VOUTP – VOUTN); VDCDCout ≤ V
DCDCUV or VHLDOout ≤ VHLDOUV
–2.57
BWOUT
Output bandwidth
375
kHz
ROUT
Output resistance
On OUTP or OUTN
0.2
Ω
Output short-circuit current
On OUTP or OUTN, sourcing or
sinking, INP = INN = HGND, outputs
shorted to either GND or VDD
14
mA
Common-mode transient immunity
|HGND – GND| = 2 kV
85
135
kV/µs
EG
Gain error
TA = 25°C
–0.2%
–0.08%
0.2%
TCEG
Gain error drift(1)
–45
±7
45
–0.3
±0.05
0.3
–4
±1
4
–0.02%
0.01%
0.02%
CMTI
1.39
300
1.44
1.49
V
V
–2.5
V
ACCURACY
voltage(1)
VOS
Input offset
TCVOS
Input offset drift(1)
TA = 25°C, INP = INN = HGND
Nonlinearity
Nonlinearity drift
SNR
Signal-to-noise ratio
THD
CMRR
PSRR
8
0.4
VIN = 2 VPP, fIN = 1 kHz,
BW = 10 kHz, 10 kHz filter
VIN = 2 VPP, fIN = 10 kHz,
BW = 100 kHz, 1 MHz filter
81
ppm/°C
mV
µV/°C
ppm/°C
85
dB
72
Total harmonic distortion
VIN = 2 Vpp, fIN = 10 kHz,
BW = 100 kHz
–84
dB
Output noise
INP = INN = HGND, fIN = 0 Hz,
BW = 100 kHz
250
µVRMS
Common-mode rejection ratio
Power-supply rejection ratio
fIN = 0 Hz, VCM min ≤ VCM ≤VCM max
–100
fIN = 10 kHz, VCM min ≤ VCM ≤VCM max
–86
VDD from 3.0 V to 5.5 V, at dc, input
referred
–98
INP = INN = HGND, VDD from 3.0 V
to 5.5 V, 10 kHz / 100 mV ripple,
input referred
–86
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –1 V to +1 V, and INN
= HGND = 0 V; typical specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No external load on HLDO
28.5
41
mA
1 mA external load on HLDO
30.5
43
mA
4.65
POWER SUPPLY
IDD
Low-side supply current
VDCDC_OUT
DC/DC output voltage
DCDC_OUT to HGND
3.1
3.5
VDCDCUV
DC/DC output undervoltage
detection threshold voltage
DCDC output falling
2.1
2.25
VHLDO_OUT
High-side LDO output voltage
HLDO to HGND, up to 1 mA external
load
3
3.2
VHLDOUV
High-side LDO output undervoltage
detection threshold voltage
HLDO output falling
2.4
2.6
IH
High-side supply current for auxiliary Load connected from HLDO_OUT to
circuitry
HGND; non-switching
tAS
Analog settling time
(1)
VDD step to 3.0 V, to OUTP and
OUTN valid, 0.1% settling
V
V
3.4
V
V
1
mA
0.6
1.1
ms
TYP
MAX
The typical value includes one standard deviation ("sigma") at nominal operating conditons.
6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
tr
Output signal rise time
1.3
µs
tf
Output signal fall time
1.3
µs
VINx to VOUTx signal delay (50% – 10%)
Unfiltered output
1.2
1.3
µs
VINx to VOUTx signal delay (50% – 50%)
Unfiltered output
1.6
2.1
µs
VINx to VOUTx signal delay (50% – 90%)
Unfiltered output
2.2
2.6
µs
6.11 Timing Diagram
1V
INP - INN
0
±1V
tf
tr
OUTN
VCMout
OUTP
50% - 10%
50% - 50%
50% - 90%
Figure 6-1. Rise, Fall, and Delay Time Waveforms
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6.12 Insulation Characteristics Curves
1800
500
VDD = 3.6 V
VDD = 5.5 V
1600
400
1400
PS (mW)
IS (mA)
1200
300
200
1000
800
600
400
100
200
0
0
0
25
50
75
TA (°C)
100
125
0
150
25
50
D001
Figure 6-2. Thermal Derating Curve for SafetyLimiting Current per VDE
75
TA (°C)
100
125
150
D002
Figure 6-3. Thermal Derating Curve for SafetyLimiting Power per VDE
1.E+11
87.5%
1.E+10
143 Yrs
76 Yrs
1.E+09
Time to Fail (sec)
1.E+08
1.E+07
TDDB Line (< 1 ppm Fail Rate)
1.E+06
Operating Zone
1.E+05
1.E+04
VDE Safety Margin Zone
1.E+03
20 %
1.E+02
1.E+01
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
Applied Voltage (VRMS)
Working Isolation Voltage = 1200 VRMS
TA upto 150 oC
Projected Insulation Lifetime = 76 Yrs
Applied Voltage Frequency = 60 Hz
Figure 6-4. Reinforced Isolation Capacitor Lifetime Projection
10
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6.13 Typical Characteristics
10
10
8
8
6
6
4
4
2
2
IIB (nA)
IIB (nA)
at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and fIN = 10 kHz (unless otherwise noted)
0
-2
-4
-6
-6
-8
-10
-1.4
-10
-1
-0.6
-0.2
0.2
VCM (V)
0.6
1
1.4
3
5
4.5
6
4
4
3.5
VOUT(V)
2
0
-2
1
-8
0.5
80
95
D004
VOUTN
VOUTP
2
-6
20 35 50 65
Temperature (°C)
5.5
3
1.5
5
5
2.5
-4
-10
4.5
Figure 6-6. Input Bias Current vs Supply Voltage
8
-25
4
VDD (V)
10
-10
-40
3.5
D003
Figure 6-5. Input Bias Current vs Common-Mode Input Voltage
IIB (nA)
-2
-4
-8
0
-1.5
110 125
D005
Figure 6-7. Input Bias Current vs Temperature
-1
-0.5
0
0.5
Differential Input Voltage (V)
1
1.5
D006
Figure 6-8. Output vs Differential Input Voltage
5
0°
0
-45°
-5
-90°
-10
Output Phase
Normalized Gain (dB)
0
-15
-20
-25
-135°
-180°
-225°
-270°
-30
-315°
-35
-40
-360°
1
10
100
1000
fIN (kHz)
1
Figure 6-9. Normalized Gain vs Input Frequency
10
100
fIN (kHz)
D007
1000
D008
Figure 6-10. Output Phase vs Input Frequency
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6.13 Typical Characteristics (continued)
390
390
380
380
370
370
BW (kHz)
BW (kHz)
at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and fIN = 10 kHz (unless otherwise noted)
360
360
350
350
340
-40
340
3
3.5
4
4.5
5
5.5
VDD (V)
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D012
Figure 6-12. Output Bandwidth vs Temperature
Figure 6-11. Output Bandwidth vs Supply Voltage
0.3
50
Device 1
Device 2
Device 3
0.2
40
0.1
30
EG (%)
Devices (%)
-25
D011
20
0
-0.1
10
-0.2
-0.3
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
3
D018
EG (%)
3.5
4
4.5
5
5.5
VDD (V)
Figure 6-13. Gain Error Histogram
D020
Figure 6-14. Gain Error vs Supply Voltage
0.3
35
Device 1
Device 2
Device 3
0.2
30
25
Devices (%)
0
15
-0.1
10
-0.2
5
45
40
35
30
25
20
-5
5
TCEG (ppm/qC)
D021
Figure 6-15. Gain Error vs Temperature
15
110 125
10
95
-10
80
-15
20 35 50 65
Temperature (°C)
-20
5
-25
-10
-30
-25
-35
0
-40
-0.3
-40
12
20
-45
EG (%)
0.1
D019
Figure 6-16. Gain Error Drift Histogram
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and fIN = 10 kHz (unless otherwise noted)
100
50
Device 1
Device 2
Device 3
75
40
30
25
VOS (PV)
Devices (%)
50
20
0
-25
-50
10
-75
-100
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
3
3.5
4
D023
VOS (mV)
4.5
5
5.5
VDD (V)
Figure 6-17. Offset Error Histogram
D027
Figure 6-18. Offset Error vs Supply Voltage
100
50
Device 1
Device 2
Device 3
75
40
Devices (%)
VOS (PV)
50
25
0
-25
-50
30
20
10
-75
20 35 50 65
Temperature (°C)
80
95
110 125
4
3
2
1
0
Figure 6-20. Offset Error Drift Histogram
0.02
0.02
Device 1
Device 2
Device 3
0.015
Device 1
Device 2
Device 3
0.015
0.01
0.01
Nonlinearity (%)
Nonlinearity (%)
D024
TCVOS (PV/qC)
D026
Figure 6-19. Offset Error vs Temperature
0.005
0
-0.005
0.005
0
-0.005
-0.01
-0.01
-0.015
-0.015
-0.02
-1
-1
5
-2
-10
-3
-25
-4
0
-100
-40
-0.02
-0.75
-0.5 -0.25
0
0.25
0.5
Differential Input Volatge (V)
0.75
1
3
Figure 6-21. Nonlinearity vs Differential Input Voltage
3.5
4
4.5
5
VDD (V)
D028
5.5
D024
D001
D029
Figure 6-22. Nonlinearity vs Supply Voltage
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6.13 Typical Characteristics (continued)
0.02
80
0.015
75
0.01
70
0.005
65
SNR (dB)
Nonlinearity (%)
at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and fIN = 10 kHz (unless otherwise noted)
0
-0.005
-0.01
-0.02
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
40
110 125
0
0.25
0.5
0.75
|VINP - VINN| (V)
D024
D001
D030
1
1.25
D032
Figure 6-24. Signal to Noise Ratio vs Differential Input Voltage
77
77
Device 1
Device 2
Device 3
76
75
75
74
74
73
73
72
71
72
71
70
70
69
69
68
68
67
-40
67
3
3.5
4
4.5
5
5.5
VDD (V)
Device 1
Device 2
Device 3
76
SNR (dB)
SNR (dB)
55
45
Figure 6-23. Nonlinearity vs Temperature
-25
-10
5
D034
Figure 6-25. Signal to Noise Ratio vs Supply Voltage
20 35 50 65
Temperature (°C)
80
95
110 125
D035
Figure 6-26. Signal to Noise Ratio vs Temperature
-70
-70
Device 1
Device 2
Device 3
-75
-75
-80
THD (dB)
-80
THD (dB)
60
50
Device 1
Device 2
Device 3
-0.015
-85
-85
-90
-90
-95
-95
-100
3
3.5
4
4.5
VDD (V)
5
5.5
-100
-40
Device 1
Device 2
Device 3
-25
D056
Figure 6-27. Total Harmonic Distortion vs Supply Voltage
14
Device 1
Device 2
Device 3
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D059
Figure 6-28. Total Harmonic Distortion vs Temperature
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and fIN = 10 kHz (unless otherwise noted)
0
10000
-40
CMRR (dB)
Noise Density (nV/—Hz)
-20
1000
-60
-80
-100
100
0.01
0.1
1
10
Frequency (kHz)
100
-120
0.01
1000
0.1
1
Figure 6-29. Input-Referred Noise Density vs Frequency
10
100
1000
fIN (kHz)
D017
D038
Figure 6-30. Common-Mode Rejection Ratio vs Input Frequency
-80
0
fIN = 10 kHz
-20
-82
PSRR (dB)
CMRR (dB)
-40
-84
-86
-60
-80
-88
-90
-40
-100
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-120
0.01
110 125
0.1
1
10
Ripple Frequency (kHz)
100
1000
D041
D039
Figure 6-31. Common-Mode Rejection Ratio vs Temperature
Figure 6-32. Power-Supply Rejection Ratio vs Ripple Frequency
0
32.5
-20
30
IDD (mA)
PSRR (dB)
-40
-60
27.5
-80
25
-100
-120
-40
22.5
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
3
Figure 6-33. Power-Supply Rejection Ratio vs Temperature
3.5
4
4.5
5
5.5
VDD (V)
D042
D043
Figure 6-34. Input-Supply Current vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and fIN = 10 kHz (unless otherwise noted)
3.4
32.5
3.35
3.3
VHLDO_OUT (V)
IDD (mA)
30
27.5
25
3.25
3.2
3.15
3.1
3.05
22.5
-40
3
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
3
2.5
2.5
2
2
tr/tf (Ps)
tr / tf (Ps)
3
1.5
1
0.5
0.5
0
-40
0
4.5
5
5.5
VDD (V)
5.5
D046
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D066
Figure 6-38. Output Rise And Fall Time vs Temperature
3.8
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
2.6
2.2
1.8
1.4
1
1
0.6
0.6
0.2
3
3.5
4
4.5
VDD (V)
5
50% - 90%
50% - 50%
50% - 10%
3.4
Signal Delay (Ps)
3
Signal Delay (Ps)
-25
D065
Figure 6-37. Output Rise And Fall Time vs Supply Voltage
5.5
0.2
-40
-25
D67_
Figure 6-39. VIN to VOUT Signal Delay Time vs Supply Voltage
16
5
1.5
1
4
4.5
Figure 6-36. High-Side LDO Line Regulation
3
3.5
4
VDD (V)
Figure 6-35. Input-Supply Current vs Temperature
3
3.5
D044
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D68_
Figure 6-40. VIN to VOUT Signal Delay Time vs Temperature
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7 Detailed Description
7.1 Overview
The AMC3330 is a fully-differential, precision, isolated amplifier with high input impedance, and an integrated
DC/DC converter that allows the device to be supplied from a single 3.3-V or 5-V voltage supply source on the
low side. The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The modulator uses
an internal voltage reference and clock generator to convert the analog input signal to a digital bitstream. The
drivers (termed TX in the Functional Block Diagram) transfer the output of the modulator across the isolation
barrier that separates the high-side and low-side voltage domains. The received bitstream and clock are
synchronized and processed by a fourth-order analog filter on the low-side and presented as a differential analog
output.
A block diagram of the AMC3330 is shown in the Functional Block Diagram. The 1.2-GΩ differential input
impedance of the analog input stage supports low gain-error signal-sensing in high-voltage applications using
high-impedance resistor dividers.
The signal path is isolated by a double capacitive silicon-dioxide (SiO 2) insulation barrier, whereas power
isolation uses an on-chip transformer separated by a thin-film polymer as the insulating material.
7.2 Functional Block Diagram
DCDC_OUT
Resonator and
Driver
Rectifier
DCDC_HGND
Bandgap
Reference
HLDO_IN
LDO
HLDO_OUT
Bandgap
Reference
TX
RX
INN
RX
TX
DCDC_GND
DIAG
LDO_OUT
LDO
VDD
Isolation
Barrier
INP
û Modulator
Diagnostics
DCDC_IN
Retiming and
4th-Order
Active
Low-Pass
Filter
OUTP
OUTN
Oscillator
AMC3330
HGND
GND
7.3 Feature Description
7.3.1 Analog Input
The input stage of the AMC3330 feeds a second-order, switched-capacitor, feed-forward ΔΣ modulator. The
modulator converts the analog signal into a bitstream that is transferred over the isolation barrier, as described in
the Isolation Channel Signal Transmission section. The high-impedance, and low bias-current input of the
AMC3330 makes the device suitable for isolated, high-voltage-sensing applications that typically employ highimpedance resistor dividers.
There are two restrictions on the analog input signals (INP and INN). First, if the input voltage exceeds the input
range specified in the Absolute Maximum Ratings table, the input current must be limited to 10 mA because the
device input electrostatic discharge (ESD) diodes turn on. Second, the linearity and noise performance of the
device are ensured only when the differential analog input voltage remains within the specified linear full-scale
range V FSR and within the specified input common-mode voltage range V CM as specified in the Recommended
Operating Conditions table.
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7.3.2 Isolation Channel Signal Transmission
The AMC3330 uses an on-off keying (OOK) modulation scheme to transmit the modulator output-bitstream
across the capacitive SiO 2-based isolation barrier. Figure 7-1 shows the block diagram of an isolation channel.
The transmitter modulates the bitstream at TX IN with an internally generated, 480-MHz carrier and sends a
burst across the isolation barrier to represent a digital one and sends a no signal to represent the digital zero.
The receiver demodulates the signal after advanced signal conditioning and produces the output. The
symmetrical design of each isolation channel improves the common-mode transient immunity (CMTI)
performance and reduces the radiated emissions caused by the high-frequency carrier.
Transmitter
Receiver
OOK
Modulation
TX IN
TX Signal
Conditioning
SiO2-Based
Capacitive
Reinforced
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Oscillator
Figure 7-1. Block Diagram of an Isolation Channel
Figure 7-2 shows the concept of the on-off keying scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
Figure 7-2. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC3330 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input
voltages (VINP – VINN) in the range from –1 V to 1 V, the device provides a linear response with a nominal gain of
2. For example, for a differential input voltage of 1 V, the differential output voltage (V OUTP – V OUTN) is 2 V. At
zero input (INP shorted to INN), both pins output the same voltage, V CMout, as specified in the Electrical
Characteristics table. For absolute differential input voltages greater than 1.0 V but less than 1.25 V, the
differential output voltage continues to increase in magnitude but with reduced linearity performance. The
outputs saturate as shown in Figure 7-3 if the differential input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping)
Linear input range (VFSR)
VOUTN
.
Common mode output voltage
(VCMout)
VOUTP
± 1.25 V
± 1.00 V
0
1.25 V
1.00 V
Differential Input Voltage (VINP ± VINN)
Figure 7-3. AMC3330 Output Behavior
The AMC3330 provides a fail-safe output that simplifies diagnostics on system level. The fail-safe output is
active when the integrated DC/DC converter or hgh-side LDO don't deliver the required supply voltage for the
high-side of the device. Figure 7-4 and Figure 7-5 illustrate the fail-safe output of the AMC3330 that is a negative
differential output voltage value that does not occur under normal operating conditions. Use the maximum V
FAILSAFE voltage specified in the Electrical Characteristics table as a reference value for the fail-safe detection on
system level.
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VOUTN
-2.492 V
VOUTP
Figure 7-4. Typical Negative Clipping Output of the AMC3330
VOUTN
-2.567 V
VOUTP
Figure 7-5. Typical Fail-Safe Output of the AMC3330
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7.3.4 Isolated DC/DC Converter
The AMC3330 offers a fully integrated isolated DC/DC converter that includes the following components
illustrated in the Functional Block Diagram:
• Low-dropout regulator (LDO) on the low-side to stabilize the supply voltage VDD that drives the low-side of
the DC/DC converter
• Low-side full-bridge inverter and drivers
• Laminate-based, air-core transformer for high immunity to magnetic fields
• High-side full-bridge rectifier
• High-side LDO to stabilize the output voltage of the DC/DC converter for high analog performance of the
signal path
The DC/DC converter uses a spread-spectrum clock generation technique to reduce the spectral density of the
electromagnetic radiation. The resonator frequency is synchronous to the operation of the ΔΣ modulator to
minimize interference with data transmission and support the high analog performance of the device.
The architecture of the DC/DC converter is optimized to drive the high-side circuitry of the AMC3330 and can
source up to 1 mA of additional current (I H) for an optional auxiliary circuit such as an active filter, pre-amplifier,
or comparator.
7.3.5 Diagnostic Output and Fail-Safe Behavior
The open-drain DIAG pin can be monitored to confirm the device is operational, and the output voltage is valid.
During power-up, the DIAG pin is actively held low until the high-side supply is in regulation and the device
operates properly. The DIAG pin is actively pulled low if:
•
•
The low-side does not receive data from the high-side (for example, because of a loss of power on the highside). The amplifier outputs are driven to negative full-scale.
The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds VDCDCUV and VHLDOUV as sepecified in the Electrical
Characteristics table. In this case, the low-side may still receive data from the high-side but the data may not
be valid. The amplifier outputs are driven to negative full-scale.
During normal operation, the DIAG pin is in a high-impedance state. Connect the DIAG pin to a pull-up supply
through a resistor or leave open if not used.
7.4 Device Functional Modes
The AMC3330 is operational when the power supply VDD is applied, as specified in the Recommended
Operating Conditions table.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The low input bias current, AC and DC errors, and temperature drift make the AMC3330 a high-performance
solution for applications where voltage measurement with high common-mode levels is required.
8.2 Typical Application
Isolated amplifiers are widely used for voltage measurements in high-voltage applications that must be isolated
from a low-voltage domain. Typical applications are AC line voltage measurements at the input of a power factor
correction (PFC) stage or the output of a solar inverter. Other applications are DC measurements at the output of
a PFC stage or DC/DC converter, or phase voltage measurements in motor and servo drives. The AMC3330
integrates an isolated power supply for the high-voltage side and therefore is particularly easy to use in
applications that do not have a high-side supply readily available or where a high-side supply is referenced to a
different ground potential than the signal to be measured.
Figure 8-1 shows a simplified schematic of the AMC3330 in a solar inverter where the AC phase voltage on the
grid-side must be measured. At that location in the system, there is no supply readily available for powering the
isolated amplifier. The integrated isolated power supply, together with its bipolar input voltage range, makes the
AMC3330 ideally suited for AC line-voltage sensing. In this example, phase current is sensed by the AMC3301
across a shunt resistor on the grid-side of an LCL filter where there is also no suitable supply available for
powering the isolated amplifier. The integrated power supply of the AMC3301 eliminates that problem and
enables current sensing at optimal locations for the system.
DC+
SW
N
HS Gate
Driver
Supply
PGND
SW
IPHASE
to grid (L1)
RL11
RSHUNT
PGND
LS Gate
Driver
Supply
RL1SNS
DC-
PGND
RL12
AMC3301
1 µF 1 nF
100 nF
DCDC_OUT
N
DCDC_IN
DCDC_HGND
DCDC_GND
HLDO_IN
47 NŸ
DIAG
to uC (optional)
100 nF
NC
LDO_OUT
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
10 Ÿ
VDD
3.3 V / 5 V supply
8.2 nF
INP
OUTP
ADS8363
INN
OUTN
16-Bit ADC
to MCU
10 Ÿ
HGND
GND
GND
AMC3330
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
DCDC_IN
DCDC_GND
47 NŸ
DIAG
to uC (optional)
100 nF
NC
LDO_OUT
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
VDD
3.3 V / 5 V supply
10 nF
INP
OUTP
ADS8363
INN
OUTN
16-Bit ADC
HGND
to MCU
GND
GND
Figure 8-1. The AMC3330 in a Solar Inverter Application
22
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8.2.1 Design Requirements
Table 8-1 lists the parameters for this typical application.
Table 8-1. Design Requirements
PARAMETER
VALUE
Low-side supply voltage
3.3 V or 5 V
Voltage drop across the sensing resistor for a linear response
1 V (maximum)
Current through the resistive divider, ICROSS
100 µA (maximum)
8.2.2 Detailed Design Procedure
Use Ohm's Law to calculate the minimum total resistance of the resistive divider to limit the cross current to the
desired value ( R TOTAL = V Lx / I CROSS ) and the required sense resistor value to be connected to the AMC3330
input: RSNS = VFSR / ICROSS.
Consider the following two restrictions to choose the proper value of the sense resistor RSNS:
•
•
The voltage drop on RSNS caused by the nominal voltage range of the system must not exceed the
recommended input voltage range: VSNS ≤ VFSR
The voltage drop on RSNS caused by the maximum allowed system overvoltage must not exceed the input
voltage that causes a clipping output: VSNS ≤ VClipping
Table 8-2 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 120-V and
230-V AC line voltages.
Table 8-2. Resistor Value Examples
PARAMETER
120-VRMS LINE VOLTAGE 120-VRMS LINE VOLTAGE 230-VRMS LINE VOLTAGE
Peak voltage
170 V
170 V
325 V
Resistive divider resistors RL11, RL12
845 kΩ
845 kΩ
1.62 MΩ
Sense resistor RSNS
10 kΩ
10 kΩ
10 kΩ
Current through resistive divider ICROSS
100 µA
100 µA
100 µA
Resulting voltage drop on sense resistor VSNS
1.00 V
1.00 V
1.00 V
8.2.2.1 Input Filter Design
TI recommends placing an RC filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
•
•
•
The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the internal ΔΣ modulator
The input bias current does not generate significant voltage drop across the DC impedance of the input filter
The impedances measured from the analog inputs are equal
Most voltage sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale
down the input voltage. In this case, a single capacitor shown in Figure 8-2 is sufficient to filter the input signal.
RSNS
10 nF
INP
INN
AMC3330
HGND
Figure 8-2. Differential Input Filter
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8.2.2.2 Differential to Single-Ended Output Conversion
For systems using single-ended input ADCs to convert the analog output voltage into digital, Figure 8-3 shows
an example of a TLV6001 -based signal conversion and filter circuit. With R1 = R2 = R3 = R4, the output voltage
equals (V OUTP – V OUTN) + V REF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 10 kΩ
and C1 = C2 = 1000 pF yields good performance.
AMC3330
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
HLDO_OUT
DCDC_IN
DCDC_GND
DIAG
C1
LDO_OUT
R2
VDD
INP
OUTP
INN
OUTN
R1
±
R3
HGND
GND
C2
ADC
+
To MCU
TLV6001
GND
R4
GND
VREF
GND
Figure 8-3. Connecting the AMC3330 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the
18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
8.2.3 Application Curve
Figure 8-4 shows the typical full-scale step response of the AMC3330
VOUTN
VIN
VOUTP
Figure 8-4. Step Respose of the AMC3330
8.3 What to Do and What Not to Do
Do not leave the analog inputs INP and INN of the AMC3330 unconnected (floating) when the device is powered
up on the high-side. If the device input is left floating, the bias current may generate a negative input voltage that
exceeds the specified input voltage range and the output of the device is invalid.
Connect the high-side ground (HGND) to INN, either directly or through a resistive path. A DC current path
between INN and HGND is required to define the input common-mode voltage. Take care not to exceed the input
common-mode range as specified in the Recommended Operating Conditions table.
24
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9 Power Supply Recommendations
The AMC3330 is powered from the low-side power supply (VDD) with a nominal value of 3.3 V (or 5 V). TI
recommends a low-ESR decoupling capacitor of 1 nF (C8 in Figure 9-1) placed as close as possible to the VDD
pin, followed by a 1-µF capacitor (C9) to filter this power-supply path.
The low-side of the DC/DC converter is decoupled with a low-ESR 100-nF capacitor (C4) positioned close to the
device between the DCDC_IN and DCDC_GND pins. Use a 1-µF capacitor (C2) to decouple the high-side in
addition to a low-ESR, 1-nF capacitor (C3) placed as close as possible to the device and connected to the
DCDC_OUT and DCDC_HGND pins.
For the high-side LDO, use low-ESR capacitors of 1-nF (C6), placed as close as possible to the AMC3330,
followed by a 100-nF decoupling capacitor (C5).
The ground reference for the high-side (HGND) is derived from the terminal of the sense resistor which is
connected to the negative input (INN) of the device. For best DC accuracy, use a separate trace to make this
connection but shorting HGND to INN directly at the device input is also acceptable. The high-side DC/DC
ground terminal(DCDC_HGND) is shorted to HGND directly at the device pins.
C2 C3
1 µF 1nF
DCDC_OUT
C4
100 nF
DCDC_IN
Resonator
And
Driver
Rectifier
DCDC_HGND
HLDO_IN
Diagnostics
DCDC_GND
R1
47 NŸ
DIAG
to MCU (optional)
NC
C5
C6
100 nF 1 nF
HLDO_OUT
LDO_OUT
LDO
VDD
INP
OUTP
INN
OUTN
C8 C9
1 nF 1 µF
3.3 V / 5 V supply
to ADC
RSNS
C10
10 nF
LDO
Reinforced Isolation
C1
100 nF
HGND
AMC3330
to ADC
GND
GND
Figure 9-1. Decoupling the AMC3330
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) capacitors typically exhibit only a fraction of
their nominal capacitance under real-world conditions and this factor must be taken into consideration when
selecting these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field
strength is higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC
bias curves that greatly simplify component selection.
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Table 9-1 lists components suitable for use with the AMC3330. This list is not exhaustive. Other components
may exist that are equally suitable (or better), however these listed components have been validated during the
development of the AMC3330.
Table 9-1. Recommended External Components
DESCRIPTION
PART NUMBER
MANUFACTURER
SIZE (EIA, L x W)
VDD
C8
1 nF ± 10%, X7R, 50 V
12065C102KAT2A
AVX
1206, 3.2 mm x 1.6 mm
C9
1 µF ± 10%, X7R, 25 V
12063C105KAT2A
AVX
1206, 3.2 mm x 1.6 mm
DC/DC CONVERTER
C4
100 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
Kemet
0603, 1.6 mm x 0.8 mm
C3
1 nF ± 10%, X7R, 50 V
C0603C102K5RACTU
Kemet
0603, 1.6 mm x 0.8 mm
C2
1 µF ± 10%, X7R, 25 V
CGA3E1X7R1E105K080AC
TDK
0603, 1.6 mm x 0.8 mm
C1
100 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
Kemet
0603, 1.6 mm x 0.8 mm
C5
100 nF ± 5%, NP0, 50 V
C3216NP01H104J160AA
TDK
1206, 3.2 mm x 1.6 mm
C6
1 nF ± 10%, X7R, 50 V
12065C102KAT2A
AVX
1206, 3.2 mm x 1.6 mm
HLDO
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10 Layout
10.1 Layout Guidelines
Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors. The same
component reference designators are used as in the Power Supply Recommendations section. Decoupling
capacitors are placed as close as possible to the AMC3330 supply pins. For best performance, place the sense
resistor close to the INP and INN inputs of the AMC3330 and keep the layout of both connections symmetrical.
This layout is used on the AMC3330 EVM and supports CISPR-11 compliant electromagnetic radiation levels.
10.2 Layout Example
C4
C3
DIAG
To MCU I/O (optional)
R1
C1
RL11
C2
Clearance area, to be
kept free of any
conductive materials.
VDD
C9
C8
C6
C5
C10
RL1SNS
AMC3330
INP
OUTP
OUTN
3.3-V or 5-V supply
To ADC / MCU
To ADC / MCU
INN
RL12
GND
Top Metal
Inner or Bottom Layer Metal
Via
Figure 10-1. Recommended Layout of the AMC3330
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Texas Instruments, Isolation Glossary
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, AMC3301 Precision, ±250-mV Input, Reinforced Isolated Amplifier With Integrated
DC/DC Converter data sheet
• Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
• Texas Instruments, 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
• Texas Instruments, 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power reference guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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4-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AMC3330DWE
ACTIVE
SOIC
DWE
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC3330
AMC3330DWER
ACTIVE
SOIC
DWE
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC3330
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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