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AMC7832
SLAS836 – MARCH 2014
AMC7832 12-Bit Analog Monitor and Control Solution
with Multi-Channel ADC, Bipolar DACs, Temperature Sensor and GPIO Ports
1 Features
3 Description
•
The AMC7832 is a highly integrated, low-power,
analog monitoring and control solution that includes a
17-channel, 12-bit analog-to-digital converter (ADC)
with programmable alarms, twelve 12-bit digital-toanalog converters (DACs) with output ranges of either
0 to +5-V, 0 to +10-V or -10 to 0-V, eight GPIOs,
internal reference and a local temperature sensor
channel. The AMC7832 high level of integration
significantly reduces component count and simplifies
closed-loop system designs.
Twelve Monotonic 12-Bit DACs
– Selectable Ranges: 0 to +5-V, 0 to +10-V and
-10 to 0-V
– High Current Drive Capability: up to ±15-mA
– Selectable Clamp Voltage
One 12-Bit SAR ADC
– 17 External Analog Inputs
– 12 Bipolar Inputs: -12.5-V to +12.5-V
Range
– 5 High Precision Inputs: 0 to +5-V Range
– Programmable Out-of-Range Alarms
Internal +2.5-V Reference
Internal Temperature Sensor
– -40°C to +125°C Operation
– ±2.5°C Accuracy
Eight General Purpose I/O Ports (GPIOs)
Low Power SPI Compatible Serial Interface
– 4-Wire Mode, +1.8-V to +5.5-V Operation
Operating Temperature Range: -40°C to +125°C
Available in 64-Terminal HTQFP PowerPAD
Package
•
•
•
•
•
•
•
2 Applications
•
Communications Infrastructure:
– Cellular Base Stations
– Microwave Backhaul
– Optical Networks
General Purpose Monitor & Control
Data Acquisition Systems
•
•
The AMC7832 is ideal for multichannel applications
where board space, size, and low power are critical.
The AMC7832’s low power, high-integration and wide
operating temperature range make it an ideal all-inone, low-cost, bias control circuit for the power
amplifiers (PA) found in multi-channel RF
communication systems. The flexible DAC output
ranges allow the device to be used as a biasing
solution for a large variety of transistor technologies
such as LDMOS, GaAs and GaN. The AMC7832
feature set is similarly beneficial in general purpose
monitor and control systems.
For applications that require a different channel
count, additional features, or converter resolutions,
Texas Instruments offers a complete family of Analog
Monitor and Control (AMC) products. Visit
http://www.ti.com/amc for more information.
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
AMC7832IPAP
HTQFP (64)
10mm x 10mm
Functional Diagram
12 BIPOLAR
ANALOG INPUTS
4 Power Amp Biasing Diagram
AMC7832
VDD
Voltage
Sense
5 UNIPOLAR
ANALOG INPUTS
RSENSE
ADC
MUX
ALARM
Current
Sense
2.5V REFERENCE
MUX
SPI
µC
AMC7832
ADC
DAC-0
12 BIPOLAR
ANALOG OUTPUTS
1
TEMP
SENSOR
Temp
Sensor
RF Out
VBIAS
RF In
POWER AMPLIFIER FET
DAC-11
SPI
DAC
SPI INTERFACE
Temp
Sense
GPIO CONTROL
8 GPIOs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC7832
SLAS836 – MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Power Amp Biasing Diagram................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
8.2
8.3
8.4
8.5
1
1
1
1
2
3
6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Programming...........................................................
Register Map...........................................................
23
24
25
39
41
Applications and Implementation ...................... 54
9.1 Application Information............................................ 54
9.2 Typical Application .................................................. 54
Absolute Maximum Ratings ...................................... 6
Handling Ratings....................................................... 6
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Timing Requirements - Serial Interface .................. 13
Typical Characteristics: DAC .................................. 15
Typical Characteristics: ADC .................................. 20
Typical Characteristics: Reference ......................... 22
Typical Characteristics: Temperature Sensor....... 22
10 Power Supply Recommendations ..................... 59
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 60
12 Device and Documentation Support ................. 64
12.1 Trademarks ........................................................... 64
12.2 Electrostatic Discharge Caution ............................ 64
12.3 Glossary ................................................................ 64
13 Mechanical, Packaging, and Orderable
Information ........................................................... 64
Detailed Description ............................................ 23
5 Revision History
2
DATE
REVISION
NOTES
March
*
Initial release.
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6 Terminal Configuration and Functions
VRANGE_C
DAC_C1
AVSS_C
DAC_C0
ADC_0
ADC_1
ADC_2
55
54
53
52
51
50
49
REF_OUT2
56
AVCC_CD
57
DAC_D2
58
AGND3
59
DAC_D3
60
VRANGE_D
61
AVSS_D
62
DAC_D4
63
64
DAC_D5
HTQFP- 64
PAP Package
(Top View)
DGND
1
48
ADC_3
DVDD
2
47
ADC_4
IOVDD
3
46
ADC_5
RESET
4
45
LV_ADC12
SDO
5
44
LV_ADC13
SDI
6
43
LV_ADC14
SCLK
7
42
LV_ADC15
CS
8
41
LV_ADC16
AMC7832
AGND2
REF_CMP
32
33
31
16
AVDD1
GPIO7
30
AVDD2
REF_OUT1
34
29
15
DAC_B6
GPIO6
28
ADC_11
AVSS_B
35
27
14
DAC_B7
GPIO5
26
ADC_10
VRANGE_B
36
25
13
AVCC_AB
GPIO4
24
ADC_9
DAC_A8
37
23
12
AGND1
GPIO3/
DAV
22
ADC_8
DAC_A9
38
21
11
VRANGE_A
GPIO2/
ADCTRIG
20
ADC_7
AVSS_A
39
19
10
DAC_A10
GPIO1/
ALARMOUT
18
ADC_6
DAC_A11
40
17
9
AVEE
GPIO0/
ALARMIN
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Terminal Functions
TERMINAL
4
DESCRIPTION
NUMBER
NAME
1
DGND
Digital ground. Ground reference point for all digital circuitry on the device. Ideally, AGND and DGND should be at the
same potential (GND) and must not differ by more than ±0.3-V.
2
DVDD
Digital supply voltage. (+4.5-V to +5.5-V). Must be the same value as AVDD.
3
IOVDD
IO supply voltage. (+1.8-V to +5.5-V). Sets the IO operating voltage and threshold levels. Must not exceed DVDD.
4
RESET
Reset input, active low. Logic low on this terminal causes the device to perform a hardware reset.
5
SDO
Serial interface data output. The SDO terminal is in high impedance when CS is high. Data is clocked out of the input
shift register on each falling edge of SCLK.
6
SDI
Serial interface data input. Data is clocked into the input shift register on each rising edge of SCLK.
7
SCLK
8
CS
Active low serial data enable. This input is the frame synchronization signal for the serial data. When this signal goes
low, it enables the input shift register.
9
GPIO0/ALARMIN
General purpose digital I/O 0 (default). This terminal is a bidirectional open-drain, digital input/output with internal 48kΩ pull-up resistor to IOVDD. Alternatively the terminal can be set to operate as ALARMIN, an alarm control signal,
digital input, active low.
10
GPIO1/ ALARMOUT
General purpose digital I/O 1 (default). This terminal is a bidirectional open-drain, digital input/output with internal 48kΩ pull-up resistor to IOVDD. Alternatively the terminal can be set to operate as ALARMOUT, a global alarm. Open
drain output. This terminal goes low (active) when an alarm event is detected.
11
GPIO2/ADCTRIG
General purpose digital I/O 2 (default). This terminal is a bidirectional open-drain, digital input/output with internal 48kΩ pull-up resistor to IOVDD. Alternatively the terminal can be set to operate as ADCTRIG, an external conversion
trigger, active low. The falling edge starts the sampling and conversion of the ADC.
12
GPIO3/DAV
General purpose digital I/O 3 (default). This terminal is a bidirectional open-drain, digital input/output with internal 48kΩ pull-up resistor to IOVDD. Alternatively the terminal can be set to operate as DAV, Data available indicator, active
low output. In direct mode, the DAV terminal goes low (active) when the conversion ends. In auto mode, a 1µs pulse
(active low) appears on this terminal when a conversion cycle finishes. DAV stays high when deactivated.
13
GPIO-4
14
GPIO-5
15
GPIO-6
16
GPIO-7
17
AVEE
18,19, 22, 24
DAC_A11,
DAC_A10,
DAC_A9,
DAC_A8
20
AVSSA
Negative analog supply for DAC group A. Sets the power-on-reset and clamp voltage values. Typically tied to AVEE
when the DAC range for group A is set to -10 to 0-V or AGND for the positive output ranges.
21
VRANGEA
This terminal determines the DAC range for DAC group A. If tied to AGND the DAC range is 0 to +5-V or 0 to+10-V.
Otherwise if tied to +2.5-V (can be tied to REF_OUT terminals) the DAC range is -10 to 0-V.
23
AGND1
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1, AGND2 and
AGND3 to the same potential, AGND.
25
AVCC_AB
Positive analog power for DAC groups A and B. Must be tied to AVCC_CD.
26
VRANGEB
This terminal determines the DAC range for DAC group B. If tied to AGND the DAC range is 0 to +5-V or 0 to +10-V.
Otherwise if tied to +2.5-V (can be tied to REF_OUT terminals) the DAC range is -10 to 0-V.
27, 29
DAC_B7,
DAC_B6
DAC group B. These channels share the same range and clamp voltage.
28
AVSSB
30
REF_OUT1
31
AVDD1
32
REF_CMP
33
AGND2
Serial interface clock.
General purpose digital I/O. This terminal is a bidirectional open-drain, digital input/output with internal 48-kΩ pull-up
resistor to IOVDD.
Lowest potential in the system. Typically tied to -12-V but if all DACs are set in a positive output range it should be
connected to AGND.
DAC group A. These channels share the same range and clamp voltage.
Negative analog supply for DAC group B. Sets the power-on-reset and clamp voltage values. Typically tied to AVEE
when the DAC range for group B is set to -10 to 0-V or AGND for the positive output ranges.
Reference output 1. Can be used to drive the VRANGE inputs.
Analog supply voltage. (+4.5-V to +5.5-V)
Internal reference compensation capacitor connection (connect 4.7-μF capacitor between this terminal and AGND2).
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1, AGND2 and
AGND3 to the same potential, AGND.
34
AVDD2
35-38
ADC_11,
ADC_10,
ADC_9,
ADC_8
Analog supply voltage. (+4.5-V to +5.5-V)
Bipolar analog inputs. Typically used to monitor the DAC_A8 to DAC_A11 outputs. The input range of these channels
is -12.5-V to +12.5-V.
39-40
ADC_7,
ADC_6
Bipolar analog inputs. Typically used to monitor the DAC_B6 to DAC_B7 outputs. The input range of these channels
is -12.5-V to +12.5-V.
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Terminal Functions (continued)
TERMINAL
DESCRIPTION
NUMBER
NAME
41-45
LV_ADC16 to
LV_ADC12
46-49
ADC_5,
ADC_4,
ADC_3,
ADC_2
Bipolar analog inputs. Typically used to monitor the DAC_D2 to DAC_D5 outputs. The input range of these channels
is -12.5-V to +12.5-V.
50-51
ADC_1,
ADC_0
Bipolar analog inputs. Typically used to monitor the DAC_C0 to DAC_C1 outputs. The input range of these channels
is -12.5-V to +12.5-V.
52,54
DAC_C1,
DAC_C0
53
AVSSC
Negative analog supply for DAC group C. Sets the power-on-reset and clamp voltage values. Typically tied to AVEE
when the DAC range for group C is set to -10 to 0-V or AGND for the positive output ranges.
55
VRANGEC
This terminal determines the DAC range for DAC group C. If tied to AGND the DAC range is 0 to +5-V or 0 to +10-V.
Otherwise if tied to +2.5-V (can be tied to REF_OUT terminals) the DAC range is -10 to 0-V.
56
REF_OUT2
Reference output 2. Can be used to drive the VRANGE inputs.
57
AVCC_CD
Positive analog power for DAC groups C and D. Must be tied to AVCC_AB.
58, 60, 63, 64
DAC_D5,
DAC_D4,
DAC_D3,
DAC_D2
DAC group D. These channels share the same range and clamp voltage.
59
AGND3
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1, AGND2 and
AGND3 to the same potential, AGND.
61
VRANGED
This terminal determines the DAC range for DAC group D. If tied to AGND the DAC range is 0 to 5-V or 0 to 10-V.
Otherwise if tied to +2.5-V (can be tied to REF_OUT terminals) the DAC range is -10 to 0-V.
62
AVSSD
—
THERMAL PAD
Unipolar analog inputs. These channels are used for general monitoring and their input range is 0 to 2 x VREF.
DAC group C. These channels share the same range and clamp voltage.
Negative analog supply for DAC group D. Sets the power-on-reset and clamp voltage values. Typically tied to AVEE
when the DAC range for group D is set to -10 to 0-V or AGND for the positive output ranges.
The thermal pad is located on the package underside. Should be tied to AVEE or left unconnected.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
MIN
MAX
UNIT
AVDD to GND
-0.3
+6
V
DVDD to GND
-0.3
+6
V
IOVDD to GND
-0.3
DVDD
V
AVCC to GND
-0.3
+18
V
AVEE to GND
-13
+0.3
V
AVSSA,B,C,D to AVEE
-0.3
+13
V
AVCC to AVSSA,B,C,D
-0.3
+26
V
AVCC to AVEE
-0.3
+26
V
DGND to AGND
-0.3
+0.3
V
ADC_[0-11] analog input voltage to GND
–13
+13
V
ADC_[0-11] analog input current
-10
+10
mA
LV_ADC[12-16] analog input voltage to GND
-0.3
AVDD + 0.3
V
LV_ADC[12-16] analog input current
-10
+10
mA
AVSS - 0.3
AVCC + 0.3
V
REF_CMP to GND
-0.3
AVDD + 0.3
V
REF_OUT[1-2] to GND
-0.3
AVDD + 0.3
V
VRANGE[A-D] to GND
-0.3
AVDD + 0.3
V
CS, SCLK, SDI and RESET to GND
-0.3
IOVDD + 0.3
V
SDO to GND
-0.3
IOVDD + 0.3
V
GPIO[0-7] to GND
-0.3
IOVDD + 0.3
V
5
mA
DAC outputs to GND
Terminal voltage/
Current range
GPIO[0-7] sinking current
Operating temperature range
-40
+125
°C
Junction temperature range (TJ max)
-40
+150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
PARAMETER
Tstg
VESD (1)
(1)
(2)
(3)
6
DEFINITION
MIN
MAX
-40
+150
°C
Human body model (HBM) ESD stress voltage (2)
2.0
kV
Charged device model (CDM) ESD stress voltage (3)
750
V
Storage temperature range
UNIT
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MIN
NOM
MAX
UNIT
AVDD
4.5
5
5.5
V
DVDD (DVDD must be equal to AVDD)
4.5
5
5.5
V
IOVDD (IOVDD must be equal or less than DVDD)
1.8
5.5
V
AVCC
4.5
12
12.5
V
AVEE
–12.5
–12
0
V
AVSSA,B,C,D
AVEE
0
V
Specified temperature range
–40
25
105
°C
Operating temperature range
–40
25
125
°C
7.4 Thermal Information
THERMAL METRIC (1)
AMC7832
PAP (64 TERMINALS)
θJA
Junction-to-ambient thermal resistance
26.5
θJCtop
Junction-to-case (top) thermal resistance
7.9
θJB
Junction-to-board thermal resistance
9.9
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
9.8
θJCbot
Junction-to-case (bottom) thermal resistance
0.3
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, IOVDD = +1.8 to +5.5-V, AGND =
DGND = 0-V, AVSSA,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range
= 0 to 10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC SPECIFICATIONS
DAC DC ACCURACY
Resolution
INL
12
Relative accuracy
DNL
TUE
Differential nonlinearity
Total unadjusted error
(1)
Offset error
Zero-code error
Gain error
(1)
Bits
Measured by line passing through codes
020h and FFFh.
0 to +10-V and -10 to 0-V ranges
±1
Measured by line passing through codes
040h and FFFh.
0 to +5-V range
±1.5
LSB
Specified monotonic.
Measured by line passing through codes
020h and FFFh.
0 to +10-V and -10 to 0-V ranges.
Measured by line passing through codes
040h and FFFh.
0 to +5-V range
±0.3
±1
LSB
TA = 25°C
0 to +10-V range and -10 to 0-V ranges
±20
mV
TA = 25°C
0 to +5-V range
±10
mV
TA = 25°C, Measured by line passing
through codes 020h and FFFh,
0 to +10-V range
±5
mV
TA = 25°C, Measured by line passing
through codes 040h and FFFh,
0 to +5-V range
±5
mV
TA = 25°C, Code 000h, -10 to 0-V range
±20
mV
TA = 25°C, Measured by line passing
through codes 020h and FFFh,
0 to +10-V and -10 to 0-V ranges
±0.2
%FSR
TA = 25°C, Measured by line passing
through codes 040h and FFFh,
0 to +5-V range
±0.2
%FSR
Offset temperature coefficient
0 to +10-V and 0 to +5-V ranges
±1
ppm/°C
Zero-code temperature coefficient
-10 to 0-V range
±2
ppm/°C
Gain temperature coefficient
All output ranges
±1
ppm/°C
DAC OUTPUT CHARACTERISTICS
Full-scale output voltage range (2)
Output voltage settling time
(1)
(2)
8
VRANGEn terminal set to AGND
DAC-5VRANGEn bit set to 0
0
10
V
VRANGEn terminal set to AGND
DAC-5VRANGEn bit set to 1
0
5
V
VRANGEn terminal set to +2.5V
DAC-5VRANGEn bit set to 0
–10
0
V
Transition: Code 400h to C00h to within
½ LSB, RL = 2kΩ, CL = 200pF,
0 to +10-V and -10 to 0-V ranges
10
µs
Transition: Code 400h to C00h to within
½ LSB, RL = 2kΩ, CL = 200pF,
0 to +5-V range
8
µs
Internal reference contribution not included.
The output voltage cannot be greater than AVCC or lower than AVSS. See the DAC Output Range Selection section for more details.
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Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, IOVDD = +1.8 to +5.5-V, AGND =
DGND = 0-V, AVSSA,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range
= 0 to 10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Slew rate
Transition: Code 400h to C00h to within
½ LSB, RL = 2kΩ, CL = 200pF,
all DAC output ranges
Short-circuit current
Full-scale current shorted to AVSS or
AVCC
MIN
TYP
MAX
UNIT
1.25
V/µs
45
mA
Source and/or sink with 1V headroom
from AVCC/AVSS, voltage drop < 25mV (3)
±15
mA
Source and/or sink with 300mV
headroom from AVCC/AVSS, voltage drop
< 25mV
±10
mA
Source with 100mV headroom from
AVCC (4)
0
mA
Maximum capacitive load (5)
RL = ∞
0
DC output impedance
Code set to 800h, ±15mA
Power-on overshoot
AVEE = AVSSA,B,C,D = GND,
AVCC = 0 to +12V, 2ms ramp
Glitch energy
Transition: Code 7FFh to 800h; 800h to
7FFh
Load current
Output noise
10
nF
1
Ω
50
mV
1
nV-s
TA = 25°C, 1kHz, code 800h, includes
internal reference noise
520
nV/√Hz
TA = 25°C, integrated noise from 0.1Hz
to 10Hz, code 800h, includes internal
reference noise
20
µVPP
DAC output range: 0 to +10-V
0
V
DAC output range: 0 to +5-V
0
V
AVSS
+2
V
CLAMP OUTPUTS
Clamp output voltage (6)
DAC output range: -10 to 0-V,
AVSS = -12-V
(3)
(4)
(5)
(6)
If all channels are loaded with 15mA simultaneously care must be taken to ensure the thermal conditions for the device are not
exceeded.
Not tested during production. Specified by design.
To be sampled during initial release to ensure compliance; not subject to production testing.
No DAC load to AVSS.
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Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, IOVDD = +1.8 to +5.5-V, AGND =
DGND = 0-V, AVSSA,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range
= 0 to 10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.5
±1
LSB
±0.75
±1.5
LSB
±0.5
±1
LSB
ADC AND TEMPERATURE SENSOR SPECIFICATIONS
Resolution
INL
Integral nonlinearity
DNL
Differential nonlinearity
12
Unipolar input channels
Bipolar input channels
Specified monotonic. All input channels
Bits
UNIPOLAR ANALOG INPUTS: LV_ADC12 to LV_ADC16
Absolute input voltage range
Full scale input range
0
Input capacitance
VREF measured at REF_CMP terminal
DC input leakage current
Unselected ADC input
2 × VREF
34
Offset error
±2
Offset error match
±1
Gain error match
V
±10
µA
±5
LSB
LSB
±5
±1
Single unipolar input, temperature sensor
disabled
V
pF
±2.5
Gain error (7)
Update time
AVDD +
0.2
GND – 0.2
LSB
LSB
11.5
µs
BIPOLAR ANALOG INPUTS: ADC_0 to ADC_11
Absolute input voltage range
Full scale input range
–13
+13
-12.5
12.5
Input resistance
175
V
V
kΩ
Offset error
±5
±10
LSB
Gain error (7)
±5
±10
LSB
Update time
Single bipolar input, temperature sensor
disabled
34.5
µs
TEMPERATURE SENSOR
Operating range
-40
±1.25
125
°C
±2.5
°C
Accuracy
TA = -40°C to 125°C, AVDD = +5-V
Resolution
LSB size
0.25
°C
Update time
All ADC input channels disabled
256
µs
All 17 ADC inputs enabled, temperature
sensor disabled
471.5
µs
All 17 ADC inputs and temperature
sensor enabled
727.5
µs
AUTOCYCLE UPDATE TIME
Autocycle update time
(7)
10
Internal reference contribution not included.
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Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, IOVDD = +1.8 to +5.5-V, AGND =
DGND = 0-V, AVSSA,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range
= 0 to 10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.4925
2.5
2.5075
UNIT
INTERNAL REFERENCE SPECIFICATIONS
INTERNAL REFERENCE (Internal reference not accessable)
Initial accuracy
TA = 25°C
Reference temp. coefficient (8)
12
V
35 ppm/°C
REF_OUT[1-2] BUFFERS (9)
Reference buffer offset
TA = 25°C
Capacitive load stability
±2.5
mV
100
pF
±5
mV
INTERNAL ADC REFERENCE BUFFER
Reference buffer offset
TA = 25°C
GENERAL SPECIFICATIONS
DIGITAL LOGIC: GPIO
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Low-level output voltage
Input impedance
IOVDD =+1.8 to +5.5-V
0.7×IOVDD
V
IOVDD = +1.8-V
0.45
V
0.3×IOVDD
V
IOVDD = +1.8-V, Iload = -2-mA
0.4
V
IOVDD= +5.5-V, Iload = -5-mA
0.4
IOVDD = +2.7 to +5.5-V
To IOVDD
48
V
kΩ
DIGITAL LOGIC: All Except GPIO
VIH
High-level input voltage
IOVDD = +1.8 to +5.5-V
0.7×IOVDD
V
IOVDD = +1.8-V
VIL
Low-level input voltage
VOH
High-level output voltage
Iload = -1-mA
VOL
Low-level output voltage
Iload = +1-mA
IOVDD = +2.7 to +5.5-V
0.45
V
0.3×IOVDD
V
IOVDD-0.4
V
High-impedance leakage
High-impedance output capacitance
0.4
V
±5
µA
10
pF
TIMING REQUIREMENTS
Reset delay
Delay to normal operation from reset
100
CL = 10nF
100
Power-down recovery time
Clamp shutdown delay
250
µs
70
µs
µs
Convert pulse width
20
ns
Reset pulse width
20
ns
POWER-SUPPLY REQUIREMENTS
IAVDD
AVDD supply current
10
mA
IAVCC
AVCC supply current
10
mA
IAVSS
AVSS supply current
IDVDD
DVDD supply current
IIOVDD
IOVDD supply current
No DAC load, all DACs at 800h code and
ADC at the fastest auto conversion rate
Power consumption
(8)
(9)
–10
mA
3
mA
15
µA
160
mW
Not tested during production. Specified by design and characterization.
Intended to drive the VRANGEA,B,C,D inputs only. An external buffer amplifier with high impedance input is required to drive any
additional external load.
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Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, IOVDD = +1.8 to +5.5-V, AGND =
DGND = 0-V, AVSSA,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range
= 0 to 10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IAVDD
AVDD supply current
2
mA
IAVCC
AVCC supply current
2
mA
IAVSS
AVSS supply current
IDVDD
DVDD supply current
IIOVDD
IOVDD supply current
Power down mode
mA
2
12
Power consumption
12
–5.5
55
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mA
µA
mW
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7.6 Timing Requirements - Serial Interface (1) (2)
AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, AGND = DGND = AVSSA,B,C,D = 0-V, DAC output range = 0 to
+10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15
MHz
IOVDD = +1.8-V to +2.7-V
fSCLK
SCLK frequency
tP
SCLK period
tPH
66.67
ns
SCLK pulse width high
27
ns
tPL
SCLK pulse width low
27
ns
tSU
SDI setup
10
ns
tH
SDI hold
10
tODZ
SDO driven to tri-state
0
15
ns
tOZD
SDO tri-state to driven
0
20
ns
tOD
SDO output delay
0
20
ns
tCSS
CS setup
5
ns
tCSH
CS hold
20
ns
tIAG
Inter-access gap
10
ns
ns
IOVDD = +2.7-V to +5.5-V
fSCLK
SCLK frequency
tP
SCLK period
tPH
SCLK pulse width high
tPL
20
MHz
50
ns
22.5
ns
SCLK pulse width low
20
ns
tSU
SDI setup
10
ns
tH
SDI hold
10
tODZ
SDO driven to tri-state
0
9
ns
tOZD
SDO tri-state to driven
0
12
ns
tOD
SDO output delay
0
15
ns
tCSS
CS setup
5
ns
tCSH
CS hold
20
ns
tIAG
Inter-access gap
10
ns
(1)
(2)
ns
Specified by design and characterization. Not tested during production.
SDO loaded with 10-pF load capacitance for SDO timing specifications.
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tiAG
tCSS
tCSH
CS
tP
tPL
SCLK
tPH
SDI
Bit 23
Bit 1
Bit 0
tH
tSU
Figure 1. Serial Interface Write Timing Diagram
tODZ
tiAG
tCSS
tCSH
CS
tP
tPL
SCLK
tPH
SDI
Bit 23
tSU
Bit 8
tH
SDO
Bit 7
tOZD
Bit 0
tOD
Figure 2. Serial Interface Read Timing Diagram
14
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7.7 Typical Characteristics: DAC
1.0
A11
A8
C0
D3
0.8
0.6
A10
B7
C1
D4
1.0
A9
B6
D2
D5
0.6
INL (LSB)
0.2
0.0
±0.2
0.0
±0.2
±0.4
±0.6
±0.6
±0.8
±0.8
±1.0
0
512
1024
1536
2048
2560
3072
3584
0
4096
Code
512
1024
1536
2048
2560
3072
3584
4096
Code
C001
C001
T = 25°C, 0V to 10V range
T = 25°C, 0V to 10V range
Figure 4. Linearity Error vs Code
Figure 3. Differential Linearity Error vs Code
1.0
A11
A8
C0
D3
0.8
0.6
A10
B7
C1
D4
1.0
A9
B6
D2
D5
C0
A9
B6
D3
0.8
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
A9
B6
D2
D5
0.2
±0.4
±1.0
0.0
±0.2
A11
A8
C1
D4
A10
B7
D2
D5
0.0
±0.2
±0.4
±0.4
±0.6
±0.6
±0.8
±0.8
±1.0
±1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Code
0
512
1024
1536
2048
2560
3072
3584
4096
Code
C001
T = 25°C, -10V to 0V range
C001
T = 25°C, -10V to 0V range
Figure 5. Differential Linearity Error vs Code
1.0
A11
A8
C0
D3
0.8
0.6
A10
B7
C1
D4
Figure 6. Linearity Error vs Code
1.0
A9
B6
D2
D5
A11
A8
C0
D3
0.8
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
A10
B7
C1
D4
0.4
0.4
DNL (LSB)
A11
A8
C0
D3
0.8
0.0
±0.2
A9
B6
D2
D5
0.0
±0.2
±0.4
±0.4
±0.6
±0.6
±0.8
±0.8
±1.0
A10
B7
C1
D4
±1.0
0
512
1024
1536
2048
2560
3072
3584
Code
4096
0
512
1024
T = 25°C, 0V to 5V range
1536
2048
2560
3072
3584
Code
C001
4096
C001
T = 25°C, 0V to 5V range
Figure 7. Differential Linearity Error vs Code
Figure 8. Linearity Error vs Code
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1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
Typical Characteristics: DAC (continued)
0.2
0.0
±0.2
±0.4
±0.6
MAX INL
±0.8
MIN DNL
±1.0
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
C001
0V to 10V range
C001
0V to 10V range
Figure 9. Linearity Error vs Temperature
Figure 10. Differential Linearity Error vs Temperature
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
MAX DNL
±0.8
MIN INL
±1.0
0.2
0.0
±0.2
±0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.6
MAX INL
±0.8
MAX DNL
±0.8
MIN INL
±1.0
MIN DNL
±1.0
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
C001
-10V to 0V range
C001
-10V to 0V range
Figure 11. Linearity Error vs Temperature
Figure 12. Differential Linearity Error vs Temperature
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.0
±0.2
±0.4
±0.6
0.2
0.0
±0.2
±0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.6
MAX INL
±0.8
MAX DNL
±0.8
MIN INL
±1.0
MIN DNL
±1.0
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
±40 ±25 ±10
5
20
35
50
TA (C)
C001
0V to 5V range
65
80
95
110 125
C001
0V to 5V range
Figure 13. Linearity Error vs Temperature
16
0.2
Figure 14. Differential Linearity Error vs Temperature
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5
20
4
15
3
Zero Scale Error (mV)
DAC Offset Error (mV)
Typical Characteristics: DAC (continued)
2
1
0
±1
±2
±3
0V to 10V Range
±4
10
5
0
±5
±10
±15
0V to 5V Range
±5
±20
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
C001
C001
-10V to 0V range
Figure 15. Offset Error vs Temperature
Figure 16. Zero-Scale Error vs Temperature
10
0.20
9
0.15
Output Voltage (V)
Gain Error (%FSR)
8
0.10
0.05
0.00
±0.05
±0.10
±0.15
±0.20
±40 ±25 ±10
5
20
35
50
65
7
6
5
4
3
0V to 10V Range
2
0V to 5V Range
-10V to 0V Range
1
80
95
TA (C)
0
±50
110 125
±40
±30
±20
±10
0
10
20
30
40
ILOAD (mA)
C001
50
C001
T = 25°C, Input Code 0x800, 0 to 10V range
Figure 18. Output Voltage vs Load Current
0.25
9.95
0.20
Output Voltage (V)
Output Voltage (V)
Figure 17. Gain Error vs Temperature
10.00
9.90
9.85
9.80
0.15
0.10
0.05
9.75
0.00
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
ILOAD (mA)
±15 ±14 ±13 ±12 ±11 ±10 ±9 ±8 ±7 ±6 ±5 ±4 ±3 ±2 ±1 0
ILOAD (mA)
C002
T = 25°C, AVCC = 10V, AVEE = 0V, Input Code 0xFFF, 0 to 10V
range
C002
T = 25°C, AVCC = 10V, AVEE = 0V, Input Code 0x000, 0 to 10V
range
Figure 19. Source Current
Figure 20. Sink Current
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Typical Characteristics: DAC (continued)
15
15
10nF, Rising Edge
10nF, Falling Edge
10
200pF, Rising Edge
5
0
±5
DAC Output Error (LSB)
DAC Output Error (LSB)
10
±10
200pF, Falling Edge
5
0
±5
±10
±15
±15
0
5
10
15
20
25
Time (µs)
0
5
10
T = 25°C, Code 0x400 to 0xC00 to within 1/2 LSB
15
20
25
Time (µs)
C001
C001
T = 25°C, Code 0xC00 to 0x400 to within 1/2 LSB
Figure 21. Settling Time vs Load Capacitance
Figure 22. Settling Time vs Load Capacitance
5000
20
15
10
VNOISE (µV)
1RLVH Q9¥+]
4000
3000
2000
5
0
±5
±10
1000
±15
0
±20
10
100
1000
10000
100000
1000000
Frequency (Hz)
0
2
T = 25°C, Input Code 0x800
10
10.0
10
5
5.0
0
0.0
±5
±5.0
AVCC
AVSS
DVDD/AVDD
DAC output
±10
±15
1.5
2
Time (ms)
14
16
18
20
C001
2.5
3
±5
±10
±15.0
±15
±0.5
3.5
0.0
0.5
1.0
1.5
Time (ms)
C002
Figure 25. Power-On Overshoot Single Supply
AVCC
AVSS
DVDD/AVDD
DAC output
0
±10.0
T = 25°C, AVSS = AVEE = AGND, AVCC 0 to 12V, 2 ms ramp
18
12
5
Voltage (V)
DAC Output (mV)
Supply Voltage (V)
15
1
10
Figure 24. 0.1Hz to 10Hz Noise
15.0
0.5
8
T = 25°C, Input Code 0x800
Figure 23. Noise Voltage vs Frequency
0
6
Time (s)
15
-0.5
4
C001
2.0
2.5
3.0
3.5
C002
T = 25°C, AVSS = AVEE = -12V, AVCC 0 to 12V, 2 ms ramp
Figure 26. Power-On Overshoot Dual Supply
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15.0
DAC Output Small Signal
10.0
DAC Output (V)
0
5.0
0.0
±5
±5.0
±10
±10.0
DAC Output (V)
DAC Output
DAC Output Small Signal (mV)
5
±2
0
2
4
6
8
10
12
14
0
2.5
±5
0.0
±2.5
DAC Output
DAC Output Small Signal
±15
16
Time (µs)
5.0
±10
±15.0
±15
5
DAC Output Small Signal (mV)
Typical Characteristics: DAC (continued)
±5.0
±5
0
5
10
15
20
25
30
35
Time (µs)
C001
T = 25°C, -10V to 0V range, DAC Code 0xFFF, No Load
C001
T = 25°C, -10V to 0V range, DAC Code 0xFFF, No Load
Figure 27. Clamp Response
Figure 28. Clamp Recovery
15
AVCC
AVSS
DVDD/AVDD
DAC Output
10
Voltage (V)
5
0
±5
±10
±15
0.00
0.25
0.50
0.75
1.00
1.25
1.50
Time (ms)
C001
T = 25°C, -10V to 0V range, DAC Code 0xFFF, No Load
Figure 29. Supply Collapse DAC Response
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1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
INL (LSB)
INL (LSB)
7.8 Typical Characteristics: ADC
0.0
±0.2
0.0
±0.2
±0.4
±0.4
±0.6
±0.6
±0.8
±0.8
±1.0
±1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Code
0
2048
2560
3072
3584
4096
C005
T = 25°C, Unipolar Input
Figure 31. Differential Linearity Error vs Code
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
INL (LSB)
INL (LSB)
1536
Code
Figure 30. Linearity Error vs Code
0.0
±0.2
0.0
±0.2
±0.4
±0.4
±0.6
±0.6
±0.8
±0.8
±1.0
±1.0
0
512
1024
1536
2048
2560
3072
3584
4096
Code
0
512
1024
1536
2048
2560
3072
3584
4096
Code
C005
T = 25°C, Bipolar Input
C005
T = 25°C, Bipolar Input
Figure 32. Linearity Error vs Code
Figure 33. Differential Linearity Error vs Code
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
1024
C005
T = 25°C, Unipolar Input
0.2
0.0
±0.2
±0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.6
MAX INL
±0.8
MAX DNL
±0.8
MIN INL
±1.0
MIN DNL
±1.0
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
±40 ±25 ±10
5
20
35
50
TA (C)
C001
Unipolar input
65
80
95
110 125
C001
Unipolar input
Figure 34. Linearity Error vs Temperature
20
512
Figure 35. Differential Linearity Error vs Temperature
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1.5
1.0
1.2
0.8
0.9
0.6
0.6
0.4
DNL (LSB)
INL (LSB)
Typical Characteristics: ADC (continued)
0.3
0.0
±0.3
±0.6
±0.6
MAX INL
±1.2
MIN INL
MIN DNL
±1.0
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
C001
Bipolar input
C001
Bipolar input
Figure 36. Linearity Error vs Temperature
Figure 37. Differential Linearity Error vs Temperature
5.0
5.0
Bipolar
Bipolar
4.0
Unipolar
Unipolar
3.0
2.0
Gain Error (LSB)
Offset Error (LSB)
MAX DNL
±0.8
±1.5
3.0
0.0
±0.2
±0.4
±0.9
4.0
0.2
1.0
0.0
±1.0
±2.0
2.0
1.0
0.0
±1.0
±2.0
±3.0
±3.0
±4.0
±4.0
±5.0
±5.0
±40 ±25 ±10
5
20
35
50
65
80
95
TA (C)
110 125
±40 ±25 ±10
C001
Figure 38. Offset vs Temperature
5
20
35
50
65
80
95
110 125
TA (C)
Figure 39. Gain Error vs Temperature
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7.9 Typical Characteristics: Reference
2.505
2.504
Output Voltage (V)
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
±40 ±25 ±10
5
20
35
50
65
80
95
110 125
TA (C)
C001
10 units, REF_OUT1
Figure 40. Output Voltage vs Temperature
7.10 Typical Characteristics: Temperature Sensor
2.5
Local Temperature Error (C)
2.0
1.5
1.0
0.5
0.0
±0.5
±1.0
±1.5
±2.0
±2.5
±40 ±25 ±10
5
20
35
50
65
80
TA (C)
95
110 125
C001
10 units
Figure 41. Temperature Sensor Error vs Temperature
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8 Detailed Description
8.1 Overview
The AMC7832 is a highly integrated analog monitoring and control solution capable of voltage and temperature
supervision. The AMC7832 includes the following:
• Twelve, 12-bit digital-to-analog converters (DACs) with adjustable output ranges
– Output ranges of 0 to +5-V, 0 to +10-V and -10 to 0-V
– The DAC power-on and clamp voltage can be terminal-selected between GND and AVSS
– The DACs can be configured to clamp automatically upon detection of an alarm event
• A multi-channel, 12-bit analog-to-digital converter (ADC) for voltage and temperature sensing
– 12 bipolar inputs: -12.5-V to +12.5-V input range
– 5 precision inputs with programmable threshold detectors: 0 to +5-V input range
– Internal temperature sensor
• Internal precision reference
• Eight General Purpose I/O (GPIO) ports
• Communication with the device is done through a 4-wire SPI compatible interface supporting +1.8-V to +5.5-V
operation
The AMC7832 is characterized for operation over the temperature range of -40ºC to 125ºC thus making it
suitable for harsh condition applications and is available in a 10mm x 10mm 64-terminal HTQFP PowerPAD
package.
The AMC7832’s high-integration make it an ideal all-in-one, low-cost, bias control circuit for the power amplifiers
(PA) found in multi-channel RF communication systems. The flexible DAC output ranges allow the device to be
used as a biasing solution for a large variety of transistor technologies such as LDMOS, GaAs and GaN. The
AMC7832 feature set is similarly beneficial in general purpose monitor and control systems.
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8.2 Functional Block Diagram
AMC7832
REF_ CMP
REF_ OUT1
Reference
(2.5V)
Bipo lar Analog Inputs
LV_ADC12
LV_ADC13
LV_ADC14
LV_ADC15
LV_ADC16
ADC Trigger
DAC Trigger
Bipolar Inputs
Scaling
ADC
12- b
GPIO
Controller
DAC_A9
DAC-2
12- b
DAC_ A10
DAC-3
12- b
DAC_ A11
DAC-4
12- b
DAC_ B6
DAC-5
12- b
DAC_ B7
DAC-6
12- b
DAC_ C0
DAC-7
12- b
DAC_ C1
DAC-8
12- b
DAC_ D2
DAC-9
12- b
DAC_ D3
DAC- 10
12- b
DAC_ D4
DAC- 11
12- b
DAC_ D5
DAC Gr oup D
Control / Limits / Status
Registers
DAC-1
12- b
DAC Gr oup C
GPIO0/ALARMIN
GPIO1/ALARMOUT
GPIO2/ADCTRIG
GPIO3/DAV
GPIO 4
GPIO 5
GPIO 6
GPIO 7
DAC_ A8
DAC G roup B
LOCAL TEMP
SENSOR
DAC-0
12- b
DAC G roup A
ADC_0
ADC_1
ADC_2
ADC_3
ADC_4
ADC_5
ADC_6
ADC_7
ADC_8
ADC_9
ADC_10
ADC_11
Unipol ar A nalog Inputs
REF_ OUT2
VRANGEA
DVDD
Synchronization Logic
DAC Range
And Clamp
Setup
Serial Interface Register & Control
VRANGEB
VRANGEC
IOVDD
24
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AVSS C
AVSS D
AVS SA
AVS SB
DGND
A VEE
AGND3
AGND2
AGND1
A VDD 2
A VDD 1
AVCC _C D
A VCC _AB
SDO
CS
S DI
SCLK
RESET
VRANGED
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8.3 Feature Description
8.3.1 Digital-to-Analog Converters (DACs)
The AMC7832 features an analog control system centered on twelve, 12-bit DACs that operate from the device
internal reference. Each DAC core consists of a string DAC and output voltage buffer.
The resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC
determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string to the amplifier. This architecture has inherent
monotonicity, voltage output, and low glitch. It is also linear because all the resistors are of equal value.
8.3.1.1 DAC Output Range and Clamp Configuration
The twelve DACs are split into four total groups: two groups of two DACs (DAC groups B and C) and two groups
of four DACs (DAC groups A and D). All of the DACs in a given group share the same output range and clamp
voltage value however these settings can be set independently for each DAC group. After power-on or a reset
event, the DAC output are directed automatically to their corresponding clamp value and all DAC buffer and
active registers are set to their default values.
The output range for each DAC group is configured as either positive or negative through its corresponding
VRANGE terminal. The VRANGE terminals can be driven directly by the REF_OUT1 and REF_OUT2 +2.5-V
outputs. When a DAC group is in positive output range the DAC Range register (address 0x1E) can be set to
specify an output range of 0 to +5-V instead of the default range of 0 to +10-V.
Additionally the power-on-reset and clamp voltage value of each DAC group is set by its corresponding AVSS
terminal. It is imperative that the clamp voltage setting for a DAC group matches its operating voltage range. The
recommended connections for AVSS are: AGND for the positive output ranges, in which case the clamp voltage
is 0-V; and -12-V for the negative output range, in which case the clamp voltage is AVSS + 2-V.
The full-scale output range for each DAC group is limited by the power supplies AVCC and its corresponding
AVSS. The maximum and minimum outputs cannot exceed AVCC or be lower than AVSS, respectively.
Table 1. DAC Group Configuration
POSITIVE OUTPUT RANGE
VRANGE = GND
NEGATIVE OUTPUT RANGE
VRANGE = +2.5-V
OUTPUT
POLARITY
SELECTION
CLAMP
VOLTAGE
SELECTION
OUTPUT RANGE
VALID CLAMP
VOLTAGE
CONNECTION
OUTPUT
RANGE
VALID CLAMP
VOLTAGE
CONNECTION
DAC
GROUP
DACs
A
DAC_A8
DAC_A9
DAC_A10
DAC_A11
VRANGEA
AVSSA
0 to +5-V
0 to +10-V
GND
-10 to 0-V
-12-V
B
DAC_B6
DAC_B7
VRANGEB
AVSSB
0 to +5-V
0 to +10-V
GND
-10 to 0-V
-12-V
C
DAC_C0
DAC_C1
VRANGEC
AVSSC
0 to +5-V
0 to +10-V
GND
-10 to 0-V
-12-V
D
DAC_D2
DAC_D3
DAC_D4
DAC_D5
VRANGED
AVSSD
0 to +5-V
0 to +10-V
GND
-10 to 0-V
-12-V
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8.3.1.2 DAC Register Structure
The DACs input data is written to the individual DAC Data registers (address 0x50 – 0x67) in straight binary
format for all output ranges.
Table 2. DAC Data Format
DIGITAL CODE
DAC OUTPUT VOLTAGE (V)
0 TO +5-V RANGE
0 TO +10-V RANGE
0000 0000 0000
0
0
-10 TO 0-V RANGE
–10
0000 0000 0001
0.00122
0.00244
-9.99756
1000 0000 0000
2.5
5
-5
1111 1111 1110
4.99756
9.99512
-0.00488
1111 1111 1111
4.99878
9.99756
-0.00244
Data written to the DAC Data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active registers is initiated by an update command in the Register Update register
(address 0x0F). Once the active registers are updated, the DAC outputs change to their new values.
The host has the option to read from either the buffer registers or the active registers when accessing the DAC
Data registers. The DAC read back option is configured by the READBACK bit in the Interface Configuration 1
register (address 0x01).
8.3.1.3 DAC Clear Operation
Each DAC can be set to a clear state using either hardware or software. When a DAC goes to clear state it is
loaded with a zero-code input and the output voltage is set according to the operating output range. The DAC
buffer or active registers do not change when the DACs enter the clear state thus allowing the possibility to
return to the same voltage being output before the clear event was issued. Note that the DAC Data registers can
be updated while the DACs are in clear state allowing the DACs to output new values upon return to normal
operation. When the DACs exit the clear state they are immediately loaded with the data in the DAC active
registers and the output is set back to the corresponding level to restore operation.
The DAC Clear registers (address 0xB0 – 0xB1) enable independent control of each DAC clear state through
software. The DACs can also be forced to a clear state through hardware using the ALARMIN terminal. For a
detailed description of this method please refer to the Programmable Out-of-Range Alarms section.
The ALARMIN controlled clear mechanism is a special case of the device capability to force the DACs into clear
state as a response to an alarm event. To enable this functionality the clear-state controlling alarm events must
first be enabled as DAC clear alarm sources in the DAC Clear Source registers (address 0x1A – 0x1B).
Additionally the DAC outputs to be cleared by the selected alarm events need also to be specified in the DAC
Clear Enable registers (address 0x18 – 0x19).
When an alarm event is triggered, the corresponding alarm bit in the Alarm Status registers is set and all the
DACs set to clear in response to this alarm in the DAC Clear Enable registers enter a clear state. Once the alarm
bit is cleared, and as long as no other clear-state controlling alarm events have been triggered, the DACs get reloaded with the contents of the DAC active registers and the outputs update accordingly.
26
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Serial Interface
DAC Data Register
WRITE
READ
1
0
DAC
Buffer Register
READBACK bit
DAC
Active Register
0
Resistor String
UPDATE
command
0x000
DAC
Output Range
Configuration
VOUT
DAC output
1
Clear State
(register or alarm-generated)
Figure 42. Simplified AMC7832 DAC Block Diagram
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8.3.2 Analog-to-Digital Converter (ADC)
The AMC7832 features a monitoring system centered on a 12-bit successive approximation register (SAR) ADC
fronted by an 18-channel multiplexer and an on-chip track-and-hold. The monitoring systems is capable of
sensing up to 12 external bipolar inputs (-12.5-V to +12.5-V range), 5 external unipolar inputs (0 to +5-V range)
and an internal analog temperature sensor.
The ADC operates from an internal 2.5-V reference and its input range is 0-V to 2 × VREF. The external bipolar
inputs to the ADC are internally mapped to this range. The ADC timing signals are derived from an on-board
temperature compensated oscillator. The conversion results can be accessed through the device serial interface.
8.3.2.1 Analog Inputs
The AMC7832 has 17 uncommitted analog inputs for external voltage sensing. Twelve of these inputs (ADC_0 to
ADC_11) are bipolar and the other five (LV_ADC12 to LV_ADC16) unipolar. Figure 43 shows the equivalent
circuit for the external analog input terminals. All switches are open while the ADC is in idle state.
Scaling Network
3.125V
SW
RS
CSAMPLE
RMUX
ADC_0
SW is closed during sampling.
SW is open during conversion.
3.125V
ADC_11
AVDD
LV_ADC12
AVDD
LV_ADC16
AGND
Figure 43. ADC External Inputs Equivalent Circuit
In order to achieve specified performance, especially at higher input frequencies, it is recommended to drive
each analog input terminal with a low impedance source. An external amplifier can also be used to drive the
input terminals.
8.3.2.1.1 Bipolar Analog Inputs
The AMC7832 supports up to twelve bipolar analog inputs. The analog input range for these channels is -12.5-V
to +12.5-V. The bipolar signal is scaled internally through a resistor divider so that it maps to the native input
range of the ADC (0-V to 2 × VREF). The input resistance of the scaling network is 175-kΩ.
The bipolar analog input conversion values are stored in straight binary format in the ADC-Data registers
(address 0x20 – 0x37). The LSB size for these channels is 10 × VREF/4096. With the internal reference equal to
2.5-V the voltage value is given by,
é CODE × 5
ù
Voltage = 5 ê
- 2.5 ú
ë 4096
û
(1)
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A typical application for the bipolar channels is monitoring of the twelve DAC outputs in the device. In this
application the bipolar inputs can be driven directly. However in applications where the signal source has high
impedance, it is recommended that the analog input is buffered prior to be input to the AMC7832. When driven
from a low impedance source such as the AMC7832 DAC outputs, the network is designed to settle well before
the start of conversion. Additional impedance may affect the settling and divider accuracy of this network.
8.3.2.1.2 Unipolar Analog Inputs
In addition to the bipolar input channels, the AMC7832 includes five unipolar analog inputs. The analog input
range for these channels is 0-V to 2 × VREF with the LSB size for these channels given by 2 × VREF/4096.
The unipolar analog input conversion values are stored in straight binary format in the ADC-Data registers
(address 0x38 – 0x41). With the internal reference equal to 2.5-V the voltage value is given by,
CODE × 5
Voltage =
4096
(2)
In applications where the signal source has high impedance, it is recommended that the unipolar analog input is
buffereded externally.
8.3.2.2 ADC Sequencing
The AMC7832 ADC supports two conversion methods: direct-mode and auto-mode. The conversion method can
be selected in the ADC Configuration register (address 0x10). The default conversion method is direct-mode.
In both methods, the single channel or sequence of channels to be converted by the ADC must be first
configured in the ADC MUX Configuration registers (address 0x13 – 0x15). The input channels to the ADC
include 12 external bipolar inputs, 5 external unipolar inputs and the internal temperature sensor.
In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger
signal. After the last enabled channel is converted, the ADC goes into idle state and waits for a new trigger.
In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is
initiated by issuing an ADC trigger. Upon completion of the first conversion sequence another sequence is
automatically started. Conversion of the selected channels is done repeatedly until the auto-mode conversion is
stopped by issuing a second trigger signal. To ensure data for all channels is updated correctly in the ADC data
registers the auto-mode conversion stop trigger should be synchronized with the data available indicator signal
(DAV, terminal 12).
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Start
(Reset)
ADC Idle State
No
ADC Trigger?
Yes
First Conversion
Yes
Direct-Mode?
Update Registers
&
Issue Data
Available Indicator
Yes
No
Is this the last
conversion?
No
Convert next
channel
Yes
ADC Trigger?
No
Figure 44. AMC7832 ADC Conversion Sequence
Regardless of the selected conversion method, the following registers should only be updated while the ADC is
in idle state:
• ADC Configuration Register (address 0x10)
• False Alarm Configuration Register (address 0x11)
• ADC MUX Configuration Registers (address 0x13 – 0x15)
• Threshold Registers (0x80 – 0x97)
• Hysteresis Register (0xA0 – 0xA5)
• Power Down Registers (0xB2 - 0xB3)
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8.3.2.3 ADC Synchronization
A trigger signal is required for getting the ADC in and out of idle state. The ADC trigger can be generated either
through software (ICONV bit in the ADC Trigger Register, 0xC0) or hardware (GPIO2/ADCTRIG, terminal 11). In
order to use the GPIO2/ADCTRIG terminal as an ADC trigger, the terminal must be configured accordingly in the
GPIO Configuration register (address 0x12). When the terminal is configured as a trigger, a falling edge starts
the sampling and conversion of the ADC.
The ADC Data registers (0x20 – 0x41) and Temperature Data registers (0x78 – 0x79) should only be accessed
while the ADC is in idle state or between conversion sequences if the ADC is in auto-mode. A data available
indicator signal is generated by the device to track the ADC status. Failure to satisfy the synchronization
requirements could lead to erroneous data reads.
The data available indicator signal is output through the GPIO3/DAV terminal. The GPIO3/DAV terminal must be
configured in the GPIO Configuration register (address 0x12) as an interrupt. In addition to the terminal indicator
the device provides a data available flag accessible through the serial interface (DAVF bit in the General Status
Register, 0x72). The DAV terminal is available in both auto and direct-mode but the DAVF flag is only available
in direct mode.
The terminal and flag behavior are dependent on the conversion mode. In direct-mode, after the conversion is
completed and the ADC returns to idle state, the DAVF bit is set immediately to ‘1’ and the DAV terminal is active
(low) to indicate new data is available. The terminal and flag are cleared automatically once a new conversion is
started or one of the ADC Data or Temperature Data registers is accessed. In auto-mode, the DAVF bit is fixed
to ‘0’ and therefore synchronization is always done through the DAV terminal. After one auto-mode conversion
sequence is complete a 1µs pulse (low) is issued on the DAV terminal. When an auto-mode conversion needs to
be stopped it is recommended to do so in synchronization with DAV.
a) Direct-Mode, software trigger
CS
Trigger
Command
1st internal
trigger
Read
Command
Trigger
Command
2nd internal
trigger
Read
Command
DAV
1st CONVERSION of the
channels specified in the ADC
MUX Registers
2nd CONVERSION of the
channels specified in the ADC
MUX Registers
b) Auto-Mode, software trigger
CS
Trigger
Command
Read
Command
1st internal
trigger
Read
Command
>4µs
1µs
DAV
1st CONVERSION of the
channels specified in the ADC
MUX Registers
2nd CONVERSION
3rd CONVERSION
Figure 45. ADC Software Trigger Synchronization
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a) Direct-Mode, hardware trigger
1st trigger
ADCTRIG
2nd trigger
Read
Command
Read
Command
CS
3rd trigger
DAV
1st CONVERSION of the
channels specified in the ADC
MUX Registers
2nd CONVERSION of the
channels specified in the ADC
MUX Registers
3rd CONVERSION of the
channels specified in the ADC
MUX Registers
b) Auto-Mode, hardware trigger
ADCTRIG
1st trigger
Read
Command
Read
Command
CS
>4µs
DAV
1µs
1st CONVERSION of the
channels specified in the ADC
MUX Registers
2nd CONVERSION
3rd CONVERSION
spacing
Figure 46. ADC Hardware Trigger Synchronization
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8.3.2.4 Programmable Out-of-Range Alarms
The AMC7832 is capable of continuously analyzing the 5 external unipolar inputs and internal temperature
sensor conversion results for normal operation.
Normal operation is established through the Lower and Upper Threshold registers (address 0x80 – 0x97). When
any of the monitored inputs is out of the specified range, an alarm event is issued and the global alarm bit, GALR
in the General Status register (0x72) is set. Details on the source of the alarm event can be determined through
the Alarm Status registers (0x70 – 0x71).
The ALARM-LATCH-DIS bit in the ALARMOUT Source 1 register (address 0x1D) sets the latching behavior for
all alarms (except for the ALARMIN alarm which is always unlatched). When the ALARM-LATCH-DIS bit is
cleared to ‘0’ the alarm bits in the Alarm Status registers are latched. The alarm bits are referred to as being
latched because they remain set until read by software. This design ensures that out-of-limit events cannot be
missed if the software is polling the device periodically. The alarm bits are cleared when their corresponding
Alarm Status register is read, and are reasserted if the out-of limit condition still exists on the next monitoring
cycle, unless otherwise noted. When the ALARM-LATCH-DIS bit is set to ‘1’, the alarm bits are not latched. The
alarm bits in the Alarm Status registers go to '0' when the error condition subsides, regardless of whether the bit
is read or not.
RESERVED
7
RESERVED
6
RESERVED
5
LV_ADC16 Alarm
4
LV_ADC15 Alarm
3
LV_ADC14 Alarm
2
LV_ADC13 Alarm
1
LV_ADC12 Alarm
0
RESERVED
7
RESERVED
6
RESERVED
5
RESERVED
4
ALARMIN Alarm
3
Die Temperature Alarm
2
Temp. Sensor High Alarm
1
Temp. Sensor Low Alarm
0
ALARM STATUS 0
0x70
GALR
ALARM STATUS 1
0x71
Figure 47. AMC7832 Alarm Status Register
All of the alarms can be set to activate the ALARMOUT terminal. The GPIO1/ALARMOUT terminal must be
configured accordingly in the GPIO Configuration register (address 0x12) to enable this functionality. The
ALARMOUT terminal works as an interrupt to the host so that it may query the Alarm Status registers to
determine the alarm source. Any alarm event can activate the terminal as long as the alarm is not masked in the
ALARMOUT Source registers (address 0x1C – 0x1D). When an alarm event is masked, the occurrence of the
event sets the corresponding status bit in the Alarm Status registers to '1', but does not activate the ALARMOUT
terminal.
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8.3.2.4.1 Unipolar Inputs Out-of-Range Alarms
The AMC7832 provides out-of-range detection for the five external unipolar ADC inputs (LV_ADC12 to
LV_ADC16, terminals 41 - 45). When the measurement is out-of-range, the corresponding alarm bit in the Alarm
Status 0 register (address 0x70) is set to '1' to flag the out-of-range condition. The values in the ADC Upper and
Lower Threshold registers (address 0x80 – 0x93) define the upper and lower bound thresholds for all five inputs.
ADCn-Upper-Thresh
Value
(upper bound)
+
LV_ADCn
Conversion Value
(n = 12 to 16)
ADCn-ALR Bit
ADCn-Lower-Thresh
Value
(lower bound)
+
Figure 48. Unipolar Inputs Out-of-Range Alarms
8.3.2.4.2 Internal Temperature Sensor Out-of-Range Alarms
The AMC7832 includes high-limit and low-limit detection for the internal temperature sensor. The values in the
LT Upper and Lower Threshold registers (address 0x94 – 0x97) set the limits for the temperature sensor. The
temperature sensor detector can issue either a high-alarm (LT-HIGH-ALR bit) or a low-alarm (LT-LOW-ALR bit)
in the Alarm Status 1 register (address 0x71) depending on whether the high or low thresholds were exceeded.
To implement single, upper-bound threshold detection for the temperature sensor, the host processor can set the
upper-bound threshold to the desired value and the lower-bound threshold to the default value. For lower-bound
threshold detection, the host processor can set the lower-bound threshold to the desired value and the upperbound threshold to the default value.
In addition to the programmable threshold alarms the temperature sensor detection circuit also includes a die
thermal alarm flag which continuously monitors the die temperature. When the die temperatures exceeds +150˚C
the die thermal alarm flag (THERM-ALR bit) in the Alarm Status 1 register (address 0x71) is set. The internal
temperature sensor must be enabled for this alarm to be functional.
Temperature
High Threshold
(upper bound)
LT-HIGH-ALR Bit
+
150°C
THERM-ALR Bit
Temperature
Data
+
Temperature
Low Threshold
(lower bound)
LT-LOW-ALR Bit
+
Figure 49. Internal Temperature Out-of-Range Alarms
34
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8.3.2.4.3 ALARMIN Alarm
The AMC7832 offers the option of using an external interrupt signal, such as the output of a comparator as an
alarm event. The GPIO0/ALARMIN terminal is used as the alarm input and must be configured accordingly in the
GPIO Configuration register (address 0x12). When the terminal is configured as an alarm input it is active low.
A typical application for ALARMIN is to use it as a hardware interrupt responsible for forcing one or more DACs
to a clear state: the DAC is loaded with a zero-code input and the output voltage is set accordingly to the
operating output range, however the DAC buffer or active registers do not change (refer to the DAC section for
more details). To enable this functionality ALARMIN must be enabled as a DAC clear alarm source in the DAC
Clear Source 1 register (address 0x1B). Additionally the DAC outputs to be cleared by the ALARMIN terminal
need to be specified in the DAC Clear Enable registers (address 0x18 – 0x19).
In this application when the ALARMIN terminal goes low, all the DACs set to clear in response to the ALARMIN
alarm in the DAC Clear Enable registers enter a clear state. When the ALARMIN terminal goes back high the
DACs get re-loaded with the contents of the DAC active registers thus allowing the DAC outputs to return to their
previous operating point without any additional commands.
8.3.2.4.4 Hysteresis
If a monitored signal is out of range and the alarm is enabled, the corresponding alarm bit is set ('1'). However,
the alarm condition is cleared only when the conversion result returns to a value of at least HYST below the
value of the high threshold register, or HYST above the value of the low threshold register. The ADC and LT
Hysteresis registers (address 0xA0 – 0xA4) store the hys value for the external unipolar inputs and internal
temperature sensor programmable alarms. HYST is the programmable value of hysteresis: 0 LSB to 127 LSB for
the unipolar inputs alarms, and 0°C to +31°C for the internal temperature sensor alarms. The die thermal alarm
hysteresis is fixed at 8°C.
High Threshold
Hysteresis
Hysteresis
Low Threshold
Over High Alarm
Below Low Alarm
Figure 50. AMC7832 Hysteresis
8.3.2.4.5 False-Alarm Protection
In order to prevent false alarms an alarm event is only registered when the monitored signal is out of range for
an N number of consecutive conversions. If the monitored signal returns to the normal range before N
consecutive conversions, an alarm event is not issued. The false alarm factor N for the unipolar input and local
temperature sensor out-of-range alarms can be configured in the False Alarm Configuration register (address
0x11).
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8.3.3 Internal Temperature Sensor
The AMC7832 has an on-chip temperature sensor used to measure the device die temperature. The normal
operating temperature range for the internal temperature sensor is limited by the operating temperature range of
the device (–40°C to +125°C).
The temperature sensor results are converted by the device ADC at a lower speed than the analog input
channels. Temperature can be monitored either continuously or as a single-time conversion depending on
whether the ADC is configured in Auto mode or Direct mode (refer to the ADC section for more details). If the
temperature sensor is not needed, it can be disabled in the ADC MUX Configuration 2 register (address 0x15).
By default the temperature sensor is disabled and not converted by the ADC.
The temperature sensor gives 0.25°C resolution over the operating temperature range. The temperature value is
stored in 12-bit two’s complement format in the Temperature data registers (address 0x78 – 0x79).
Table 3. Temperature Sensor Data Format
TEMPERATURE (°C)
DIGITAL CODE
-40
1111 0110 0000
-25
1111 1001 1100
-10
1111 1101 1000
-0.25
1111 1111 1111
0
0000 0000 0000
+0.25
0000 0000 0001
+10
0000 0010 1000
+25
0000 0110 0100
+50
0000 1100 1000
+75
0001 0010 1100
+100
0001 1001 0000
+105
0001 1010 0100
+125
0001 1111 0100
If the output data MSB is ‘0’, the temperature can be calculated by,
ADC_Code
Positive Temperature (°C ) =
4
4096 - ADC_Code
Negative Temperature (°C ) =
4
36
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8.3.4 Internal Reference
The AMC7832 includes a high performance internal reference for the on-chip ADC and twelve DACs. The
internal reference is a 2.5-V bipolar transistor-based, precision bandgap reference. A compensation capacitor
(4.7-μF, typical) should be connected between the REF_CMP terminal and AGND2.
The AMC7832 includes two buffers to access the internal reference voltage through terminals REF_OUT1 and
REF_OUT2. If unused, the two reference buffers can be powered down independently in the Power-down 1
register (address 0xB3). A third buffer is used to drive the ADC and should not be used to drive any external
circuitry. The ADC reference buffer is powered down by default and should be enabled in the ADC Configuration
Register (address 0x10) during device initialization.
The REF_OUT1 and REF_OUT2 outputs can directly drive the VRANGEA,B,C,D inputs thus enabling adjustment
of the DAC output ranges without the need for external circuitry. The internal reference buffers are not intended
to drive external loads. If driving an external load, a high impedance buffer amplifier is required.
REF_OUT1
Internal
Reference
(2.5V)
REF_OUT2
VRANGEA
VRANGEB
C > 4.7 µF
(Minimize
inductance to pin)
DAC RANGE
SETUP
REF_CMP
VRANGEC
VRANGED
AGND2
* Each VRANGEn pin should be connected to either
GND or one of the REF_OUT pins according to the
desired output range for DAC group n.
MUX
DAC-1
12-b
ADC
12-b
LOCAL
TEMP
SENSOR
DAC OUTPUTS
ANALOG INPUTS
DAC-0
12-b
DAC-11
12-b
Figure 51. AMC7832 Internal Reference
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8.3.5 General Purpose I/Os
The AMC7832 includes eight General Purpose I/O (GPIO) terminals, each with an internal 48-kΩ pull-up resistor
to IOVDD. The GPIO[0-3] terminals have dual functionality and can be programmed as either bidirectional digital
I/O terminals or interrupt signals in the GPIO Configuration register (address 0x12). The GPIO[4-7] terminals are
dedicated GPIOs.
Table 4. Dual Functionality GPIO Pins
PIN
DEFAULT PIN NAME
ALTERNATIVE PIN NAME
ALTERNATIVE FUNCTIONALITY
9
GPIO0
ALARMIN
DAC clear control signal.
10
GPIO1
ALARMOUT
Global alarm output.
11
GPIO2
ADCTRIG
External ADC conversion trigger.
12
GPIO3
DAV
ADC data available indicator.
The GPIOs can receive an input or produce an output. When the GPIO acts as an output its status is determined
by the corresponding GPIO bit in the GPIO Register (address 0x7A).
To use a GPIO terminal as an input, the corresponding GPIO bit in the GPIO Register must be set to '1'. When a
GPIO terminal acts as input, the digital value on the terminal is acquired by reading the corresponding GPIO bit.
After a power-on reset or any forced reset, all GPIO bits are set to '1', and the GPIO terminals have a 48-kΩ
input impedance to IOVDD.
IOVDD
48k
GPIOn
ENABLE
GPIOn Bit
(when writing)
GPIOn Bit
(when reading)
Figure 52. AMC7832 GPIO Pin
38
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8.4 Programming
The AMC7832 is controlled through a flexible four-wire serial interface that is compatible with SPI type interfaces
used on many microcontrollers and DSP controllers. The interface provides read/write access to all registers of
the AMC7832.
Each serial interface access cycle is exactly (N+2) bytes long, where N is the number of data bytes. A frame is
initiated by asserting CS low. The frame ends when CS is deasserted high. In MSB first mode, the first bit
transferred is the R/W bit. The next 15 bits are the register address (32768 addressable registers), and the
remaining bits are data. For all writes, data is committed in bytes as the 8th data bit of a data field is clocked in
on the rising edge of SCLK. If the write access is not a multiple of 8 clocks, the trailing data bits will not be
committed. On read access, data is clocked out on the falling edge of SCLK on the SDO terminal.
The figures below show the access protocol used by the interface. Data is by default accepted as MSB (Most
Significant Bit) first but the AMC7832 can be configured to accept LSB (Least Significant Bit) first operations as
long as the LSB_Order bit in the Interface Configuration 0 register (address 0x00) is set accordingly.
CS
1
2
3
4
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D1
D0
SCLK
Addr N +1 (ascending )
Addr N -1 (descending )
Addr N
SDI
R/W
A14
A13
A12
A2
A1
A0
SDO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
Figure 53. Serial Interface Write Bus Cycle
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
17
18
19
20
21
22
23
24
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDI
SDO
Figure 54. Serial Interface Read Bus Cycle
For operations that require large amounts of data to be passed to or from the AMC7832, streaming mode is
supported. In streaming mode multiple bytes of data can be written to or read from the AMC7832 without
specifically providing instructions for each byte and is implemented by continually holding the CS active and
continuing to shift new data in or old data out of the device.
The instruction phase includes the starting address. The AMC7832 starts reading or writing data to this address
and continues as long as CS is asserted and single byte writes has not been enabled in the Interface
Configuration 1 register (address 0x01). The AMC7832 automatically increments or decrements the address
depending on the setting of the address ascension bit in the Interface Configuration 0 register (address 0x00).
If the address is decrementing and 0x0000 is reached, the next address used is address 0x7FFF. If the address
is incrementing and address 0x7FFF is reached, the next address used is 0x0000. Care should be taken when
writing to 0x0000 and 0x0001 as writing to these addresses may change the configuration of the serial interface.
Therefore it is advised that 0x0001 be the first address written and that streaming stops prior to reaching this
address.
The figures below show the access protocol used in streaming mode.
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Programming (continued)
CS
1
2
3
4
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCLK
Addr N+1 (ascending)
Addr N-1 (descending)
Addr N
SDI
R/W
A14
A13
A12
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
28
29
30
31
32
D1
D0
SDO
Figure 55. Serial Interface Streaming Write Example
CS
1
2
3
4
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SCLK
Addr N+1 (ascending)
Addr N-1 (descending)
Addr N
SDI
R/W
A14
A13
A12
A2
SDO
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
Figure 56. Serial Interface Streaming Read Example
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8.5 Register Map
Table 5. Register Map
ADDRESS
(HEX)
R/W
DEFAULT
(HEX)
ADDRESS
(HEX)
R/W
DEFAULT
(HEX)
0x00
R/W
3C
Interface Configuration 0
0x54
R/W
00
DACA10-Data (low byte)
0x01
R/W
0x02
R/W
00
Interface Configuration 1
0x55
R/W
00
DACA10-Data (high byte)
03
Device Configuration
0x56
R/W
00
0x03
DACA11-Data (low byte)
R
08
Chip Type
0x57
R/W
00
DACA11-Data (high byte)
0x04
R
32
Chip ID (low byte)
0x58
R/W
00
DACB6-Data (low byte)
0x05
R
0C
Chip ID (high byte)
0x59
R/W
00
DACB6-Data (high byte)
0x06
R
00
Chip Version
0x5A
R/W
00
DACB7-Data (low byte)
0x07 – 0x0B
—
—
Reserved
0x5B
R/W
00
DACB7-Data (high byte)
0x0C
R
51
Manufacturer ID (low byte)
0x5C
R/W
00
DACC0-Data (low byte)
0x0D
R
04
Manufacturer ID (high byte)
0x5D
R/W
00
DACC0-Data (high byte)
0x0E
—
—
Reserved
0x5E
R/W
00
DACC1-Data (low byte)
0x0F
W
00
Register Update
0x5F
R/W
00
DACC1-Data (high byte)
0x10
R/W
00
ADC Configuration
0x60
R/W
00
DACD2-Data (low byte)
0x11
R/W
07
False Alarm Configuration
0x61
R/W
00
DACD2-Data (high byte)
0x12
R/W
00
GPIO Configuration
0x62
R/W
00
DACD3-Data (low byte)
0x13
R/W
00
ADC MUX Configuration 0
0x63
R/W
00
DACD3-Data (high byte)
0x14
R/W
00
ADC MUX Configuration 1
0x64
R/W
00
DACD4-Data (low byte)
0x15
R/W
00
ADC MUX Configuration 2
0x65
R/W
00
DACD4-Data (high byte)
0x16
—
—
Reserved
0x66
R/W
00
DACD5-Data (low byte)
0x17
—
—
Reserved
0x67
R/W
00
DACD5-Data (high byte)
0x18
R/W
00
DAC Clear Enable 0
0x68–0x6F
—
—
Reserved
0x19
R/W
00
DAC Clear Enable 1
0x70
R
00
Alarm Status 0
0x1A
R/W
00
DAC Clear Source 0
0x71
R
00
Alarm Status 1
0x1B
R/W
00
DAC Clear Source 1
0x72
R
00
General Status
0x1C
R/W
00
ALARMOUT Source 0
0x73–0x77
R/W
00
Reserved
0x1D
R/W
00
ALARMOUT Source 1
0x78
R
00
Temperature Data (low byte)
0x1E
R/W
00
DAC Range
0x79
R
00
Temperature Data (high byte)
0x1F
—
—
Reserved
0x7A
R/W
FF
GPIO
0x20
R
00
ADC0-Data (low byte)
0x7B–0x7F
—
—
Reserved
0x21
R
00
ADC0-Data (high byte)
0x80
R/W
FF
ADC12-Upper-Thresh (low byte)
0x22
R
00
ADC1-Data (low byte)
0x81
R/W
0F
ADC12-Upper-Thresh (high byte)
0x23
R
00
ADC1-Data (high byte)
0x82
R/W
00
ADC12-Lower-Thresh (low byte)
0x24
R
00
ADC2-Data (low byte)
0x83
R/W
00
ADC12-Lower-Thresh (high byte)
0x25
R
00
ADC2-Data (high byte)
0x84
R/W
FF
ADC13-Upper-Thresh (low byte)
0x26
R
00
ADC3-Data (low byte)
0x85
R/W
0F
ADC13-Upper-Thresh (high byte)
0x27
R
00
ADC3-Data (high byte)
0x86
R/W
00
ADC13-Lower-Thresh (low byte)
0x28
R
00
ADC4-Data (low byte)
0x87
R/W
00
ADC13-Lower-Thresh (high byte)
0x29
R
00
ADC4-Data (high byte)
0x88
R/W
FF
ADC14-Upper-Thresh (low byte)
0x2A
R
00
ADC5-Data (low byte)
0x89
R/W
0F
ADC14-Upper-Thresh (high byte)
0x2B
R
00
ADC5-Data (high byte)
0x8A
R/W
00
ADC14-Lower-Thresh (low byte)
0x2C
R
00
ADC6-Data (low byte)
0x8B
R/W
00
ADC14-Lower-Thresh (high byte)
0x2D
R
00
ADC6-Data (high byte)
0x8C
R/W
FF
ADC15-Upper-Thresh (low byte)
0x2E
R
00
ADC7-Data (low byte)
0x8D
R/W
0F
ADC15-Upper-Thresh (high byte)
0x2F
R
00
ADC7-Data (high byte)
0x8E
R/W
00
ADC15-Lower-Thresh (low byte)
0x30
R
00
ADC8-Data (low byte)
0x8F
R/W
00
ADC15-Lower-Thresh (high byte)
0x31
R
00
ADC8-Data (high byte)
0x90
R/W
FF
ADC16-Upper-Thresh (low byte)
0x32
R
00
ADC9-Data (low byte)
0x91
R/W
0F
ADC16-Upper-Thresh (high byte)
0x33
R
00
ADC9-Data (high byte)
0x92
R/W
00
ADC16-Lower-Thresh (low byte)
0x34
R
00
ADC10-Data (low byte)
0x93
R/W
00
ADC16-Lower-Thresh (high byte)
REGISTER
REGISTER
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Register Map (continued)
Table 5. Register Map (continued)
ADDRESS
(HEX)
R/W
DEFAULT
(HEX)
ADDRESS
(HEX)
R/W
DEFAULT
(HEX)
0x35
R
00
ADC10-Data (high byte)
0x94
R/W
FF
LT-Upper-Thresh (low byte)
0x36
R
0x37
R
00
ADC11-Data (low byte)
0x95
R/W
07
LT-Upper-Thresh (high byte)
00
ADC11-Data (high byte)
0x96
R/W
00
0x38
LT-Lower-Thresh (low byte)
R
00
ADC12-Data (low byte)
0x97
R/W
08
LT-Lower-Thresh (high byte)
0x39
R
00
ADC12-Data (high byte)
0x98–0x9F
—
—
Reserved
0x3A
R
00
ADC13-Data (low byte)
0xA0
R/W
08
ADC12-Hysteresis
0x3B
R
00
ADC13-Data (high byte)
0xA1
R/W
08
ADC13-Hysteresis
0x3C
R
00
ADC14-Data (low byte)
0xA2
R/W
08
ADC14-Hysteresis
0x3D
R
00
ADC14-Data (high byte)
0xA3
R/W
08
ADC15-Hysteresis
0x3E
R
00
ADC15-Data (low byte)
0xA4
R/W
08
ADC16-Hysteresis
0x3F
R
00
ADC15-Data (high byte)
0xA5
R/W
08
LT-Hysteresis
0x40
R
00
ADC16-Data (low byte)
0xA6—0xAF
—
—
Reserved
0x41
R
00
ADC16-Data (high byte)
0xB0
R/W
00
DAC Clear 0
0x42–0x4F
—
—
Reserved
0xB1
R/W
00
DAC Clear 1
0x50
R/W
00
DACA8-Data (low byte)
0xB2
R
00
Power-Down 0
0x51
R/W
00
DACA8-Data (high byte)
0xB3
R/W
00
Power-Down 1
0x52
R/W
00
DACA9-Data (low byte)
0xB4–0xBF
—
—
Reserved
0x53
R/W
00
DACA9-Data (high byte)
0xC0
W
00
ADC Trigger
42
REGISTER
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8.5.1 Interface Configuration: Address 0x00 – 0x02
Table 6. Register name: Interface Configuration 0 – Address: 0x00, Default: 0x3C (READ/WRITE)
REGISTER
NAME
Interface
Config 0
ADDRESS
BIT
0x00
DEFAULT
VALUE
NAME
DESCRIPTION
7
SOFT-RESET
Soft reset (self-clearing)
0: no action
1: reset – resets everything except address 0x00, 0x01
0
6
LSB-ORDER
LSB First
0: MSB first
1: LSB first
0
5
ADDR-ASCEND
Address Ascend
0: Descend – decrements address while streaming (address
wrap from 0x0000 to 0x7FFF)
1: Ascend – increments address while streaming (address wrap
from 0x7FFF to 0x0000)
1
4
Reserved
Reserved for factory use
1
REVERSECONFIG
Bits 3:0 should always mirror bits 7:4 so that it does not matter
whether the part is in MSB or LSB first mode. Bits should be set
as follows:
Bit 0 = Bit 7
Bit 1 = Bit 6
Bit 2 = Bit 5
Bit 3 = Bit 4
3:0
0xC
Table 7. Register name: Interface Configuration 1 – Address: 0x01, Default: 0x00 (READ/WRITE)
REGISTER
NAME
Interface
Config 1
ADDRESS
BIT
0x01
DEFAULT
VALUE
NAME
DESCRIPTION
7
SINGLE-INSTR
Single instruction enable
0: streaming mode (default)
1: single instruction
0
6
Reserved
Reserved for factory use
0
5
READBACK
Read back
0: DAC read back from active registers (default)
1: DAC read back from buffer registers
0
4
Reserved
Reserved for factory use
0
3
Reserved
Reserved for factory use
0
2
Reserved
Reserved for factory use
0
1
Reserved
Reserved for factory use
0
0
Reserved
Reserved for factory use
0
Table 8. Register name: Device Configuration – Address: 0x02, Default: 0x03 (READ/WRITE)
REGISTER
NAME
Device
Config
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x02
7:2
Reserved
Reserved for factory use
1:0
POWER-MODE
Mode:
00: Normal operation – full power and full performance
11: Sleep – lowest power, non-operational except SPI One time
overwrite of the power-down registers (0xB2 and 0xB3)
All zeros
11
8.5.2 Device Identification: Address 0x03 – 0x0D
Table 9. Register name: Chip Type – Address: 0x03, Default: 0x08 (READ ONLY)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
DEFAULT
VALUE
Chip Type
0x03
7:4
Reserved
Reserved for factory use
0x0
3:0
CHIP-TYPE
Identifies the device as a precision analog monitor and control
0x8
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Table 10. Register name: Chip ID low byte – Address: 0x04, Default: 0x32 (READ ONLY)
REGISTER
NAME
Chip ID Low
Byte
ADDRESS
BIT
NAME
DESCRIPTION
0x04
7:0
CHIPID-LOW
Chip ID. Low byte
DEFAULT
VALUE
0x32
Table 11. Register name: Chip ID high byte – Address: 0x05, Default: 0x0C (READ ONLY)
REGISTER
NAME
Chip ID
High Byte
ADDRESS
BIT
NAME
DESCRIPTION
0x05
7:0
CHIPID-HIGH
Chip ID. High byte
DEFAULT
VALUE
0x0C
Table 12. Register name: Version ID – Address: 0x06, Default: 0x00 (READ ONLY)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
DEFAULT
VALUE
Version ID
0x06
7:0
VERSIONID
AMC7832 Version ID. Subject to change.
0x00
Table 13. Register name: Manufacturer ID low byte – Address: 0x0C, Default: 0x51 (READ ONLY)
REGISTER
NAME
Manuf. ID
Low Byte
ADDRESS
BIT
NAME
DESCRIPTION
0x0C
7:0
VENDORID-LOW
Manufacturer ID. Low byte
DEFAULT
VALUE
0x51
Table 14. Register name: Manufacturer ID high byte – Address: 0x0D, Default: 0x04 (READ ONLY)
REGISTER
NAME
Manuf. ID
High Byte
ADDRESS
BIT
NAME
0x0D
7:0
VENDORID-HIGH Manufacturer ID. High byte
DEFAULT
VALUE
DESCRIPTION
0x04
8.5.3 Register Update (Buffered Registers): Address 0x0F
Table 15. Register name: Register Update – Address: 0x0F, Default: 0x00 (SELF CLEARING)
REGISTER
NAME
Register
Update
44
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x0F
7:1
Reserved
Reserved for factory use
0
UPDATE
Update (self clearing)
0: disabled
1: enabled – transfers data from buffers to active registers (DAC
registers only)
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8.5.4 General Device Configuration: Address 0x10 – 0x17
Table 16. Register name: ADC Configuration – Address: 0x10, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADDRESS
BIT
ADC Config
0x10
7
DEFAULT
VALUE
NAME
DESCRIPTION
CMODE
ADC Conversion Mode Bit. This bit selects the ADC conversion
mode.
0: Direct mode. The analog inputs specified in the ADC channel
registers are converted sequentially one time. When one set of
conversions is complete, the ADC is idle and waits for a new
trigger.
1: Auto mode. The analog inputs specified in the AMC channel
registers are converted sequentially and repeatedly. When one
set of conversions is complete, the ADC multiplexer returns to
the first channel and repeats the process. In this mode data
should be read synchronously with the DAV terminal.
0
6:5
CONV-RATE[1:0]
ADC Conversion rate bits
00
4
ADC-REF-BUFF
ADC Reference Buffer bit. This bit must be set to 1 after device
power-up to enable the internal reference buffer driving the ADC.
0: ADC reference buffer is disabled.
1: ADC reference buffer is enabled.
0
Reserved
Reserved for factory use
3:0
0000
Table 17. Register name: False Alarm Configuration – Address: 0x11, Default: 0x70 (READ/WRITE)
REGISTER
NAME
False Alarm
Config
DEFAULT
VALUE
ADDRESS
BIT
NAME
0x10
7:5
CH-FALR-CT[2:0] False alarm protection for ADC channels.
4:3
2:0
DESCRIPTION
TEMP-FALRCT[1:0]
Reserved
011
CH-FALR-CT
N
CONSECUTIVE
SAMPLES
BEFORE
ALARM IS SET
000
1
001
4
010
8
011
16 (default)
100
32
101
64
110
128
111
256
False alarm protection for temperature sensor.
TEMP-FALR-CT
N
CONSECUTIVE
SAMPLES
BEFORE
ALARM IS SET
00
1
01
2
10
4 (default)
11
8
Reserved for factory use
000
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Table 18. Register name: GPIO Configuration – Address: 0x12, Default: 0x00 (READ/WRITE)
REGISTER
NAME
GPIO
Config
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x12
7:5
Reserved
Reserved for factory use
000
4
Reserved
Reserved for factory use
0
3
EN-DAV
DAV terminal enable
0: GPIO3 operation (default)
1: DAV operation
0
2
EN-ADCTRIG
ADCTRIG terminal enable
0: GPIO2 operation (default)
1: ADCTRIG operation
0
1
EN-ALARMOUT
ALARMOUT terminal enable
0: GPIO1 operation (default)
1: ALARMOUT operation
0
0
EN-ALARMIN
ALARMIN terminal enable
0: GPIO0 operation (default)
1: ALARMIN operation
0
Table 19. Register name: ADC MUX Configuration 0 – Address: 0x13, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADC MUX
Config 0
ADDRESS
BIT
0x13
DEFAULT
VALUE
NAME
DESCRIPTION
7
CH7
6
CH6
5
CH5
When set to ‘1’ the corresponding analog input channel ADC_n is
accessed during an ADC conversion cycle.
When cleared to ‘0’ the corresponding input channel ADC_n is
ignored during an ADC conversion cycle.
4
CH4
0
3
CH3
0
2
CH2
0
1
CH1
0
0
CH0
0
0
0
0
Table 20. Register name: ADC MUX Configuration 1 – Address: 0x14, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADC MUX
Config 1
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x14
7
CH15
6
CH14
5
CH13
When set to ‘1’ the corresponding analog input channel ADC_n is
accessed during an ADC conversion cycle.
When cleared to ‘0’ the corresponding input channel ADC_n is
ignored during an ADC conversion cycle.
4
CH12
0
3
CH11
0
2
CH10
0
1
CH9
0
0
CH8
0
0
0
0
Table 21. Register name: ADC MUX Configuration 2 – Address: 0x15, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADC MUX
Config 2
46
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0X15
7:2
Reserved
Reserved for factory use
1
TEMP-CH
When set to ‘1’ the local temperature sensor is enabled for ADC
conversion.
When cleared to ‘0’ the local temperature sensor is ignored.
0
0
CH16
When set to ‘1’ the corresponding analog input channel ADC_n is
accessed during an ADC conversion cycle.
When cleared to ‘0’ the corresponding input channel ADC_n is
ignored during an ADC conversion cycle.
0
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Table 22. Register name: DAC Clear Enable 0 – Address: 0x18, Default: 0x00 (READ/WRITE)
REGISTER
NAME
DAC Clear
Enable 0
ADDRESS
BIT
0x18
DEFAULT
VALUE
NAME
DESCRIPTION
7
CLREN-C1
6
CLREN-C0
5
CLREN-B7
4
CLREN-B6
3
CLREN-A11
This register determines which DACs go into clear state when a
clear event is detected as configured in the DAC-CLEARSOURCE registers.
If CLRENn = '1', DAC_n is forced into a clear state with a clear
event.
If CLRENn = '0', a clear event does not affect the state of
DAC_n.
2
CLREN-A10
0
1
CLREN-A9
0
0
CLREN-A8
0
0
0
0
0
0
Table 23. Register name: DAC Clear Enable 1 – Address: 0x19, Default: 0x00 (READ/WRITE)
REGISTER
NAME
DAC Clear
Enable 1
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x19
7:4
Reserved
Reserved for factory use
3
CLREN-D5
2
CLREN-D4
1
CLREN-D3
0
CLREN-D2
This register determines which DACs go into clear state when a
clear event is detected as configured in the DAC-CLEARSOURCE registers.
If CLRENn = '1', DAC_n is forced into a clear state with a clear
event.
If CLRENn = '0', a clear event does not affect the state of
DAC_n.
All zeros
0
0
0
0
8.5.5 DAC Clear And ALARMOUT Source Select: Address 0x1A – 0x1D
Table 24. Register name: Register name: DAC Clear Source 0 – Address: 0x1A, Default: 0x00
(READ/WRITE)
REGISTER
NAME
DAC Clear
Source 0
ADDRESS
BIT
NAME
DESCRIPTION
0x1A
7:5
DEFAULT
VALUE
Reserved
Reserved for factory use
4
ADC16-ALR-CLR
3
ADC15-ALR-CLR
2
ADC14-ALR-CLR
This register selects which alarm forces DACs into a clear state,
regardless of which DAC operation mode is active, auto or
manual. In order for DAC_n to go into clear mode, it must be
enabled in the DAC Clear Enable registers.
000
1
ADC13-ALR-CLR
0
0
ADC12-ALR-CLR
0
0
0
0
Table 25. Register name: Register name: DAC Clear Source 1 – Address: 0x1B, Default: 0x00
(READ/WRITE)
REGISTER
NAME
DAC Clear
Source 1
ADDRESS
BIT
NAME
DESCRIPTION
0x1B
7:4
DEFAULT
VALUE
Reserved
Reserved for factory use
3
ALARMIN-ALR
2
THERM-ALR
1
LT-HIGH-ALR
This register selects which alarm forces DACs into a clear state,
regardless of which DAC operation mode is active, auto or
manual. In order for DAC_n to go into clear mode, it must be
enabled in the DAC Clear Enable registers.
0000
0
LT-LOW-ALR
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0
0
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Table 26. Register name: ALARMOUT Source 0 – Address: 0x1C, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ALARM
OUT Source
0
ADDRESS
BIT
NAME
DESCRIPTION
0x1C
7:5
Reserved
Reserved for factory use
4
DEFAULT
VALUE
000
0
2
ADC16-ALR-OUT This register selects which alarms can activate the ALARMOUT
terminal. The ALARMOUT must be enabled for this function to
ADC15-ALR-OUT
take effect.
ADC14-ALR-OUT
1
ADC13-ALR-OUT
0
0
ADC12-ALR-OUT
0
3
0
0
Table 27. Register name: ALARMOUT Source 1 – Address: 0x1D, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ALARM
OUT Source
1
ADDRESS
BIT
NAME
DESCRIPTION
0x1D
7:5
DEFAULT
VALUE
Reserved
Reserved for factory use
4
ALARM-LATCHDIS
Alarm latch disable bit. When cleared to 0 the alarm bits are
latched. When an alarm occurs, the corresponding alarm bit is
set to “1”. The alarm bit remains until the error condition subsides
and the alarm register is read. Before reading, the alarm bit is not
cleared even if the alarm condition disappears. When set to 1 the
alarm bits are not latched. When the alarm condition subsides,
the alarm bits are cleared regardless of whether the alarm bits
have been read or not.
000
0
3
ALRIN-ALR-OUT
THERM-ALROUT
This register selects which alarms can activate the ALARMOUT
terminal. The ALARMOUT must be enabled for this function to
take effect.
0
2
1
LT-HIGH-ALROUT
0
0
LT-LOW-ALROUT
0
0
8.5.6 DAC Range: Address 0x1E
Table 28. Register name: DAC Range – Address: 0x1E, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
DAC Range
0xE1
7:4
Reserved
Reserved for factory use
3
2
1
0
DEFAULT
VALUE
0000
DAC-5VRANGED DAC_n output voltage range bit.
VRANGEn terminal is connected to AGND:
DAC-5VRANGEC
When the DAC-5VRANGEn bit is cleared to 0 the DAC_n group
DAC-5VRANGEB output voltage range is set to 0-10V.
DAC-5VRANGEA When the DACn-RANGE bit is set to 1 the DAC_n group output
voltage range is set to 0-5V.
VRANGEn terminal is connected to +2.5V: If the VRANGEn
terminal is connected to +2.5V the DAC-5VRANGEn bit must be
cleared to 0.
0
0
0
0
8.5.7 ADC Data: Address 0x20 – 0x41
Table 29. Register name: ADCn-Data (low byte) – Address: 0x20 - 0x41, Default: 0x00 (READ ONLY)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
ADCn Data
(low)
0x20 to
0x41
7:0
ADCn-DATA(7:0)
Stores the 12-bit ADC_n conversion results in straight binary
format for both types of inputs channels (unipolar and bipolar)
48
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DEFAULT
VALUE
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Table 30. Register name: ADCn-Data (high byte) – Address: 0x20 - 0x41, Default: 0x00 (READ ONLY)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
DEFAULT
VALUE
ADCn Data
(high)
0x20 to
0x41
7:4
Reserved
Reserved for factory use
All zeros
3:0
ADCn-DATA
(11:8)
Stores the 12-bit ADC_n conversion results in straight binary
format for both types of inputs channels (unipolar and bipolar).
All zeros
8.5.8 DAC Data: Address 0x50 – 0x67
Table 31. Register name: DACn-Data (low byte) – Address: 0x50 - 0x67, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
DEFAULT
VALUE
DACn Data
(low)
0x50 to
0x67
7:0
DACn-DATA(7:0)
Stores the 12-bit data to be loaded to the DAC_n latches in
straight binary format. The straight binary format is used for both
DAC ranges: -10 to 0V and 0 to 10V.
All zeros
Table 32. Register name: DACn-Data (high byte) – Address: 0x50 - 0x67, Default: 0x00 (READ/WRITE)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
DEFAULT
VALUE
DACn Data
(high)
0x50 to
0x67
7:4
Reserved
Reserved for factory use
All zeros
3:0
DACn-DATA
(11:8)
Stores the 12-bit data to be loaded to the DAC_n latches in
straight binary format. The straight binary format is used for both
DAC ranges: -10 to 0V and 0 to 10V.
All zeros
8.5.9 Status Registers: Address 0x70 – 0x72
The AMC7832 continuously monitors all unipolar analog inputs and local temperature sensor during normal
operation. When any input is out of the specified range N consecutive times, the corresponding alarm bit is set
('1'). If the input returns to the normal range before N consecutive times, the corresponding alarm bit remains
clear ('0'). This configuration avoids any false alarms. When an alarm status occurs, the corresponding alarm bit
is set ('1'). When the corresponding bit in the ALARMOUT Source Registers is cleared ('0'), the ALARMOUT
terminal is latched. Whenever an alarm status bit is set, it remains set until the event that caused it is resolved
and its status register is read. Reading the Alarm Status Registers clears the alarm status bits. The alarm bit can
only be cleared by reading its Alarm Status register after the event is resolved, or by hardware reset, software
reset, or power-on reset. All alarm status bits are cleared when reading the Alarm Status registers, and all these
bits are reasserted if the out-of-limit condition still exists after the next conversion cycle, unless otherwise noted.
Table 33. Register name: Register name: Alarm Status 0 – Address: 0x70, Default: 0x00 (READ ONLY)
REGISTER
NAME
Alarm
Status 0
ADDRESS
BIT
NAME
DESCRIPTION
0X70
7:5
DEFAULT
VALUE
Reserved
Reserved for factory use
4
ADC16-ALR
ADC16-ALR = '1' when ADC16 is out of the range defined by the
corresponding threshold registers. ADC16-ALR = '0' when the
analog input is not out of the specified range.
000
0
3
ADC15-ALR
ADC15-ALR = '1' when ADC16 is out of the range defined by the
corresponding threshold registers. ADC15-ALR = '0' when the
analog input is not out of the specified range.
0
2
ADC14-ALR
ADC14-ALR = '1' when ADC16 is out of the range defined by the
corresponding threshold registers. ADC14-ALR = '0' when the
analog input is not out of the specified range.
0
1
ADC13-ALR
ADC13-ALR = '1' when ADC16 is out of the range defined by the
corresponding threshold registers. ADC13-ALR = '0' when the
analog input is not out of the specified range.
0
0
ADC12-ALR
ADC12-ALR = '1' when ADC16 is out of the range defined by the
corresponding threshold registers. ADC12-ALR = '0' when the
analog input is not out of the specified range.
0
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Table 34. Register name: Alarm Status 1 – Address: 0x71, Default: 0x00 (READ ONLY)
REGISTER
NAME
Alarm
Status 1
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0X71
7:4
Reserved
Reserved for factory use
3
ALARMIN-ALR
The ALARMIN-ALR is set to ‘1’ if the ALARMIN terminal is
enabled and set high.
0
2
THERM-ALR
Thermal alarm flag. When the die temperature is equal to or
greater than +150°C, the bit is set ('1') and the THERM-ALR flag
activates. The on-chip temperature sensor (LT) monitors the die
temperature. If LT is disabled, the THERM-ALR bit is always '0'.
The hysteresis of this alarm is 8°C.
0
1
LT-HIGH-ALR
LT-LOW-ALR = '1' when the temperature sensor is out of the
range defined by the upper threshold.
0
0
LT-LOW-ALR
LT-LOW-ALR = '1' when the temperature sensor is out of the
range defined by the lower threshold.
0
0000
Table 35. Register name: General Status – Address: 0x72, Default: 0x00 (READ ONLY)
REGISTER
NAME
General
Status
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x72
7:3
Reserved
Reserved for factory use
All zeros
2
Reserved
Reserved for factory use
0
1
GALR
Global alarm bit.
This bit is the OR function or all individual alarm bits of the status
register.
0
0
DAVF
ADC Data available flag bit. Direct mode only. Always cleared in
Auto mode.
0: ADC conversion is in progress or ADC is in Auto mode
1: ADC conversions are complete and new data is available
0
8.5.10 Temperature And GPIO Data: Address 0x78 – 0x7A
Table 36. Register name: Temperature Data (low byte) – Address: 0x78, Default: 0x00 (READ ONLY)
REGISTER
NAME
Temp Data
(low)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x78
7:0
TEMP-DATA(7:0)
Stores the temperature sensor reading in twos complement
format.
0x00
Table 37. Register name: Temperature Data (high byte) – Address: 0x79, Default: 0x00 (READ ONLY)
REGISTER
NAME
Temp Data
(high)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x79
7:4
Reserved
Reserved for factory use.
3:0
TEMPDATA(11:8)
Stores the temperature sensor reading in twos complement
format.
All zeros
0x00
Table 38. Register name: GPIO – Address: 0x7A, Default: 0xFF (READ/WRITE)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
GPIO
0x7A
7
GPIO-7
6
GPIO-6
5
GPIO-5
4
GPIO-4
3
GPIO-3
For write operation the GPIO terminal operates as an output.
Writing a ‘1’ to the GPIO-n bit sets the GPIO-N terminal to high
impedance. Writing a ‘0’ sets the GPIO-n terminal to logic low.
For read operations the GPIO terminal operates as an input.
Read the GPIO-n bit to receive the status of the GPIO-n terminal.
After power-on reset, or any forced hardware or software reset,
the GPIO-n terminal has a 48-kΩ input impedance to IOVDD.
2
GPIO-2
1
1
GPIO-1
1
0
GPIO-0
1
50
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DEFAULT
VALUE
1
1
1
1
1
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8.5.11 Out-Of-Range ADC Thresholds: Address 0x80 – 0x93
The unipolar analog inputs (LV_ADC12 to LV_ ADC16) and the local temperature sensor implement an out-ofrange alarm function. The Upper-Thresh and Lower-Thresh registers define the upper bound and lower bounds
for these inputs. This window determines whether the analog input or temperature is out-of-range. When the
input is outside the window, the corresponding CH-ALR-n bit in the Status Register is set to '1'. For normal
operation, the value of the upper threshold must be greater than the value of lower threshold; otherwise, an
alarm is always indicated. The analog input threshold values are specified in straight binary format while the local
temperature ones are specified in two’s complement format.
Table 39. Register name: ADCn-Upper-Thresh (low byte) – Address: 0x80 - 0x93, Default: 0xFF
(READ/WRITE)
REGISTER
NAME
ADCn
Upper
Thresh (low)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x80 to
0x93
7:0
THRUn(7:0)
Sets 12-bit upper threshold value for the ADC_n channel in
straight binary format.
0xFF
Table 40. Register name: ADCn-Upper-Thresh (high byte) – Address: 0x80 - 0x93, Default: 0x0F
(READ/WRITE)
REGISTER
NAME
ADCn
Upper
Thresh
(high)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x80 to
0x93
7:4
Reserved
Reserved for factory use.
3:0
THRUn(11:8)
Sets 12-bit upper threshold value for ADC_n channel in straight
binary format.
All zeros
0x0F
Table 41. Register name: ADCn-Lower-Thresh (low byte) – Address: 0x80 - 0x93, Default: 0x00
(READ/WRITE)
REGISTER
NAME
ADCn
Lower
Thresh (low)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x80 to
0x93
7:0
THRLn(7:0)
Sets 12-bit lower threshold value for the ADC_n channel in
straight binary format.
0x00
Table 42. Register name: ADCn-Lower-Thresh (high byte) – Address: 0x80 - 0x93, Default: 0x00
(READ/WRITE)
REGISTER
NAME
ADCn
Lower
Thresh
(high)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x80 to
0x93
7:4
Reserved
Reserved for factory use.
3:0
THRLn(11:8)
Sets 12-bit lower threshold value for ADC_n channel in straight
binary format.
All zeros
0x00
Table 43. Register name: LT-Upper-Thresh (low byte) – Address: 0x94, Default: 0xFF (READ/WRITE)
REGISTER
NAME
LT Upper
Thresh (low)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x94
7:0
THRU-LT(7:0)
Sets 12-bit upper threshold value for the local temperature
sensor in two’s complement format.
0xFF
Table 44. Register name: LT-Upper-Thresh (high byte) – Address: 0x95, Default: 0x07 (READ/WRITE)
REGISTER
NAME
LT Upper
Thresh
(high)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x95
7:4
Reserved
Reserved for factory use.
3:0
THRU-LT(11:8)
Sets 12-bit upper threshold value for the local temperature
sensor in two’s complement format.
All zeros
0x07
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Table 45. Register name: LT-Lower-Thresh (low byte) – Address: 0x96, Default: 0x00 (READ/WRITE)
REGISTER
NAME
LT Lower
Thresh (low)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x96
7:0
THRL-LT(7:0)
Sets 12-bit lower threshold value for the local temperature sensor
in two’s complement format.
0x00
Table 46. Register name: LT-Lower-Thresh (high byte) – Address: 0x97, Default: 0x08 (READ/WRITE)
REGISTER
NAME
LT Lower
Thresh
(high)
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0x97
7:4
Reserved
Reserved for factory use.
3:0
THRL-LT(11:8)
Sets 12-bit lower threshold value for the local temperature sensor
in two’s complement format.
All zeros
0x08
8.5.12 Hysteresis: Address 0xA0 – 0xA5
The hysteresis registers define the hysteresis in the out-of-range alarms.
Table 47. Register name: ADCn-Hysteresis – Address: 0xA0 - 0xA4, Default: 0x08 (READ/WRITE)
REGISTER
NAME
ADDRESS
ADCn
Hysterisis
0xA0 to
0xA4
BIT
7
6:0
DEFAULT
VALUE
NAME
DESCRIPTION
Reserved
Reserved for factory use.
HYSTn(6:0)
Hysteresis of unipolar LV_ADCn, 1 LSB per step
0
0x08
Table 48. Register name: LT-Hysteresis – Address: 0xA5, Default: 0x08 (READ/WRITE)
REGISTER
NAME
LT
Hysterisis
DEFAULT
VALUE
ADDRESS
BIT
NAME
DESCRIPTION
0xA5
7:5
Reserved
Reserved for factory use.
4:0
HYST-LT(4:0)
Hysteresis of local temperature sensor, 1°C per step. The range
is 0°C to 31°C.
000
All zeros
8.5.13 Power-Down Registers: Address 0xB0 – 0xB3
Table 49. Register name: DAC Clear 0 – Address: 0xB0, Default: 0x00 (READ/WRITE)
REGISTER
NAME
DAC Clear
0
ADDRESS
BIT
0xB0
DEFAULT
VALUE
NAME
DESCRIPTION
7
CLR-C1
6
CLR-C0
This register uses software to force the DAC into a clear state.
If CLRn = '1', DAC_n is forced into a clear state.
If CLRn = '0', DAC_n is restored to normal operation.
5
CLR-B7
0
4
CLR-B6
0
3
CLR-A11
0
2
CLR-A10
0
1
CLR-A9
0
0
CLR-A8
0
0
0
Table 50. Register name: DAC Clear 1 – Address: 0xB1, Default: 0x00 (READ/WRITE)
REGISTER
NAME
DAC Clear
1
52
ADDRESS
BIT
NAME
DESCRIPTION
0xB1
7:4
DEFAULT
VALUE
Reserved
Reserved for factory use
3
CLR-D5
2
CLR-D4
This register uses software to force the DAC into a clear state.
If CLRn = '1', DAC_n is forced into a clear state.
If CLRn = '0', DAC_n is restored to normal operation.
1
CLR-D3
0
0
CLR-D2
0
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0
0
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Table 51. Register name: Register name: Power-down 0 – Address: 0xB2, Default: 0x00 (READ/WRITE)
REGISTER
NAME
Power
Down 0
ADDRESS
BIT
0xB2
DEFAULT
VALUE
NAME
DESCRIPTION
7
PDAC-C1
6
PDAC-C0
5
PDAC-B7
4
PDAC-B6
3
PDAC-A11
2
PDAC-A10
1
PDAC-A9
After power-on or reset, all bits in the Power-Down Register are
cleared to '0', and all the components controlled by this register
are either powered-down or off. The Power-Down Register allows
the host to manage the AMC7832 power dissipation. When not
required, the ADC, internal reference, reference buffer amplifiers,
and any of the DACs can be put into an inactive low-power mode
to reduce current drain from the supply. The bits in the PowerDown Register control this power-down function. Set the
respective bit to '1' to activate the corresponding function.
0
PDAC-A8
0
0
0
0
0
0
0
0
Table 52. Register name: Register name: Power-down 1 – Address: 0xB3, Default: 0x00 (READ/WRITE)
REGISTER
NAME
Power
Down 1
ADDRESS
BIT
0xB3
DEFAULT
VALUE
NAME
DESCRIPTION
7
PREF_OUT1
6
PREF_OUT2
5
PREF
4
PADC
3
PDAC-D5
2
PDAC-D4
1
PDAC-D3
After power-on or reset, all bits in the Power-Down Register are
cleared to '0', and all the components controlled by this register
are either powered-down or off. The Power-Down Register allows
The Power-Down Register allows the host to manage the
AMC7832 power dissipation. When not required, the ADC,
internal reference, reference buffer amplifiers, and any of the
DACs can be put into an inactive low-power mode to reduce
current drain from the supply. The bits in the Power-Down
Register control this power-down function. Set the respective bit
to '1' to activate the corresponding function.
0
PDAC-D2
0
0
0
0
0
0
0
0
8.5.14 ADC Trigger: Address 0xC0
Table 53. Register name: ADC Trigger – Address: 0xC0, Default: 0x00 (WRITE ONLY)
REGISTER
NAME
ADDRESS
BIT
NAME
DESCRIPTION
ADC Trigger
0xC0
7:1
Reserved
Reserved for factory use
ICONV
Internal ADC conversion bit. Set this bit to ‘1’ to start the ADC
conversion internally. The bit is automatically cleared to ‘0’.
0
DEFAULT
VALUE
All zeros
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9 Applications and Implementation
9.1 Application Information
The AMC7832 device is a highly integrated, low-power, complete analog monitoring and control solution.
Although the device can be used in many different systems -- Industrial Control, Test and Measurement, and
Optical Communications -- the device is largely used in multi-channel RF communication driven applications
which incorporate power amplifiers.
Power amplifiers (PAs) include transistor technologies that are extremely temperature sensitive, and require DC
biasing circuits to optimize RF performance, power efficiency, and stability. The AMC7832 device provides 12
DAC channels, which can be used to bias the inputs of the power amplifiers. The device also includes an internal
local temperature sensor, and 17 ADC channels for general-purpose monitoring.
There are mainly two different types of monitoring schemes: current sensing, and temperature sensing. In the
current-sense application the PA drain current is monitored by measuring the shunt resistor’s differential voltage
drop. The devices internal local temperature sensor and analog inputs – which can be configured for remote
temperature ICs or thermistors – can be used to detect temperature variations during PA operation. Figure 57
shows the block diagrams to these different systems.
9.2 Typical Application
AMC7832
GPIO
ADC
Digital Interface
MUX
Temperature
Sensor
DAC
Power
Power
Rshunt
Ps
Power
Amplifier
RF IN
RF IN
Temp
Sensor Heat Sink
Temperature Sensing
Power
Amplifier
Heat Sink
Current Sensing
Figure 57. AMC7832 Example Control and Monitor System
54
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Typical Application (continued)
9.2.1 Application Schematic
An example schematic incorporating the AMC7832 is listed in Figure 58.
AVSS_C
AVSS_D
Control Connection
(DAC Bank C&D)
AVCC 0.1PF
0.1PF
AVSS_C
57
59
AVCC_CD
DACC_0
DACC_1
REF_OUT2
54 52 53
5
6
MISO
8
/CS
/RESET
SDO
LVADC_12
SDI
LVADC_13
SCLK
LVADC_14
LVADC_15
/CS
GPIO
12
13
14
15
16
47
46
ADC_5
9
10
11
48
ADC_4
7
SCLK
49
ADC_3
GPIO0 (/ALARMIN)
GPIO1 (/ALARMOUT)
GPIO2 (/ADCTRIG)
GPIO3 (/DAV)
GPIO4
GPIO5
GPIO6
GPIO7
AMC7832
45
44
43
42
41
LVADC_16
ADC_6
40
ADC_7
ADC_8
39
ADC_9
37
ADC_10
36
38
35
ADC_11
AVDD2
ADC0-ADC16
MOSI
50
ADC_1
ADC_2
DGND
4
/RESET
51
ADC_0
Monitor Connection
Digital Control
1
IOVDD
55 56
VRANGE_C
3
DVDD
DACD_2
AVSS_D
IOVDD
DACD_3
2
0.1PF
VDD
DACD_4
DVDD
DACD_5
IOVDD
VRANGE_D
61
64 63 60 58 62
AGND3
0.1PF
34
AVDD
31
AVDD1
AVEE
27 29 28
25
AGND1
AVCC_AB
AVSS_B
DACB_7
DACB_6
REF_OUT1
VRANGE_B
21 26 30
AGND2
0
32
23
AVSS_B
AVSS_A
Analog
GND
Note: 1 Bypass Capacitor
for AVDD1 and AVDD2
REF_CMP
AVCC
Digital
GND
0.1PF
33
4.7PF
Note: 4.7PF Compensation Cap
connected to AGND2
0.1PF
18 19 22 24 20
VRANGE_A
DACA_8
AVSS_A
DAP
DACA_9
65
0.1PF
DACA_10
GND
AVEE
DACA_11
0.1PF
17
AVEE
AVSS_A
AVSS_B
AVSS_C
AVSS_D
Control Connection
(DAC Bank A&B)
Figure 58. AMC7832 Example Schematic
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Typical Application (continued)
9.2.2 Design Requirements
The AMC7832 Example Schematic uses most of the following design parameters.
Table 54. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
AVCC
AVEE
IOVDD
DVDD
AVDD
5V
-12V
3.3V
5V
5V
ADC Bipolar inputs
ADC Unipolar inputs
(ADC0 – ADC11)
(LV_ADC12 – LV_ADC16)
-12.5 to +12.5-V input range
0 to +5-V range
DAC Output voltage Ranges
VRANGEA: GND
VRANGEB: GND
VRANGEC: 2.5V (REF_OUT2)
VRANGED: 2.5V (REF_OUT2)
[0 to +5-V Range]
[0 to +5-V Range]
[-10 to 0-V Range]
[-10 to 0-V Range]
Remote temperature sensing
IC Temperature sensor (LM50) or thermistor
9.2.3 Detailed Design Procedure
The following displays a set of parameters and concepts that will facilitate the design process:
• AVCC and AVEE voltage values
• ADC input voltage range
• DAC Output voltage Ranges
• Remote temperature applications
9.2.3.1 ADC Input Conditioning
The AMC7832 has a single ADC core that features a multi-channel multiplexer input stage to a successive
approximation register (SAR) ADC. The analog inputs are separated into two input classes: bipolar ADC inputs
(high-voltage) and unipolar ADC Inputs (low-voltage). The high-voltage analog inputs (ADC_0 – ADC_11) feature
a -12.5-V to +12.5-V input range, while the low-voltage analog inputs (LV_ADC12 – LV_ADC16) accept a fullscale range of 0 to 2 x VREF (VREF corresponds to a +2.5-V internal reference to the ADC block, and is externally
available on the REF_CMP pin). For additional noise filtering, a 4.7-µF capacitor is recommended between the
REF_CMP and GND. The value of this cap must exceed 470nF to ensure reference stability. A high-quality
ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and very low
dissipation factor.
During conversion the input current per channel will vary with the total update time which is determined by the
number and type of channels (NCH) and the conversion rate setting CONV-RATE in the ADC Configuration
register (address 0x10). This information is displayed in Table 55.
IIN = FS × DV × CIN
(5)
Where:
CIN: Internal ADC input channel capacitance
ΔV : The maximum voltage difference between analog inputs
FS = f(CONVRATE, NCHBIPOLAR, NCHUNIPOLAR) = 1/TS
The total update time (TS) can be determined from Table 55.
Table 55. ADC Update Time per Input Channel
56
CONV-RATE[1:0]
TS (μs) / CHANNEL
UNIPOLAR INPUT CHANNEL
TS (μs) / CHANNEL
BIPOLAR INPUT CHANNEL
TS (μs)
TEMPERATURE SENSOR CHANNEL
00
11.5
34.5
256
01
23
34.5
256
10
34.5
34.5
256
11
69
69
256
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To reduce DC error in sampling, it is recommended to decrease the ADC input impedance and reduce any input
capacitance to ground. Increasing the input capacitance essentially increases CIN, and therefore increases the
required amount of input current (IIN).
In applications where the signal source has high impedance, it is recommended that the analog input is buffered
before applying to the ADC channel.
Special care must be taken when biasing the two input classes, as both classes have different voltages – with
respect to GND – that they cannot exceed. These voltage values are located in Absolute Maximum Ratings.
9.2.3.2 DAC Output Range Selection
The AMC7832 contains 12 DACs that are arranged by different DAC banks, where each channel within a bank
shares a common programmable voltage range. Each DAC bank is fully programmable with up to three different
voltage ranges: -10 to 0-V, 0 to +10-V, and 0 to +5-V. The VRANGE terminals combined with the DAC
configuration register sets the different DAC voltage ranges.
The output buffer is capable of generating rail-to rail voltages on its output, giving an output range of AVSS to
AVCC. The maximum source and sink capability of this internal amplifier is listed in the Electrical Characteristics
DAC Output Characteristics.
The graphs listed in the Application plots section illustrate the relationship of both stability and settling time with
different capacitive and resistive loading structures.
9.2.3.3 Temperature Sensing Applications
The AMC7832 contains one local temperature and 5 low-voltage unipolar channels that are easily configurable to
remote temperature sensor circuits. The integrated temperature sensor and analog input registers automatically
update with every conversion. An example of a remote temperature sensor connection is displayed in Figure 59.
The temperature sensor described is a LM50, a high precision integrated-circuit temperature sensor that can
sense a -40°C to +125°C temperature range using a single positive supply. The full-scale output of the
temperature sensor ranges from +100mV to +1.75V for a -40°C to +125°C temperature range. In an extremely
noisy environment it may be necessary to add some filtering to minimize noise pickup. A typical recommended
value for the bypass capacitor is 0.1µF from V+ to GND. A high-quality ceramic type NP0 or X7R is
recommended for its optimal performance across temperature, and very low dissipation factor.
LM50
DVDD
4
0.1PF
V+
VO 3
LV_ADC15
1
NC
GND
2
5
Figure 59. External Remote Temperature IC (LM50) Connected to AMC7832 (LV_ADC15) Input Pin
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9.2.3.4 Application Curves
15
15
10nF, Rising Edge
10nF, Falling Edge
10
200pF, Rising Edge
5
0
±5
±10
200pF, Falling Edge
5
0
±5
±10
±15
±15
0
5
10
15
20
Time (µs)
25
0
5
10
15
20
Time (µs)
C001
T = 25°C, Code 0x400 to 0xC00 to within 1/2 LSB
25
C001
T = 25°C, Code 0xC00 to 0x400 to within 1/2 LSB
Figure 60. Settling Time vs Load Capacitance
58
DAC Output Error (LSB)
DAC Output Error (LSB)
10
Figure 61. Settling Time vs Load Capacitance
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10 Power Supply Recommendations
The preferred (not required) order for applying power is IOVDD, DVDD/AVDD and then AVCC/AVEE. When power
sequencing, ensure that all digital terminals are not powered, or in an active state while IOVDD ramps. This can
be accomplished by attaching 10-kΩ pull-up resistors to IOVDD, or pull-down resistors to DGND.
The supply voltage ranges are specified in the Recommended Operating Conditions but are repeated here for
convenience.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE RANGE
AVDD
4.5
5
5.5
V
DVDD
DVDD must be equal to AVDD
4.5
5
5.5
V
IOVDD
IOVDD must be equal or less than DVDD
1.8
5.5
V
AVCC
4.5
12
12.5
V
AVEE
–12.5
–12
0
V
AVSSA,B,C,D
AVEE
0
V
105
°C
OPERATING RANGE
Specified temperature
range
–40
25
All registers initialize to the default values after these supplies have been established. Communication with the
AMC7832 will be valid after a 250-µS maximum power-on reset delay. The default state of all analog blocks is off
as determined by the power-down registers (0xB2 and 0xB3). Before writing to this register, a hardware reset
should be issued to ensure specified operation of the AMC7832. Communication to the AMC7832 will be valid
after a maximum 250-µS reset delay from the rising edge of RESET.
If DVDD falls below +4.5-V, the minimum supply value of DVDD, either a hardware or power-on reset should be
issued before proper operation can be resumed.
When powered on, the internal POR circuit invokes a power-on reset, which performs the equivalent function of
the RESET terminal. To ensure a POR, DVDD must start from a level below 750-mV.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
All Power Supply terminals should be bypassed to ground with a low ESR ceramic bypass capacitor. The
typical recommended bypass capacitance is 10-µF ceramic with a X7R or NP0 dielectric.
To minimize interaction between the analog and digital return currents, the digital and analog sections should
have separate ground planes that eventually connect at some point.
To reduce noise on the internal reference, a 4.7-µF capacitor is recommended between the REF_CMP and
GND.
A high-quality ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and
very low dissipation factor.
11.2 Layout Example
Bypass Capacitor
close to AVCC
DAC_C0
ADC_2
AVSS_C
52
ADC_1
DAC_C1
53
49
VRANGE_C
54
ADC_0
REF_OUT2
55
50
AVCC_CD
56
51
DAC_D2
57
DAC_D3
58
VRANGE_D
60
AGND3
AVSS_D
61
59
DAC_D4
62
43
LV_ADC14
SCLK
7
42
LV_ADC15
CS
8
41
LV_ADC16
GPIO0/ALARMIN
9
40
ADC_6
GPIO1/ALARMOUT
10
39
ADC_7
GPIO2/ADCTRIG
11
38
ADC_8
GPIO3/DAV
12
37
ADC_9
GPIO4
13
36
ADC_10
GPIO5
14
35
ADC_11
GPIO6
15
34
AVDD2
GPIO7
16
33
0.1uF
32
AGND2
0.1uF
REF_CMP
AVDD1
REF_OUT1
DAC_B6
AVSS_B
DAC_B7
VRANGE_B
AVCC_AB
AGND1
DAC_A8
DAC_A9
VRANGE_A
AVSS_A
DAC_A10
17
AVEE
0.1uF
DAC_A11
Bypass Capacitor
close to AVEE
31
6
30
LV_ADC13
SDI
29
44
28
5
27
LV_ADC12
SDO
26
45
25
4
24
ADC_5
RESET
23
46
22
3
21
ADC_4
IOVDD
20
ADC_3
47
19
48
2
18
1
DVDD
DGND
0.1uF
DAC_D5
0.1uF
63
Bypass Capacitor
close to DVDD
64
0.1uF
0.1uF
Bypass Capacitors
close to AVDD
0.1uF
Compensation Capacitor
close to REF-CMP pin
Figure 62. AMC7832 Example Board Layout
60
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Layout Example (continued)
49
51
50
52
55
54
56
57
59
58
60
61
63
62
64
DGND
53
Recommended:
Split planes on DGND and AGND. (Minimize
interaction between digital and analog return
currents.)
1
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
32
31
30
29
28
27
26
25
24
23
22
33
21
16
20
34
19
35
15
18
14
17
Ground planes should be
connected with small trace
connection or external jumper.
48
2
AGND
Figure 63. AMC7832 Example Board Layout – Ground Planes
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49
51
50
52
53
55
54
56
57
59
58
60
61
63
62
64
Layout Example (continued)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
DVDD and AVDD Split
Planes
32
31
30
29
28
27
26
25
24
23
22
33
21
16
20
34
19
35
15
18
14
17
DVDD
AVDD
Figure 64. AMC7832 Example Board Layout – Power Planes
62
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Layout Example (continued)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AVEE and AVCC Split Planes
33
32
34
16
31
35
15
30
36
14
29
37
13
28
38
12
27
39
11
26
40
10
25
41
9
24
42
8
23
43
7
22
44
6
21
45
5
20
46
4
19
47
3
18
48
2
17
1
AVCC
AVEE
Figure 65. AMC7832 Example Board Layout – Analog Power Planes
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
64
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AMC7832IPAP
ACTIVE
HTQFP
PAP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC7832
AMC7832IPAPR
ACTIVE
HTQFP
PAP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC7832
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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