AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
Analog Monitor and Control Circuit
with 10-Bit, Multi-Channel ADC and Four DACs, Temperature
Sensor, and 12 GPIOs
Check for Samples: AMC7891
FEATURES
APPLICATIONS
•
•
•
•
•
1
23
•
•
•
•
•
•
•
•
10-Bit, 500-kSPS SAR ADC:
– 8 External Analog Inputs
– VREF, 2 × VREF Input Ranges
Four 10-Bit Monotonic DACs:
– 0 to 5-V Output Range
– Up to 10-mA Sink and Source Capability
– Power-On Reset to 0 V
Internal 2.5-V Reference
Internal Temperature Sensor:
– –40°C to +125°C Operation
– Accuracy of ±2.5°C
12 General-Purpose I/O Ports:
– 1.8-V to 5.5-V Operation
Low-Power SPI™-Compatible Serial Interface:
– 4-Wire Mode, 1.8-V to 5.5-V Operation
– SCLK up to 30 MHz
Temperature Range: –40°C to +105°C
Low Power: 32.5 mW at 5 V, Full Operating
Conditions
Space-Saving Package: 36-pin,
6-mm x 6-mm QFN
AMC7891
DESCRIPTION
The AMC7891 is a highly-integrated, low-power,
complete analog monitoring and control system in a
very small package.
For monitoring functions, the AMC7891 has 8
uncommitted inputs multiplexed into a 10-bit SAR
analog-to-digital converter (ADC) and an accurate
on-chip temperature sensor. Control signals are
generated through four, independent, 10-bit
digital-to-analog converters (DACs). Additional digital
signal monitoring and control is accomplished through
twelve configurable GPIOs. An internal reference can
be used to drive the ADC and DACs.
Communication to the device is performed through a
versatile, four-wire serial interface compatible with
industry-standard
microprocessors
and
microcontrollers. The serial interface can operate at
clock rates up to 30 MHz, allowing quick access to
critical system data.
The device is characterized for operation over the
temperature range of –40ºC to 105ºC and is available
in a very small, 36-pin, 6-mm x 6-mm QFN package.
2.5-V Reference
ADC
DAC
DAC
DAC
Serial
Interface
Serial Interface
TEMP
SENSOR
GPIO Control
Four DAC Outputs
Eight Analog Inputs
DAC
MUX
Cellular Base Stations
RF Communication Systems
Optical Networks
General-Purpose Monitor and Control
The AMC7891’s low power, small size and
high-integration make it an ideal low-cost, bias control
circuit for modern RF transistor modules such as the
power amplifiers (PA) and low-noise amplifiers (LNA)
found in RF communication systems. The AMC7891
feature set is similarly beneficial in general purpose
monitor and control systems.
For applications that require a different channel
count, additional features, or converter resolutions,
Texas Instruments offers a complete family of Analog
Monitor and Control (AMC) Products. See
http://www.ti.com/amc.
12 GPIOs
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
REF
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
RHH PACKAGE
QFN-36
(TOP VIEW)
36
35
34
33
32
31
30
29
28
DGND
3
25
GPIOA2
GPIOVDD
4
24
GPIOA3
SPIVDD
5
23
GPIOB0
CS
6
22
GPIOB1
SCLK
7
21
GPIOB2
SDI
8
20
GPIOB3
SDO
9
19
DAV
DACOUT3
10
11
12
13
14
15
16
17
18
GPIOC0
GPIOA1
GPIOC1
26
GPIOC2
2
GPIOC3
AGND1
AGND2
GPIOA0
DACOUT0
27
DACOUT1
1
DACOUT2
AVDD
AMC7891 Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
AVDD
I
Analog supply voltage. (4.75 V to 5.5 V)
2
AGND1
I
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1 and
AGND2 to the same potential, AGND.
3
DGND
I
Digital ground. Ground reference point for all digital circuitry on the device. Ideally, AGND and DGND should
be at the same potential and must not differ by more than 0.3 V.
4
GPIOVDD
I
GPIO supply voltage. (1.8 V to 5.5 V)
Sets the GPIO operating voltage and threshold levels.
5
SPIVDD
I
Serial interface supply voltage. (1.8 V to 5.5 V)
Sets the serial interface operating voltage and threshold levels.
6
CS
I
Active low serial data enable. Schmitt-trigger logic input.
This input is the frame synchronization signal for the serial data. When this signal goes low, it enables the
input shift register and data is sampled on subsequent falling clock edges. The DAC output and register
settings update following the 24th clock. If CS goes high before the 23th clock edge, the command is
ignored.
2
7
SCLK
I
Serial interface clock. Schmitt-trigger logic input.
Maximum SCLK rate is 30MHz.
8
SDI
I
Serial interface data input. Schmitt-trigger logic input.
Data is clocked into the input shift register on each falling edge of SCLK.
9
SDO
O
Serial interface data output. The SDO pin is in high impedance when CS is high.
Data is clocked out of the input shift register on each rising edge of SCLK.
10
DACOUT3
O
DAC3 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
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AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
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AMC7891 Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
11
DACOUT2
O
DAC2 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
12
DACOUT1
O
DAC1 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
13
DACOUT0
O
DAC0 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
14
AGND2
I
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1 and
AGND2 to the same potential, AGND.
15
GPIOC3
I/O
General purpose digital I/O C3. Maximum voltage is set by GPIOVDD
16
GPIOC2
I/O
General purpose digital I/O C2. Maximum voltage is set by GPIOVDD
17
GPIOC1
I/O
General purpose digital I/O C1. Maximum voltage is set by GPIOVDD
18
GPIOC0
I/O
General purpose digital I/O C0. Maximum voltage is set by GPIOVDD
19
DAV
O
ADC data available indicator. Open-drain, active low output.
In direct-mode, DAV goes low when an ADC conversion cycle finishes. In auto-mode a 1µs pulse appears
on this pin when the conversion cycle finishes (see ADC Operation for details). DAV stays high when
deactivated. If used, an external 10 kΩ pull-up resistor to GPIOVDD is required. If unused, the pin can be
connected to DGND.
20
GPIOB3
I/O
General purpose digital I/O B3. Maximum voltage is set by GPIOVDD
21
GPIOB2
I/O
General purpose digital I/O B2. Maximum voltage is set by GPIOVDD
22
GPIOB1
I/O
General purpose digital I/O B1. Maximum voltage is set by GPIOVDD
23
GPIOB0
I/O
General purpose digital I/O B1. Maximum voltage is set by GPIOVDD
24
GPIOA3
I/O
General purpose digital I/O A3. Maximum voltage is set by GPIOVDD
25
GPIOA2
I/O
General purpose digital I/O A2. Maximum voltage is set by GPIOVDD
26
GPIOA1
I/O
General purpose digital I/O A1. Maximum voltage is set by GPIOVDD
27
GPIOA0
I/O
General purpose digital I/O A1. Maximum voltage is set by GPIOVDD
28
AIN0
I
Uncommitted analog input 0. (0 V to 5 V)
29
AIN1
I
Uncommitted analog input 1. (0 V to 5 V)
30
AIN2
I
Uncommitted analog input 2. (0 V to 5 V)
31
AIN3
I
Uncommitted analog input 3. (0 V to 5 V)
32
AIN4
I
Uncommitted analog input 4. (0 V to 5 V)
33
AIN5
I
Uncommitted analog input 5. (0 V to 5 V)
34
AIN6
I
Uncommitted analog input 6. (0 V to 5 V)
35
AIN7
I
Uncommitted analog input 7. (0 V to 5 V)
36
REF
I/O
Used as external ADC reference input when the internal reference buffer is disabled in register AMC_power,
ref_on = ‘0’ (default). A decoupling capacitor is recommended between the external reference output an
AGND for noise filtering.
Used as internal reference output when the internal reference buffer is enabled in register AMC_power,
ref_on = ‘1’. Requires a 4.7 µF decoupling capacitor to AGND when used as reference output. An external
buffer amplifier with high impedance input is required to drive an external load.
–
THERMAL
PAD
–
The thermal pad is located on the package underside. Connect to the board ground plane using multiple
vias.
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AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
AMC7891
Internal Reference
(2.5V)
REF
ref_on
AIN0
AIN1
DAC0
10-Bit
AIN3
AIN4
Multiplexer
AIN2
DACOUT0
10-Bit
ADC
dac0_clear
DAC1
10-Bit
AIN5
AIN6
DACOUT1
Temperature
Sensor
dac1_clear
AIN7
DAC2
10-Bit
DACOUT2
Configuration
Registers
DAV
dac2_clear
DAC3
10-Bit
DACOUT3
dac3_clear
SCLK
SDI
Serial Peripheral
Interface
CS
AVDD
SDO
GPIOVDD
GPIO Control
4
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DGND
AGND2
AGND1
GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
GPIOA0
SPIVDD
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): AMC7891
AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
ORDERING INFORMATION (1)
TA
–40°C to 105°C
(1)
(2)
(3)
PACKAGE
DRAWING/TYPE (2) (3)
TRANSPORT
MEDIA
RHH / 36-QFN Quad Flatpack No-Lead
Tape and Reel
ORDER CODE
AMC7891SRHHT
AMC7891SRHHR
QUANTITY
250
2000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
Thermal Pad Size: 4.39 mm x 4.39 mm
MSL Peak Temperature: Level-3-260C-168 HR
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
Supply voltage range
Pin voltage range
MAX
AVDD to AGND (2)
–0.3
6
V
GPIOVDD to DGND
–0.3
6
V
SPIVDD to DGND
–0.3
6
V
AGND to DGND
–0.3
0.3
V
AIN[0:7], DACOUT[0:3], REF to AGND
–0.3
AVDD + 0.3
V
CS, SCLK, SDI to DGND
–0.3
6
V
SDO to DGND
–0.3
SPIVDD + 0.3
V
GPIOA[0:3], GPIOB[0:3], GPIOC[0:3] to DGND
–0.3
GPIOVDD + 0.3
V
DAV to DGND
–0.3
6
V
–40
105
°C
–40
150
°C
Human body model (HBM)
2.5
kV
Charged device model (CDM)
1.0
kV
Operating free-air temperature range, TA: AMC7891
(3) (4)
Storage temperature range
ESD ratings:
(1)
(2)
(3)
(4)
UNIT
MIN
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
AGND1 and AGND2 must be tied together as AGND.
Air flow or heat sinking reduces θJA and may be required for sustained operation at 105°C and maximum operating conditions.
Soldering the device thermal pad to the board ground plane is strongly recommended.
THERMAL INFORMATION
AMC7891
THERMAL METRIC (1)
RHH PACKAGE
UNITS
36 PINS
θJA
Junction-to-ambient thermal resistance
30.6
θJCtop
Junction-to-case (top) thermal resistance
16.0
θJB
Junction-to-board thermal resistance
5.3
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
5.3
θJCbot
Junction-to-case (bottom) thermal resistance
0.8
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
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ELECTRICAL CHARACTERISTICS (DAC SPECIFICATIONS)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD,
TA = –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.05
±1
LSB
STATIC ACCURACY
Resolution
10
Bits
INL
Relative accuracy
DNL
Differential nonlinearity
Specified monotonic
±0.1
±1
LSB
Offset error
Code 0x008
±0.5
±5
mV
±0.025
±0.2
Gain error
±1
ppm/°C
Gain temperature coefficient
±1
ppm/°C
DAC OUTPUT
(1)
Full scale output voltage range
Output voltage settling time
0
Transition: Code 0x008 to 0x3F8 to within 1/2 LSB,
CL = 2 nF, RL = ∞
Slew rate
V
5
µs
2
V/µs
Full-scale current shorted to ground or pulled to AVDD
±30
mA
Load current
Source and/or sink within 300 mV of supply
±10
mA
Capacitive load stability
RL = ∞
10
nF
1
Ω
10
mV
Power-on overshoot
AVDD 0 to 5 V, 2 ms ramp
Glitch energy
Transition: Code 0x1FF to 0x200; 0x200 to 0x1FF
0.15
nV-s
TA = 25°C, 1 kHz
260
nV/√Hz
20
µVPP
Output noise
6
AVDD
Short circuit current
DC output impedance
(1)
%FSR
Offset temperature coefficient
Integrated noise from 0.1 Hz to 10 Hz
Specified by design and characterization. Not tested during production.
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ELECTRICAL CHARACTERISTICS – (ADC SPECIFICATIONS)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD,
TA = –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.1
±1
LSB
DC ACCURACY
Resolution
10
INL
Integral nonlinearity
DNL
Differential nonlinearity
Bits
±0.1
±1
LSB
Offset error
±0.5
±2
LSB
Offset error match
±0.4
Gain error
±0.5
Gain error match
±0.4
LSB
500
kSPS
16
µs
Specified monotonic
LSB
±2
LSB
CONVERSION TIME
ADC conversion rate
Autocycle update rate
All 8 ADC input channels enabled
Throughput rate
SCLK ≥ 12 MHz, single analog channel
Conversion delay
Delay from trigger to conversion start
500
kSPS
2
4
µs
AGND – 0.2
AVDD + 0.2
V
V
ANALOG INPUT
Absolute input voltage range
Full scale input voltage range
Independent of gain setting
Gain = 1, adcn_gain = '0'
0
VREF
Gain = 2, adcn_gain = '1'
0
2 × VREF
Input capacitance (1)
V
40
DC input leakage current
pF
±1
Measured with ADC in Hold mode
µA
AC PERFORMANCE
SFDR
Spurious Free Dynamic Range
fIN = 1 kHz, –1 dBFS sine wave
SNR
Signal to Noise Ratio
SINAD
Signal to Noise+Distortion Ratio
Total Harmonic Distortion
THD
76
dBc
fIN = 1 kHz, –1 dBFS sine wave
61
dBc
fIN = 1 kHz, –1 dBFS sine wave
60.5
dBc
fIN = 1 kHz, –1 dBFS sine wave, Measured
up to the fifth harmonic
75
dBc
Reference output voltage
Internal ADC reference buffered output at
REF pin
2.5
V
Reference buffer power
AVDD = 5 V
360
µA
10
ppm/°C
INTERNAL ADC REFERENCE
VREF
(2)
Reference temperature coefficient
EXTERNAL ADC REFERENCE
VREF
Reference input voltage
Input resistance
(1)
External ADC reference input to REF pin
0.3
VREF = 5 V, AIN = 5 V
AVDD
20
V
kΩ
TEMPERATURE SENSOR
–40
Operating range
Accuracy
TA = –40°C to 125°C, AVDD = 5 V
Resolution
LSB size
Conversion time
(1)
(2)
±1
125
°C
±2.5
°C
0.125
°C
15
ms
Specified by design. Not tested during production.
Use an external buffer amplifier with high impedance input to drive any external load.
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ELECTRICAL CHARACTERISTICS – GENERAL SPECIFICATIONS
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD,
TA = –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL PURPOSE I/O
VIH
VIL
VOH
VOL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input capacitance
GPIOVDD = 1.8 V
GPIOVDD = 3.3 to 5.5 V
0.7×GPIOVDD
V
2.1
V
GPIOVDD = 1.8 V
0.3
V
GPIOVDD = 3.3 to 5.5 V
0.8
V
Iload = 1.6 mA, GPIOVDD = 1.8V, All GPIOs
loaded and set to '1'
GPIOVDD - 0.25
V
Iload = 1.6 mA, GPIOVDD = 3.3 to 5.5V, All
GPIOs loaded and set to '1'
GPIOVDD - 0.2
V
Iload = -1.6 mA, All GPIOs loaded
0.4
(1)
High impedance output
capacitance (1)
V
1
pF
1
pF
LOGIC INPUTS: CS, SDI, SCLK
VIH
VIL
High-level input voltage
Low-level input voltage
SPIVDD = 1.8 V
SPIVDD = 3.3 to 5.5 V
0.7×SPIVDD
V
2.1
V
SPIVDD = 1.8 V
0.3
V
SPIVDD = 3.3 to 5.5 V
0.7
V
±1
µA
Input current
Input capacitance
(1)
High impedance output
capacitance (1)
1
pF
1
pF
LOGIC OUTPUT: SDO
VOH
High-level output voltage
Iload = 1.6 mA
VOL
Low-level output voltage
Iload = -1.6 mA
SPIVDD - 0.2
0.4
V
V
Iload = -2 mA
0.4
V
5.5
V
LOGIC OUTPUT: DAV
VOL
Low-level output voltage
POWER REQUIREMENTS
AVDD
IDD
4.75
5
GPIOVDD
1.8
5.5
V
SPIVDD
1.8
5.5
V
10
mA
Total supply current, AVDD +
GPIOVDD + SPIVDD
Power consumption
Operating mode (2)
6.5
Power down mode
1.25
2
mA
Operating mode (2)
32.5
55
mW
Power down mode
6.25
11
mW
25
105
°C
OPERATING RANGE
–40
Specified temperature range
(1)
(2)
8
Specified by design. Not tested in production.
AVDD = GPIOVDD = SPIVDD = 5 V. No DAC load, all DACs at 0x200 code and ADC at the fastest auto conversion rate.
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TIMING SPECIFICATIONS (1) (2)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD,
TA = –40°C to 105°C (unless otherwise noted).
PARAMETER
fSCLK
TEST CONDITIONS
SCLK frequency
MAX
UNIT
SPIVDD = 5.5 V
MIN
TYP
30
MHz
SPIVDD = 2.7 V
15
MHz
SPIVDD = 1.8 V
10
MHz
tR
Input rise time
10% to 90% of SPIVDD
2
ns
tF
Input fall time
10% to 90% of SPIVDD
2
ns
t1
SCLK cycle time
t2
t3
SCLK high time
SCLK low time
SPIVDD = 5.5 V
33
ns
SPIVDD = 2.7 V
66
ns
SPIVDD = 1.8 V
100
ns
SPIVDD = 5.5 V
13
ns
SPIVDD = 2.7 V
30
ns
SPIVDD = 1.8 V
50
ns
SPIVDD = 5.5 V
13
ns
SPIVDD = 2.7 V
26
ns
SPIVDD = 1.8 V
40
ns
5
ns
t4
Frame start time
CS falling edge to SCLK rising edge
t5
SDI setup time
SDI valid to falling edge of SCLK
4
ns
t6
SDI hold time
SDI valid after falling edge of SCLK
12
ns
t7
Frame stop time
SCLK falling edge to CS rising edge
15
ns
t8
CS high time
t9
SDO delay
t10
Wait time
(1)
(2)
50
ns
SPIVDD = 5.5 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 4 ns
5
16
ns
SPIVDD = 2.7 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 5 ns
6
22
ns
SPIVDD = 1.8 V, CL = 10 pF, 2 ns ≤ tR,F(SDO) ≤ 8 ns
8
39
ns
CS rising edge to next SCLK rising edge
5
ns
Specified by design. Not tested during production.
Digital inputs and outputs timed from a voltage level of SPIVDD/2.
TIMING INFORMATION
t8
t4
t7
CS
t1
SCLK
t10
tf
t3
t2
tr
SDI
Bit 23
t5
Bit 1
Bit 0
t6
Figure 1. Serial Interface Write Timing Diagram
t8
t4
t7
CS
tf
t1
tr
t3
t2
SCLK
Read Command
SDI
Bit 23
t5
SDO
Any Command
Bit 0
t6
Bit 23
Bit 1
Bit 0
Bit 23
Bit 1
Bit 0
t9
Data read from the register selected in previous operation
Figure 2. Serial Interface Read Timing Diagram
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TYPICAL CHARACTERISTICS: DAC
1.000
1.000
0.750
0.750
0.500
0.500
0.250
0.250
DNL (LSB)
INL (LSB)
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
0.000
−0.250
−0.500
0.000
−0.250
−0.500
−0.750
−0.750
T=25ºC
−1.000
0
128
256
384
512
Code
640
768
896
T=25ºC
−1.000
1024
640
768
896
1024
G002
0.250
0.000
−0.250
INL Min
−0.500
DNL Max
0.500
DNL (LSB)
INL (LSB)
512
Code
0.750
INL Max
0.500
0.250
0.000
−0.250
DNL Min
−0.500
−0.750
−0.750
−20
0
20
40
60
Temperature (°C)
80
100
120
−1.000
−40
−20
0
G003
Figure 5. DAC INL vs. TEMPERATURE
20
40
60
Temperature (°C)
80
100
120
G004
Figure 6. DAC DNL vs. TEMPERATURE
5
200
4
150
Gain Error (m%FSR)
3
Offset Error (mV)
384
1.000
0.750
2
1
0
−1
−2
−3
100
50
0
−50
−100
−150
−4
−20
0
20
40
60
Temperature (°C)
80
100
120
−200
−40
G005
Figure 7. DAC OFFSET ERROR vs. TEMPERATURE
10
256
Figure 4. DAC DIFFERENTIAL NON-LINEARITY
1.000
−5
−40
128
G001
Figure 3. DAC INTEGRAL NON-LINEARITY
−1.000
−40
0
−20
0
20
40
60
Temperature (°C)
80
100
120
G006
Figure 8. DAC GAIN ERROR vs. TEMPERATURE
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TYPICAL CHARACTERISTICS: DAC (continued)
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
5.000
2.502
Output Voltage (V)
Output Voltage (V)
4.950
2.501
2.500
2.499
4.900
4.850
4.800
4.750
Code = 0x200
2.498
−10
−8
−6
−4
−2
0
2
4
Load Current (mA)
6
8
Code = 0x3FF
4.700
10
0
1
2
3
G007
Figure 9. DAC OUTPUT VOLTAGE vs. LOAD CURRENT
4
5
6
7
Source Current (mA)
8
9
10
G008
Figure 10. DAC SOURCE CURRENT
0.300
Output Voltage (V)
0.250
0.200
0.150
0.100
0.050
Code = 0x000
0.000
0
1
2
3
4
5
6
Sink Current (mA)
7
8
9
10
G009
Figure 11. DAC SINK CURRENT
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TYPICAL CHARACTERISTICS: ADC
1.000
1.000
0.750
0.750
0.500
0.500
0.250
0.250
DNL (LSB)
INL (LSB)
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
0.000
−0.250
−0.500
0.000
−0.250
−0.500
−0.750
−0.750
T=25ºC
−1.000
0
128
256
384
512
Code
640
768
896
T=25ºC
−1.000
1024
640
768
896
1024
G014
0.250
0.000
−0.250
INL Min
−0.500
DNL Max
0.500
DNL (LSB)
INL (LSB)
512
Code
0.750
INL Max
0.500
0.250
0.000
−0.250
DNL Min
−0.500
−0.750
−0.750
−20
0
20
40
60
Temperature (°C)
80
100
−1.000
−40
120
1.500
1.500
1.000
1.000
Gain Error (LSB)
2.000
0.500
0.000
−0.500
−1.500
100
100
120
G016
0.000
−1.500
80
80
−0.500
−1.000
20
40
60
Temperature (°C)
20
40
60
Temperature (°C)
0.500
−1.000
0
0
Figure 15. ADC DNL vs. TEMPERATURE
2.000
−20
−20
G015
Figure 14. ADC INL vs. TEMPERATURE
Offset Error (LSB)
384
1.000
0.750
120
−2.000
−40
G017
Figure 16. ADC OFFSET ERROR vs. TEMPERATURE
12
256
Figure 13. ADC DIFFERENTIAL NON-LINEARITY
1.000
−2.000
−40
128
G013
Figure 12. ADC INTEGRAL NON-LINEARITY
−1.000
−40
0
−20
0
20
40
60
Temperature (°C)
80
100
120
G017
Figure 17. ADC GAIN ERROR vs. TEMPERATURE
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TYPICAL CHARACTERISTICS: ADC (continued)
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
2.000
2.000
1.500
1.500
1.000
1.000
Gain Error (LSB)
Offset Error (LSB)
(unless otherwise noted)
0.500
0.000
−0.500
−1.000
0.500
0.000
−0.500
−1.000
−1.500
−1.500
AVDD = 5 V
−2.000
0.0
0.5
1.0
1.5 2.0 2.5 3.0 3.5
External ADC Vref (V)
4.0
4.5
AVDD = 5 V
−2.000
0.0
5.0
2.505
2.505
2.504
2.504
2.503
2.503
2.502
2.502
2.501
2.500
2.499
2.497
2.496
2.496
2.495
2.5
2.495
−40
5.0
4.5
5.0
G020
2.499
2.498
4.5
4.0
2.500
2.497
4.0
AVDD (V)
1.5 2.0 2.5 3.0 3.5
External ADC Vref (V)
2.501
2.498
3.5
1.0
Figure 19. ADC GAIN ERROR vs. REFERENCE VOLTAGE
Reference (V)
Reference (V)
Figure 18. ADC OFFSET ERROR vs. REFERENCE
VOLTAGE
3.0
0.5
G019
5.5
15 units
−20
0
20
40
60
Temperature (°C)
G021
Figure 20. ADC INTERNAL REFERENCE vs. AVDD
80
100
120
G022
Figure 21. ADC INTERNAL REFERENCE vs.
TEMPERATURE
2.5
2.0
1.5
Error (°C)
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−40
15 units
−20
0
20
40
60
Temperature (°C)
80
100
120
G000
Figure 22. TEMPERATURE SENSOR ERROR vs TEMPERATURE
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THEORY OF OPERATION
SERIAL INTERFACE
The AMC7891 is controlled through a flexible four-wire serial interface compatible with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers of the AMC7891
with clock rates up to 30 MHz.
The interface is compatible with most synchronous transfer formats and is configured as a 4 pin interface. SCLK
is the serial interface input clock and CS is serial interface enable. Data is input into SDI and latched into the
24-bit wide SPI shift register on SCLK falling edges, while CS is low. Data is clocked out of SDO on SCLK rising
edges, while CS is low. The contents of the SPI shift register are loaded into the device internal register on a CS
rising edge after some delay. When CS is high, both SCLK and SDI inputs are blocked out and the SDO output
is in high-impedance state.
The serial interface works with both a continuous and a non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock to
latch the data.
Each SPI command is input to SDI and framed by signal CS (Serial Data Enable) asserted low. The frame’s first
byte into SDI is the instruction cycle which identifies the request as a read or write as well as the 7-bit address to
be accessed. The following two bytes in the frame form the data cycle.
Instruction Cycle
Data Cycle
CS
SCLK
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Serial Interface Command
Bit 23
R/W. Identifies the communication as a read or write command to the addressed register. Bit =
‘0’ sets the write operation. Bit = ‘1’ sets the read operation.
Bits[22:16]
A[6:0]. Register address; specifies the register to be accessed during the read or write
operation.
Bits[15:0]
D[15:0]. Data cycle bits.
If a write command, the data cycle bits are the values to be written to the register with address
A[6:0].
If a read command, the data cycle bits are don’t care values.
A read command causes an output on the SDO pin during the next SPI command cycle. The SDO read value
frame is formed by the previous communication instruction cycle and the data read from the specified register.
Table 1. Serial Data Format
SPI FRAME
Write Command
Frame
Read Command
Frame
Read Value Frame
14
PIN
SDI
SDO
SDI
SDO
SDI
SDO
INSTRUCTION CYCLE
DATA CYLE
Bit 23
Bits [22:16]
Bits [15:0]
0 (R/W)
A[6:0]
Data In[15:0]
Undefined or Read Value Frame depending on previous
command
1 (R/W)
A[6:0]
Don’t care
Undefined or Read Value Frame depending on previous
command
New Write or Read Command Frame
1 (R/W)
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A[6:0]
Data Out[15:0]
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The serial clock can be continuous or gated as long as there are exactly 24 falling clock edges within the frame.
A write command issued in frames whose width is not 24 bits is incorrect and ignored by the AMC7891. A read
command frame not equal to 24 bits may result in abnormal data on SDO and must be ignored by the host
processor. In order for another serial transfer to occur, CS must be brought low again to start a new cycle.
Figure 24 and Figure 25 show multiple write and read operations.
CS
SDI
SDO
W0
W1
W2
W3
XX
XX
XX
XX
Wn = Write Command for Register N
XX = Don’t care, undefined
Figure 24. Serial Interface Write Operation
CS
SDI
R0
SDO
XX
R1
D0
R2
D1
R3
Any Command
D2
D3
Rn = Read Command for Register N
Dn = Data from Register N
XX = Don’t care, undefined
Figure 25. Serial Interface Read Operation
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REGISTER MAP
The AMC7891 has 16-bit registers containing device configuration and conversion results. A 7-bit register
address indicates the proper register.
Table 2. Register Map
MSB
LSB
NAME
ADDR
DEFAULT
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
TEMP_data
0x00
0x0000
0
0
0
0
TEMP_config
0x0A
0x0008
0
0
0
0
0
0
0
0
0
0
0
0
temp_
en
TEMP_rate
0x0B
0x0007
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC0_data
0x23
0x0000
0
0
0
0
0
0
adc0_data(9:0)
ADC1_data
0x24
0x0000
0
0
0
0
0
0
adc1_data(9:0)
ADC2_data
0x25
0x0000
0
0
0
0
0
0
adc2_data(9:0)
ADC3_data
0x26
0x0000
0
0
0
0
0
0
adc3_data(9:0)
ADC4_data
0x27
0x0000
0
0
0
0
0
0
adc4_data(9:0)
ADC5_data
0x28
0x0000
0
0
0
0
0
0
adc5_data(9:0)
ADC6_data
0x29
0x0000
0
0
0
0
0
0
adc6_data(9:0)
ADC7_data
0x2A
0x0000
0
0
0
0
0
0
adc7_data(9:0)
DAC0_data
0x2B
0x0000
0
0
0
0
0
0
dac0_data(9:0)
DAC1_data
0x2C
0x0000
0
0
0
0
0
0
dac1_data(9:0)
DAC2_data
0x2D
0x0000
0
0
0
0
0
0
dac2_data(9:0)
DAC3_data
0x2E
0x0000
0
0
0
0
0
0
dac3_data(9:0)
DAC0_clear
0x2F
0x0000
0
0
0
0
0
0
dac0_clear(9:0)
DAC1_clear
0x30
0x0000
0
0
0
0
0
0
dac1_clear(9:0)
DAC2_clear
0x31
0x0000
0
0
0
0
0
0
dac2_clear(9:0)
DAC3_clear
0x32
0x0000
0
0
0
0
0
0
ioc2_
io
ioc1_
io
ioc0_
io
iob3_
io
iob2_
io
iob1_
io
iob0_
io
ioa3_
io
ioa2_
io
ioa1_
io
ioa0_
io
tempdata(11:0)
temp_rate(2:0)
dac3_clear(9:0)
GPIO_config
0x33
0x0000
0
0
0
0
ioc3_
io
GPIO_out
0x34
0x0000
0
0
0
0
ioc3_
out
ioc2_
out
ioc1_
out
ioc0_
out
iob3_
out
iob2_
out
iob1_
out
iob0_
out
ioa3_
out
ioa2_
out
ioa1_
out
ioa0_
out
GPIO_in
0x35
NA
0
0
0
0
ioc3_
in
ioc2_
in
ioc1_
in
ioc0_
in
iob3_
in
iob2_
in
iob1_
in
iob0_
in
ioa3_
in
ioa2_
in
ioa1_
in
ioa0_
in
AMC_config
0x36
0x2000
0
0
adc_
mode
adc_tr
ig
dac_lo
ad
resvd
adc_rate(1:0)
adc_r
eady
0
0
0
0
0
0
0
adc1_
en
resvd
adc2_
en
adc3_
en
resvd
adc4_
en
adc5_
en
adc6_
en
adc7_
en
0
0
0
0
0
adc2_
gain
adc3_
gain
adc4_
gain
adc5_
gain
adc6_
gain
adc7_
gain
0
0
0
0
0
0
0
0
dac2_
clear
dac1_
clear
dac0_
clear
ADC_enable
0x37
0x0000
0
adc0_
en
ADC_gain
0x38
0xFF00
adc0_
gain
adc1_
gain
DAC_clear
0x39
0x0000
0
0
0
0
0
0
0
0
0
0
0
0
dac3_
clear
DAC_sync
0x3A
0x0000
0
0
0
0
0
0
0
0
0
0
0
0
dac3_
sync
dac2_
sync
dac1_
sync
dac0_
sync
AMC_power
0x3B
0x0000
0
adc_o
n
ref_on
dac0_
on
dac1_
on
dac2_
on
dac3_
on
0
0
0
0
0
0
0
0
0
AMC_reset
0x3E
0x0000
reset(15:0)
AMC_ID
0x40
0x0044
device_id(15:0)
16
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REGISTER DESCRIPTIONS
Register name: temp_data – Address: 0x00, Default: 0x0000 (READ ONLY)
Register
Name
temp_data
Address
0x00
Bit
Name
Function
Default Value
15:12
11:0
Reserved
Reserved for factory use.
temp_data(11:0) Stores the temperature sensor reading in twos complement format.
0.125°C/LSB.
All zeros
0x000
Register name: temp_config – Address: 0x0A, Default: 0x0008 (READ/WRITE)
Register
Address Bit
Name
temp_config
0x0A
15:4
3
2:0
Name
Function
Default Value
Reserved
temp_en
Reserved
Reserved for factory use.
When set to ‘1’, the on-chip temperature sensor is enabled.
Reserved for factory use.
All zeros
1
All zeros
Register name: temp_rate – Address: 0x0B, Default: 0x0007 (READ/WRITE)
Register
Name
temp_rate
Address
0x0B
Bit
15:3
2:0
Name
Reserved
temp_rate(2:0)
Function
Default Value
Reserved for factory use.
Sets the temperature sensor ADC conversion time
temp_rate(2:0)
000
001
010
011
100
101
110
111
All zeros
111
Conversion time
128x
64x
32x
16x
8x
4x
2x
15 ms
Register name: ADCn_data – Address: 0x23 to 0x2A, Default: 0x0000 (READ ONLY) (1)
Register
Name
ADCn_
data
(1)
Address Bit
0x23 to
0x2A
15:10
9:0
Name
Function
Default Value
Reserved
Reserved for factory use.
adcn_data(9:0) Stores the 10-bit ADCn conversion results in straight binary format.
Input Channel
ADC Register Value
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
adc0_data(9:0)
adc1_data(9:0)
adc2_data(9:0)
adc3_data(9:0)
adc4_data(9:0)
adc5_data(9:0)
adc6_data(9:0)
adc7_data(9:0)
All zeros
All zeros
Register
Address
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
All ADCn_data registers are formatted in the manner shown here. n = 0, 1, …, 7
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Register name: DACn_data – Address: 0x2B to 0x2E, Default: 0x0000 (READ/WRITE) (1)
Register
Name
DACn_ data
Addres Bit
s
0x2B to 15:10
0x2E 9:0
Name
Reserved
dacn_data(9:0)
Function
Reserved for factory use.
Stores the 10-bit data to be loaded to the DACn latches in straight
binary format.
Output Channel
DAC Register
Value
dac0_data(9:0)
dac1_data(9:0)
dac2_data(9:0)
dac3_data(9:0)
DACOUT_0
DACOUT_1
DACOUT_2
DACOUT_3
(1)
Default
Value
All zeros
All zeros
Register
Address
0x2B
0x2C
0x2D
0x2E
All DACn_data registers are formatted in the manner shown here. n = 0, 1, …, 3
Register name: DACn_clear – Address: 0x2F to 0x32, Default: 0x0000 (READ/WRITE) (1)
Register
Name
DACn_ clear
(1)
Address
0x2F to
0x32
Bit
15:10
9:0
Name
Function
Reserved
dacn_clear(9:0
)
Reserved for factory use.
Stores the 10-bit data to be loaded to the DACn when cleared.
Straight binary format.
Output Channel
DAC Clear Value
DACOUT_0
DACOUT_1
DACOUT_2
DACOUT_3
dac0_clear(9:0)
dac1_clear(9:0)
dac2_clear(9:0)
dac3_clear(9:0)
Default
Value
All zeros
All zeros
Register
Address
0x2F
0x30
0x31
0x32
All DACn_data registers are formatted in the manner shown here. n = 0, 1, …, 3
Register name: GPIO_config – Address: 0x33, Default: 0x0000 (READ/WRITE)
Register
Name
GPIO_config
Address
Bit
0x33
15:12
11
10
9
8
7
6
5
4
3
2
1
0
18
Name
Function
Reserved
ioc3_io
Reserved for factory use.
When cleared to ‘0’ the corresponding GPIO is configured as an input and
set on high-impedance state (default).
ioc2_io
ioc1_io
ioc0_io
iob3_io
iob2_io
iob1_io
iob0_io
ioa3_io
ioa2_io
ioa1_io
ioa0_io
When set to ‘1’ the corresponding GPIO is configured as an output.
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Default
Value
All zeros
0
0
0
0
0
0
0
0
0
0
0
0
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Register name: GPIO_out – Address: 0x34, Default: 0x0000 (READ/WRITE)
Register
Name
GPIO_out
Address
Bit
0x34
15:12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Function
Reserved
ioc3_out
ioc2_out
ioc1_out
ioc0_out
iob3_out
iob2_out
iob1_out
iob0_out
ioa3_out
ioa2_out
ioa1_out
ioa0_out
Reserved for factory use.
If the corresponding GPIO is configured as an output in register
GPIO_config, 0x33, the value on this bit sets the digital output.
If the corresponding GPIO is configured as an input in register
GPIO_config, 0x33, this bit is a don’t care.
Default
Value
All zeros
0
0
0
0
0
0
0
0
0
0
0
0
Register name: GPIO_in – Address: 0x35, Default: NA (READ ONLY)
Register
Name
GPIO_in
Address
Bit
0x35
15:12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Function
Reserved
ioc3_in
Reserved for factory use.
If the corresponding GPIO is configured as an output in register
GPIO_config, 0x33, the value on this bit correspods to the digital output.
ioc2_in
ioc1_in
ioc0_in
iob3_in
iob2_in
iob1_in
iob0_in
ioa3_in
ioa2_in
ioa1_in
ioa0_in
Default
Value
All zeros
0
If the corresponding GPIO is configured as an output in register
GPIO_config 0x33, this bit matches the corresponding value in register
GPIO_out, 0x34.
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0
0
0
0
0
0
0
0
0
0
0
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Register name: AMC_config – Address: 0x36, Default: 0x2000 (READ/WRITE)
Register
Name
AMC_config
Address
0x36
Bit
Name
15:4
13
Reserved
adc_mode
12
adc_trig
11
dac_load
10
9:8
Reserved
adc_rate(1:0)
7
adc_ready
6:0
Reserved
Function
Reserved for factory use.
When set to ‘1’, the ADC is in Auto-mode conversion.
When cleared to ‘0’, the ADC is in Direct-mode conversion.
When set to ‘1’ triggers a new ADC conversion cycle. The bit is
cleared to ‘0’ automatically after the ADC conversion cycle starts.
When set to ‘1’ data is loaded into the DAC output channels set to
synchronous mode in register dac_sync, 0x3A.
The AMC7891 updates the DAC output only if the corresponding
dacn_data register has been accessed since the last dac_load
trigger. Any DAC channels that have not been accessed are not
reloaded again.
Reserved for factory use.
Sets the primary ADC conversion rate
adc_rate(1:0)
Conversion time (kSPS)
00
500
01
250
10
125
11
62.5
ADC data available indicator in Direct-mode conversion. Always
cleared to ‘0’ in Auto-mode conversion.
A ‘1’ read from this bit indicates the ADC conversion cycle is
complete and new data is available.
A ‘0’ read from this bit indicates the ADC conversion cycle is in
progress or the ADC is in Auto-mode.
To clear this bit one of the following events has to occur:
1. Reading the adcn_data registers.
2. Starting a new ADC conversion cycle.
Reserved for factory use.
Default
Value
All zeros
1
0
0
0
00
0
All zeros
Register name: ADC_enable – Address: 0x37, Default: 0x0000 (READ/WRITE)
Register
Name
ADC_enable
20
Address
Bit
Name
Function
0x37
15
14
13
11
10
8
7
6
5
12,9
Reserved
adc0_en
adc1_en
adc2_en
adc3_en
adc4_en
adc5_en
adc6_en
adc7_en
Reserved
Reserved for factory use.
When set to ‘1’ the corresponding analog input channel AIN_n
(n = 0, 1, …, 7) is accessed during an ADC conversion cycle.
4:0
Reserved
When cleared to ‘0’ the corresponding input channel AIN_n
(n = 0, 1, …, 7) is ignored during an ADC conversion cycle.
Reserved for factory use. Must be set to 0 for proper device
operation.
Reserved for factory use.
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Default
Value
All zeros
0
0
0
0
0
0
0
0
All zeros
All zeros
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Register name: ADC_gain – Address: 0x38, Default: 0xFF00 (READ/WRITE)
Register
Name
ADC_gain
Address
Bit
Name
Function
0x38
15
adc0_gain
When set to ‘1’ the corresponding analog input channel AIN_n (n = 0, 1,
…, 7) input range is 2 × VREF.
14
13
adc1_gain
adc2_gain
12
11
10
9
8
7:0
adc3_gain
adc4_gain
adc5_gain
adc6_gain
adc7_gain
Reserved
Default
Value
1
1
1
When cleared to ‘0’ the corresponding input channel AIN_n (n = 0, 1, …,
7) input range is VREF.
1
1
1
1
1
All zeros
Reserved for factory use.
Register name: DAC_clear – Address: 0x39, Default: 0x0000 (READ/WRITE)
Register
Name
ADC_clear
Address
Bit
Name
Function
0x39
15:4
3
2
1
Reserved
dac3_clear
dac2_clear
dac1_clear
Reserved for factory use.
When set to ‘1’ clears the corresponding DACout_n (n = 0, 1, …, 3)
output to the value specified in register dacn_clear, 0x2F to 0x32.
0
dac0_clear
When cleared to ‘0’ the corresponding DACout_n (n = 0, 1, …, 3)
output returns to normal operation.
Default
Value
All zeros
0
0
0
0
Register name: DAC_sync – Address: 0x3A, Default: 0x0000 (READ/WRITE)
Register
Name
DAC_sync
Address
Bit
Name
Function
0x3A
15:4
3
2
1
Reserved
dac3_sync
dac2_sync
dac1_sync
Reserved for factory use.
When set to ‘1’ clears the corresponding DACout_n (n = 0, 1, …, 3) is set to
synchronous-mode.
0
dac0_sync
When cleared to ‘0’ the corresponding DACout_n (n = 0, 1, …, 3) is set to
asynchronous-mode.
Default
Value
All zeros
0
0
0
0
Register name: AMC_power – Address: 0x3B, Default: 0x0000 (READ/WRITE)
Register
Address
Name
AMC_power
0x3B
Bit
Name
Function
15
14
Reserved
adc_on
13
ref_on
12
dac0_on
11
dac1_on
10
dac2_on
9
dac3_on
8:0
Reserved
Reserved for factory use.
When cleared to '0' the primary ADC is in power-down mode.
When set to '1' the primary ADC is in active mode.
When cleared to '0' the internal reference buffer is in power-down mode; the
device is in External ADC Reference mode and the REF pin is an input.
When set to '1' the internal reference buffer is active; the device is in
Internal ADC Reference mode and the REF pin is an output.
When cleared to '0' DAC0 is in power-down mode. DACout_0 is in
high-impedance state.
When set to '1' DAC0 is in active mode.
When cleared to '0' DAC1 is in power-down mode. DACout_1 is in
high-impedance state.
When set to '1' DAC1 is in active mode.
When cleared to '0' DAC2 is in power-down mode. DACout_2 is in
high-impedance state.
When set to '1' DAC2 is in active mode.
When cleared to '0' DAC3 is in power-down mode. DACout_3 is in
high-impedance state.
When set to '1' DAC3 is in active mode.
Reserved for factory use.
Default
Value
0
0
0
0
0
0
0
All zeros
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Register name: AMC_reset – Address: 0x3E, Default: 0x0000 (READ/WRITE)
Register
Name
AMC_reset
Address
0x3E
Bit
Name
Function
Default Value
15:0
reset(15:0)
Writing 0x6600 to this register forces a reset operation. During reset,
all SPI communication is blocked. After issuing the reset, there is a
wait of at least 30 μs before communication can be resumed.
All zeros
Register name: AMC_ID – Address: 0x40, Default: 0x0044 (READ ONLY)
Register
Name
AMC_ID
22
Address Bit
0x40
15:0
Name
Function
device_id(15:0)
A hardwired register that contains the AMC7891 ID.
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Default Value
0x0044
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ADC OPERATION
The AMC7891 has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary
ADC consists of an 8-channel multiplexer, an on-chip track-and-hold, and a successive approximation register
(SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at rates up to 500 kSPS and
converts the uncommitted analog channel inputs, AIN0 to AIN7.
The analog input range for the device can be selected as 0 V to VREF or 0 V to (2 × VREF). The AMC7891 has an
on-chip buffered 2.5V reference that can be disabled when an external reference is preferred. The secondary
ADC is a part of the on-chip temperature sensing function.
PRIMARY ADC OPERATION
The following sections describe the operation of the primary ADC. The temperature sensor ADC always operates
in the background.
ANALOG INPUT FULL SCALE RANGE
The values in register ADC_gain determine the full-scale range of the analog inputs. The full-scale range for
input channel AINn is VREF when bit adcn_gain = 0, or 2 × VREF when adcn_gain = 1. Each input must not
exceed the supply value of AVDD + 0.2 V or AGND – 0.2 V.
When internal ADC reference is enabled, the buffered internal reference is used as the ADC reference. When
external ADC reference is selected, an external reference voltage applied to the REF pin is the ADC reference.
ANALOG INPUTS
The AMC7891 has 8 uncommitted single-ended analog inputs. Figure 26 shows the equivalent input circuit of the
AMC7891. The (peak) input current through the analog inputs depends on the sample rate, input voltage, and
source impedance. The current into the AMC7891 charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no further input current. The source of the analog input
voltage must be able to charge the input capacitance to a 10-bit settling level within the acquisition time. When
the converter goes into hold mode, the input impedance is greater than 1 GΩ.
In applications where the signal source has high impedance, it is recommended to buffer the analog input before
applying it to the ADC. The analog input range can be programmed to be either 0 V to VREF or 0 V to (2 × VREF).
With a gain of 2, the input is effectively divided by two before the conversion takes place. Note that the voltage
with respect to AGND on the ADC analog input cannot exceed AVDD.
AV DD
50 W
40 W
40 pF
AIN0
AV DD
50 W
AIN7
50 W
Device in Hold Mode
40 W
40 pF
AGND
Figure 26. ADC Equivalent Input Circuit
ADC TRIGGER SIGNALS
The ADC can be triggered internally by writing to the adc_trig bit in register AMC_config. When a new trigger
activates, the ADC stops any existing conversion immediately and starts a new cycle. For example, the ADC is
programmed to sample input channels 0 to channel 3 repeatedly (auto-mode). During the conversion of channel
1, a trigger is activated. The ADC stops the conversion of channel 1 immediately and starts the conversion of
channel 0 again, instead of proceeding to convert channel 2.
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CONVERSION MODES
Two types of ADC conversions are available: direct-mode and auto-mode. adc_mode bit (AMC_config register,
bit 13) sets the conversion mode. The default conversion mode is auto-mode (adc_mode = '1').
In direct-mode conversion, each analog channel within the specified group in register ADC_enable is converted a
single time. After the last channel is converted, the ADC goes into an idle state and waits for a new trigger.
Auto-mode conversion, on the other hand, is a continuous operation. In auto-mode, each analog channel within
the specified group is converted sequentially and repeatedly.
The flow chart of the ADC conversion sequence in Figure 27 shows the conversion process.
Start
(Reset)
Wait for
ADC Trigger
First Conversion
New Trigger
or
adc_mode Changed?
Yes
No
Stop current conversion
Yes
Input Channel
Register been
Rewritten?
No
Yes
Is this the last conversion?
No
Yes
Direct Mode
Convert next channel
No
Figure 27. ADC Conversion Sequence
24
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When any of the following events occur, the current conversion cycle stops immediately:
• A new trigger is issued.
• The conversion mode changes.
• Either ADC channe register is rewritten.
When a new trigger activates, the ADC starts a new conversion cycle. The trigger should not be issued at the
same time the conversion mode is changed. If a ‘1’ is simultaneously written to the adc_trig bit when changing
the adc_mode bit from ‘0’ to '1', the current conversion stops and immediately returns to the wait for ADC trigger
state.
To avoid noise caused by the bus clock, it is recommended that no bus clock activity occurs for at least the
conversion process time immediately after the ADC conversion starts.
DOUBLE-BUFFERED ADC DATA REGISTER
The host can access all eight, double-buffered ADCn_data registers, as shown in Figure 28. The conversion
result from the analog input with channel address n, (where n = 0 to 7) is stored in adcn_data[9:0] in straight
binary format. When the conversion of an individual channel is completed, the data is immediately transferred
into the corresponding adcn_tmpry temporary register, the first stage of the data buffer. When the conversion of
the last channel completes, all data in the adcn_tmpry registers is simultaneously transferred to the
corresponding adcn_data[9:0] value, the second stage of the data buffer.
In the case when a data transfer is in progress between any ADCn_data register and the AMC7891 shift register,
all ADCn_data registers are not updated until the data transfer is complete.
AIN0
AIN1
AIN2
AIN3
ADC
adc0_tmpry
adc0_data
AIN4
To Shift
Register
AIN5
AIN6
AIN7
.
.
.
Input Range
Selection
adc_trig
(Internal Trigger)
adc7_tmpry
adc7_data
GPIOVDD
adc_ready
10 kW
DAV
Figure 28. ADC Structure
PROGRAMMABLE CONVERSION RATE
The maximum ADC conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 3. The
conversion rate is programmable through adc_rate[1:0] (AMC_config register, [9:8] bits). When more than one
channel is selected, the conversion rate is divided by the number of channels selected in register ADC_enable.
In auto mode, the adc_rate[1:0] value determines the actual conversion rate. In direct mode, adc_rate[1:0] limits
the maximum possible conversion rate. The actual conversion rate in direct mode is determined by the rate of
the conversion trigger. Note that when a trigger is issued, there may be a delay of up to 4 μs to internally
synchronize and initiate the start of the sequential channel conversion process. In both direct- and auto- modes,
when adc_rate[1:0] is set to a value other than the maximum rate ('00'), nap mode is activated between
conversions. By activating nap mode, the AVDD supply current is reduced.
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Table 3. ADC Conversion Rate
adc_rate[1:0]
tACQ
(µs)
tCONV
(µs)
NAP
ENABLED
THROUGHPUT
(Single-Channel Auto Mode)
00
0.375
01
2.375
1.625
No
500 kSPS (default)
1.625
Yes
10
250 kSPS
6.375
1.625
Yes
125 kSPS
11
14.375
1.625
Yes
62.5 kSPS
HANDSHAKING WITH THE HOST
The DAV pin and adc_ready bit (AMC_config register, bit 7) provide handshaking with the host. The DAV pin is
an open-drain, active low output. If used, an external 10 kΩ pull-up resistor to GPIOVDD is required. If unused,
the pin can be connected to DGND. Pin and bit status depend on the conversion mode (direct or auto), as shown
in Figure 29.
In direct mode, after the ADCn_data registers of all the selected channels in register adc_enable are updated,
adc_ready is set immediately to '1' and the DAV pin is active (low) to signify that new data is available.
The adc_ready bit is reset to '0' and the DAV pin goes back to inactive (high) either by reading any of the
ADCn_data registers or when a new ADC conversion is started by issuing a trigger by adc_trig. The update
takes place immediately after the read command frame indicating the read operation or trigger event.
In auto-mode, after the adcn_data[9:0] values are updated, a pulse of 1μs (low) appears on the DAV pin to
signify that new data is available. However, the adc_trig bit is inactive and always set to ‘0’.
a ) Direct Mode
CS
adc_trig
set to “1”
1st internal
trigger
adc_trig
set to “1”
Read Data
Command Frame
Read
Instruction
SDI
Read Data
2nd internal
Command Frame
trigger
Read
Instruction
DAV
1st CONVERSION of the
channels specified in the ADC
Channel Register
2nd CONVERSION of the
channels specified in the ADC
Channel Register
b) Auto Mode
CS
adc_trig
set to “1”
1st internal
trigger
SDI
1µs
DAV
1st CONVERSION of the
channels specified in the ADC
Channel Register
2nd CONVERSION
3rd CONVERSION
Figure 29. ADC Handshaking
26
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TEMPERATURE SENSOR OPERATION (SECONDARY ADC)
The AMC7891 contains an on-chip temperature sensor used to measure the device temperature. The
temperature sensor is continuously monitoring, and new readings are automatically available every cycle. The
analog temperature reading is converted by a secondary ADC that runs in the background at a lower speed than
the primary ADC.
The temperature measurement relies on the characteristics of a semiconductor junction operating at a fixed
current level. The forward voltage of the diode (VBE) depends on the current passing through it and the ambient
temperature. The change in VBE when the diode operates at two different currents (a low current of ILOW and a
high current of IHIGH, is shown in Equation 1:
VBE_HIGH – VBE_LOW = ηkT/q × ln(IHIGH/ILOW)
(1)
Where:
k is Boltzmann’s constant.
q is the charge of the carrier.
T is the absolute temperature in Kelvins (K).
η is the ideality of the transistor as sensor.
ILOW
SW1
IHIGH
SW2
Mux
LPF and Signal
Conditioning
Secon ADC
and Signal
Processing
temp _data
register
Diode
Temperature
Sensor
Figure 30. Integrated Temperature Sensor
The temperature sensor can be disabled by clearing to ‘0’ the temp_en bit (TEMP_config register, bit 3). When
disabled, the sensor is not converted. The AMC7891 continuously monitors the temperature sensor in the
background, leaving the user free to perform conversions on the primary ADC. When one monitor cycle finishes,
a signal passes to the control logic to automatically initiate a new conversion.
The analog sensing signal is preprocessed by a low-pass filter and signal conditioning circuitry, and then
digitized by the secondary ADC. The resulting digital signal is further processed by the digital filter and
processing unit. The final result is stored as a 12-bit value in the TEMP_data register as tempdata[11:0]. The
format of the final result is in twos complement, as shown in Table 4. Note that the device measures the
temperature from –40°C to 150°C.
If a data transfer is in progress between the TEMP_data register and the AMC Shift Register, the TEMP_data
register is frozen until the data transfer is complete.
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Table 4. Temperature Data Format
TEMPERATURE (°C)
DIGITAL CODE
+255.875
011111111111
+150
010010110000
+100
001100100000
+50
000110010000
+25
000011001000
+1
000000001000
0
000000000000
–1
111111111000
–25
111100111000
–50
111001110000
–100
110011100000
–150
101101010000
–256
100000000000
The temperature conversion time is by default 15 ms but it can be increased by setting temp_rate[2:0]
(TEMP_rate register, bits [2:0]) as shown in Table 5.
Table 5. Temperature Conversion Time
28
adc_rate[2:0]
CONVERSION TIME
000
128x
001
64x
010
32x
011
16x
100
8x
101
4x
110
2x
111
15 ms
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REFERENCE OPERATION
The AMC7891 includes a buffered internal reference for the ADC, DACs and temperature sensor. The internal
reference is a 2.5 V, bipolar transistor-based, precision bandgap reference.
The internal reference always drives the DACs and the internal temperature sensor directly (unbuffered);
however the ADC can be driven either by the internal reference (buffered) or by an external one as determined
by the ref_on bit (AMC_power register, bit 13). If used, the external reference is applied to the dual purpose REF
pin. A decoupling capacitor is recommended between the external reference output an AGND for noise filtering.
In internal ADC reference mode, the buffered internal reference is available at the REF pin. A compensating
4.7µF capacitor is recommended between the internal buffered reference output and AGND.
On power-up, the AMC7891 is configured for ADC external reference (ref_on bit cleared to ‘0’). In this case it is
important that the external reference source is not input into the REF pin until AVDD is stable. If using the internal
reference to drive the ADC, the ref_on must be set to ‘1’ to enable the internal reference buffer.
ref_on = 0
ADC Reference
External
Reference
Internal Reference
(2.5 V)
DAC and Temp Sensor
Reference
AIN0
AIN1
AIN3
AIN4
MUX
AIN2
ADC
10-b
AIN5
AIN6
DAC0
10-b
DACOUT0
DAC1
10-b
DACOUT1
DAC2
10-b
DACOUT2
DAC3
10-b
DACOUT3
AIN7
Temperature
Sensor
Figure 31. External ADC Reference
ref_on = 1
Internal Reference
(2.5 V)
C>4.7 mF
(Minimize
inductance to pin)
ADC Reference
DAC and Temp Sensor
Reference
AIN0
AIN1
AIN3
AIN4
MUX
AIN2
ADC
10-b
AIN5
AIN6
DAC0
10-b
DACOUT0
DAC1
10-b
DACOUT1
DAC2
10-b
DACOUT2
DAC3
10-b
DACOUT3
AIN7
Temperature
Sensor
Figure 32. Internal ADC Reference
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DAC OPERATION
The AMC7891 contains 4 independent DACs that provide analog control with 10 bits of resolution using an
internal reference. Each DAC core consists of a 10-bit string DAC and an output voltage buffer.
The DAC latch stores the code that determines the output voltage from the DAC string. The code is transferred
from the DACn_data registers to the DACn data latches when the internal DAC load signal is generated.
DACn
Data Latch
dacn_data
Register Value
10-bit
Resistor String
VOUT
DACOUTn
DAC Load (1)
(1) Internal DAC load is generated by writing '1' to the dac_load bit in synchronous mode. In
asynchronous mode, the DAC latch is transparent.
Figure 33. DAC Block Diagram
The resistor string structure is shown in Figure 34. It consists of a string of resistors, each of value R. The code
loaded to the DAC Latch determines at which node on the string the voltage is tapped off to be fed into the
output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier.
This architecture has inherent monotonicity, voltage output, and low glitch. It is also linear because all the
resistors are of equal value.
R
R
R
To Output
Amplifier
R
R
Figure 34. Resistor String
30
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DAC OUTPUT
The full-scale output range of each DAC is set by the product of the internal reference voltage times a fixed gain
of 2 in the DAC output buffer (2 × VREF). The full-scale output range of each DAC is limited by the analog power
supply. The maximum and minimum outputs from the DAC cannot exceed AVDD or be lower than AGND,
respectively.
After power-on or a reset event, the DAC output buffers are in power-down mode. In this mode all dacn_data
registers and DACn data latches are set to their default values, the output buffers are in a high-impedance state
and each DACoutn output pin connects to AGND through an internal 10 kΩ resistor.
DOUBLE-BUFFERED DAC DATA REGISTERS
There are 4 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data
register. Data is initially written to the individual DACn_data register as the value dacn_data[9:0] and then
transferred to its corresponding DACn latch. When the DACn latch is updated, the output from pin DACoutn
changes to the newly set value. When the host reads from DACn_data, the value held in the DACn latch is
returned (not the value held in the data register).
The DACs update mode is determined by the dacn_sync setting in the DAC_sync register. When dacn_sync is
cleared to ‘0’, the DACn is in asynchronous mode. In asynchronous mode, a write to the DACn_data register
results in an immediate update of the DACn latch and corresponding DACoutn output.
Synchronous mode is selected by setting dacn_sync to ‘1’. In synchronous mode writing to the DACn_data
register does not update the DACn latch DACout_n output. Instead, the update occurs only until the dac_load bit
(AMC_config register, bit 11) is set to ‘1’. By setting the DAC_sync register properly, several DACs can be
updated at the same time.
Table 6. DAC Output Modes
MODE
dacn_sync
WRITING TO
dac_load
Asynchronous
0
Don’t care
Synchronous
1
1
OPERATION
Update DACn individually. The DACn latch and DACoutn output are immediately
updated after writing to DACn_data.
Simultaneously update all DACs by internal trigger. Writing ‘1’ to dac_load generates
an internal load DAC trigger signal that updates the DACn latches and DACoutn
outputs with the contents of the corresponding dacn_data[9:0] register values.
The AMC7891 updates the DAC latches only if it has been accessed since the last time dac_load was issued,
thereby eliminating any unnecessary glitch. Any DAC channels that have not been accessed are not reloaded
again. When the DAC latch is updated, the corresponding output changes to the new level immediately.
CLEAR DACS
Each DAC can be cleared using the DAC_clear register. When setting the corresponding dacn_clear bit to ‘1’,
DACn goes to a clear state in which the DACoutn is immediately updated with the predefined value in the
DACn_clear register, regardless of the dacn_sync status. The data register value dacn_data[9:0] does not
change.
When the DAC goes back to normal operation, the DACoutn output is set back to the DACn latch value
regardless of the dac_sync status.
dacn_data
Register Value
DACn
Data Latch
0
DACn
1
dacn_clear
Register Value
dacn_clear
Figure 35. Clear DAC Operation
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AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
GENERAL PURPOSE INPUT/OUTPUT PINS
The AMC7891 has twelve GPIO pins. Each GPIO provides a bidirectional, digital I/O signal. These pins can
receive an input or produce an output as configured by the GPIO_config register.
To configure the GPIOxx pin as an output, the corresponding ioxx_io bit needs to be set to ‘1’. The GPIOxx is an
output driver with a pull to the value of the corresponding ioxx_out bit in register GPIO_out.
To set the GPIOxx pin as an input, the corresponding ioxx_io bit has to be cleared to ‘0’. In this mode the
GPIOxx pin is in high-impedance state and the read value is stored in the corresponding ioutxx_in bit in register
GPIO_in. When set as an input, writes to the GPIO_out register do not affect the GPIO values.
After a power-on or reset event, all the GPIO pins are set as inputs and, hence in high-impedance state.
POWER-UP SEQUENCE
After all supplies are established, serial communication with the AMC7891 is valid only after a 200 µs power-up
reset delay. Following this, a software reset should be issued to ensure proper operation of the AMC7891. A
software reset is issued by writing the value ‘0x6600’ to reset[15:0] in register AMC_reset. Communication to the
AMC7891 is re-established after a 200 µS delay from the reset operation (measured from the rising edge of CS
establishing the end of the reset command frame).
At power-up or after a software-reset command all registers are set to the default values (see Table 6). The
default state of all analog blocks is off as determined by the default value of the AMC_power register.
For the device to work properly, AVDD must power up before applying any inputs to the GPIO pins. In addition, if
using an external ADC reference AVDD must power up before the external reference voltage is applied to the
REF pin.
The following power-up sequence is recommended for the AMC7891.
1. No input should be applied to the GPIO pins. Also, if using an external ADC reference, it should not be
applied to the REF pin.
2. Supply all voltages (AVDD, GPIOVDD and SPIVDD). If possible, it is recommended to apply IOVDD before
AVDD. However, the supplies can be powered up simultaneously or in any order with no detrimental effect to
the device.
3. After AVDD has been applied there is a 200 µs power-up reset delay. No serial communication should be
attempted during this time.
4. Issue a software-reset command by writing the value ‘0x6600’ to reset[15:0] in register AMC_reset.
5. Wait at least 200 µs from the rising edge of CS to complete the software-reset.
6. Program the registers according to the desired mode of operation.
32
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AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
APPLICATION INFORMATION
BASE STATION AMPLIFIER MONITOR AND CONTROL
The AMC7891 is a highly integrated, low-power, complete analog monitoring and control system in a small
package; all of these features make the AMC7891’s an ideal low-cost, bias control circuit for modern RF
transistor modules such as the power amplifiers (PA) and low-noise amplifiers (LNA) found in RF communication
systems.
The AMC7891 is used in RF amplifier signal chains to set the transistor’s optimal bias condition as well as to
monitor for any possible malfunction. The AMC7891 four independent DAC outputs allow control of the
transistor’s gate bias voltages as well as of any variable-gain amplifiers (VGAs) in the signal chain. The
AMC7891 twelve configurable GPIOs enable digital signal control and monitoring. Additionally, the device has 8
uncommitted analog inputs driving a highly precise ADC and an accurate on-chip temperature sensor that allow
continuous monitoring of the main factors determining optimal amplifier operation such as temperature, supply
voltages as well as drain bias currents through external current shunt monitors. The use of external current shunt
monitors gives the system designer the flexibility to choose the optimal number of current measurements for the
amplifier topology as well as the accuracy, voltage range and gain setting according to the drain current level to
be measured. The Texas Instruments’ INA282 family, which includes the INA282, INA283, INA284, INA285 and
INA286 devices, are highly-accurate, wide common-mode range current shunt monitors with gains going from
50V/V to 1000V/V.
The circuit in Figure 36 shows a typical multi-stage Doherty PA monitoring and control system using the
AMC7891. The AMC7891 DAC outputs are used to set the bias gate voltage of each LDMOS transistor in the PA
as well as to set the gain of the VGA driving the PA. The AMC7891 ADC inputs are used to monitor the most
important parameters in the PA operation: supply voltages, drain bias currents as well as the TX and RX signal
power. The GPIOs give additional system flexibility. In the system example below three GPIOs are used to
address an external 8:1 multiplexer used for giving additional inputs to the AMC7891 ADC.
CS
AMC7891
SCLK
SDI
SPI
DAC
µController
SDO
DAC
DAV
ADC
DAC
TEMP
SENSOR
Remote Temp
8:1
Mux
8 Analog Inputs
TMP20
Digital I/O
VGA
Peak PA
Gate Bias
Carrier PA
Gate Bias
Pre-amplifier
Gate Bias
Pre-amplifier
Doherty Amplifier
RF In
VDD
Carrier PA
Bidirectional Coupler
RSENSE
INA282
Current Sense 2
RF Out
VDD
Peak PA
VDD
Carrier PA
VDD
General
Peak PA
RSENSE
TX Power
Current Sense 1
Reflected Power
GPIO
INA282
Attenuator
Attenuator
RMS Power
Meter
RMS Power
Meter
Vsupp1 (e.g. 3.3V)
Vsupp2 (e.g. 1.8V)
MUX
VGA Control
DAC
Figure 36. PA Monitor and Control System
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AMC7891
SBAS518A – AUGUST 2011 – REVISED DECEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Original (August 2011) to Revision A
Page
•
Changed from a 3 page Product Preview To a Prodcution Data Sheet ............................................................................... 1
•
Added the TYPICAL CHARACTERISTICS: DAC section .................................................................................................. 10
•
Added the TYPICAL CHARACTERISTICS: ADC section .................................................................................................. 12
34
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
AMC7891SRHHR
ACTIVE
VQFN
RHH
36
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AMC7891
AMC7891SRHHT
ACTIVE
VQFN
RHH
36
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AMC7891
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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