AWR2243
SWRS223C – FEBRUARY 2020 – REVISED JUNE 2022
AWR2243 Single-Chip 76- to 81-GHz FMCW Transceiver
•
•
1 Features
•
•
•
•
FMCW transceiver
– Integrated PLL, transmitter, receiver, baseband,
and ADC
– 76- to 81-GHz coverage with 5 GHz available
bandwidth
– Four receive channels
– Three transmit channels
– Ultra-accurate chirp engine based on
Fractional-N PLL
– TX power: 13 dBm
– RX noise figure: 12 dB
– Phase noise at 1 MHz:
• –96 dBc/Hz (76 to 77 GHz)
• –94 dBc/Hz (77 to 81 GHz)
Built-in calibration and self-test
– Built-in firmware (ROM)
– Self-calibrating system across process and
temperature
Host interface
– Control interface with external processor over
SPI or I2C interface
– Data interface with external processor over
MIPI D-PHY and CSI2 v1.1
– Interrupts for Fault Reporting
Functional Safety-Compliant
– Developed for functional safety applications
– Documentation available to aid ISO 26262
functional safety system design up to ASIL-D
– Hardware integrity up to ASIL-B
– Safety-related certification
• ISO 26262 certified up to ASIL B by TUV
SUD
Crystal
RX1
RX2
Antenna
Structure
RX3
RX4
•
•
•
•
AEC-Q100 qualified
AWR2243 advanced features
– Embedded self-monitoring with limited Host
processor involvement
– Complex baseband architecture
– Option of cascading multiple devices to
increase channel count
– Embedded interference detection capability
Power management
– Built-in LDO Network for enhanced PSRR
– I/Os support dual voltage 3.3 V/1.8 V
Clock source
– Supports externally driven clock (square/sine)
at 40 MHz
– Supports 40 MHz crystal connection with load
capacitors
Easy hardware design
– 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm
flip chip BGA package for easy assembly and
low-cost PCB design
– Small solution size
Operating Conditions
– Junction temp range: –40°C to 140°C
2 Applications
•
•
•
•
Automated Highway Driving
Automatic Emergency Braking
Adaptive Cruise Control
Imaging Radar using Cascading Configuration
Power Management
SPI/I2C
External
MCU
AWR2243
CSI2 (4 Lane Data + 1 Clock lane)
TX1
TX2
TX3
Automotive
Interface PHY
Reset
Error
MCU Clock
Figure 2-1. Radar Sensor for Automotive Applications
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AWR2243
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SWRS223C – FEBRUARY 2020 – REVISED JUNE 2022
3 Description
The AWR2243 device is an integrated single-chip FMCW transceiver capable of operation in the 76- to 81-GHz
band. The device enables unprecedented levels of integration in an extremely small form factor. AWR2243 is an
ideal solution for low power, self-monitored, ultra-accurate radar systems in the automotive space.
The AWR2243 device is a self-contained FMCW transceiver single-chip solution that simplifies the
implementation of Automotive Radar sensors in the band of 76 to 81 GHz. It is built on TI’s low-power 45-nm
RFCMOS process, which enables a monolithic implementation of a 3TX, 4RX system with built-in PLL and ADC
converters. Simple programming model changes can enable a wide variety of sensor implementation (Short,
Mid, Long) with the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally,
the device is provided as a complete platform solution including reference hardware design, software drivers,
sample configurations, API guide, and user documentation.
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE
AWR2243ABGABLQ1 (Tray)
FCBGA (161)
10.4 mm × 10.4 mm
AWR2243ABGABLRQ1 (Reel)
FCBGA (161)
10.4 mm × 10.4 mm
(1)
2
For more information, see Section 13, Mechanical Packaging and Orderable Information.
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4 Functional Block Diagram
LNA
IF
ADC
LNA
IF
ADC
Digital Front-end
(Decimation filter
chain)
LNA
IF
ADC
LNA
IF
ADC
ADC Buffer
CSI2
16KB PING/PONG
PA
û-
PA
û-
Phase
Shifter
Control (A)
x4
Synth
(20 GHz)
Ramp Generator
Synth Cycle
Counter
PA
ADC output
interface
SPI/I2C
Host control
interface
û-
RF Control / BIST
Multi-chip cascading (B)
Osc.
VMON
Temp(C)
GPADC
RF/Analog Subsystem
A.
Phase Shift Control:
B.
C.
• 0° / 180° BPM
• 0° / 180° BPM and 5.625° resolution control option for AWR2243, and AWR1843
Multi-chip cascading feature is available in AWR2243
Internal temperature sensor accuracy is ± 7 °C.
Digital
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Comparison......................................................... 7
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagram................................................................ 9
7.2 Signal Descriptions................................................... 13
8 Specifications................................................................ 17
8.1 Absolute Maximum Ratings ..................................... 17
8.2 ESD Ratings............................................................. 17
8.3 Power-On Hours (POH) ........................................... 18
8.4 Recommended Operating Conditions ......................18
8.5 Power Supply Specifications ....................................19
8.6 Power Consumption Summary ................................ 20
8.7 RF Specification........................................................21
8.8 Thermal Resistance Characteristics for FCBGA
Package [ABL0161] ....................................................22
8.9 Timing and Switching Characteristics....................... 23
9 Detailed Description......................................................37
9.1 Overview................................................................... 37
9.2 Functional Block Diagram......................................... 37
9.3 Subsystems.............................................................. 38
9.4 Other Subsystems.................................................... 40
10 Monitoring and Diagnostic Mechanisms...................44
11 Applications, Implementation, and Layout............... 46
11.1 Application Information............................................46
11.2 Short-, Medium-, and Long-Range Radar...............46
11.3 Imaging Radar using Cascade Configuration......... 47
11.4 Reference Schematic..............................................48
12 Device and Documentation Support..........................49
12.1 Device Nomenclature..............................................49
12.2 Tools and Software................................................. 50
12.3 Documentation Support.......................................... 51
12.4 Support Resources................................................. 51
12.5 Trademarks............................................................. 51
12.6 Electrostatic Discharge Caution..............................51
12.7 Export Control Notice..............................................51
12.8 Glossary..................................................................51
13 Mechanical, Packaging, and Orderable
Information.................................................................... 52
13.1 Packaging Information............................................ 52
5 Revision History
Changes from February 11, 2020 to August 30, 2020 (from Revision * (February 2020) to
Revision A (August 2020))
Page
• Global: Updated the numbering format for tables, figures, and cross-references throughout the document..... 1
• Global: Added/Updated cascading feature in supported on the AWR2243P only.............................................. 1
• Global: Added/Updated Functional Safety-Compliant targeted information....................................................... 1
• Global: Updated AWR2243 Product Status from "Advance Information (AI)" to "Production Data (PD)"...........1
• (Device Information): Updated/Changed table to reflect production part numbers.............................................2
• (Functional Block Diagram): Updated/Changed footnotes to reflect AWR2243, AWR2243P, and AWR1843.... 3
• Table 6-1 (Device Features Comparison): Added AWR2243P device-specific features to table and updated
associated footnotes...........................................................................................................................................7
• Table 6-1: Updated/Changed Max sampling rate FUNCTION to separate complex 1x and 2x cases............... 7
• Table 7-1 (Signal Descriptions): Updated/Changed the DEFAULT PULL STATUS and DESCRIPTION for
NRESET (P12)................................................................................................................................................. 13
• Table 7-1: Added recommended connectivity for GPIO[0] (N4) during Debug................................................. 13
• Section 8.1 (Absolute Maximum Ratings): Updated/Changed the MAX value for Operating junction
temperature range from "125" to "140", as Automotive.................................................................................... 17
• Section 8.3 (Power-On Hours (POH)): Updated/Changed table to reflect automotive junction temp POH
percentages...................................................................................................................................................... 18
• Section 8.4 (Recommended Operating Conditions): Added TJ, Operating junction temperature range.......... 18
• Section 8.6 (Power Consumption Summary): Added missing table reference to the paragraph......................20
• Table 8-3 (Maximum Current Ratings at Power Terminals): Added the current consumption VDDIN MAX value
of "850 mA" for AWR2243................................................................................................................................ 20
• Section 8.7 (RF Specification): Updated/Changed the MAX values for IF bandwidth and A2D sampling rate
for both "(real/complex 2x)" and "(complex 1x)" to reflect the AWR2243P and AWR2243 devices................. 21
• Section 8.7: Added 20GHz SYNC OUT output level max value of 10 dBm and 20GHz SYNC IN input level
max value of 7 dBm with associated footnote. ................................................................................................ 21
• Section 8.7: Corrected the phase noise measurement conditions to reflect VCO1 value only......................... 21
4
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•
•
•
•
•
•
•
•
•
•
•
•
•
SWRS223C – FEBRUARY 2020 – REVISED JUNE 2022
Section 8.7: Updated/Changed the 1-dB compression point TYP value from "-8" to "-9" dBm, and updated the
corresponding footnote frequency from "50" to "10" kHz..................................................................................21
Figure 8-1 (Noise Figure, In-band P1dB vs Receiver Gain): Updated figure....................................................21
Section 8.8 (Thermal Resistance Characteristics): Deleted the 125°C junction temperature reference from
footnote (3).........................................................................................................................................................22
Figure 8-2 (Device Wake-Up Sequence): Removed associated MCU_CLK_OUT footnote from image..........23
Section 8.9.3.1 (Clock Specifications): Added the External Clock Mode Specifications table .........................25
Section 8.9.4 (Multibuffered / Standard Serial Peripheral Interface (MibSPI)): Updated section..................... 27
Figure 8-6 (SPI Communication): Updated figure.............................................................................................29
Section 10 (Monitoring and Diagnostic Mechanisms): Added new section...................................................... 44
(Monitoring and Diagnostic Mechanisms) : Added a new note on Functional Safety related collateral........... 44
Figure 11-1 (Short-, Medium-, and Long-Range Radar): Updated figure......................................................... 46
Section 11.3 (Imaging Radar using Cascade Configuration): Updated figure.................................................. 47
(Reference Schematic): Updated/Changed the VBGAP decoupling capacitor value from "0.22 uF" to "47 nF"..
48
Figure 12-1 (Device Nomenclature): Updated/Changed figure........................................................................ 49
Changes from September 1, 2020 to December 5, 2021 (from Revision A (September 2020) to
Revision B (December 2021))
Page
• Global: Updated to reflect Functional Safety-Compliance and relevant certification collateral...........................1
• Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and
Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminology.................................. 1
• (Features) : Mentioned the specific operating temperature range for the mmWave Sensor.............................. 1
• (Applications) :Added application weblink for "Automatic Emergency Braking"................................................. 1
• (Device Feature Comparison): Removed a row on Functional-Safety compliance and instead added a tablenote for this; Also added a table-note for LVDS operation..................................................................................7
• (Device Feature Comparison): Updated GPADC row to reflect applicability for AWR2243 and AWR2243P
devices................................................................................................................................................................7
• (Signal Descriptions): Updated/modified GPADC pin description, and CLKP/CLKM decriptions for Reference
Oscillator...........................................................................................................................................................13
• (Signal Descriptions): Added a table-note for QSPI Interface usage................................................................13
• (Maximum Current Ratings at Power Terminals) : Added a table-note for 3.3V Power rail.............................. 20
• (RF Specification) : Updated the link for mmWave Radar Interface Control document in the footnotes.......... 21
• (Frame Trigger Timing) : Updated the maximum pulse width to 4us in the table. ............................................23
• (Clock Specifications): Updated/Changed "Crystal Electrical Characteristics (Oscillator Mode)" to reflect
correct device operating temperature range; Revised frequency tolerance specs in "External Clock Mode
Specifications" table..........................................................................................................................................25
• (Switching Characteristics for Output Timing versus Load Capacitance): Updated/Modified the table to
remove Slew Rate = 1 condition; removed a footnote...................................................................................... 34
• (Other Subsytems) : Added a new chapter for ADC channels for user service application..............................40
• (GPADC) :Additional chapter appended to describe ADC Channels for User Application............................... 42
• (Monitoring and Diagnostic Mechanisms) : Added a new note on Functional Safety related collateral........... 44
• (Reference Schematic) : Added weblinks to AWR2243 EVM documentation collateral...................................48
• (Device Nomenclature): Updated/Changed figure to reflect Functional Safety Compliance............................ 49
Changes from December 6, 2021 to June 30, 2022 (from Revision B (December 2021) to
Revision C (June 2022))
Page
• (Device Information): Updated/Changed table to remove unsupported production part variants.......................2
• (Functional Block Diagram): Updated/Changed footnotes to reflect cascade support in AWR2243 and
removed the mention of unsupported part variants............................................................................................ 3
• (Device Feature Comparison): Removed unsupported devices from the table and updated the feature set for
AWR2243 (Including Max IF Bandwidth, Sampling rates and cascade support)................................................7
• (Signal Descriptions): Added a table-note for QSPI Interface usage................................................................13
• (Maximum Current Ratings at Power Terminals) : Removed data for unsupported part variant AWR2243P...20
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•
6
(RF Specification): Removed data for unsupported part variant AWR2243P and updated feature set for
AWR2243 (Including Max IF Bandwidth, Sampling rates and cascade support)..............................................21
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6 Device Comparison
Table 6-1. Device Features Comparison
AWR2243 (1)
AWR1243
AWR1443
AWR1642
AWR1843
4
4
4
4
4
Number of transmitters
3(2)
3
3
2
3(2)
On-chip memory
—
—
576KB
1.5MB
2MB
Max I/F (Intermediate Frequency) (MHz)
20
15
5
5
10
Max real/complex 2x sampling rate (Msps)
45
37.5
12.5
12.5
25
22.5
18.75
6.25
6.25
12.5
MCU (R4F)
—
—
Yes
Yes
Yes
DSP (C674x)
—
—
—
Yes
Yes
Serial Peripheral Interface (SPI) ports
1
1
1
2
2
Quad Serial Peripheral Interface (QSPI)
—
—
Yes
Yes
Yes
Inter-Integrated Circuit (I2C) interface
1
—
1
1
1
Controller Area Network (DCAN) interface
—
—
Yes
Yes
Yes
CAN FD
—
—
—
Yes
Yes
Trace
—
—
—
Yes
Yes
PWM
—
—
—
Yes
Yes
FUNCTION
Number of receivers
Max complex 1x sampling rate (Msps)
Processor
Peripherals
Hardware In Loop (HIL/DMM)
—
—
—
Yes
Yes
GPADC
Yes
—
Yes
Yes
Yes
LVDS/Debug(3)
Yes
Yes
Yes
Yes
Yes
CSI2
Yes
Yes
—
—
—
Hardware accelerator
—
—
Yes
—
Yes
1-V bypass mode
Yes
Yes
Yes
Yes
Yes
Cascade (20-GHz sync)
Yes
—
—
—
—
JTAG
—
—
Yes
Yes
Yes
Number of Tx that can be simultaneously used(2)
3(2)
2
2
2
3(2)
Per chirp configurable Tx phase shifter
Yes
—
—
—
Yes
PD
PD
PD
PD
PD
Product
status(4)
(1)
(2)
(3)
(4)
PRODUCT PREVIEW (PP),
ADVANCE INFORMATION (AI),
or PRODUCTION DATA (PD)
Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation
for more details.
3 Tx Simultaneous operation is supported only in AWR1843 and AWR2243 with 1V LDO bypass and PA LDO disable mode. In this
mode 1V supply needs to be fed on the VOUT PA pin.
The LVDS interface is not a production interface and is only used for debug
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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6.1 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less
power using the smallest footprint mmWave sensor portfolio for automotive applications.
Automotive
TI’s automotive mmWave sensor portfolio offers high-performance radar front end to ultrammWave Sensors high resolution, small and low-power single-chip radar solutions. TI’s scalable sensor
portfolio enables design and development of ADAS system solution for every performance,
application and sensor configuration ranging from comfort functions to safety functions in
all vehicles.
8
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7 Terminal Configuration and Functions
7.1 Pin Diagram
Figure 7-1 shows the pin locations for the 161-pin FCBGA package. Figure 7-2, Figure 7-3, Figure 7-4, and
Figure 7-5 show the same pins, but split into four quadrants.
1
2
3
A
VSSA
VOUT_PA
VSSA
B
FM_CW
_SYNCIN1
VOUT_PA
VSSA
TX1
VSSA
TX2
VSSA
C
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
D
FM_CW
_SYNCOUT
VIN
_13RF2
E
VSSA
VSSA
VSSA
VSS
RX4
VSSA
VIN_18BB
VSSA
VSSA
VIN
_13RF1
RX3
VSSA
VIN
_13RF1
VSSA
VSSA
VIN
_13RF1
RX2
VSSA
VIN_18BB
VSSA
VSSA
VSS
RX1
VSSA
F
G
VSSA
H
J
VSSA
K
L
VSSA
M
4
5
6
7
VSSA
8
9
10
VSSA
VOUT
_14APLL
TX3
VSSA
VBGAP
VSSA
VSSA
VSSA
11
VIN
_18CLK
12
VIN
_18VCO
13
14
15
VOUT
_14SYNTH
OSC
_CLKOUT
VSSA
VSSA
VSSA
FM_CW
_CLKOUT
ANAMUX
VSENSE
VSSA
VIOIN
_18DIFF
N
VSSA
VSSA
VSSA
GPIO[0]
P
Analog Test 1
Analog Test 2
Analog Test 3
I2C_SCL
R
VSSA
Analog Test 4
I2C_SDA
Reserved
RS232_RX
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RS232_TX
VDDIN
SPI_CS_1
VSSA
CLKP
VSS
VDDIN
CLKM
Reserved
CSI2
_TXM[0]
CSI2
_TXP[0]
TDI
CSI2
_TXM[1]
CSI2
_TXP[1]
TDO
CSI2_CLKM
CSI2_CLKP
VIOIN_18
CSI2
_TXM[2]
CSI2
_TXP[2]
TMS
CSI2
_TXM[3]
CSI2
_TXP[3]
TCK
HS_M
_Debug1
HS_P
_Debug1
VSS
VSS
VSS
VSS
GPIO[1]
VSS
VSS
VSS
VSS
MISO_1 SPI_HOST_INTR_1NERROR_IN
Reserved
VSS
VSS
VSS
VSS
NERROR_OUTMCU_CLK_OUT
FM_CW
_SYNCIN2
VSSA
Sync_in
VDDIN
WARM
_RESET
GPIO[2]
HS_M
_Debug2
HS_P
_Debug2
QSPI_CS
QSPI[1]
QSPI[3]
Sync_out
NRESET
PMIC_CLK_OUT
VNWA
VDDIN
MOSI_1
SPI_CLK_1
QSPI_CLK
QSPI[0]
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
Figure 7-1. Pin Diagram
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1
2
3
A
VSSA
VOUT_PA
VSSA
B
FM_CW
_SYNCIN1
VOUT_PA
VSSA
TX1
VSSA
TX2
VSSA
TX3
C
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
D
FM_CW
_SYNCOUT
VIN
_13RF2
E
VSSA
VSSA
VSSA
VSS
VSS
RX4
VSSA
VIN_18BB
VSSA
VSSA
VIN
_13RF1
F
G
VSSA
4
5
6
7
VSSA
8
VSSA
VSS
VSS
VSS
VSS
Not to scale
1
2
3
4
Figure 7-2. Top Left Quadrant
9
10
11
A
VSSA
VOUT
_14APLL
B
VSSA
VBGAP
C
VSSA
VIN
_18CLK
12
VIN
_18VCO
13
14
15
VOUT
_14SYNTH
OSC
_CLKOUT
VSSA
VSSA
VSSA
FM_CW
_CLKOUT
ANAMUX
VSENSE
VSSA
VIOIN
_18DIFF
D
E
VSS
F
VSS
G
VSS
FM_CW
_SYNCIN2
VSS
VSSA
CLKP
VSS
VDDIN
CLKM
Reserved
CSI2
_TXM[0]
VSSA
CSI2
_TXP[0]
Not to scale
1
2
3
4
Figure 7-3. Top Right Quadrant
10
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1
H
J
VSSA
K
L
VSSA
M
2
3
4
RX3
VSSA
VIN
_13RF1
VSSA
VSSA
VIN
_13RF1
RX2
VSSA
VIN_18BB
VSSA
VSSA
VSS
VSS
RX1
VSSA
RS232_RX
RS232_TX
N
VSSA
VSSA
VSSA
GPIO[0]
P
Analog Test 1
Analog Test 2
Analog Test 3
I2C_SCL
R
VSSA
Analog Test 4
I2C_SDA
Reserved
5
6
7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GPIO[1]
MISO_1 SPI_HOST_INTR_1NERROR_IN
Reserved
8
VDDIN
SPI_CS_1
NERROR_OUT
QSPI_CS
MOSI_1
Not to scale
1
2
3
4
Figure 7-4. Bottom Left Quadrant
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9
H
10
11
VSS
12
VSS
J
VSS
K
VSS
VSS
L
VSS
VSS
M
13
14
15
TDI
CSI2
_TXM[1]
CSI2
_TXP[1]
TDO
CSI2_CLKM
CSI2_CLKP
VIOIN_18
CSI2
_TXM[2]
CSI2
_TXP[2]
TMS
CSI2
_TXM[3]
CSI2
_TXP[3]
TCK
HS_M
_Debug1
HS_P
_Debug1
N
MCU_CLK_OUT
Sync_in
VDDIN
WARM
_RESET
GPIO[2]
HS_M
_Debug2
HS_P
_Debug2
P
QSPI[1]
QSPI[3]
Sync_out
NRESET
PMIC_CLK_OUT
VNWA
VDDIN
R
SPI_CLK_1
QSPI_CLK
QSPI[0]
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
1
2
3
4
Figure 7-5. Bottom Right Quadrant
12
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7.2 Signal Descriptions
Table 7-1 lists the pins by function and describes that function.
Note
All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;
hence, care needs to be taken that they are not driven externally without the VIO supply being present
to the device.
Table 7-1. Signal Descriptions
FUNCTION
Transmitters
Receivers
CSI2 TX
Chip-to-chip
cascading
synchronization
signals
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS(1)
TX1
B4
O
—
Single-ended transmitter1 o/p
TX2
B6
O
—
Single-ended transmitter2 o/p
TX3
B8
O
—
Single-ended transmitter3 o/p
RX1
M2
I
—
Single-ended receiver1 i/p
RX2
K2
I
—
Single-ended receiver2 i/p
RX3
H2
I
—
Single-ended receiver3 i/p
RX4
F2
I
—
Single-ended receiver4 i/p
CSI2_TXP[0]
G15
O
—
CSI2_TXM[0]
G14
O
—
Differential data Out – Lane 0 (for CSI and LVDS
debug interface)
CSI2_CLKP
J15
O
—
CSI2_CLKM
J14
O
—
CSI2_TXP[1]
H15
O
—
CSI2_TXM[1]
H14
O
—
CSI2_TXP[2]
K15
O
—
CSI2_TXM[2]
K14
O
—
CSI2_TXP[3]
L15
O
—
CSI2_TXM[3]
L14
O
—
HS_DEBUG1_P
M15
O
—
HS_DEBUG1_M
M14
O
—
HS_DEBUG2_P
N15
O
—
HS_DEBUG2_M
N14
O
—
FM_CW_CLKOUT
B15
FM_CW_SYNCOUT
D1
O
—
20-GHz single-ended output. Modulated waveform
FM_CW_SYNCIN1
B1
FM_CW_SYNCIN2
D15
I
—
20-GHz single-ended input. Only one of these pins
should be used. Multiple instances for layout flexibility.
A14
O
—
Reference clock output from clocking subsystem after
cleanup PLL. Can be used by the secondary chip in
multichip cascading
SYNC_OUT
P11
O
Pull Down
Low-frequency frame synchronization signal output.
Can be used by the secondary chip in multichip
cascading
SYNC_IN
N10
I
Pull Down
Low-frequency frame synchronization signal input.
This signal could also be used as a hardware trigger
for frame start
SIGNAL NAME
Reference clock OSC_CLKOUT
System
synchronization
DESCRIPTION
Differential clock Out (for CSI and LVDS debug
interface)
Differential data Out – Lane 1 (for CSI and LVDS
debug interface)
Differential data Out – Lane 2 (for CSI and LVDS
debug interface)
Differential data Out – Lane 3 (for CSI and LVDS
debug interface)
Differential debug port 1 (for LVDS debug interface)
Differential debug port 2 (for LVDS debug interface)
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Table 7-1. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS(1)
DESCRIPTION
SPI control
interface from
external MCU
(default
peripheral
mode)
SPI_CS_1
R7
I
Pull Up
SPI_CLK_1
R9
I
Pull Down
MOSI_1
R8
I
Pull Up
SPI data input
MISO_1
P5
O
Pull Up
SPI data output
SPI_HOST_INTR_1
P6
O
Pull Down
Reserved
RESERVED
R4, R5
NRESET
P12
I
—
Power on reset for chip. Active low.
The NRESET needs to be pulled low for a minimum
of 20 μsec to ensure proper device reset.
WARM_RESET(3)
N12
O
Open Drain
Open-drain fail-safe warm reset signal. Can be used
as a status signal that the device is going through
reset.
SOP2
P13
I
—
SOP1
P11
I
—
SOP0
J13
I
—
The SOP pins are driven externally (weak drive) and
the AWR device senses the state of these pins during
bootup to decide the bootup mode. After boot the
same pins have other functionality.
[SOP2 SOP1 SOP0] = [0 0 1] -> Functional SPI mode
[SOP2 SOP1 SOP0] = [1 0 1] -> Flashing mode
[SOP2 SOP1 SOP0] = [0 1 1] -> debug mode
[SOP2 SOP1 SOP0] = [1 1 1] -> Functional I2C mode
NERROR_OUT
N8
O
Open Drain
Open-drain fail-safe output signal. Connected to
PMIC/Processor/MCU to indicate that some severe
criticality fault has happened. Recovery would be
through reset.
NERROR_IN
P7
I
Open Drain
Fail-safe input to the device. Error output from
any other device can be concentrated in the error
signaling monitor module inside the device and
appropriate action can be taken by firmware
TMS
L13
I
Pull Up
TCK
M13
I
Pull Down
TDI
H13
I
Pull Up
TDO
J13
O
—
CLKP
E14
I
—
In XTAL mode: Input for reference crystal
In External clock mode: Single ended input reference
clock port
CLKM
F14
O
—
In XTAL mode: Feedback drive for the reference
crystal
In External clock mode: Connect this port to ground
VBGAP
B10
O
—
Safety
Reference
oscillator
14
SPI interrupt to host
Reserved. For debug purposes, it is recommended to
have test points on these pins.
Sense on Power
Band-gap
voltage
SPI clock
—
Reset
JTAG
SPI chip select
JTAG port for TI internal development.
For debug purposes, it is recommended to have test
points on these pins.
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Table 7-1. Signal Descriptions (continued)
FUNCTION
PIN
NUMBER
SIGNAL NAME
VDDIN
PIN
TYPE
F13,N11,P15
POW
,R6
DEFAULT PULL
STATUS(1)
—
1.2-V digital power supply
VIN_SRAM
R14
POW
—
1.2-V power rail for internal SRAM
VNWA
P14
POW
—
1.2-V power rail for SRAM array back bias
VIOIN
R13
POW
—
I/O supply (3.3-V or 1.8-V): All CMOS I/Os would
operate on this supply.
VIOIN_18
K13
POW
—
1.8-V supply for CMOS IO
VIN_18CLK
B11
POW
—
1.8-V supply for clock module
VIOIN_18DIFF
D13
POW
—
1.8-V supply for CSI2 port
Reserved
G13
POW
—
No connect
VIN_13RF1
G5,J5,H5
POW
—
VIN_13RF2
C2,D2
POW
—
1.3-V Analog and RF supply,VIN_13RF1 and
VIN_13RF2 could be shorted on the board
VIN_18BB
K5,F5
POW
—
1.8-V Analog baseband power supply
B12
VIN_18VCO
POW
—
1.8-V RF VCO supply
VSS
E5,E6,E8,E1
0,E11,F9,F11
,G6,G7,G8,G
10,H7,H9,H1
1,J6,J7,J8,J1 GND
0,K7,K8,K9,
K10,K11,L5,
L6,L8,L10,R
15
—
Digital ground
VSSA
A1,A3,A5,A7
,A9,A15,B3,
B5,B7,B9,B1
3,B14,C1,C3
,C4,C5,C6,C
7,C8,C9,C15
,E1,E2,E3,E
13,E15,F3,G
1,G2,G3,H3,
J1,J2,J3,K3,
L1,L2,L3,
M3,N1,N2,N
3,R1
GND
—
Analog ground
VOUT_14APLL
A10
O
—
VOUT_14SYNTH
A13
O
—
Power supply
A2,B2
IO
—
When internal PA LDO is used this pin provides the
output voltage of the LDO. When the internal PA LDO
is bypassed and disabled 1V supply should be fed on
this pin. This is mandatory in 3TX simultaneous use
case.
PMIC_CLK_OUT
P13
O
—
Dithered clock input to PMIC
MCU_CLK_OUT
N9
O
—
Programmable clock given out to external MCU or the
processor
Internal LDO
output/inputs
VOUT_PA
External clock
out
DESCRIPTION
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Table 7-1. Signal Descriptions (continued)
FUNCTION
PIN
NUMBER
PIN
TYPE
DEFAULT PULL
STATUS(1)
GPIO[0]
N4
IO
Pull Down
GPIO[1]
N7
IO
Pull Down
SIGNAL NAME
QSPI for Serial
Flash(2)
Flash
programming
and RS232
UART
GPADC
General
purpose
ADC inputs for
external voltage
monitoring
(1)
(2)
(3)
(4)
16
General-purpose IOs. These pins are also used to set
the I2C address incase of functional I2C mode.
GPIO[2:0] -> 0x000 -> I2C address 0x28
GPIO[2:0] -> 0x001 -> I2C address 0x29
GPIO[2:0] -> 0x111 -> I2C address 0x2F
Generalpurpose I/Os
I2C interface
from external
MCU (Target
mode)
DESCRIPTION
GPIO[2]
N13
IO
Pull Down
I2C_SDA
R3
IO
Open Drain
I2C_SCL
P4
I
Open Drain
QSPI_CS
P8
O
Pull Up
QSPI_CLK
R10
O
Pull Down
Clock output from the device. Device is a controller
connected to serial flash peripheral.
QSPI[0]
R11
IO
Pull Down
Data IN/OUT
QSPI[1]
P9
IO
Pull Down
Data IN/OUT
QSPI[2]
R12
IO
Pull Up
Data IN/OUT
QSPI[3]
P10
IO
Pull Up
Data IN/OUT
RS232_TX
N6
O
Pull Down
RS232_RX
N5
I
Pull Up
Analog Test1 / ADC1
P1
IO
—
ADC channel 1(4)
Analog Test2 / ADC2
P2
IO
—
ADC channel 2(4)
Analog Test3 / ADC3
P3
IO
—
ADC channel 3(4)
Analog Test4 / ADC4
R2
IO
—
ADC channel 4(4)
ANAMUX / ADC5
C13
IO
—
ADC channel 5(4)
VSENSE / ADC6
C14
IO
—
ADC channel 6(4)
It is recommended that the GPIO[0] signal is
connected to the host processor digital pin for debug.
For proper operations, the host processor needs to be
able to drive a pulse on this pin.
I2C data
I2C clock
The host interface of I2C is selected by booting the
device in SOP mode 7 [111]. The I2C address is
selected using the GPIO[2:0] pins.
Chip-select output from the device. Device is a
controller connected to serial flash peripheral.
UART pins for programming external flash
For debug purposes, it is recommended to have test
points on these pins.
Status of PULL structures associated with the IO after device POWER UP.
This option is for development/debug in preproduction phase only. In the production version, the Functional Firmware will execute from
ROM.
For the AWR2243, WARM_RESET can be used as an output only pin for status indication.
For details, see Section 9.4.2
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
VDDIN
1.2 V digital power supply
PARAMETERS
–0.5
1.4
V
VIN_SRAM
1.2 V power rail for internal SRAM
–0.5
1.4
V
VNWA
1.2 V power rail for SRAM array back bias
–0.5
1.4
V
VIOIN
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
–0.5
2
V
VIN_18CLK
1.8 V supply for clock module
–0.5
2
V
VIOIN_18DIFF
1.8 V supply for CSI2 port
–0.5
2
V
VIN_13RF1
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
–0.5
1.45
V
1-V Internal LDO bypass mode. Device supports mode
where external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
–0.5
1.4
V
VIN_18BB
1.8-V Analog baseband power supply
–0.5
2
V
VIN_18VCO supply
1.8-V RF VCO supply
–0.5
2
V
RX1-4
Externally applied power on RF inputs
10
dBm
TX1-4
Externally applied power on RF outputs(3)
10
dBm
VIN_13RF2
VIN_13RF1
VIN_13RF2
Input and output
voltage range
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
–0.3V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
UNIT
VIOIN + 0.3
VIOIN + 20% up to
20% of signal period
V
CLKP, CLKM
Input ports for reference crystal
–0.5
2
V
Clamp current
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
140
°C
TSTG
Storage temperature range after soldered onto PC board
–55
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma= 1 can be applied on
the TX output.
8.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
All pins
±2000
All pins
±500
Corner pins
(A1, A15, R1, R15)
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.3 Power-On Hours (POH)
JUNCTION
TEMPERATURE (Tj)
OPERATING
CONDITION
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)(1) (2)
–40°C
600 (6%)
75°C
95°C
(1)
(2)
2000 (20%)
100% duty cycle
1.2
6500 (65%)
130°C
800 (8%)
140°C
100 (1%)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would
not be applicable, if the Tx gain table is overwritten using an API.
8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDDIN
1.2 V digital power supply
1.14
1.2
1.32
V
VIN_SRAM
1.2 V power rail for internal SRAM
1.14
1.2
1.32
V
VNWA
1.2 V power rail for SRAM array back bias
1.14
1.2
1.32
V
VIOIN
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
3.135
3.3
3.465
1.71
1.8
1.89
VIOIN_18
1.8 V supply for CMOS IO
1.71
1.8
1.9
V
VIN_18CLK
1.8 V supply for clock module
1.71
1.8
1.9
V
VIOIN_18DIFF
1.8 V supply for CSI2 port
1.71
1.8
1.9
V
VIN_13RF1
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
0.95
1
1.05
V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO
bypass mode)
VIN_13RF2
(1-V Internal LDO
bypass mode)
V
VIN18BB
1.8-V Analog baseband power supply
1.71
1.8
1.9
V
VIN_18VCO
1.8V RF VCO supply
1.71
1.8
1.9
V
Voltage Input High (1.8 V mode)
1.17
Voltage Input High (3.3 V mode)
2.25
VIH
VIL
V
Voltage Input Low (1.8 V mode)
0.3*VIOIN
Voltage Input Low (3.3 V mode)
0.62
VOH
High-level output threshold (IOH = 6 mA)
VOL
Low-level output threshold (IOL = 6 mA)
450
VIL (1.8V Mode)
0.45
NRESET
SOP[2:0]
VIOIN – 450
VIH (1.8V Mode)
0.65
VIH (3.3V Mode)
TJ
18
mV
0.96
VIL (3.3V Mode)
V
mV
V
1.57
Operating junction temperature range
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140
℃
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8.5 Power Supply Specifications
Table 8-1 describes the four rails from an external power supply block of the AWR2243 device.
Table 8-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
1.8 V
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, CSI2
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal
LDO bypass mode)(1)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM
(1)
Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply
needs to be fed on the VOUT PA pin.
The 1.3V (1.0V) and 1.8V power supply ripple specifications mentioned in Table 8-2 are defined to meet a target
spur level of –105dBc (RF Pin = –15dBm) at the RX. The spur and ripple levels have a dB to dB relationship, for
example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level. Values quoted are rms levels for
a sinusoidal input applied at the specified frequency.
Table 8-2. Ripple Specifications
RF RAIL
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
(µVRMS)
1.3 V (µVRMS)
1.8 V (µVRMS)
137.5
7
648
83
275
5
76
21
550
3
22
11
1100
2
4
6
2200
11
82
13
4400
13
93
19
6600
22
117
29
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8.6 Power Consumption Summary
Table 8-3 and Table 8-4 summarize the power consumption at the power terminals.
Table 8-3. Maximum Current Ratings at Power Terminals
PARAMETER(1)
SUPPLY NAME
VDDIN, VIN_SRAM, VNWA
VIN_13RF1, VIN_13RF2
Current consumption
(1)
(2)
(3)
DESCRIPTION
MIN
TYP
Total current drawn by all
nodes driven by 1.2V rail
MAX
850
Total current drawn by all
nodes driven by 1.3V (or 1V
in LDO Bypass mode) rail
when 3 transmitters are used
2500
mA
(2)
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by all
nodes driven by 1.8V rail
VIOIN
Total current drawn by all
nodes driven by 3.3V rail(3)
UNIT
850
50
The specified current values are at typical supply voltage level.
Three transmitters can simultaneously be deployed in the AWR2243 device with 1V / LDO bypass and PA LDO disable mode. In this
mode 1V supply needs to be fed on the VOUT PA pin. For a 2Tx use case, the peak 1V supply current goes up to 2000 mA.
The exact VIOIN current depends on the peripherals used and their frequency of operation.
Table 8-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
Average power
1.0-V internal LDO
consumption in single chip
bypass mode
mode.
DESCRIPTION
1TX, 4RX
2TX, 4RX
3TX, 4RX
MIN
The frame is set to 50% duty cycle.
4lane CSI interface is enabled at
600Mbps for ADC data transfer
TYP
MAX UNIT
1.42
1.62
W
1.82
Average power
consumption in Cascade
mode for Primary Sensor
1.0-V internal LDO
bypass mode
3TX, 4RX
The frame is set to 50% duty cycle.
4lane CSI interface is enabled at
600Mbps for ADC data transfer
1.97
W
Average power
consumption in Cascade
mode for Secondary
Sensor
1.0-V internal LDO
bypass mode
3TX, 4RX
The frame is set to 50% duty cycle.
4lane CSI interface is enabled at
600Mbps for ADC data transfer
1.85
W
20
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8.7 RF Specification
over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETER
MIN
TYP
13
dB
1-dB compression point (Out Of Band)(1)
–9
dBm
Maximum gain
52
dB
Gain range
20
dB
2
dB
30
dB
Image Rejection Ratio (IMRR)
IF
bandwidth(2)
A2D sampling rate
(Real/ Complex 2x)
A2D sampling rate
(Complex 1x)
A2D resolution
Return loss (S11)
Gain mismatch variation (over temperature)
Phase mismatch variation (over temperature)
Msps
12
Bits
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