CC3120
SWAS034A – FEBRUARY 2017 – REVISED MAY 2021
CC3120 SimpleLink™ Wi-Fi® Network Processor,
Internet-of-Things Solution for MCU Applications
1 Features
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CC3120R SimpleLink™ Wi-Fi® Consists of a
Wireless Network Processor (NWP) and PowerManagement Subsystems
Featuring a Dedicated Wi-Fi Internet-on-a chip™
Wi-Fi NWP that Completely Offloads Wi-Fi
and Internet Protocols from the Application
Microcontroller Unit (MCU)
Wi-Fi Modes:
– 802.11b/g/n Station
– 802.11b/g/n Access Point (AP) Supports up to
Four Stations
– Wi-Fi Direct® Client/Group Owner
WPA2 Personal and Enterprise Security: WEP,
WPA™/ WPA2™ PSK, WPA2 Enterprise (802.1x),
WPA3™ Personal, WPA3™ Enterprise
IPv4 and IPv6 TCP/IP Stack
– Industry-Standard BSD Socket Application
Programming Interfaces (APIs):
• 16 Simultaneous TCP or UDP Sockets
• 6 Simultaneous TLS and SSL Sockets
IP Addressing: Static IP, LLA, DHCPv4, and
DHCPv6 With Duplicate Address Detection (DAD)
SimpleLink Connection Manager for Autonomous
and Fast Wi-Fi Connections
Flexible Wi-Fi Provisioning With SmartConfig™
Technology, AP Mode, and WPS2 Options:
RESTful API Support Using Internal HTTP Server
Wide Set of Security Features:
– Hardware Features:
• Separate Execution Environments
• Device Identity
– Networking Security:
• Personal and Enterprise Wi-Fi Security
• Secure Sockets (SSLv3, TLS1.0/1.1/
TLS1.2)
• HTTPS Server
• Trusted Root-Certificate Catalog
• TI Root-of-Trust Public Key
•
– Software IP Protection:
• Secure Key Storage
• File System Security
• Software Tamper Detection
• Cloning Protection
Embedded Network Applications Running on the
Dedicated NWP:
– HTTP/HTTPS Web Server With Dynamic User
Callbacks
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– mDNS, DNS-SD, DHCP Server
– Ping
Recovery Mechanism—Can Recover to Factory
Defaults or to a Complete Factory Image
Wi-Fi TX Power:
– 18.0 dBm at 1 DSSS
– 14.5 dBm at 54 OFDM
Wi-Fi RX Sensitivity:
– –96.0 dBm at 1 DSSS
– –74.5 dBm at 54 OFDM
Application Throughput:
– UDP: 16 Mbps
– TCP: 13 Mbps
Power-Management Subsystem
– Integrated DC/DC Converters Support a Wide
Range of Supply Voltage:
• VBAT Wide-Voltage Mode: 2.1 V to 3.6 V
• VIO is Always Tied With VBAT
• Preregulated 1.85-V Mode
– Advanced Low-Power Modes
• Shutdown: 1 µA
• Hibernate: 4.5 µA
• Low-Power Deep Sleep (LPDS): 115 µA
• RX Traffic : 59 mA at 54 OFDM
• TX Traffic : 229 mA at 54 OFDM, Maximum
Power
• Idle Connected (MCU in LPDS): 690 µA at
DTIM = 1
Clock Source
– 40.0-MHz Crystal With Internal Oscillator
– 32.768-kHz Crystal or External RTC
RGK Package
– 64-Pin, 9-mm × 9-mm Very Thin Quad Flat
Nonleaded (VQFN) Package, 0.5-mm Pitch
Operating Temperature
– Ambient Temperature Range: –40°C to +85°C
Device Supports SimpleLink MCU Platform
Developers' Ecosystem
2 Applications
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For Internet-of-Things (IoT) applications, such as:
– Cloud Connectivity
– Internet Gateway
– Home and Building Automation
– Appliances
– Access Control
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC3120
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Security Systems
Smart Energy
Industrial Control
Smart Plug and Metering
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Wireless Audio
IP Network Sensor Nodes
Asset Tracking
Medical Devices
3 Description
The CC3120R device is part of the SimpleLink™ microcontroller (MCU) platform that consists of Wi-Fi®,
Bluetooth® low energy, Sub-1 GHz and host MCUs. All share a common, easy-to-use development environment
with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink™
platform enables you to add any combination of the devices from the portfolio into your design, allowing 100
percent code reuse when your design requirements change. For more information, visit www.ti.com/simplelink.
Connect any microcontroller (MCU) to the internet-of-things (IoT) cloud with the CC3120R device from
Texas Instruments™. The Wi-Fi Alliance®-certified CC3120R device is part of the second generation of the
SimpleLink™ Wi-Fi® family that dramatically simplifies the implementation of low-power internet connectivity.
The CC3120R has all of the Wi-Fi and internet protocols implemented in the ROM, which runs from the
dedicated on-chip Arm® network processor and significantly offloads the host MCU and simplifies the system
integration.
The CC3120R Wi-Fi® Internet-on-a chip™ device contains a dedicated Arm® MCU that offloads many of the
networking activities from the host MCU. This subsystem includes an 802.11b/g/n radio, baseband, and MAC
with a powerful crypto engine for fast, secure internet connections with 256-bit encryption. The CC3120R
device supports station, AP, and Wi-Fi direct modes. The device also supports WPA2™ personal and enterprise
security and WPA3™ personal and enterprise. The device includes embedded TCP/IP and TLS/SSL stacks,
an HTTP server, and multiple internet protocols. The CC3120R device supports a variety of Wi-Fi provisioning
methods, including HTTP based on AP mode, SmartConfig™ technology, and WPS2.0.
As part of TI’s SimpleLink™ Wi-Fi® family second generation, the CC3120R device introduces new features and
enhanced capabilities, such as the following:
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IPv6
Enhanced Wi-Fi provisioning
Optimized low-power management
Wi-Fi AP connection with up to four stations
More concurrently opened BSD sockets; up to 16 BSD sockets, of which 6 are secure
HTTPS support
RESTful API support
Asymmetric keys crypto library
The CC3120R device is delivered with a slim and user-friendly host driver to simplify the integration and
development of networking applications. The host driver can easily be ported to most platforms and operating
systems (OS). The driver is written in strict ANSI-C (C99) programming language and requires a minimal
platform adaptation layer (porting layer). The driver has a small memory footprint and can run on 8-, 16-, or
32-bit MCUs with any clock speed (no performance or real-time dependency).
The CC3120R device comes in an easy-to-layout VQFN package and is delivered as a complete platform
solution, including various tools and software, sample applications, user and programming guides, reference
designs, and the TI E2E™ support community. The CC3120R device is part of the SimpleLink MCU Ecosystem.
Device Information
PART NUMBER (1)
CC3120RNMARGKT/R
(1)
2
PACKAGE
BODY SIZE (NOM)
VQFN (64)
9.00 mm × 9.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
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4 Functional Block Diagrams
Figure 4-1 shows the functional block diagram of the CC3120R SimpleLink Wi-Fi solution.
VCC
SPI
flash
32-MHz
crystal
40-MHz
crystal
32 kHz
MCU
MCU
CC3120R
Network Processor
nHIB
HOST_INTR
SPI/UART
Figure 4-1. Functional Block Diagram
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Figure 4-2 shows the CC3120R hardware overview.
External MCU
Wi-Fi® Network Processor
Host Interface
Hardware
1× SPI
1× UART
Power Management
Network Processor
Oscillators
Wi-Fi® Driver
TCP/IP Stack
RAM
Arm® Cortex®
ROM
Radio
RTC
Baseband
DC/DC
MAC
Processor
Crypto Engines
Application
Protocols
Synthesizer
Figure 4-2. CC3120R Hardware Overview
4
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Figure 4-3 shows an overview of the CC3120R embedded software.
User Application
6LPSOH/LQNΠ'ULYHU
SPI or UART Driver
External Microcontroller
Internet Protocols
Embedded Internet
TLS/SSL
TCP/IP
Supplicant
Wi-Fi® Driver
Wi-Fi® MAC
Embedded Wi-Fi®
Wi-Fi® Baseband
Wi-Fi® Radio
Arm® Processor (Wi-Fi® Network Processor)
Figure 4-3. CC3120R Software Overview
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................2
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 6
6 Device Comparison......................................................... 8
6.1 Related Products........................................................ 9
7 Terminal Configuration and Functions........................10
7.1 Pin Diagram.............................................................. 10
7.2 Pin Attributes.............................................................11
7.3 Connections for Unused Pins................................... 13
8 Specifications................................................................ 14
8.1 Absolute Maximum Ratings...................................... 14
8.2 ESD Ratings............................................................. 14
8.3 Power-On Hours (POH)............................................ 14
8.4 Recommended Operating Conditions.......................15
8.5 Current Consumption Summary .............................. 15
8.6 TX Power and IBAT versus TX Power Level
Settings....................................................................... 16
8.7 Brownout and Blackout Conditions........................... 18
8.8 Electrical Characteristics (3.3 V, 25°C)..................... 19
8.9 WLAN Receiver Characteristics................................20
8.10 WLAN Transmitter Characteristics..........................20
8.11 WLAN Filter Requirements..................................... 21
8.12 Thermal Resistance Characteristics....................... 21
8.13 Reset Requirement................................................. 21
8.14 Timing and Switching Characteristics..................... 22
8.15 External Interfaces.................................................. 30
9 Detailed Description......................................................34
9.1 Device Features........................................................34
9.2 Power-Management Subsystem...............................37
9.3 Low-Power Operating Modes................................... 38
9.4 Memory..................................................................... 39
9.5 Restoring Factory Default Configuration...................40
10 Applications, Implementation, and Layout............... 41
10.1 Application Information........................................... 41
10.2 PCB Layout Guidelines...........................................45
11 Device and Documentation Support..........................48
11.1 Development Tools and Software........................... 48
11.2 Firmware Updates...................................................49
11.3 Device Nomenclature..............................................49
11.4 Documentation Support.......................................... 50
11.5 Support Resources................................................. 52
11.6 Trademarks............................................................. 52
11.7 Electrostatic Discharge Caution.............................. 52
11.8 Export Control Notice.............................................. 52
11.9 Glossary.................................................................. 52
12 Mechanical, Packaging, and Orderable
Information.................................................................... 53
12.1 Packaging Information............................................ 53
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from February 7, 2018 to May 13, 2021 (from Revision * (Feb 2017) to Revision A
(May 2021))
Page
• Updated formatting and organization to reflect current TI standards..............................................................0
• Added WPA3 Personal and WPA3 Enterprise to Section 1 ............................................................................... 1
• Changed Features section..................................................................................................................................1
• Added WPA3 Personal and WPA3 Enterprise to Section 3 ............................................................................... 2
• Changed Description section .............................................................................................................................2
• Added Functional Block Diagram to the Functional Block Diagrams section..................................................... 3
• Added CC3120R Hardware Overview block diagram ........................................................................................3
• Added Device Comparison section.....................................................................................................................8
• Changed Device Features Comparison table.....................................................................................................8
• Changed CC3120 SDK Plug-In link....................................................................................................................9
• Added NC = No internal connection note to the pinout diagram ......................................................................10
• Changed Pin Attributes table............................................................................................................................ 11
• Deleted the pin number for GND_TAB .............................................................................................................11
• Changed Connections for Unused Pins table...................................................................................................13
• Changed the typical value for Hibernate from "4 µA" to "4.5 µA"..................................................................... 15
• Deleted the + sign from the typical values in the WLAN Transmitter Characteristics table.............................. 20
• Added the table note "Power of 802.11b rates are reduced to meet ETSI requirements" to the WLAN
Transmitter Characteristics table...................................................................................................................... 20
• Added Reset Requirement table ......................................................................................................................21
• Changed from "200-mS" to 200-ms" in the Device Reset section ................................................................... 22
• Changed from "pin 32" to "pin 52" in the second list item of the Device Reset section ................................... 22
• Changed the Host SPI Interface Timing diagram............................................................................................. 28
• Changed the parameter numbers in the Host SPI Interface Timing Parameters table ....................................28
6
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SWAS034A – FEBRUARY 2017 – REVISED MAY 2021
Changed Flash SPI Interface Timing diagram..................................................................................................29
Changed the parameter numbers in the Flash SPI Interface Timing Parameters table .................................. 29
Added WPA3 Personal and WPA3 Enterprise to Section 9 ............................................................................. 34
Added WPA3 Personal and WPA3 Enterprise to Section 9.1.1 ....................................................................... 34
Added WPA3 personal and enterprise to Table 9-1 .........................................................................................34
Added "The typical battery drain in this mode is 4.5 µA" to the Hibernate section........................................... 38
Added "The typical battery drain in this mode is 1 µA" to the Shutdown section..............................................38
Changed the table title from "Title" to "Recommended Flash Size" .................................................................39
Changed the CC3120R Wide-Voltage Mode Application Circuit diagram........................................................ 41
Added R14 information to the Bill of Materials for CC3120R in Wide-Voltage Mode table...............................41
Changed the CC3120R Preregulated 1.85-V Mode Application Circuit diagram ............................................ 43
Added R13 information to the Bill of Materials for CC3120R in Preregulated, 1.85-V Mode table...................43
Changed from "XTALM" to "XTAL_N" in the Clock Interfaces section..............................................................46
Changed Tools and Software section............................................................................................................... 48
Changed CC3120R Device Nomenclaturefigure.............................................................................................. 49
Changed Documentation Support section........................................................................................................ 50
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6 Device Comparison
Table 6-1 shows the features supported across different CC3220 devices.
Table 6-1. Device Features Comparison
DEVICE
FEATURE
CC3220R
CC3220S
CC3220SF
On-Chip Application Memory
RAM
256KB
256KB
256KB
Flash
–
–
1MB
Enhanced Application Level
Security
–
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming
Hardware Acceleration
Hardware Crypto Engines
Hardware Crypto Engines
Hardware Crypto Engines
Additional Networking Security
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Unique Device Identity
Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Secure Boot
No
Yes
Yes
Security Features
Additional Features
Standard
TCP/IP Stack
8
802.11 b/g/n
IPv4, IPv6
Package
9 mm × 9 mm VQFN
Sockets
16
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6.1 Related Products
For information about other devices in this family of products or related products, see the following links:
SimpleLink™ MCU
Portfolio
This portfolio offers a single development environment that delivers flexible hardware,
software and tool options for customers developing wired and wireless applications.
With 100 percent code reuse across host MCUs, Wi-Fi™, Bluetooth® low energy, Sub-1
GHz devices and more, choose the MCU or connectivity standard that fits your design.
A one-time investment with the SimpleLink software development kit (SDK) allows you
to reuse often, opening the door to create unlimited applications.
SimpleLink™ Wi-Fi®
Family
This device platform offers several Internet-on-a chip™ solutions, which address the
need of battery operated, security enabled products. Texas instruments offers a single
chip wireless microcontroller and a wireless network processor which can be paired
with any MCU, to allow developers to design new wi-fi products, or upgrade existing
products with wi-fi capabilities.
MSP432™ Host MCU These MCUs feature the Arm® Cortex®-M4 processor that offers ample processing
capability with floating point unit and memory footprint for advanced processing
algorithm, communication protocols and application needs, while incorporating a 14bit 1-msps ADC14 that provides a flexible and low-power analog with best-in-class
performance to enable developers to add differentiated sensing and measurement
capabilities to their Wi-Fi applications.
Reference Designs for TI Designs Reference Design Library is a robust reference design library spanning
CC3100 and CC3120 analog, embedded processor and connectivity. Created by TI experts to help you jump
Devices
start your system design, all TI Designs include schematic or block diagrams, BOMs
and design files to speed your time to market. Search and download designs at ti.com/
tidesigns.
SimpleLink™ Wi-Fi®
CC3120 SDK Plug-in
This SDK plug-in contains drivers, sample applications for Wi-Fi features and internet,
and documentation required to use the CC3120 solution.
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7 Terminal Configuration and Functions
7.1 Pin Diagram
VDD_ANA1
VDD_ANA2
DCDC_ANA2_SW_N
DCDC_ANA2_SW_P
VIN_DCDC_DIG
DCDC_DIG_SW
DCDC_PA_OUT
DCDC_PA_SW_N
DCDC_PA_SW_P
VIN_DCDC_PA
DCDC_ANA_SW
VIN_DCDC_ANA
LDO_IN1
SOP0
SOP1
VDD_PA_IN
VQFN 64-Pin Assignments Top View shows pin assignments for the 64-pin VQFN package.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
VIN_IO2
54
27
NC
UART1_TX
55
26
NC
VDD_DIG2
56
25
LDO_IN2
UART1_RX
57
24
VDD_PLL
TEST_58
58
23
WLAN_XTAL_P
TEST_59
59
22
WLAN_XTAL_N
TEST_60
60
21
SOP2/TCXO_EN
UART1_nCTS
61
20
NC
TEST_62
62
19
RESERVED
NC
63
18
NC
NC
64
17
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
28
HOSTINTR
53
FLASH_SPI_CS
NC
FLASH_SPI_MISO
RESERVED
FLASH_SPI_MOSI
29
FLASH_SPI_CLK
52
VIN_IO1
RTC_XTAL_N
VDD_DIG1
RESERVED
HOST_SPI_nCS
30
HOST_SPI_MISO
51
HOST_SPI_MOSI
RTC_XTAL_P
HOST_SPI_CLK
RF_BG
NC
nRESET
31
RESERVED
32
nHIB
49
50
NC
VDD_RAM
UART1_nRTS
NC = No internal connection
Figure 7-1. VQFN 64-Pin Assignments Top View
10
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7.2 Pin Attributes
Table 7-1 describes the CC3120R pins.
Note
If an external device drives a positive voltage to signal pads when the CC3120R device is not
powered, DC current is drawn from the other device. If the drive strength of the external device is
adequate, an unintentional wakeup and boot of the CC3120R device can occur. To prevent current
draw, TI recommends one of the following:
• All devices interfaced to the CC3120R device must be powered from the same power rail as the
CC3120R device.
• Use level shifters between the CC3120R device and any external devices fed from other
independent rails.
• The nRESET pin of the CC3120R device must be held low until the VBAT supply to the device is
driven and stable.
Table 7-1. Pin Attributes
PIN
2
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE(1)
DESCRIPTION
Hibernate signal input to the NWP subsystem
(active low). This is connected to the MCU
GPIO. If the GPIO from the MCU can float while
the MCU enters low power, consider adding a
pullup resistor on the board to avoid floating.
nHIB
Hi-Z
I
3
Reserved
Hi-Z
—
Reserved for future use
5
HOST_SPI_CLK
Hi-Z
I
Host interface SPI clock
6
HOST_SPI_MOSI
Hi-Z
I
Host interface SPI data input
7
HOST_SPI_MISO
Hi-Z
O
Host interface SPI data output
8
HOST_SPI_nCS
Hi-Z
I
Host interface SPI chip select (active low)
9
VDD_DIG1
Hi-Z
Power
Digital core supply (1.2 V)
10
VIN_IO1
Hi-Z
Power
I/O supply
11
FLASH_SPI_CLK
Hi-Z
O
Serial Flash interface: SPI clock
12
FLASH_SPI_MOSI
Hi-Z
O
Serial Flash interface: SPI data out
13
FLASH _SPI_MISO
Hi-Z
I
Serial Flash interface: SPI data in (active high)
14
FLASH _SPI_CS
Hi-Z
O
Serial Flash interface: SPI chip select
(active low)
15
HOST_INTR
Hi-Z
O
Interrupt output (active high)
19
Reserved
Hi-Z
—
Connect a 100-kΩ pulldown resistor to ground.
21
SOP2/TCXO_EN
Hi-Z
O
Controls restore to default mode. Enable signal
for external TCXO. Add a 10-kΩ pulldown
resistor to ground.
22
WLAN_XTAL_N
Hi-Z
Analog
Connect the WLAN 40-MHz crystal here.
23
WLAN_XTAL_P
Hi-Z
Analog
Connect the WLAN 40-MHz crystal here.
24
VDD_PLL
Hi-Z
Power
Internal PLL power supply (1.4-V nominal)
25
LDO_IN2
Hi-Z
Power
Input to internal LDO
Reserved
Hi-Z
O
Reserved for future use
31
RF_BG
Hi-Z
RF
2.4-GHz RF TX, RX
32
nRESET
Hi-Z
I
RESET input for the device. Active low input.
Use RC circuit (100 k || 0.1 µF) for power on
reset (POR).
33
VDD_PA_IN
Hi-Z
Power
Power supply for the RF power amplifier (PA)
29
30
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Table 7-1. Pin Attributes (continued)
(1)
12
PIN
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE(1)
34
SOP1
Hi-Z
—
SOP[2:0] used for factory restore. Add 100-kΩ
pulldown to ground. See .
35
SOP0
Hi-Z
—
SOP[2:0] used for factory restore. Add 100-kΩ
pulldown to ground. See .
36
LDO_IN1
Hi-Z
Power
Input to internal LDO
37
VIN_DCDC_ANA
Hi-Z
Power
Power supply for the DC/DC converter for
analog section
38
DCDC_ANA_SW
Hi-Z
Power
Analog DC/DC converter switch output
39
VIN_DCDC_PA
Hi-Z
Power
PA DC/DC converter input supply
40
DCDC_PA_SW_P
Hi-Z
Power
PA DC/DC converter switch output +ve
41
DCDC_PA_SW_N
Hi-Z
Power
PA DC/DC converter switch output –ve
42
DCDC_PA_OUT
Hi-Z
Power
PA DC/DC converter output. Connect the output
capacitor for DC/DC here.
43
DCDC_DIG_SW
Hi-Z
Power
Digital DC/DC converter switch output
44
VIN_DCDC_DIG
Hi-Z
Power
Power supply input for the digital DC/DC
converter
45
DCDC_ANA2_SW_P
Hi-Z
Power
Analog2 DC/DC converter switch output +ve
46
DCDC_ANA2_SW_N
Hi-Z
Power
Analog2 DC/DC converter switch output –ve
47
VDD_ANA2
Hi-Z
Power
Analog2 power supply input
48
VDD_ANA1
Hi-Z
Power
Analog1 power supply input
49
VDD_RAM
Hi-Z
Power
Power supply for the internal RAM
50
UART1_nRTS
Hi-Z
O
51
RTC_XTAL_P
Hi-Z
Analog
32.768-kHz XTAL_P or external CMOS level
clock input
52
RTC_XTAL_N
Hi-Z
Analog
32.768-kHz XTAL_N or 100-kΩ external pullup
for external clock
54
VIN_IO2
Hi-Z
Power
I/O power supply. Same as battery voltage.
55
UART1_TX
Hi-Z
O
56
VDD_DIG2
Hi-Z
Power
57
UART1_RX
Hi-Z
I
UART host interface; connect to test point on
prototype for Flash programming.
60
TEST_60
Hi-Z
O
Test signal; connect to an external test point.
61
UART1_nCTS
Hi-Z
I
UART host interface (active low)
62
TEST_62
Hi-Z
O
Test signal; connect to an external test point.
—
GND
—
Power
DESCRIPTION
UART host interface (active low)
UART host interface. Connect to test point on
prototype for Flash programming.
Digital power supply (1.2 V)
Ground tab used as thermal and electrical
ground
I = Input
O = Output
RF = radio frequency
I/O = bidirectional
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7.3 Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. Table 7-2 provides a list of NC pins.
Table 7-2. Connections for Unused Pins
PIN
DEFAULT FUNCTION
STATE AT RESET
AND HIBERNATE
I/O TYPE
1
NC
WLAN analog
—
Unused; leave unconnected.
4
NC
WLAN analog
—
Unused; leave unconnected.
16
NC
WLAN analog
—
Unused; leave unconnected.
17
NC
WLAN analog
—
Unused; leave unconnected.
18
NC
WLAN analog
—
Unused; leave unconnected.
20
NC
WLAN analog
—
Unused; leave unconnected.
26
NC
WLAN analog
—
Unused; leave unconnected.
27
NC
WLAN analog
—
Unused; leave unconnected.
28
NC
WLAN analog
—
Unused; leave unconnected.
53
NC
WLAN analog
—
Unused; leave unconnected.
58
NC
WLAN analog
—
TEST_58 Unused; leave
unconnected.
59
NC
WLAN analog
—
TEST_59 Unused; leave
unconnected.
63
NC
WLAN analog
—
TEST_60 Unused; leave
unconnected.
64
NC
WLAN analog
—
Unused; leave unconnected.
DESCRIPTION
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8 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
8.1 Absolute Maximum Ratings
These specifications indicate levels where permanent damage to the device can occur. Functional operation is not ensured
under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term
reliability of the device. (1) (2)
VBAT and VIO
Pins: 37, 39, 44
VIO – VBAT (differential)
Pins: 10, 54
MIN
MAX
UNIT
–0.5
3.8
V
0.0
V
Digital inputs
–0.5
VIO + 0.5
V
RF pins
–0.5
2.1
V
Analog pins, crystal
–0.5
2.1
V
Operating temperature, TA
–40
85
°C
Storage temperature, Tstg
–55
125
°C
(1)
(2)
Pins: 22, 23, 51, 52
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
8.2 ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Power-On Hours (POH)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's
standard terms and conditions for TI semiconductor products.
OPERATING CONDITION
TA up to 85°C(1)
(1)
14
POWER-ON HOURS [POH]
(hours)
87,600
The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
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8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2)
VBAT, VIO
(shorted to VBAT)
Pins: 10, 37, 39,
44, 54
Direct battery
connection(3)
(3)
(4)
(5)
(6)
TYP
MAX
2.1(6)
3.3
3.6
Preregulated 1.85 V(4) (5)
Ambient thermal slew
(1)
(2)
MIN
–20
20
UNIT
V
°C/minute
Operating temperature is limited by crystal frequency variation.
When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the
transmission.
To ensure WLAN performance, ripple on the 2.1- to 3.3-V supply must be less than ±300 mV.
To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).
TI recommends keeping VBAT above 1.85 V. For lower voltages, use a boost converter.
The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1
V, and care must be taken when operating at the minimum specified voltage.
8.5 Current Consumption Summary
TA = 25°C, VBAT = 3.6 V
TEST CONDITIONS(1) (4)
PARAMETER
1 DSSS
6 OFDM
TX
54 OFDM
RX(6)
MIN
TYP
TX power level = 0
272
TX power level = 4
188
TX power level = 0
248
TX power level = 4
179
TX power level = 0
223
TX power level = 4
160
1 DSSS
53
54 OFDM
53
MAX UNIT
mA
mA
Idle connected(2)
690
µA
LPDS
115
µA
Hibernate(5)
4.5
µA
1
µA
Shutdown
Peak calibration current(3) (6)
(1)
(2)
(3)
(4)
(5)
(6)
VBAT = 3.6 V
420
VBAT = 3.3 V
450
VBAT = 2.1 V
670
VBAT = 1.85 V
700
mA
TX power level = 0 implies maximum power (see Figure 8-1, Figure 8-2, and Figure 8-3). TX power level = 4 implies output power
backed off approximately 4 dB.
DTIM = 1
The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is
performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.
There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further
details, see CC3120, CC3220 SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
The CC3120R system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
For the 1.85-V mode, the hibernate current is higher by 50 µA across all operating modes because of leakage into the PA and analog
power inputs.
The RX current is measured with a 1-Mbps throughput rate.
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8.6 TX Power and IBAT versus TX Power Level Settings
Figure 8-1, Figure 8-2, and Figure 8-3 show TX Power and IBAT versus TX power level settings for modulations
of 1 DSSS, 6 OFDM, and 54 OFDM, respectively.
In Figure 8-1, the area enclosed in the circle represents a significant reduction in current during transition from
TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends
using TX power level 4 to reduce the current.
1 DSSS
19.00
280.00
Color by
17.00
264.40
TX Power (dBm)
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
TX Power (dBm)
15.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
15
Figure 8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
16
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54 OFDM
19.00
280.00
Color by
17.00
IBAT (VBAT @ 3.6 V)
249.00
13.00
233.30
11.00
218.00
9.00
202.00
7.00
186.70
5.00
171.00
3.00
155.60
1.00
140.00
0
1
2
3
4
5
6
7
8
9
10
TX power level setting
11
12
13
14
IBAT (VBAT @ 3.6 V)(mAmp)
15.00
TX Power (dBm)
264.40
TX Power (dBm)
15
Figure 8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
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8.7 Brownout and Blackout Conditions
The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 8-4 and Figure
8-5). This condition must be considered during design of the power supply routing, especially when operating
from a battery. High-current operations, such as a TX packet or any external activity (not necessarily related
directly to networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The
resistance includes the internal resistance of the battery, the contact resistance of the battery holder (four
contacts for 2× AA batteries), and the wiring and PCB routing resistance.
Note
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during
HIBERNATE state.
Figure 8-4. Brownout and Blackout Levels (1 of 2)
Figure 8-5. Brownout and Blackout Levels (2 of 2)
18
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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the
Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout
condition is equivalent to a hardware reset event in which all states within the device are lost.
Table 8-1 lists the brownout and blackout voltage levels.
Table 8-1. Brownout and Blackout Voltage Levels
CONDITION
VOLTAGE LEVEL
UNIT
Vbrownout
2.1
V
Vblackout
1.67
V
8.8 Electrical Characteristics (3.3 V, 25°C)
GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
Pin capacitance
VIH
High-level input voltage
0.65 × VDD
VDD + 0.5 V
V
VIL
Low-level input voltage
–0.5
0.35 × VDD
V
IIH
High-level input current
5
nA
IIL
Low-level input current
5
nA
VOH
VOL
IOH
IOL
4
UNIT
CIN
High-level output voltage
Low-level output voltage
High-level
source current
Low-level
sink current
pF
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 8 mA; configured I/O drive
strength = 8 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.75
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.7
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 8 mA; configured I/O drive
strength = 8 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
VDD × 0.25
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
VDD × 0.35
2-mA drive
2
4-mA drive
4
6-mA drive
6
2-mA drive
2
4-mA drive
4
6-mA drive
6
V
V
mA
mA
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GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1)
PARAMETER
VIL
(1)
(2)
TEST CONDITIONS
nRESET(2)
MIN
NOM
MAX
0.6
UNIT
V
TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk
of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
The nRESET pin must be held below 0.6 V for the device to register a reset.
8.9 WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER
TEST CONDITIONS (Mbps)
Sensitivity
(8% PER for 11b rates, 10% PER for 11g/11n
rates) (10% PER)(3)
TYP(1)
1 DSSS
–96.0
2 DSSS
–94.0
11 CCK
–88.0
6 OFDM
–90.5
9 OFDM
–90.0
18 OFDM
–86.5
36 OFDM
–80.5
54 OFDM
–74.5
(GF)(2)
–71.5
MCS7 (MM)(2)
–70.5
MCS7
Maximum input level
(10% PER)
(1)
(2)
(3)
MIN
802.11b
–4.0
802.11g
–10.0
MAX
UNIT
dBm
dBm
In preregulated 1.85-V mode, RX sensitivity is 0.25- to 1-dB lower.
Sensitivity for mixed mode is 1-dB worse.
Sensitivity is 1-dB worse on channel 13 (2472 MHz).
8.10 WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz).(1) (2) (3)
PARAMETER
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
TEST CONDITIONS(3)
MIN
18.0
2 DSSS
18.0
11 CCK
18.3
6 OFDM
17.3
9 OFDM
17.3
18 OFDM
17.0
36 OFDM
16.0
54 OFDM
14.5
MCS7 (MM)
Transmit center frequency accuracy
(1)
(2)
(3)
20
TYP
1 DSSS
MAX
UNIT
dBm
13.0
–25
25
ppm
The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits.
Power of 802.11b rates are reduced to meet ETSI requirements.
In preregulated 1.85-V mode, maximum TX power is 0.25- to 0.75-dB lower for modulations higher than 18 OFDM.
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8.11 WLAN Filter Requirements
The device requires an external band-pass filter to meet the various emission standards, including FCC. Section
8.11.1 presents the attenuation requirements for the band-pass filter. TI recommends using the same filter used
in the reference design to ease the process of certification.
8.11.1 WLAN Filter Requirements
PARAMETER
FREQUENCY (MHz)
Return loss
Insertion
2412 to 2484
loss(1)
TYP
Reference impendence
UNIT
dB
1
800 to 830
30
45
1600 to 1670
20
25
3200 to 3300
30
48
4000 to 4150
45
50
4800 to 5000
20
25
5600 to 5800
20
25
6400 to 6600
20
35
7200 to 7500
35
45
7500 to 10000
20
25
2412 to 2484
Filter type
MAX
10
2412 to 2484
Attenuation
(1)
MIN
1.5
dB
dB
50
Ω
Bandpass
Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
8.12 Thermal Resistance Characteristics
8.12.1 Thermal Resistance Characteristics for RGK Package
AIR FLOW
PARAMETER
0 lfm (C/W)
150 lfm (C/W)
250 lfm (C/W)
500 lfm (C/W)
θja
23
14.6
12.4
10.8
Ψjt
0.2
0.2
0.3
0.1
Ψjb
2.3
2.3
2.2
2.4
θjc
6.3
θjb
2.4
8.13 Reset Requirement
PARAMETER
VIH
MIN
Operation mode level
VIL
Shutdown mode
level(1)
0
Minimum time for nReset low for resetting the module
Tr and Tf
(1)
TYP
0.65 × VBAT
Rise and fall times
0.6
5
MAX
UNIT
V
V
ms
20
µs
The nRESET pin must be held below 0.6 V for the module to register a reset.
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8.14 Timing and Switching Characteristics
8.14.1 Power Supply Sequencing
For proper operation of the CC3120R device, perform the recommended power-up sequencing as follows:
1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board.
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K
||, 1 µF, RC = 100 ms).
3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see Section 8.14.3.
8.14.2 Device Reset
When a device restart is required, the user may either issue a negative pulse on the nHIB pin (pin 2) or on the
nRESET pin (pin 32), keeping the other pulled high, depending on the configuration of the platform. In case the
nRESET pin is used, the user must follow one of the two alternatives to ensure the reset is properly applied:
•
•
A high-to-low reset pulse (on pin 32) of at least 200-ms duration
If the above cannot be ensured, a pulldown resistor of 2 MΩ should be connected to pin 52 (RTC_XTAL_N).
If implemented, a shorter pulse of at least 100 µs can be used.
To ensure a proper reset sequence, the user has to call the sl_stop function prior to toggling the reset.
8.14.3 Reset Timing
8.14.3.1 nRESET (32-kHz Crystal)
Figure 8-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal.
T1
T2
T3
VBAT
VIO
nRESET
nHIB
STATE POWER RESET
OFF
HW INIT
Device Ready to
serve API calls
FW INIT
32-kHz
XTAL
Figure 8-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)
Section 8.14.3.2 describes the timing requirements for the crystal first-time power-up and reset removal.
8.14.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
ITEM
NAME
T1
Supply settling time
T2
Hardware wake-up time
T3
Initialization time
DESCRIPTION
Depends on application board
power supply, decoupling capacitor,
and so on
32-kHz crystal settling plus
firmware initialization time plus
radio calibration
MIN
TYP
MAX
UNIT
3
ms
25
ms
1.35
s
8.14.3.3 nRESET (External 32-kHz)
Figure 8-7 shows the reset timing diagram for the external 32-kHz first-time power-up and reset removal.
22
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T1
T2
T3
RESET
HW INIT
FW INIT
VBAT
VIO
nRESET
nHIB
STATE
POWER
OFF
Device Ready to
serve API calls
32-kHz
RTC CLK
Figure 8-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz)
Section 8.14.3.3.1 describes the timing requirements for the external first-time power-up and reset removal.
8.14.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
ITEM
NAME
T1
Supply settling time
T2
Hardware wake-up time
T3
Initialization time
DESCRIPTION
Depends on application board power
supply, decoupling capacitor, and so
on
Firmware initialization time plus radio
calibration
MIN
TYP
MAX
UNIT
3
ms
25
ms
250
ms
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8.14.4 Wakeup From HIBERNATE Mode
Figure 8-8 shows the timing diagram for wakeup from HIBERNATE mode.
Thib_min
Twake_from_hib
HIBERNATE
HW WAKEUP+FW INIT
VBAT
VIO
nRESET
nHIB
ACTIVE
ACTIVE
HIBERNATE
32-kHz
XTAL/CXO
Figure 8-8. nHIB Timing Diagram
Note
The 32.768-kHz crystal is kept enabled by default when the chip goes into HIBERNATE mode in
response to nHIB being pulled low.
Section 8.14.4.1 Section 8.14.4.1 describes the timing requirements for nHIB.
8.14.4.1 nHIB Timing Requirements
ITEM
NAME
DESCRIPTION
Thib_min
Minimum hibernate time
Minimum pulse width of nHIB being low(2)
Twake_from_hib
Hardware wakeup time plus
firmware initialization time
See(1)
(1)
(2)
MIN
TYP
10
MAX
UNIT
ms
50
ms
If temperature changes by more than 20°C, initialization time from HIB can increase by 200 ms due to radio calibration.
Ensure that the nHIB pulse width is kept above the minimum requirement under all conditions (such as power up, MCU reset, and so
on).
8.14.5 Clock Specifications
The CC3120R device requires two separate clocks for its operation:
•
•
A slow clock running at 32.768 kHz is used for the RTC.
A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.
The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated
TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system
and to reduce overall cost.
8.14.5.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock
frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P
(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.
Figure 8-9 shows the crystal connections for the slow clock.
24
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51
RTC_XTAL_P
10 pF
GND
32.768 kHz
RTC_XTAL_N
52
10 pF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 8-9. RTC Crystal Connections
Section 8.14.5.1.1 lists the RTC crystal requirements.
8.14.5.1.1 RTC Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
MAX
UNIT
±150
ppm
32.768
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
32.768 kHz
kHz
70
kΩ
8.14.5.2 Slow Clock Using an External Clock
When an RTC oscillator is present in the system, the CC3120R device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must be a
CMOS-level clock compatible with VIO fed to the device.
Figure 8-10 shows the external RTC input connection.
RTC_XTAL_P
32.768 kHz
VIO
Host system
100 KΩ
RTC_XTAL_N
Copyright © 2017, Texas Instruments Incorporated
Figure 8-10. External RTC Input
Section 8.14.5.2.1 lists the external RTC digital clock requirements.
8.14.5.2.1 External RTC Digital Clock Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
Frequency accuracy
(Initial plus temperature plus aging)
tr, tf
Input transition time tr, tf (10% to 90%)
MIN
TYP
MAX
UNIT
32768
Hz
±150
ppm
100
ns
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CHARACTERISTICS
TEST CONDITIONS
Frequency input duty cycle
Vih
Slow clock input voltage limits
Vil
Square wave, DC coupled
MIN
TYP
MAX
20%
50%
80%
0.65 × VIO
VIO
0
0.35 × VIO
1
Input impedance
UNIT
V
Vpeak
MΩ
5
pF
8.14.5.3 Fast Clock (Fref) Using an External Crystal
The CC3120R device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The
crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading
capacitors.
Figure 8-11 shows the crystal connections for the fast clock.
23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
WLAN_XTAL_N
22
6.2 pF
GND
SWAS031-030
A.
The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for
information on frequency tuning.
Figure 8-11. Fast Clock Crystal Connections
Section 8.14.5.3.1 lists the WLAN fast-clock crystal requirements.
8.14.5.3.1 WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
Frequency
TYP
MAX
40
Frequency accuracy
Initial plus temperature plus aging
Crystal ESR
40 MHz
26
MIN
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UNIT
MHz
±25
ppm
60
Ω
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8.14.5.4 Fast Clock (Fref) Using an External Oscillator
The CC3120R device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the
clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external
TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the
system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the
LDO improves noise on the TCXO power supply.
Figure 8-12 shows the connection.
Vcc
XO (40 MHz)
C
CC3120R
EN
TCXO_EN
82 pF
WLAN_XTAL_P
OUT
WLAN_XTAL_N
Copyright © 2017, Texas Instruments Incorporated
Figure 8-12. External TCXO Input
Section 8.14.5.4.1 lists the external Fref clock requirements.
8.14.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
CHARACTERISTICS
TEST CONDITIONS
MIN
Frequency
TYP
Frequency accuracy (Initial plus temperature plus
aging)
45%
Sine or clipped sine wave, AC
coupled
Clock voltage limits
0.7
at 1 kHz
Phase noise at 40 MHz
55%
1.2
–143
12
Capacitance
Vpp
–138.5 dBc/Hz
at 100 kHz
Input impedance
ppm
–125
at 10 kHz
Resistance
50%
UNIT
MHz
±25
Frequency input duty cycle
Vpp
MAX
40.00
kΩ
7
pF
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8.14.6 Interfaces
This section describes the interfaces that are supported by the CC3120R device:
•
•
Host SPI
Flash SPI
8.14.6.1 Host SPI Interface Timing
Figure 8-13 shows the Host SPI interface timing diagram.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 8-13. Host SPI Interface Timing
Section 8.14.6.1.1 lists the Host SPI interface timing parameters.
8.14.6.1.1 Host SPI Interface Timing Parameters
PARAMETER
NUMBER
(1)
(2)
28
MIN
MAX
Clock frequency at VBAT = 3.3 V
20
Clock frequency at VBAT ≤ 2.1 V
12
UNIT
T1
F(1)
T2
tclk (1) (2)
Clock period
T3
tLP (1)
Clock low period
T4
tHT
(1)
T5
D(1)
Duty cycle
T6
tIS (1)
RX data setup time
4
ns
T7
tIH (1)
RX data hold time
4
ns
(1)
T8
tOD
T9
tOH (1)
50
Clock high period
45%
MHz
ns
25
ns
25
ns
55%
TX data output delay
20
ns
TX data hold time
24
ns
The timing parameter has a maximum load of 20 pF at 3.3 V.
Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. The nCS can be deasserted 10 ns after the clock
edge.
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8.14.6.2 Flash SPI Interface Timing
Figure 8-14 shows the Flash SPI interface timing diagram.
T2
CLK
T6
T7
MISO
T9
T8
MOSI
Figure 8-14. Flash SPI Interface Timing
Section 8.14.6.2.1 lists the Flash SPI interface timing parameters.
8.14.6.2.1 Flash SPI Interface Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
20
MHz
T1
F
Clock frequency
T2
tclk
Clock period
T3
tLP
Clock low period
T4
tHT
Clock high period
T5
D
Duty cycle
T6
tIS
RX data setup time
1
ns
T7
tIH
RX data hold time
2
ns
T8
tOD
TX data output delay
T9
tOH
TX data hold time
50
45%
ns
25
ns
25
ns
55%
8.5
ns
8
ns
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8.15 External Interfaces
8.15.1 SPI Flash Interface
The external serial Flash stores the user profiles and firmware patch updates. The CC3120R device acts as a
master in this case; the SPI serial Flash acts as the slave device. This interface can work up to a speed of 20
MHz.
Figure 8-15 shows the SPI Flash interface.
CC3120R (master)
Serial Flash
FLASH_SPI_CLK
SPI_CLK
FLASH_SPI_CS
SPI_CS
FLASH_SPI_MISO
SPI_MISO
FLASH_SPI_MOSI
SPI_MOSI
Figure 8-15. SPI Flash Interface
Section 8.15.1.1 lists the SPI Flash interface pins.
8.15.1.1 SPI Flash Interface
PIN NAME
DESCRIPTION
FLASH_SPI_CLK
Clock (up to 20 MHz) CC3120R device to serial Flash
FLASH_SPI_CS
CS signal from CC3120R device to serial Flash
FLASH_SPI_MISO
Data from serial Flash to CC3120R device
FLASH_SPI_MOSI
Data from CC3120R device to serial Flash
30
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8.15.2 SPI Host Interface
The device interfaces to an external host using the SPI interface. The CC3120R device can interrupt the host
using the HOST_INTR line to initiate the data transfer over the interface. The SPI host interface can work up to a
speed of 20 MHz.
Figure 8-16 shows the SPI host interface.
MCU
CC3120R (slave)
HOST_SPI_CLK
SPI_CLK
HOST_SPI_nCS
SPI_nCS
HOST_SPI_MISO
SPI_MISO
HOST_SPI_MOSI
SPI_MOSI
HOST_INTR
INTR
nHIB
GPIO
Copyright © 2017, Texas Instruments Incorporated
Figure 8-16. SPI Host Interface
Section 8.15.2.1 lists the SPI host interface pins.
8.15.2.1 SPI Host Interface
PIN NAME
DESCRIPTION
HOST_SPI_CLK
Clock (up to 20 MHz) from MCU host to CC3120R device
HOST_SPI_nCS
CS (active low) signal from MCU host to CC3120R device
HOST_SPI_MOSI
Data from MCU host to CC3120R device
HOST_INTR
Interrupt from CC3120R device to MCU host
HOST_SPI_MISO
Data from CC3120R device to MCU host
nHIB
Active-low signal that commands the CC3120R device to enter hibernate mode (lowest
power state)
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8.15.3 Host UART Interface
The SimpleLink device requires the UART configuration described in Section 8.15.3.1.
8.15.3.1 SimpleLink™ UART Configuration
PROPERTY
SUPPORTED CC3120R CONFIGURATION
Baud rate
115200 bps, no auto-baud rate detection, can be changed by the host up to 3 Mbps using a special command
Data bits
8 bits
Flow control
CTS/RTS
Parity
None
Stop bits
1
Bit order
LSBit first
Host interrupt polarity
Active high
Host interrupt mode
Rising edge or level 1
Endianness
Little-endian only(1)
(1)
The SimpleLink device does not support automatic detection of the host length while using the UART interface.
8.15.3.2 5-Wire UART Topology
Figure 8-17 shows the typical 5-wire UART topology comprised of four standard UART lines plus one IRQ line
from the device to the host controller to allow efficient low-power mode.
HOST MCU
UART
nRTS
nRTS
nCTS
nCTS
TX
TX
RX
RX
HOST_INTR(IRQ)
CC3120R SL
UART
HOST_INTR(IRQ)
Copyright © 2017, Texas Instruments Incorporated
Figure 8-17. Typical 5-Wire UART Topology
This topology is recommended because the configuration offers the maximum communication reliability and
flexibility between the host and the SimpleLink device.
8.15.3.3 4-Wire UART Topology
The 4-wire UART topology eliminates the host IRQ line (see Figure 8-18). Using this topology requires meeting
one of the following conditions:
•
•
The host is always awake or active.
The host goes to sleep, but the UART module has receiver start-edge detection for auto wakeup and does
not lose data.
HOST MCU
UART
nRTS
nRTS
nCTS
nCTS
TX
TX
RX
RX
H_IRQ
X
CC3120R SL
UART
H_IRQ
Copyright © 2017, Texas Instruments Incorporated
Figure 8-18. 4-Wire UART Configuration
32
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8.15.3.4 3-Wire UART Topology
The 3-wire UART topology requires only the following lines (see Figure 8-19):
•
•
•
RX
TX
CTS
nRTS
nRTS
X
nCTS
HOST MCU
UART
nCTS
TX
TX
RX
RX
H_IRQ
X
CC3120R SL
UART
H_IRQ
Copyright © 2017, Texas Instruments Incorporated
Figure 8-19. 3-Wire UART Topology
Using this topology requires meeting one of the following conditions:
•
•
•
The host always stays awake or active.
The host goes to sleep but the UART module has receiver start-edge detection for auto-wake-up and does
not lose data.
The host can always receive any amount of data transmitted by the SimpleLink device because there is no
flow control in this direction.
Because there is no full flow control, the host cannot stop the SimpleLink device to send its data; thus, the
following parameters must be carefully considered:
• Maximum baud rate
• RX character interrupt latency and low-level driver jitter buffer
• Time consumed by the user's application
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9 Detailed Description
The CC3120R Wi-Fi Internet-on-a-chip contains a dedicated Arm MCU that offloads many of the networking
activities from the host MCU. The device includes an 802.11b/g/n radio, baseband, and MAC with a powerful
crypto engine for a fast, secure WLAN and Internet connections with 256-bit encryption. The CC3120R device
supports station, AP, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security,
WPS 2.0, and WPA3 personal and enterprise security. The Wi-Fi network processor includes an embedded IPv6
and IPv4 TCP/IP stack.
9.1 Device Features
9.1.1 WLAN
The WLAN features are as follows:
•
802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP,
Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels 1 to 13.
Note
802.11n is supported only in Wi-Fi station, Wi-Fi direct, and P2P client mode
•
•
•
•
•
Autocalibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna without
requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial Flash allows automatic
fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal, and WPA3
Enterprise.
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the provisioning
decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point using HTTPS
– SmartConfig Technology: a 1-step, 1-time process to connect a CC3120R-enabled device to the home
wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it is usable by
deeply embedded applications
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without
adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working
channel, rate, and transmitted power. The receiver mode works with the filtering options.
9.1.2 Network Stack
The Network Stack features are as follows:
•
Integrated IPv4, IPv6 TCP/IP stack with BSD (BSD adjacent) socket APIs for simple Internet connectivity with
any MCU, microprocessor, or ASIC
Note
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
•
34
Support of 16 simultaneous TCP, UDP, or RAW sockets
Support of 6 simultaneous SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
Built-in network application and utilities:
– HTTP/HTTPS
• Web page content stored on serial Flash
• RESTful APIs for setting and configuring application content
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• Dynamic user callbacks
– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized
server. After connecting to the access point, the CC3120R device provides critical information, such as
device name, IP, vendor, and port number.
– DHCP server
– Ping
Table 9-1 summarizes the NWP features.
Table 9-1. NWP Features
Feature
Description
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
Wi-Fi
Channels 1 to 13
Wi-Fi security
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise
Wi-Fi provisioning
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP/HTTPS web server
IP protocols
IPv4/IPv6
IP addressing
Static IP, LLA, DHCPv4, DHCPv6 (Stateful) with DAD and stateless auto configuration
Cross layer
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW IP
Ping
Network applications and
utilities
HTTP/HTTPS web server
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Security
Trusted root-certificate catalog
TI root-of-trust public key
Power management
Enhanced power policy management uses 802.11 power save and deep sleep power modes
RF Transceiver
Other
Programmable RX Filters with Events trigger mechanism including WoWLAN
Recovery mechanism – Restore to factory default
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9.1.3 Security
The SimpleLink Wi-Fi CC3120R Internet-on-a-chip device enhances the security capabilities available for
development of IoT devices, while completely offloading these activities from the MCU to the networking
subsystem. The security capabilities include the following key features:
Wi-Fi and Internet Security:
•
Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK)
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0 MSCHAPv2
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
•
Secure sockets
– Protocol versions: SSL v3/TLS 1.0/TLS 1.1/TLS 1.2
– On-chip powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES
encryption for TLS and SSL connections
– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
36
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•
•
•
•
SWAS034A – FEBRUARY 2017 – REVISED MAY 2021
– Server authentication
– Client authentication
– Domain name verification
– Socket upgrade to secure socket – STARTTLS
Secure HTTP server (HTTPS)
The Trusted root-certificate catalog verifies that the CA used by the application is trusted and known secure
content delivery
The TI root-of-trust public key is a hardware-based mechanism that allows authenticating TI as the genuine
origin of a given content using asymmetric keys
Secure content delivery allows file transfer to the system in a secure way on any unsecured tunnel
Code and Data Security:
•
•
Secured network information: Network passwords and certificates are encrypted
Secured and authenticated service pack: SP is signed based on TI certificate
9.1.4 Host Interface and Driver
•
•
•
Interfaces over a 4-wire serial peripheral interface (SPI) with any MCU or a processor at a clock speed of 20
MHz.
Interfaces over UART with any MCU with a baud rate up to 3 Mbps. A low footprint driver is provided for TI
MCUs and is easily ported to any processor or ASIC.
Simple APIs enable easy integration with any single-threaded or multithreaded application.
9.1.5 System
•
•
•
Works from a single preregulated power supply or connects directly to a battery
Ultra-low leakage when disabled (hibernate mode) with a current of less than 4 µA with the RTC running
Integrated clock sources
9.2 Power-Management Subsystem
The CC3120R power-management subsystem contains DC/DC converters to accommodate the different voltage
or current requirements of the system.
•
•
•
Digital DC/DC (Pin 44)
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
ANA1 DC/DC (Pin 38)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the ANA1 DC/DC converter is bypassed.
PA DC/DC (Pin 39)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the PA DC/DC converter is bypassed.
The CC3120R device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage
supply range. The internal power management, including DC/DC converters and LDOs, generates all of the
voltages required for the device to operate from a wide variety of input sources. For maximum flexibility, the
device can operate in the modes described in Section 9.2.1 and Section 9.2.2.
9.2.1 VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the device is powered directly by the battery or preregulated 3.3-V
supply . All other voltages required to operate the device are generated internally by the DC/DC converters. This
scheme supports wide-voltage operation from 2.1 to 3.6 V and is thus the most common mode for the device.
9.2.2 Preregulated 1.85V
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at pins 10, 25, 33, 36,
37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V supply. This mode
provides the lowest BOM count version in which inductors used for PA DC/DC and ANA1 DC/DC (2.2 and 1 µH)
and a capacitor (22 µF) can be avoided.
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In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following characteristics:
• Load current capacity ≥900 mA
• Line and load regulation with
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