BQ2014SN-D120

bq2014 Gas Gauge IC with External Charge Control Features General Description ➤ Conservative and repeatable measurement of available charge in rechargeable batteries The bq2014 Gas Gauge IC is intended for battery-pack or in-system installation to maintain an accurate record of available battery charge. The IC monitors the voltage drop across a sense resistor connected in series between the negative battery terminal and ground to determine charge and discharge activity of the battery. ➤ Charge control output operates an external charge controller such as the bq2004 Fast Charge IC ➤ Designed for battery pack integration - 120µA typical standby current ➤ Display capacity via single-wire serial communication port or direct drive of LEDs ➤ Measurements compensated for current and temperature ➤ Self-discharge compensation using internal temperature sensor ➤ User-selectable end-of-discharge threshold ➤ Battery voltage, nominal available charge, temperature, etc. available over serial port ➤ 16-pin narrow SOIC Pin Connections Self-discharge of NiMH and NiCd batteries is estimated based on an internal timer and temperature sensor. Compensations for battery temperature and rate of charge or discharge are applied to the charge, discharge, and self-discharge calculations to provide available charge information across a wide range of operating conditions. Battery capacity is automatically recalibrated, or “learned,” in the course of a discharge cycle from full to empty. Nominal Available Charge (NAC) may be directly indicated using a five-segment LED display. The bq2014 supports a simple singleline bidirectional serial link to an external processor (with a common ground). The bq2014 outputs battery information in response to external commands over the serial link. Internal registers include available charge, temperature, capacity, battery voltage, battery ID, battery status, and programming pin settings. To support subassembly testing, the outputs may also be controlled. The external processor may also overwrite some of the bq2014 gas gauge data registers. The bq2014 may operate directly from three or four cells. With the REF output and an external transistor, a simple, inexpensive regulator can be built to provide VCC across a greater number of cells. The bq2014 includes a charge control output that controls an external Fast Charge IC such as the bq2004. Pin Names LCOM LCOM 1 16 VCC SEG1/PROG1 2 15 REF SEG2/PROG2 3 14 CHG SEG3/PROG3 4 13 DQ SEG4/PROG4 5 12 EMPTY SEG5/PROG5 6 11 SB DONE 7 10 DISP VSS 8 9 LED common output SEG1/PROG1 LED segment 1/ program 1 input SEG2/PROG2 LED segment 2/ program 2 input SEG3/PROG3 LED segment 3/ program 3 input SEG4/PROG4 LED segment 4/ program 4 input REF Voltage reference output CHG Charge control output DQ Serial communications input/output EMPTY Empty battery indicator output SB Battery sense input DISP Display control input SR Sense resistor input VCC 3.0–6.5V VSS System ground SR 16-Pin Narrow SOIC PN201401.eps SEG5/PROG5 LED segment 5/ program 5 input DONE Fast charge complete 12/95 C 1 bq2014 SR Pin Descriptions LCOM The voltage drop (VSR) across the sense resistor RS is monitored and integrated over time to interpret charge and discharge activity. The SR input is tied to the high side of the sense resistor. VSR < VSS indicates discharge, and VSR > VSS indicates charge. The effective voltage drop VSRO, as seen by the bq2014, is VSR + VOS (see Table 5). LED common output Open-drain output switches VCC to source current for the LEDs. The switch is off during initialization to allow reading of the soft pull-up or pull-down programming resistors. LCOM is also in a high impedance state when the display is off. SEG1– SEG5 LED display segment outputs (dual function with PROG1—PROG5) DISP Programmed full count selection imputs (dual function with SEG1—SEG5) These three-level input pins define the programmed full count (PFC) thresholds described in Table 2. PROG3– PROG4 SB Gas gauge rate selection inputs (dual function with SEG3—SEG4) Self-discharge rate selection (dual function with SEG5) EMPTY Charge control output DQ This open-drain output becomes active high when charging is allowed. DONE Battery empty output This open-drain output becomes highimpedance on detection of a valid final endof-discharge voltage (VEDVF) and is low following the next application of a valid charge. This three-level input pin defines the selfdischarge compensation rate shown in Table 1. CHG Secondary battery input This input monitors the single-cell voltage potential through a high-impedance resistive divider network for the end-of-discharge voltage (EDV) thresholds,maximum charge voltage (MCV), and battery removed. These three-level input pins define the programmed full count (PFC) thresholds described in Table 2. PROG5 Display control input DISP high disables the LED display. DISP tied to VCC allows PROGX to connect directly to VCC or VSS instead of through a pull-up or pull-down reistor. DISP floating allows the LED display to be active during a valid charge or during discharge if the NAC register is updated at a rate equivalent to V SRO ≤ -4mV. DISP low activates the display. See Table 1. Each output may activate an LED to sink the current sourced from LCOM. PROG1– PROG5 Sense resistor input Serial I/O pin This is an open-drain bidirectional pin. REF Fast charge complete Voltage reference output for regulator REF provides a voltage reference output for an optional micro-regulator. This input is used to communicate the status of an external charge controller such as the bq2004 Fast Charge IC. Note: This pin must be pulled down to VSS using a 200KΩ resistor. 2 VCC Supply voltage input VSS Ground bq2014 Figure 1 shows a typical battery pack application of the bq2014 using the LED display capability as a chargestate indicator. The bq2014 is configured to display capacity in a relative display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery “full” reference. The LED segments output a percentage of the available charge based on NAC and LMD. A push-button display feature is available for momentarily enabling the LED display. Functional Description General Operation The bq2014 determines battery capacity by monitoring the amount of charge input to or removed from a rechargeable battery. The bq2014 measures discharge and charge currents, estimates self-discharge, monitors the battery for low-battery voltage thresholds, and compensates for temperature and charge/discharge rates. The charge measurement is made by monitoring the voltage across a small-value series sense resistor between the battery’s negative terminal and ground. The available battery charge is determined by monitoring this voltage over time and correcting the measurement for the environmental and operating conditions. The bq2014 monitors the charge and discharge currents as a voltage across a sense resistor (see RS in Figure 1). A filter between the negative battery terminal and the SR pin is required. Figure 1. Battery Pack Application Diagram—LED Display, 3 bq2014 compensations, self-discharge counting, and available charge display translation. The temperature range is available over the serial port in 10°C increments as shown below: Voltage Thresholds In conjunction with monitoring VSR for charge/discharge currents, the bq2014 monitors the single-cell battery potential through the SB pin. The single-cell voltage potential is determined through a resistor/divider network per the following equation: R2 = N −1 R3 where N is the number of cells, R2 is connected to the positive battery terminal, and R3 is connected to the negative battery terminal. The single-cell battery voltage is monitored for the end-of-discharge voltage (EDV) and for maximum cell voltage (MCV). EDV threshold levels are used to determine when the battery has reached an “empty” state, and the MCV threshold is used for fault detection during charging. Two EDV thresholds for the bq2014 are programmable with the default values fixed at: EDV1 (early warning) = 1.05V EDVF (empty) = 0.95V If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of VSB, until the next valid charge (as defined in the section entitled “Gas Gauge Operation”). The VSB value is also available over the serial port. During discharge and charge, the bq2014 monitors VSR for various thresholds. These thresholds are used to compensate the charge and discharge rates. Refer to the count compensation section for details. EDV monitoring is disabled if VSR ≤ -250mV typical and resumes ½ second after VSR > -250mV. TMPGG (hex) Temperature Range 0x < -30°C 1x -30°C to -20°C 2x -20°C to -10°C 3x -10°C to 0°C 4x 0°C to 10°C 5x 10°C to 20°C 6x 20°C to 30°C 7x 30°C to 40°C 8x 40°C to 50°C 9x 50°C to 60°C Ax 60°C to 70°C Bx 70°C to 80°C Cx > 80°C Layout Considerations The bq2014 measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally: EMPTY Output The EMPTY output switches to high impedance when VSB < VEDF and remains latched until a valid charge occurs. Reset The bq2014 recognizes a valid battery whenever VSB is greater than 0.1V typical. VSB rising from below 0.25V or falling from above 2.25V (VMCV) resets the device. Reset can also be accomplished with a command over the serial port as described in the Reset Register section. Temperature The bq2014 internally determines the temperature in 10°C steps centered from -35°C to +85°C. The temperature steps are used to adapt charge and discharge rate 4 n The capacitors (C2 and C3) should be placed as close as possible to the SB and VCC pins, respectively, and their paths to VSS should be as short as possible. A high-quality ceramic capacitor of 0.1µf is recommended for VCC. n The sense resistor (R1, C1) should be placed as close as possible to the SR pin. n The sense resistor (R16) should be as close as possible to the bq2014. bq2014 charge lasts long enough to cause an increment in NACH. Small increments of charging are not considered “valid” if they result in counts in NACL but do not generate a roll-over (carry) that increments NACH. NACL is reset anytime the counter direction changes from down to up, so the number of counts required to cause a roll-over and a valid charge is always 256. The counter may be incrementing by 2, 4, 8, or more counts per increment, however, depending on the scaling factors selected. Therefore, a valid charge may be constituted by a smaller number of counter increments. Gas Gauge Operation The operational overview diagram in Figure 2 illustrates the operation of the bq2014. The bq2014 accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. Charge and discharge currents are temperature and rate compensated, whereas self-discharge is only temperature compensated. The main counter, Nominal Available Charge (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging and self-discharge decrement the NAC register and increment the DCR (Discharge Count Register). 1. LMD is the last measured discharge capacity of the battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent discharges, the LMD is updated with the latest measured capacity in the Discharge Count Register (DCR) representing a discharge from full to below EDV1. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register. The LMD also serves as the 100% reference threshold used by the relative display mode. The Discharge Count Register (DCR) is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2014 adapts its capacity determination based on the actual conditions of discharge. The battery's initial capacity is equal to the Programmed Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime. 2. Charge Current Discharge Current Self-Discharge Timer Rate and Temperature Compensation Rate and Temperature Compensation Temperature Compensation + Main Counters and Capacity Reference (LMD) + - Nominal Available Charge (NAC) < Last Measured Discharged (LMD) Chip-Controlled Available Charge LED Display + Discharge Count Qualified Register (DCR) Transfer Temperature Step, Other Data Temperature Translation Outputs Programmed Full Count (PFC) or initial battery capacity: The initial LMD and gas gauge rate values are programmed by using PROG1—PROG4. The bq2014 is configured for a given application by selecting a PFC value from Table 2. The correct PFC may be Many actions in the bq2014 are triggered by detection of a “valid charge.” NAC is stored in an asynchronous, 2byte counter; the lower byte is NACL and the upper byte is NACH. A valid charge has occurred anytime the Inputs Last Measured Discharge (LMD) or learned battery capacity: Serial Port FG201002.eps Figure 2. Operational Overview 5 bq2014 determined by multiplying the rated battery capacity in mAh by the sense resistor value: Relative display mode Serial port only Self-discharge = C 64 Voltage drop over sense resistor = 5mV to 400mV Battery capacity (mAh) * sense resistor (Ω) = Therefore: PFC (mVh) 2200mAh ∗ 0.1Ω = 220mVh Selecting a PFC slightly less than the rated capacity for absolute mode provides capacity above the full reference for much of the battery's life. Select: PFC = 33792 counts or 211mVh PROG1 = float PROG2 = float PROG3 = float PROG4 = low PROG5 = float DONE = low Example: Selecting a PFC Value Given: Sense resistor = 0.1Ω Number of cells = 6 Capacity = 2200mAh, NiCd battery Current range = 50mA to 2A Table 1. bq2014 Programming Pin Connection PROG5 Self-Discharge Rate DISP Display State H Disabled LED disabled Z NAC L NAC LED enabled on discharge when VSRO < -4mV or during a valid charge 64 LED on 47 Table 2. bq2014 Programmed Full Count mVh Selections PROGx 1 2 Programmed Full PROG4 = L PROG4 = Z Count (PFC) PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L Units - - - Scale = 1/80 H H 49152 614 307 154 76.8 38.4 19.2 mVh H Z 45056 563 282 141 70.4 35.2 17.6 mVh H L 40960 512 256 128 64.0 32.0 16.0 mVh Z H 36864 461 230 115 57.6 28.8 14.4 mVh Z Z 33792 422 211 106 53.0 26.4 13.2 mVh Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh L H 27648 346 173 86.4 43.2 21.6 10.8 mVh L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh L L 22528 282 141 70.4 35.2 17.6 8.8 mVh 90 45 22.5 11.25 5.6 2.8 mV VSR equivalent to 2 counts/s (nom.) Scale = 1/160 Scale = 1/320 Scale = 1/640 Scale = 1/1280 Scale = 1/2560 mVh/ count 6 bq2014 The initial full battery capacity is 211mVh (2110mAh) until the bq2014 “learns” a new capacity with a qualified discharge from full to EDV1. 3. Charge Control Charge control is provided by the CHG output. This output is asserted continuously when NAC > 0.94 ∗ LMD. CHG is also asserted when a valid charge is detected (CHGS in the FLGS1 register is also set). CHG is low when NAC < 0.94 ∗ LMD and there is no valid charge activity. Nominal Available Charge (NAC): NAC counts up during charge to a maximum value of LMD and down during discharge and selfdischarge to 0. NAC is reset to 0 on initialization and on the first valid charge after EDV = 1. To prevent overstatement of charge during periods of overcharge, NAC stops incrementing when NAC = LMD. 4. DONE Input When the bq2014 detects a valid charge complete with an active-high signal on the DONE input, NAC is set to LMD for NAC 64 (NiCd) self-discharge setting. NAC is set to 94% of LMD (if NAC is below 94%) for NAC 47 (NiMH) self-discharge setting. VDQ is set along with DONE. Discharge Count Register (DCR): The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0 until VSB < EDV1. Prior to NAC = 0 (empty battery), both discharge and selfdischarge increment the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches FFFFh. Discharge Counting All discharge counts where VSRO < VSRD cause the NAC register to decrement and the DCR to increment if EDV1 = 0. Exceeding the fast discharge threshold (FDQ) if the rate is equivalent to VSRO < -4mV activates the display, if enabled. The display becomes inactive after VSRO rises above -4mV. V SRD is a programmable threshold as described in the Digital Magnitude Filter section. The default value for VSRD is -300µV. The DCR value becomes the new LMD value on the first charge after a valid discharge to VEDV1 if: n n n No valid charges have occurred during the period between NAC = LMD and EDV1 detected. The self-discharge count is not more than 4096 counts (8% to 18% of PFC, specific percentage threshold determined by PFC). Self-Discharge Estimation The bq2014 continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge count rate is programmed to be a nominal 1 64 * NAC or 1 47 ∗ NAC per day or disabled as selected by PROG5. This is the rate for a battery whose temperature is between 20°C–30°C. The NAC register cannot be decremented below 0. The temperature is ≥ 0°C when the EDV1 level is reached during discharge. The valid discharge flag (VDQ) indicates whether the present discharge is valid for LMD update. Charge Counting Count Compensations Charge activity is detected based on a positive voltage on the VSR input. The bq2014 determines charge activity sustained at a continuous rate equivalent to VSRO (VSR + VOS) > VSRQ. Once a valid charge is detected, charge counting continues until VSRO falls below VSRQ. VSRQ is a programmable threshold (as described in the Digital Magnitude Filter section) and has a default value of 375µV. If charge activity is detected, the bq2014 increments the NAC at a rate proportional to VSRO. If enabled, the bq2014 then activates an LED display. Charge actions increment the NAC after compensation for charge rate and temperature. The bq2014 determines fast charge when the NAC updates at a rate of ≥ 2 counts/sec. Charge and discharge activity is compensated for temperature and charge/discharge rate before updating the NAC and/or DCR. Selfdischarge estimation is compensated for temperature before updating the NAC or DCR. Charge Compensation Two charge efficiency compensation factors are used for trickle charge and fast charge. Fast charge is defined as a rate of charge resulting in ≥ 2 NAC counts/sec (≥ 0.15C to 0.32C depending on PFC selections; see Table 2). The compensation defaults to the fast charge factor until the actual charge rate is determined. 7 bq2014 Temperature adapts the charge rate compensation factors over three ranges between nominal, warm, and hot temperatures. The compensation factors are shown below. Charge Temperature Trickle Charge Compensation Table 3. Self-Discharge Compensation Temperature Step Fast Charge Compensation Typical Rate PROG5 = Z < 10°C NAC < 40°C 0.80 0.95 10–20°C NAC > 40°C 0.75 0.90 20–30°C NAC 30–40°C NAC 40–50°C NAC 50–60°C NAC 60–70°C NAC > 70°C NAC Discharge Compensation Corrections for the rate of discharge are made by adjusting an internal discharge compensation factor. The discharge factor is based on the dynamically measured VSR. The compensation factors during discharge are: PROG5 = L NAC 256 188 NAC 128 NAC 64 NAC 32 NAC 16 NAC 8 NAC 4 NAC 2 94 47 23 .5 11 .8 5 .88 2 .94 1 .47 Digital Magnitude Filter Approximate VSR Threshold Discharge Compensation Factor Efficiency VSR > -150 mV 1.00 100% VSR < -150 mV 1.05 95% The bq2014 has a programmable digital filter to eliminate charge and discharge counting below a set threshold. The default setting is -0.30mV for V SRD and +0.38mV for VSRQ. The proper digital filter setting can be calculated using the following equation. Table 4 shows typical digital filter settings. VSRD (mV) = Temperature compensation during discharge also takes place. At lower temperatures, the compensation factor increases by 0.05 for each 10°C temperature range below 10°C. −45 DMF VSRQ (MV) = -125 ∗ VSRD Comp. factor = 1.00 + (0.05 * N) Table 4. Typical Digital Filter Settings Where N = number of 10°C steps below 10°C and -150mV < V SR < 0. DMF 75 100 150 (default) 175 200 For example: T > 10°C: Nominal compensation, N = 0 0°C < T < 10°C: N = 1 (i.e., 1.00 becomes 1.05) -10°C < T < 0°C: N = 2 (i.e., 1.00 becomes 1.10) -20°C < T < -10°C: N = 3 (i.e., 1.00 becomes 1.15) DMF Hex. 4B 64 96 AF C8 VSRD (mV) -0.60 -0.45 -0.30 -0.26 -0.23 VSRQ (mV) 0.75 0.56 0.38 0.32 0.28 Error Summary -20°C < T < -30°C: N = 4 (i.e., 1.00 becomes 1.20) Self-Discharge Compensation Capacity Inaccurate The self-discharge compensation is programmed for a nominal rate of 1 64 * NAC per day, 1 47 ∗ NAC per day, or disabled. This is the rate for a battery within the 20°C–30°C temperature range (TMPGG = 6x). This rate varies across 8 ranges from 70°C, doubling with each higher temperature step (10°C). See Table 3 The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value includes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description on page 7). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual battery capacity. A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description) and is reset 8 bq2014 Table 5. Current-Sensing Error as a Function of VSR Symbol Parameter Typical INL Integrated non-linearity error ±2 INR Integrated nonrepeatability error ±1 Maximum Units Notes ±4 % Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. ±2 % Measurement repeatability given similar operating conditions. either polled or interrupt processing. Data input from the bq2014 may be sampled using the pulse-width capture timers available on some microcontrollers. whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges. Communication is normally initiated by the host processor sending a BREAK command to the bq2014. A BREAK is detected when the DQ pin is driven to a logic-low state for a time, tB or greater. The DQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2014 is now ready to receive a command from the host processor. Current-Sensing Error Table 5 illustrates the current-sensing error as a function of V SR . A digital filter eliminates charge and discharge counts to the NAC register when VSRO (VSR + VOS) is between VSRQ and VSRD. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2014 taking the DQ pin to a logic-low state for a period, tSTRH,B. The next section is the actual data transmission, where the data should be valid by a period, tDSU, after the negative edge used to start communication. The data should be held for a period, tDV, to allow the host or bq2014 to sample the data bit. Communicating With the bq2014 The bq2014 includes a simple single-pin (DQ plus return) serial data interface. A host processor uses the interface to access various bq2014 registers. Battery characteristics may be easily monitored by adding a single contact to the battery pack. The open-drain DQ pin on the bq2014 should be pulled up by the host system, or may be left floating if the serial interface is not used. The interface uses a command-based protocol, where the host processor sends a command byte to the bq2014. The command directs the bq2014 to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte. The final section is used to stop the transmission by returning the DQ pin to a logic-high state by at least a period, tSSU, after the negative edge used to start communication. The final logic-high state should be held until a period, tSV, to allow time to ensure that the bit transmission was stopped properly. The timings for data and break communication are given in the serial communication timing specification and illustration sections. The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using Communication with the bq2014 is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication sequence to read the bq2014 NAC register. Written by Host to bq2014 CMDR = 03h LSB Received by Host to bq2014 NAC = 65h MSB Break 1 1 0 0 0 0 0 0 LSB MSB 1 0 1 0 011 0 DQ TD201401.eps Figure 3. Typical Communication With the bq2014 9 bq2014 Where CHGS is: bq2014 Registers The bq2014 command and status registers are listed in Table 6 and described below. Command Register (CMDR) W/R bit n Command address Either discharge activity detected or VSRO < VSRQ 1 VSRO > VSRQ The battery replaced flag (BRP) is asserted whenever the potential on the SB pin (relative to VSS), VSB, falls from above the maximum cell voltage, MCV (2.25V), or rises above 0.1V. The BRP flag is also set when the bq2014 is reset (see the RST register description). BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset. The write-only CMDR register is accessed when eight valid command bits have been received by the bq2014. The CMDR register contains two fields: n 0 The W/R bit of the command register is used to select whether the received command is for a read or a write function. The BRP values are: The W/R values are: FLGS1 Bits CMDR Bits 7 6 5 4 3 2 1 0 W/R - - - - - - - The bq2014 outputs the requested register contents specified by the address portion of CMDR. 1 The following eight bits should be written to the register specified by the address portion of CMDR. CMDR Bits - 6 5 AD6 AD5 5 4 3 2 1 0 - BRP - - - - - - 0 Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted 1 VSB dropping from above MCV, VSB rising from below 0.1V, or a serial port initiated reset has occurred The battery removed flag (BRM) is asserted whenever the potential on the SB pin (relative to VSS) rises above MCV or falls below 0.1V. The BRM flag is asserted until the condition causing BRM is removed. Because of signal filtering, 30 seconds may have to transpire for BRM to react to battery insertion or removal. The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored. 7 6 Where BRP is: Where W/R is: 0 7 The BRM values are: 4 3 2 1 0 AD4 AD3 AD2 AD1 AD0 (LSB) FLGS1 Bits Primary Status Flags Register (FLGS1) The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when VSRO > VSRQ. A VSRO of less than VSRQ or discharge activity clears CHGS. FLGS1 Bits 6 5 4 3 2 1 0 - - - - - - - 5 4 3 2 1 0 - - BRM - - - - - 0 0.1V < VSB < 2.25V 1 0.1V > VSB or VSB > 2.25V The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2014 is reset. The flag is cleared after an LMD update. The CHGS values are: 7 6 Where BRM is: The read-only FLGS1 register (address=01h) contains the primary bq2014 flags. CHGS 7 10 bq2014 Table 6. bq2014 Command and Status Registers Symbol Register Name Command CMDR register Primary FLGS1 status flags register Temperature TMPGG and gas gauge register Nominal available NACH charge high byte register Nominal available NACL charge low byte register Battery BATID identification register Last measured disLMD charge register Secondary FLGS2 status flags register Program pin PPD pull-down register Program pin PPU pull-up register Capacity CPI inaccurate count register Digital magDMF nitude filter register Battery VSB voltage End-ofdischarge VTS threshold select RST Reset register Note: Control Field 4 3 Loc. (hex) Read/ Write 7(MSB) 6 5 00h Write W/R AD6 AD5 AD4 01h Read CHGS BRP BRM 02h Read TMP3 TMP2 TMP1 03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0 17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0 04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0 05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0 06h Read CR DR2 DR1 DR0 n/u n/u n/u OVLD 07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0 0Ah R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0 0Bh Read VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 0Ch R/W VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0 39h Write RST 0 0 0 0 0 0 0 n/u = not used 11 2 1 0(LSB) AD3 AD2 AD1 AD0 CI VDQ n/u EDV1 EDVF TMP0 GG3 GG2 GG1 GG0 bq2014 Where EDV1 is: The CI values are: FLGS1 Bits 7 6 5 4 3 2 1 0 - - - CI - - - - When LMD is updated with a valid full discharge 1 After the 64th valid charge action with no LMD updates or when the device is reset The valid discharge flag (VDQ) is asserted when the bq2014 is discharged from NAC = LMD or DONE is valid. The flag remains set until either LMD is updated or one of three actions that can clear VDQ occurs: n n n Valid charge action detected,VSB ≥ VTS 1 VSB < VTS providing that OVLD=0 (see FLGS2 register description) The final end-of-discharge warning flag (EDVF) flag is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EMPTY pin is also forced to a high-impedance state on assertion of EDVF. The host system may pull EMPTY high, which may be used to disable circuitry to prevent deep-discharge of the battery. The EDVF threshold is set 100mV below the EDV1 threshold. Where CI is: 0 0 The EDVF values are: FLGS1 Bits The self-discharge count register (SDCR) has exceeded the maximum acceptable value (4096 counts) for an LMD update. A valid charge action sustained at VSRO > VSRQ for at least 256 NAC counts. 7 6 5 4 3 2 1 0 - - - - - - - EDVF Where EDVF is: The EDV flag was set at a temperature below 0°C 0 Valid charge action detected, VSB ≥ VTS - 100mV 1 VSB < VTS - 100mV providing that OVLD=0 (see FLGS2 register description) The VDQ values are: FLGS1 Bits 7 6 5 4 3 2 1 0 - - - - VDQ - - - Voltage Threshold Register (VTS) The end-of-discharge threshold voltages (EDV1 and EDVF) can be set using the VTS register (address=0ch). The read/write VTS register sets the EDV1 trip point. EDVF is set 100mV below EDV1. The default value in the VTS register is 70h, representing EDV1 = 1.05V and EDVF = 0.95V. EDV1 = 2.4V ∗ (VTS/256). Where VDQ is: 0 SDCR ≥ 4096, subsequent valid charge action detected, or EDV1 is asserted with the temperature less than 0°C 1 On first discharge after NAC = LMD or DONE is valid VTS Register Bits 7 The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG1, is modulated at a 4Hz rate if the display is enabled once EDV1 is asserted, which should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has been detected. The EDV1 threshold is externally controlled via the VTS register (see Voltage Threshold Register on this page). 6 5 4 3 2 1 0 VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0 Battery Voltage Register (VSB) The read-only battery voltage register is used to read the single-cell battery voltage on the SB pin. The VSB register is updated approximately once per second with the present value of the battery voltage. VSB = 2.4V ∗ (VSB/256) The EDV1 values are: FLGS1 Bits VSB Register Bits 7 6 5 4 3 2 1 0 - - - - - - EDV1 - 7 6 5 4 3 2 1 0 VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0 12 bq2014 Temperature and Gas Gauge Register (TMPGG) Table 7. Temperature Register Translation The read-only TMPGG register (address=02h) contains two data fields. The first field contains the battery temperature. The second field contains the available charge from the battery. TMPGG Temperature Bits 7 6 5 TMP3 TMP2 4 TMP1 TMP0 3 2 1 - - - 0 The bq2014 contains an internal temperature sensor. The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient. The temperature register contents may be translated as shown in Table 7. The bq2014 calculates the available charge as a function of NAC, temperature, and LMD. The results of the calculation are available via the display port or the gas gauge field of the TMPGG register. The register is used to give available capacity in 116 increments from 0 to 1516. 6 5 4 3 2 1 0 - - - - GG3 GG2 GG1 GG0 TMP2 TMP1 TMP0 Temperature 0 0 0 0 T < -30°C 0 0 0 1 -30°C < T < -20°C 0 0 1 0 -20°C < T < -10°C 0 0 1 1 -10°C < T < 0°C 0 1 0 0 0°C < T < 10°C 0 1 0 1 10°C < T < 20°C 0 1 1 0 20°C < T < 30°C 0 1 1 1 30°C < T < 40°C 1 0 0 0 40°C < T < 50°C 1 0 0 1 50°C < T < 60°C 1 0 1 0 60°C < T < 70°C 1 0 1 1 70°C < T < 80°C 1 1 0 0 T > 80°C On reset, NACH and NACL are cleared to 0. When the bq2014 detects a charge, NACL resets to 0. NACH and NACL are reset to 0 on the first valid charge after VSB = EDV1. Writing to the NAC registers affects the available charge counts and, therefore, affects the bq2014 gas gauge operation. Do not write the NAC registers to a value greater than LMD. TMPGG Gas Gauge Bits 7 TMP3 Battery Identification Register (BATID) The gas gauge display and the gas gauge portion of the TMPGG register are adjusted for cold temperature dependencies. A piece-wise correction is performed as follows: The read/write BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as VCC is greater than 2V. The contents of BATID have no effect on the operation of the bq2014. There is no default setting for this register. Temperature Available Capacity Calculation > 0°C NAC / “Full Reference” -20°C < T < 0°C 0.75 * NAC / “Full Reference” Last Measured Discharge Register (LMD) < -20°C 0.5 * NAC / “Full Reference” LMD is a read/write register (address=05h) that the bq2014 uses as a measured full reference. The bq2014 adjusts LMD based on the measured discharge capacity of the battery from full to empty. In this way the bq2014 updates the capacity of the battery. LMD is set to PFC during a bq2014 reset. The adjustment between > 0°C and -20°C < T < 0°C has a 10°C hysteresis. Nominal Available Charge Register (NACH/NACL) Secondary Status Flags Register (FLGS2) The read-only FLGS2 register (address=06h) contains the secondary bq2014 flags. The read/write NACH register (address=03h) and the read-only NACL low-byte register (address=17h) are the main gas gauging registers for the bq2014. The NAC registers are incremented during charge actions and decremented during discharge and self-discharge actions. The correction factors for charge/discharge efficiency are applied automatically to NAC. The charge rate flag (CR) is used to denote the fast charge regime. Fast charge is assumed whenever a charge action is initiated. The CR flag remains asserted if the charge rate does not fall below 2 counts/sec. 13 bq2014 pull-down resistors, the contents of PPD are xx101001. (Note: DONE must be pulled down for proper operation.) The CR values are: FLGS2 Bits 7 6 5 4 3 2 1 0 Program Pin Pull-Up Register (PPU) CR - - - - - - - The read-only PPU register (address=08h) contains the rest of the programming pin information for the bq2014. The segment drivers, SEG1–5 and DONE, have corresponding PPU register locations, PPU1–6. A given location is set if a pull-up resistor has been detected on its corresponding segment driver. For example, if SEG3 and DONE have pull-up resistors, the contents of PPU are xx100100. Where CR is: 0 When charge rate falls below 2 counts/sec 1 When charge rate is above 2 counts/sec The fast charge regime efficiency factors are used when CR = 1. When CR = 0, the trickle charge efficiency factors are used. The time to change CR varies due to the user-selectable count rates. PPD/PPU Bits The discharge rate flags, DR2–0, are bits 6–4. FLGS2 Bits 7 6 5 4 3 2 1 - DR2 DR1 DR0 - - - 0 DR1 DR0 VSR (V) 0 0 0 VSR > -150mV 0 0 1 VSR < -150mV 5 4 3 2 1 0 - - - - - - - OVLD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1 6 5 4 3 2 1 - - PPD6 PPD5 PPD4 PPD3 PPD2 PPD1 The CPI register is incremented every time a valid charge is detected. When NAC > 0.94 ∗ LMD, however, the CPI register increments on the first valid charge; CPI does not increment again for a valid charge until NAC < 0.94 ∗ LMD. This prevents continuous trickle charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset whenever an update of the LMD register is performed, and the CI flag is also cleared. FLGS2 Bits 6 - The read-only CPI register (address=09h) is used to indicate the number of times a battery has been charged without an LMD update. Because the capacity of a rechargeable battery varies with age and operating conditions, the bq2014 adapts to the changing capacity over time. A complete discharge from full (NAC=LMD) to empty (EDV1=1) is required to perform an LMD update assuming there have been no intervening valid charges, the temperature is greater than or equal to 0°C, and the self-discharge counter is less than 4096 counts. The overload flag (OVLD) is asserted when a discharge overload is detected, VSR < -250mV. OVLD remains asserted as long as the condition persists and is cleared after VSR > -150mV. The overload condition is used to stop sampling of the battery terminal characteristics for end-of-discharge determination when excessive discharges occur. 7 7 - Capacity Inaccurate Count Register (CPI) They are used to determine the current discharge regime as follows: DR2 8 DR2–0 and OVLD are set based on the measurement of the voltage at the SR pin relative to VSS. The rate at which this measurement is made varies with device activity. Digital Magnitude Filter (DMF) The read-write DMF register (address=0Ah) provides the system with a means to change the default settings of the digital magnitude filter. By writing different values into this register, the limits of VSRD and VSRQ can be adjusted. Program Pin Pull-Down Register (PPD) The read-only PPD register (address=07h) contains some of the programming pin information for the bq2014. The segment drivers, SEG1–5 and DONE, have corresponding PPD register locations, PPD1–6. A given location is set if a pull-down resistor has been detected on its corresponding segment driver. For example, if SEG1 and SEG4 have Note: Care should be taken when writing to this register. A VSRD and VSRQ below the specified VOS may adversely affect the accuracy of the bq2014. Refer to Table 4 for recommended settings for the DMF register. 14 bq2014 When DISP is tied to VCC, the SEG1–5 outputs are inactive. Note: DISP must be tied to VCC if the LEDs are not used. When DISP is left floating, the display becomes active whenever the NAC registers are counting at a rate equivalent to VSRO < -4mV or charge current is detected, VSRO > VSRQ. When pulled low, the segment outputs become active immediately. A capacitor tied to DISP allows the display to remain active for a short period of time after activation by a push-button switch. Reset Register (RST) The reset register (address=39h) provides the means to perform a software-controlled reset of the device. By writing the RST register contents from 00h to 80h, a bq2014 reset is performed. Setting any bit other than the most-significant bit of the RST register is not allowed, and results in improper operation of the bq2014. Resetting the bq2014 sets the following: n LMD = PFC n CPI, VDQ, NAC, and NACL = 0 n CI and BRP = 1 The segment outputs are modulated as two banks of three, with segments 1, 3, and 5 alternating with segments 2 and 4. The segment outputs are modulated at approximately 100Hz, with each segment bank active for 30% of the period. Note: Self-discharge is disabled when PROG5 = H. SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables the display output. Display The bq2014 can directly display capacity information using low-power LEDs. If LEDs are used, the program pins should be resistively tied to VCC or VSS for a program high or program low, respectively.. Microregulator The bq2014 can operate directly from 3 or 4 cells. To facilitate the power supply requirements of the bq2014, an REF output is provided to regulate an external low-threshold nFET. A micropower source for the bq2014 can be inexpensively built using the FET and an external resistor; see Figure 1. The bq2014 displays the battery charge state in relative mode. In relative mode, the battery charge is represented as a percentage of the LMD. Each LED segment represents 20% of the LMD. The capacity display is also adjusted for the present battery temperature. The temperature adjustment reflects the available capacity at a given temperature but does not affect the NAC register. The temperature adjustments are detailed in the TMPGG register description. 15 bq2014 Absolute Maximum Ratings Minimum Maximum Unit VCC Symbol Relative to VSS Parameter -0.3 7.0 V All other pins Relative to VSS -0.3 7.0 V REF Relative to VSS -0.3 8.5 V Current limited by R1 (see Figure 1) VSR Relative to VSS TOPR Operating temperature Note: Notes -0.3 7.0 V Minimum 100Ω series resistor should be used to protect SR in case of a shorted battery (see the bq2014 application note for details). 0 70 °C Commercial Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V) Symbol Parameter Minimum Typical Maximum Unit Notes 0.92 0.95 0.98 V SB VEDVF Final empty warning, default VEDV1 First empty warning, default 1.02 1.05 1.08 V SB VSR1 Discharge compensation threshold -120 -150 -180 mV SR VSRO SR sense range -300 - 2000 mV SR VOVLD Overload threshold -220 -250 -280 mV SR VSRQ Valid charge 375 - - µV VSR + VOS (see note 1) VSRD Valid discharge - - -300 µV VSR + VOS (see note 1) VMCV Maximum single-cell voltage 2.20 2.25 2.30 V SB - 0.1 0.25 V SB pulled low 2.20 2.25 2.30 V SB pulled high VBR Battery removed/replaced Notes: 1. Default value; value set in DMF register. VOS is affected by PC board layout. Proper layout guide lines should be followed for optimal performance. 2. To ensure correct threshold determination and proper operation, VCC > VSB + 1.5V 16 bq2014 DC Electrical Characteristics (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit VCC Supply voltage 3.0 4.25 6.5 V VOS Offset referred to VSR ±50 6.0 5.0 90 120 170 - ±150 6.3 7.5 135 180 250 2.4 5 0.2 - µV V V MΩ µA µA µA V MΩ µA µA KΩ Notes VCC excursion from < 2.0V to ≥ 3.0V initializes the unit. DISP = VCC RREF Reference at 25°C Reference at -40°C to +85°C Reference input impedance ICC Normal operation VSB RSBmax IDISP ILCOM RDQ Battery input SB input impedance DISP input leakage LCOM input leakage Internal pulldown 5.7 4.5 2.0 10 -0.2 500 VSR Sense resistor input -0.3 - 2.0 V RSR VIH VIL VIZ SR input impedance Logic input high Logic input low Logic input Z 10 VCC - 0.2 float - VSS + 0.2 float MΩ V V V VOLSL SEGX output low, low VCC - 0.1 - V VOLSH SEGX output low, high VCC - 0.4 - V VOHLCL VOHLCH IIH IIL IOHLCOM IOLS LCOM output high, low VCC LCOM output high, high VCC PROG1-5 input high current PROG1-5 input low current LCOM source current SEGX sink current VCC - 0.3 VCC - 0.6 -33 - 1.2 1.2 - 11.0 V V µA µA mA mA IOL Open-drain sink current - - 5.0 mA VOL VIHDQ VILDQ 2.5 - - 0.5 0.8 V V V - - 200 KΩ PROG1–PROG5 RFLOAT Open-drain output low DQ input high DQ input low Soft pull-up or pull-down resistor value (for programming) Float state external impedance - 5 - MΩ PROG1–PROG5 Notes: 1. All voltages relative to VSS. VREF RPROG 2. DONE must be pulled low for proper operation. 17 IREF = 5µA IREF = 5µA VREF = 3V VCC = 3.0V VCC = 4.25V VCC = 6.5V 0 < VSB < VCC VDISP = VSS DISP = VCC VSR < VSS = discharge; VSR > VSS = charge -200mV < VSR < VCC PROG1–PROG5 PROG1–PROG5; note 2 PROG1–PROG5 VCC = 3V, IOLS ≤ 1.75mA SEG1–SEG5 VCC = 6.5V, IOLS ≤ 11.0mA SEG1–SEG5 VCC = 3V, IOHLCOM = -5.25mA VCC = 6.5V, IOHLCOM = -33.0mA VPROG = VCC/2 VPROG = VCC/2 At VOHLCH = VCC - 0.6V At VOLSH = 0.4V At VOL = VSS + 0.3V DQ, EMPTY, CHG IOL ≤ 5mA, DQ, EMPTY DQ DQ bq2014 Serial Communication Timing Specification Symbol Parameter Minimum Typical Maximum Unit tCYCH Cycle time, host to bq2014 3 - - ms tCYCB Cycle time, bq2014 to host 3 - 6 ms tSTRH Start hold, host to bq2014 5 - - ns tSTRB Start hold, bq2014 to host 500 - - µs tDSU Data setup - - 750 µs tDH Data hold 750 - - µs tDV Data valid 1.50 - - ms tSSU Stop setup - - 2.25 ms tSH Stop hold 700 - - µs tSV Stop valid 2.95 - - ms tB Break 3 - - ms tBR Break recovery 1 - - ms Note: Notes See note The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation. DQ may be left floating if the serial interface is not used. Serial Communication Timing Illustration DQ (R/W "1") DQ (R/W "0") tSTRH tSTRB tDH tDSU tDV tSH tSSU DQ (BREAK) tSV tCYCH, tCYCB, tB tBR TD201002.eps 18 bq2014 16-Pin SOIC Narrow (SN) 16-Pin SN (SOIC Narrow) D e Dimension Minimum A 0.060 A1 0.004 B 0.013 C 0.007 D 0.385 E 0.150 e 0.045 H 0.225 L 0.015 All dimensions are in inches. B E H A C A1 Maximum 0.070 0.010 0.020 0.010 0.400 0.160 0.055 0.245 0.035 .004 L Data Sheet Revision History ChangeNo. Page No. 1 1, 3, 5, 6, 7, 13, 15 1 Notes: Description Nature of Change Changed display mode Relative display mode only 1, 17 DONE pin Removed PROG6 1 2, 17 DONE pin Added: DONE pin must be pulled to VSS with a 200KΩ resistor 1 6 Table 1 Removed PROG6 1 7 DONE input Was: NAC is set to 90%... Is: NAC is set to 94%... 1 8, Table 3 PROG5 = Z Was: PROG5 = Z or H Is: PROG5 = Z 2 8 Temperature Compensation table Replaced 2 6 Table 2 Added VSR definition 2 6 Valid charge definition Added definition 2 14 Overload flag Was: 0.5sec. after VSR> -250mV Is: after VSR = -150mV Change 1 = Dec. 1994 B “Final” changes from Aug. 1994 A “Preliminary.” Change 2 = Dec. 1995 C from Dec. 1994 B. 19 bq2014 Ordering Information bq2014 Temperature Range: blank = Commercial (0 to +70°C) Package Option: SN = 16-pin narrow SOIC Device: bq2014 Gas Gauge IC 17919 Waterview Parkway Dallas, Texas 75252 Fax: (972) 437-9198 Tel: (972) 437-9195 www.benchmarq.com or www.unitrode.com Copyright © 1995, Unitrode Corporation. All rights reserved. No part of this data sheet may be reproduced in any form or means, without express permission from Unitrode. Unitrode reserves the right to make changes in its products without notice. Unitrode assumes no responsibility for use of any products or circuitry described within. No license for use of intellectual property (patents, copyrights, or other rights) owned by Unitrode or other parties is granted or implied. Unitrode does not authorize the use of its components in life-support systems where failure or malfunction may cause injury to the user. If Unitrode components are used in life-support systems, the user assumes all responsibilities and indemnifies Unitrode from all liability or damages. Benchmarq is a registered trademark of Unitrode Corporation 20 Printed in U.S.A. PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ2014SN-D120 NRND SOIC D 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 2014 D120 BQ2014SN-D120TR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 2014 D120 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of