BQ21080YBGR

BQ21080 SLUSF49 – JANUARY 2023 BQ21080 I2C Controlled, 1-Cell, 0.8-A Linear Battery Charger with Power Path and Ship Mode 1 Features 2 Applications • • • • • • • • • • 800-mA Power path linear battery charger – 3.0-V to 5.9-V input voltage operating range optimized for battery to battery charging and USB adapter – 25-V tolerant input voltage – Configurable battery regulation voltage with 0.5% accuracy from 3.6 V to 4.65 V in 10-mV steps – 5-mA to 800-mA configurable fast charge current – 55-mΩ battery FET ON resistance – Up to 2.5-A discharge current to support high system loads – Configurable termination current down to 0.5 mA – Configurable NTC charging profile thresholds including JEITA support – Power cycle and advanced reset mechanisms to recover system Power path management for powering the system and charging the battery – Regulated system voltage (SYS) ranging from 4.4 V to 4.9 V in addition to battery voltage tracking and input pass-though options – Configurable input current limit – Selectable adapter or battery power for system – Dynamic power path management optimizes charging from weak adapters Ultra low quiescent current modes – 30-nA Shutdown mode – 3.2-μA Ship mode with button press wake – 4 μA in Battery Only mode – 45-μA input adapter Iq in Sleep mode One push-button wake-up and reset input Integrated fault protection – Input overvoltage protection (VIN_OVP) – Battery undervoltage protection (VBUVLO) – Battery short protection (BATSC) – Battery overcurrent protection (BATOCP) – Input current limit protection (ILIM) – Thermal regulation (TREG) and thermal shutdown (TSHUT) – Battery thermal fault protection (TS) – Watchdog and safety timer fault – System short protection – System overvoltage protection TWS headset and charging case Smart glasses, AR and VR Smart watches and other wearable devices Retail automation and payment Building automation 3 Description The BQ21080 is a linear battery charger IC focusing on small solution size and low quiescent current for extending battery life. The device is available in an 8-ball chipscale package which does not need HDI PCB process for fabrication thereby reducing the PCB cost. The device can support up to 800-mA charging and system loads of up to 2.5 A. Device Information PACKAGE(1) PART NUMBER BQ21080 (1) DSBGA (8) BODY SIZE (NOM) 1.6 mm x 1.1 mm For all available packages, see the orderable addendum at the end of the data sheet. SYS IN VBUS 10uF Regulated Load 1uF /INT SCL Device Control SDA BAT Host 1uF VIO + TS/MR – NTC BQ21080 GND Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Thermal Information....................................................5 7.4 Recommended Operating Conditions.........................5 7.5 Electrical Characteristics.............................................6 7.6 Timing Requirements.................................................. 9 7.7 Typical Characteristics.............................................. 10 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 15 8.3 Feature Description...................................................15 8.4 Device Functional Modes..........................................24 8.5 Register Maps...........................................................25 9 Application and Implementation.................................. 33 9.1 Application Information............................................. 33 9.2 Typical Application.................................................... 33 10 Power Supply Recommendations..............................40 11 Layout........................................................................... 41 11.1 Layout Guidelines................................................... 41 11.2 Layout Example...................................................... 41 12 Device and Documentation Support..........................42 12.1 Device Support....................................................... 42 12.2 Receiving Notification of Documentation Updates..42 12.3 Support Resources................................................. 42 12.4 Trademarks............................................................. 42 12.5 Electrostatic Discharge Caution..............................42 12.6 Glossary..................................................................42 13 Mechanical, Packaging, and Orderable Information.................................................................... 43 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES January 2023 * Initial Release Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 5 Description (continued) The battery is charged using a standard Li-ion or LiFePO4 charge profile with three phases: precharge, constant current and constant voltage. Thermal regulation provides the maximum charge current while managing the device temperature. The charger is also optimized for battery to battery charging with 3-V minimum input voltage operation and can withstand 25-V absolute maximum line transients. The device integrates a single push-button input and reset circuitry to reduce the total solution footprint. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 3 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 6 Pin Configuration and Functions 1 2 A /INT IN B SCL SYS SDA BAT TS/MR GND C D Figure 6-1. YBG Package 8-Pin DSBGA (Top View) Table 6-1. Pin Functions PIN (1) 4 I/O(1) DESCRIPTION NAME NO. IN A2 P DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with at least 1 μF of capacitance using a ceramic capacitor. SYS B2 P Regulated System Output. Connect at least 10-μF ceramic capacitor (at least >1 μF of ceramic capacitance with DC bias derating) from SYS to GND as close to the SYS and GND pins as possible. BAT C2 P Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 μF of ceramic capacitance. GND D2 - Ground connection. Connect to the ground plane of the circuit. SCL B1 I/O I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ pullup resistor. SDA C1 I/O I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ pullup resistor. /INT A1 O INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-μs active low pulse is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT bit in the control register. Can be pulled up to the logic rail through a 1-kΩ to 20-kΩ resistor. TS/MR D1 I/O Manual Reset Input/ NTC thermistor pin. TS/MR is a general purpose input that must be held low for greater than tLPRESS to go into Ship mode or perform a hardware reset. It can also be used to detect shorter button press durations such as tWAKE1 and tWAKE2 TSMR may be driven by a momentary push-button or a MOS switch. The TSMR pin can also have an NTC thermistor connected on to it. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX Input Voltage IN -0.3 25 V Voltage All other pins -0.3 5.5 V Input Current (DC) IN 1.1 A SYS Discharge Current(DC) SYS 1.5 A SYS Discharge Current (tpulse VBUVLO, VSYS>VBAT-VBSUP2 VIN = 5V, ILIM =50mA ILIM 6 Input Current Limit 72 mV 5.9 40 mV 20 40 50 V mV 60 mA VIN = 5V, ILIM =100mA 80 90 98 mA VIN = 5V, ILIM= 300mA 270 300 330 mA VIN = 5V, ILIM= 500mA 450 475 498 mA VIN = 5V, ILIM= 1050mA 995 1050 1100 mA Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 7.5 Electrical Characteristics (continued) VIN = 5V, VBAT = 3.6V. TJ =25°C unless otherwise noted. PARAMETER VINDPM_A CC VINDPM accuracy TEST CONDITIONS VINDPM target is not disabled MIN TYP -3 MAX 3 UNIT % VINDPM Input voltage threshold when input current VINDPM target =4.2V is reduced 4.2 V VDPPM SYS voltage threshold when charge current is reduced 0.1 V VSYS_REG _ACCURAC Programmable SYS regulation accuracy Y VMINSYS VSYS_TRA CK RSYS_PD VBAT = 3.6V, VSYS = VDPPM + VBAT before charge current is reduced. All settings, ISYS from 0-0.5A, VIN = VSYS_REG + VIN_MIN_TH, All settings except passthrough mode and battery tracking mode –3 3 % ISYS = 100mA, VIN = VSYS_REG + VIN_MIN_TH, All settings except passthrough mode and battery tracking mode –2 2 % Minimum SYS voltage when in battery tracking mode VBAT < 3.6V 3.8 V Voltage regulation threshold for SYS when VBAT >3.6V in battery tracking mode VBAT = 4V, VSYS = VBAT + VSYS_TRACK 225 mV SYS pull down resistance VSYS = 3.6V 25 Ω BATTERY CHARGER RON_BAT Battery FET on-resistance VBAT = 4.5V, IBAT =500mA RON_IN Input FET on-resistance IN = 5V, IIN = 1A VREG_RA Typical BAT charge voltage regulation range 10mV steps, programmabe through I2C BAT charge voltage accuracy, summary for all settings All VBATREG settings, typical measurement at VBATREG = 4.2V Typical charge current regulation range VOUT > VLOWV NGE VREG_AC C ICHG_RAN GE 55 110 mΩ 270 350 mΩ 3.5 4.65 V –0.5 0.5 % 5 800 mA ICHG_ACC Charge current accuracy VIN = 5V, Fastcharge >=40mA 10 % ICHG_ACC Charge current accuracy Fastcharge current = 40mA –10 36 40 44 mA ICHG_ACC Charge current accuracy Fastcharge current = 630mA 567 630 693 mA IPRECHG Typical pre-charge current, as percentage VOUT < VLOWV of ICHG IPRECHG_ Precharge current accuracy Fastcharge current >=40mA –10 10 % Termination current accuracy IBAT = 3mA (IFCHG = 30mA) Tj = 25°C –10 10 % Termination current accuracy IBAT = 3mA (IFCHG = 30mA) Tj = 25°C 2.7 3.3 mA VLOWV Pre-charge to fast-charge transition threshold VLOWVSEL = 3.0V, VBAT rising 2.9 3 3.1 V VLOWV Pre-charge to fast-charge transition threshold VLOWVSEL = 2.8V, VBAT rising 2.7 2.8 2.9 V VLOWV_H Battery LOWV hysteresis All settings ACC ITERM_AC C ITERM_AC C YS 20 100 % mV Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 7 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 7.5 Electrical Characteristics (continued) VIN = 5V, VBAT = 3.6V. TJ =25°C unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Battery UVLO, VBAT falling BUVLO setting = b000 3 V Battery UVLO, VBAT falling BUVLO setting = b011 2.8 V Battery UVLO, VBAT falling BUVLO setting = b100 2.6 V Battery UVLO, VBAT falling BUVLO setting = b101 2.4 V Battery UVLO, VBAT falling BUVLO setting = b110 2.2 V Battery UVLO, VBAT falling BUVLO setting = b111 2.0 V Battery UVLO hysteresis, VBAT rising Any BUVLO Setting, value above VBAT, VIN = 5V VBATPOR Battery only power up voltage, VBAT rising -40C < Tj < 125C VRCH Battery recharge threshold VBATSC Short on battery threshold for trickle charge, VBAT rising VBATSC_H Battery short circuit voltage hysteresis VBUVLO VBUVLO_H YS YS IBATSC Trickle Charge Current 110 150 190 mV 3.08 3.21 3.46 V BAT falling, VRCH bit = 0 75 100 130 mV BAT falling, VRCH bit = 1 175 200 230 mV 1.6 1.8 2.0 V VBAT VBATSC No No Yes Precharge safety timer expired? Start Precharge Yes Yes No Stop Charging and interrupt VBAT > VLOWV Charging or VIN toggled Yes No Start FastCharge Icharge set by I2C Yes Fast Charge safety timer expired? IBAT < ITERM Yes Charge Done (Set bit, interrupt, and disconnect BATFET) No No Yes VBAT < VRCH Figure 8-1. Charger Flow Diagram 8.1.1.1 Trickle Charge In order to prevent damage to the battery, the device will charge the battery at a much lower current level (IBATSC) when the battery voltage (VBAT) is below the VBATSC threshold. During trickle charge, the device still counts against the precharge safety timer. Rather trickle charge and precharge are counting against the same duration of 25% of the fast charge timer. 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 8.1.1.2 Precharge When battery voltage is above the VBATSC but lower than VLOWV threshold, the battery is charged with the precharge current level. The precharge current (IPRECHARGE) can be programmed through I2C and can be adjusted by the host. Once the battery voltage reaches VLOWV, the charger will then operate in Fast Charge mode, charging the battery at ICHG. During precharge, the safety timer is set to 25% of the safety timer value during fast charge. In the case where termination is disabled, precharge current is set to 20% of fast charge current setting. 8.1.1.3 Fast Charge The charger has two main control loops that control charging when VBAT > VLOWV: the Constant Current (CC) and Constant Voltage (CV) loops. When the CC loop is dominant, the battery is charged at the maximum charge current level ICHG, unless there is a TS fault condition (JEITA operation), VINDPM is active, thermal regulation or DPPM is active. (See respective sections for details on these modes of operation). Once the battery voltage approaches the battery regulation target, the CV loops becomes more dominant and the charging current starts tapering off. Once the charging current reaches the termination current (ITERM) the charge is done, Charge_done status is set. If the I2C setting of VBATREG is set higher than 4.65 V, the battery regulation voltage is still maintained at 4.65 V. The device will switch to fastcharge mode based on VLOWV setting on the register map. 8.1.1.4 Termination The device will automatically terminate charging once the charge current reaches ITERM, which is programmable through I2C. After termination the charger will operate in high impedance mode, disabling the BATFET to disconnect the battery. Power is provided to the system (SYS) by IN supply as long as VIN > VUVLO, VIN > VBAT + VSLEEPZ and VIN < VIN_OVP. Termination is only enabled when the charger CV loop is active in fast charge operation. Termination is disabled if the charge current reaches ITERM while the VINDPM, DPPM, or thermal regulation loops are active. The charger will only go into the termination when the current drops to ITERM due to the battery reaching the target voltage and not due to the charge current limitation imposed by the previously mentioned controlled loops. Post termination, the battery FET is disabled and the voltage on BAT pin is monitored to check if it has dropped to the VRCH threshold. If it does, a new charge cycle is established. The safety timers are reset. During charging or even when charge is done, a higher SYS load will be supported through the supplement operation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 13 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Regulation Voltage VSET VRCH Battery Voltage Charge Current ISET Charge Current VLOWV VBATSC IPRECHG ITERM IBATSC Trickle Charge Pre-charge Precharge Timer Fast-Charge CC Taper-Charge CV Charge Done Recharge Safety Timer Figure 8-2. Typical Charging Profile of a Battery 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 8.2 Functional Block Diagram SYS Q1/Q2 IN GND VIN_DPM Power Path and Charge Control IBATREG BUVLO VBATREG VIN SCL SDA I2C Interface Charge Control SYS Control Q3 Thermal Shutdown Device Control BAT – /INT + VBUVLO Interrupts TS Interface and Push button controller TS/MR VTS_CLAMP ITSMR Figure 8-3. Functional Block Diagram 8.3 Feature Description 8.3.1 Input Voltage Based Dynamic Power Management (VINDPM) The VINDPM loop prevents the input voltage from collapsing to a point where charging could be interrupted due to adapter voltage crashing below VINDPM value. This is done by reducing the current drawn by the charger enough to keep VIN > VINDPM setting. During the normal charging process, if the input power source is not able to support the programmed or default charging current and system load, the supply voltage decreases. Once the supply drops to VINDPM, the input DPM current and voltage loops will reduce the input current through the blocking FETs Q1 and Q2 to prevent the further drop of the supply. The VINDPM threshold is programmable through the I2C register and can be completely disabled. This is set through the VINDPM_0 and VINDPM_1 selection bits. When the device enters this mode, the charge current may be lower than the set value and the VINDPM_ACTIVE_STAT bit is set. If the 2x timer is set through the 2XTMR_EN bit, the safety timer is extended while VINDPM is active. Additionally, termination is disabled when VINDPM is active. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 15 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 8.3.2 Dynamic Power Path Management Mode (DPPM) With a valid input source connected, the power path management circuitry monitors the input voltage and current continuously. The current into IN is shared at SYS between charging the battery and powering the system load at SYS. If the sum of the charging and load currents exceeds the preset maximum input current, the input DPM loop reduces input current. If SYS drops below the DPPM voltage threshold, the charging current is reduced by the DPPM loop through the BATFET (Q3). If SYS falls below the supplement mode threshold after BATFET charging current is reduced to zero, the part will enter supplement mode. SYS voltage is maintained above battery voltage when the DPPM loop is in control. Battery termination is disabled when the DPPM loop is active. The VDPPM threshold is typically 100 mV above VBAT. The VDPPM disable bit (VDPPM_DIS = b1) will allow the charger to operate with lower headroom on VSYS. In VBAT tracking mode where VSYS is VBAT+225 mV, disabling this bit will have no effect. 8.3.3 Battery Supplement Mode While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the programmed input current limit, the voltage at SYS reduces further. When the SYS voltage drops below the battery voltage to VBSUP1, the battery supplements the system load. The battery stops supplementing the system load when the voltage on the SYS pin rises within the battery voltage to VBSUP2. During supplement mode, the battery supplement current is not regulated, however, the BATOCP protection circuit is active if enabled. Battery termination is disabled while in supplement mode. Battery voltage has to be higher than the battery undervoltage lockout threshold (VBUVLO) in order to supplement the system. 8.3.4 SYS Power Control (SYS_MODE bit control) The device also offers the option to control SYS through the I2C SYS_MODE bits. These bits can force SYS to be supplied by BAT instead of IN (even if VIN > VBAT + VSLEEP), disconnect SYS from either supply, pull SYS down or leave it floating. The table below shows the device behavior based on SYS_MODE setting: Table 8-1. Settings SYS_MODE DESCRIPTION SYS SUPPLY SYS PULLDOWN 00 Normal Operation IN or BAT Off except during HW reset 01 Force BAT power (IN disconnected) BAT Off except during HW reset 10 SYS Off –Floating None Off 11 SYS Off – Pulled Down None On SYS_MODE = 00 This is the default state/normal operation of the device. SYS will be powered from IN if VIN > VUVLO, VIN > VBAT + VSLEEPZ, and VIN < VIN_OVP. SYS will powered by BAT if these conditions are not met. SYS will only be disconnected from IN or BAT and pulled down when a HW Reset occurs or the device goes into Ship mode. SYS_MODE = 01 When this configuration is set, SYS will be powered by BAT if VBAT > VBUVLO regardless of VIN state. This allows the host to minimize the current draw from the adapter while it is still connected as needed in the system. If SYS_MODE = 01 is set while VBAT < VBUVLO, the SYS_MODE = 01 setting will be ignored and the device will go to SYS_MODE = 00. In the same manner, if the adapter (VIN) is removed and then connected the device will also switch to SYS_MODE = 00. This prevents the device from needing a POR in order to restore power to the system thereby allowing battery charging. If SYS_MODE = 01 is set during charging, charging will be stopped and the battery will start to provide power to SYS as needed. The behavior is similar to that when the input adapter is disconnected. SYS_MODE = 10 When this configuration is set, SYS will be disconnected and left floating. The device remains on and active. Toggling VIN(VIN VUVLO, VIN > VBAT + VSLEEPZ and VIN < VIN_OVP rather than meeting the VIN_Powergood condition. The SYS voltage regulation target can be controlled through the SYS_REG_CTRL_2:0 bits in the SYS_REG register to either track the battery, set to a fixed voltage, or enable pass through modes. In battery tracking mode, the minimum voltage is at the VMINSYS value for a battery < 3.6 V. As battery voltage increases VSYS is regulated to 225 mV above battery. If VIN < VMINSYS and VIN_Powergood is still active, then SYS will be in dropout. In fixed voltage mode, SYS voltage is regulated to a target set by the host ranging from 4.4 V to 4.9 V. If VIN voltage is less than the SYS target voltage, then the device will be in dropout mode. In pass through mode, the SYS path is unregulated and the VSYS voltage is equal to VIN. Table 8-3. SYS Voltage Regulation Settings SYS_REG_CTRL VSYS TARGET 000 VBAT + 225 mV (3.8 V minimum) 001 4.4 010 (default) 4.5 011 4.6 100 4.7 101 4.8 110 4.9 111 Pass through 8.3.6 ILIM Control The input current limit can be controlled through I2C by selecting the the ILIM bits. If the ILIM clamp is active, the ILIM_ACTIVE_STAT bit is set. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 17 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 MASK_ILIM will prevent an interrupt from being issued but does not override the ILIM behavior itself. The ILIM value can be programmed dynamically through the I2C by the host. The ILIM settings of 100mA and 500mA are designed to be the maximum value to support standard systems. 8.3.7 Protection Mechanisms 8.3.7.1 Input Overvoltage Protection Input overvoltage protection protects the device and downstream components connected to SYS, and BAT against damage from overvoltage on the input supply. When VIN > VIN_OVP, a VIN overvoltage condition is determined to exist. During the VIN overvoltage condition, the device turns the input FET OFF, battery discharge FET ON, sends a single 128-μs pulse on INT, and the fault bit (VIN_OVP_FAULT_FLAG) is updated over I2C. The VIN_PGOOD_STAT bit also is affected by the VIN overvoltage condition as the VIN powergood condition will fail. Once the VIN overvoltage condition is removed (VIN ≤ VIN_OVP - VIN_OV_HYS ), the VIN_OVP_STAT bit is cleared and the device returns to normal operation. Thereafter, a VIN powergood condition is determined if VIN > VBAT + VSLEEPZ and VIN > VIN_UVLO. 8.3.7.2 Battery Undervoltage Lockout In order to prevent deep discharge of the battery the device integrates a battery undervoltage lockout feature which will disengage the BAT to SYS path when voltage at the battery drops below the programmed BUVLO setting present in the CHARGERCTRL1 register. BUVLO status can also be read when a valid voltage on VIN is present. 8.3.7.3 System Overvoltage Protection The system overvoltage protection is to prevent SYS from overshooting to a high voltage due to the input supply. SYS_OVP will momentarily disconnect the blocking FETs and re-engage when the thresholds have dropped to less than the SYS_OVP_FALLING threshold. The SYS_OVP_RISING threshold is typically 105% of the target SYS voltage and the SYS_OVP_FALLING threshold is 102.5% of the target SYS voltage. 8.3.7.4 System Short Protection When a valid adapter is connected to the device, the device turns ON the input blocking FET for 5 ms and it detects the SYS pin to be shorted (voltage on SYS TSHUT_RISING prior to power being applied to the device (either battery or adapter), the input FET or BATFET will not turn ON, regardless of the TSMR pin. Thereafter if temperature falls below TSHUT_FALLING, the device will automatically power up if VIN is present or if in battery only mode. During the charging process, to prevent overheating in the device, the device monitors the junction temperature of the die and reduces the charging current once TJ reaches the thermal regulation threshold (TREG) based on bits set by the THERM_REG setting. If the charge current is reduced to 0, the battery supplies the current needed to supply the SYS output. Thermal regulation can be disabled through I2C. Ensure that system power dissipation is under the limit of the device. The power dissipated by the device can be calculated using the following equation: PDISS = PSYS + PBAT Where: PSYS = (VIN – VSYS) * IIN PBAT = (VSYS – VBAT) * IBAT The die junction temperature, TJ, can be estimated based on the expected board performance using the following equation: TJ = TA + θJA * PDISS θJA is largely driven by board layout. For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics Application Report. Under typical conditions, the time spent in this state is very short. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 19 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 8.3.8 Pushbutton Wake and Reset Input The pushbutton function implemented through the TSMR pin has three main functions. First, it serves as a means to wake the device from ultra-low power modes like ship mode. Second, it serves as a short button press detector, sending an interrupt to the host when the button driving the TSMR pin has been pressed for Wake1, Wake2, or long press durations. This allows the implementation of different functions in the end application such as menu selection and control. Finally it serves as a means to get the device into ship mode or reset the system by performing a power cycle/ hardware reset (shut down SYS and automatically powering it back on) after detecting a long button press. The timing for the short and long button press duration is programmable through I2C for added flexibility and allows system designers to customize the end user experience of a specific application. Note that if a specific timer duration is changed through I2C while that timer is active and has not expired, the new programmed value will be ignored until the timer expires and/or is reset by new push button action. In battery only mode the device will automatically pulse the TSMR current source ON for tTS_DUTY_ON duration and turn it OFF for tTS_DUTY_OFF duration to check if a button is pressed. If a button press is registered, the device will begin counting against Wake1, Wake2 or long press durations. This button press detection routine in battery only mode is run as long as it is enabled by the EN_PUSH bit. When a valid adapter is present, the TSMR current source is always ON to monitor charging. 8.3.8.1 Pushbutton Wake or Short Button Press Functions There are two programmable wake or short button press timers, WAKE1 and WAKE2. There are no specific actions taken by the tWAKE1 or tWAKE2 durations other than issuing an interrupt and updating the wake registers. For a wake from shipmode event when the button press is enabled, the push button has to be low for tshipwake before the device can turn ON the SYS rail. In the case where a valid VIN (VIN > VUVLO) is connected prior to the tshipwake timer expiring, the device will exit shipmode immediately regardless of the TS/MR or wake timer state. Refer to Section 8.5 for more details. 8.3.8.2 Pushbutton Reset or Long Button Press Functions tLPRESS tRESET_WARN tWAKE2 tWAKE1 Depending on the configuration set on the pushbutton long press action register bits, the device will perform a shipmode entry or hardware reset or completely ignore the long button press action. tRESTART TS/MR VIN INT 128us VSYS SW Reset PB_LPRESS_ACTION 01 – Hardware Reset Don’t care Default Figure 8-4. Pushbutton Long Press Reset 20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com tLPRESS tRESET_WARN tWAKE2 tWAKE1 SLUSF49 – JANUARY 2023 Shipmode enabled when TS/MR is high TS/MR VIN INT 128 us SYS SHIPMODE Don’t care PB_LPRESS_ACTION Ready to Enter Shipmode Figure 8-5. Pushbutton Long Press Shipmode 8.3.9 15-Second Timeout for HW Reset Based on the I2C register bit WATCHDOG_15S_ENABLE the device can perform a HW reset/power cycle in the same manner a long button press or HW_RESET would. This 15-second watchdog or timeout is gated upon VIN> VVBAT + VSLEEPZ so that the HW reset would only occur if the host does not respond after a charger is connected and VIN_PGOOD_STAT is set. If the charger is connected and the host responds before the 15-second watchdog expires, the part continues in normal operation and starts the normal 50-second watchdog timer if enabled. The 15-second watchdog may be enabled/disabled through I2C with the WATCHDOG_15S_ENABLE bit. 8.3.10 Hardware Reset The BQ21080 is capable of a hardware reset to completely powercycle the system. This is partcularly useful when a soft reset on the MCU or host fails to work. Below is a sequence of events during a hadware reset: 1. 2. 3. 4. 5. 6. 7. Turn OFF (if adapter is present) input blocking FET (Q1/Q2) Turn OFF battery FET (Q3) Engage pulldown on SYS Start the Autowake timer Once the Autowake timer expires, disconnect the pulldown on SYS Reset all registers to default Turn ON battery FET and input FET (if applicable) 8.3.11 Software Reset When a software reset is issued either through a watchdog action configurable through the WATCHDOG_SEL bits or register reset configurable through the REG_RST bit, the device will reset all of the registers to the defaults. Any bits loaded through OTP memory are also loaded. If the device was waiting to go to shipmode (all conditions for entering ship are fulfilled except adapter removal), a hardware or software reset will cancel the pending shipmode request. If the shipmode request was written through I2C, the host can cancel the ship entry by clearing the bit before shipmode entry has happened. 8.3.12 Interrupt Indicator (/INT) Pin The device contains an open-drain output that signals its status and is valid only after the device has completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 21 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 The /INT pin is normally in high impedance and is pulled low for 128 μs when an interrupt condition occurs. When a fault or status change occurs or any other condition that generates an interrupt, a 128-μs pulse (/INT pin pulled down) is sent on /INT to notify the host. Interrupts can be masked through I2C. If the interrupt condition occurs while the interrupt is masked an interrupt pulse will not be sent. If the interrupt is unmasked while the fault condition is still present, an interrupt pulse will not be sent until the /INT trigger condition occurs while unmasked. Below are a list of interrupts that can be masked through I2C. Table 8-5. Mask Bit MASK BIT ACTION ILIM_INT_MASK Do not issue an /INT pulse when ILIM limiting occurs VDPM_INT_MASK Do not issue an /INT pulse when VINDPM or DDPM is active TS_INT_MASK Do not issue an /INT pulse when any of the TS events have occured. TREG_INT_MASK Do not issue an /INT pulse when TREG is actively reducing the current PG_INT_MASK Do not issue an /INT pulse when VIN meets VIN_PG condition BAT_INT_MASK Do not issue an /INT pulse when BATOCP or BUVLO event is triggered CHG_STATUS_INT_MASK Do not send an interrupt anytime there is a charging status change. 8.3.13 External NTC Monitoring (TS) 8.3.13.1 TS Biasing and Function The device can be configured to meet JEITA requirements or a simpler HOT/COLD function only. Additionally, the TS charger control function can be disabled through the TS_EN bit. This will only disable the TS charge action but the faults are still reported based on the TS voltage. To satisfy the JEITA requirements, four temperature thresholds are monitored: cold battery threshold, cool battery threshold, warm battery threshold, and hot battery threshold. These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT thresholds in the Electrical Characteristics table. Charging and safety timers are suspended when VTS < VHOT or VTS > VCOLD. When VCOOL < VTS < VCOLD, the charging current is reduced to the value programmed in the TS_Setting register/bit TS_ICHG_0. When VHOT < VTS < VWARM, the battery regulation voltage is reduced by 100 mV or 200 mV based on the value programmed in the TS_VRCG_0 bit within the TS_Setting register. For devices where the TS function is not needed, tie a 10-kΩ resistor to the TS pin. There is an active voltage clamp present on this device which will prevent the voltage on the TSMR pin from rising above the VTS_CLAMP threshold. This will particularly be ON when the TSMR pin is floating. The bit TS_OPEN_STAT is set when this clamp is active. This will also be ON regardless of the TS_EN bit. The interrupt is asserted as long as the TS_INT mask is not written. The bits TS_HOT/TS_COLD, TS_WARM, and TS_COOL will allow these thresholds to be adjusted. The hysteresis will also move along with these thresholds. When the TS_WARM condition occurs, the device will lower the battery target regulation voltage by TS_VRCG but will not modify the VBAT_CTRL register. The TS_ICHG bit will reduce charging current based on the factor described in the register map when the TSMR pin hits a TS_COOL condition. The TREG function will still be based on this reduced threshold. The TS_VRCG_0 bit will reduce the charging voltage when the TSMR pin hits the TS_WARM threshold. The factor will be based on the register map. When the button is detected as pressed (TSMR pin low) during the charging process, charging will be momentarily suspended until the button is high again. When charging is disabled in any of the TS faults, trickle charging is also disabled. In a TS fault where the current is reduced (COOL), the trickle charging current is not altered. 22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 8.3.14 I2C Interface The BQ21080 device uses a fully compliant I2C interface to program and read control parameters, status bits, and so on. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA, and SCL. A controller device, usually a micro-controller or a digital signal processor, controls the bus. The controller is responsible for generating the SCL signal and device addresses. The controller also generates specific conditions that indicate the START and STOP of data transfer. A peripheral device receives and transmits data on the bus under control of the controller device. The BQ21080 works as a peripheral and supports the following data transfer modes, as defined in the I2C Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as VBAT or VIN voltages remains above their respective UVLO levels. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The BQ21080 device 7-bit address is 0×6A (shifted 8-bit address is 0xD4). 8.3.14.1 F/S Mode Protocol The controller initiates a data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 8-6. All I2C-compatible devices should recognize a start condition. DATA CLK S P START Condition STOP Condition Figure 8-6. START and STOP Condition The controller then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the controller ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 8-7). All devices recognize the address sent by the controller and compare it to their internal fixed addresses. Only the peripheral device with a matching address generates an acknowledge (see Figure 8-8) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows that communication link with a peripheral has been established. DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 8-7. Bit Transfer on the Serial Interface The controller generates further SCL cycles to either transmit data to the peripheral (R/W bit 0) or receive data from the peripheral (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the controller or by the peripheral, depending Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 23 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 8-6). This releases the bus and stops the communication link with the addressed peripheral. All I2C compatible devices must recognize the stop condition. Upon receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the controller needs to send a STOP condition to prevent the peripheral I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section results in FFh being read out. Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Controller 1 S 2 7 8 START Condition 9 Clock Pulse for Acknowledgement Figure 8-8. Acknowledge on the I2C Bus Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal Acknowledgement signal from peripheral P MSB SDA Address Sr Acknowledgement signal from peripheral R/W
 SCL 1 S or Sr 2 7 8 9 1 2 8 ACK 9 P or Sr ACK Figure 8-9. Bus Protocol 8.4 Device Functional Modes The BQ21080 has four main modes of operation: Battery Mode, Ship Mode, Charge/Adapter Mode when a supply is connected to IN, and Shutdown mode. The table below summarizes the functions that are active for each operation mode. Table 8-6. Function Availability Based on Primary Mode of Operation 24 FUNCTION CHARGE/ADAPTER MODE BATTERY MODE SHIP MODE SHUTDOWN MODE Input overvoltage Yes Yes No No Input undervoltage Yes Yes Yes Yes Battery overcurrent Yes, if enabled Yes Yes, if enabled No Battery undervoltage Yes Yes No No Input DPM Yes, if enabled No No No Dynamic power path management Yes, if enabled No No No Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table 8-6. Function Availability Based on Primary Mode of Operation (continued) FUNCTION CHARGE/ADAPTER MODE BATTERY MODE SHIP MODE SHUTDOWN MODE BATFET Yes Yes No No TS measurement Yes No No No Battery charging Yes, if enabled No No No ILIM Yes (Register Value) No No No Pushbutton input Yes Yes, if enabled Yes No INT output Yes Yes No No I2C Yes Yes No No 8.5 Register Maps 8.5.1 I2C Registers Table 8-7 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 8-7 should be considered as reserved locations and the register contents should not be modified. Table 8-7. I2C Registers Offset Acronym Register Name Section 0h STAT0 Charger Status Section 8.5.1.1 1h STAT1 Charger Status and Faults Section 8.5.1.2 2h FLAG0 Charger Flag Registers Section 8.5.1.3 3h VBAT_CTRL Battery Voltage Control Section 8.5.1.4 4h ICHG_CTRL Fast Charge Current Control Section 8.5.1.5 5h CHARGECTRL0 Charger Control 0 Section 8.5.1.6 6h CHARGECTRL1 Charger Control 1 Section 8.5.1.7 7h IC_CTRL IC Control Section 8.5.1.8 8h TMR_ILIM Timer and Input Current Limit Control Section 8.5.1.9 9h SHIP_RST Shipmode, Reset and Pushbutton Control Section 8.5.1.10 Ah SYS_REG SYS Regulation Voltage Control Section 8.5.1.11 Bh TS_CONTROL TS Control Section 8.5.1.12 Ch MASK_ID MASK and Device ID Section 8.5.1.13 Complex bit access types are encoded to fit into small table cells. Table 8-8 shows the codes that are used for access types in this section. Table 8-8. I2C Access Type Codes Access Type Code Description R R Read RC R C Read to Clear W Write Read Type Write Type W Reset or Default Value -n Value after reset or the default value Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 25 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 8.5.1.1 STAT0 Register (Offset = 0h) [Reset = X] STAT0 is shown in Table 8-9. Return to the Table 8-7. Table 8-9. STAT0 Register Field Descriptions Bit Field Type Reset Description 7 TS_OPEN_STAT R X TS Open Status 1b0 = TSMR pin is not Open 1b1 = TSMR pin is Open 6-5 CHG_STAT_1:0 R X Charging Status Indicator 2b00 = Not Charging while charging is enabled. 2b01 = Constant Current Charging (Trickle Charge/ Pre Charge or in Fast Charge Mode) 2b10 = Constant Voltage Charging 2b11 = Charge Done or charging is disabled by the host. 4 ILIM_ACTIVE_STAT R X Input Curent Limit Active 1b0 = Not Active 1b1 = Active 3 VDPPM_ACTIVE_STAT R X VDPPM Mode Active 1b0 = Not Active 1b1 = Active 2 VINDPM_ACTIVE_STAT R X VINDPM Mode Active 1b0 = Not Active 1b1 = Active 1 THERMREG_ACTIVE_ST R AT X Thermal Regulation Active 1b0 = Not Active 1b1 = Active 0 VIN_PGOOD_STAT X VIN Power Good 1b0 = VIN Power Not Good 1b1 = VIN Power Good R 8.5.1.2 STAT1 Register (Offset = 1h) [Reset = X] STAT1 is shown in Table 8-10. Return to the Table 8-7. Table 8-10. STAT1 Register Field Descriptions Bit Field Type Reset Description 7 VIN_OVP_STAT R 1b0 VIN_OVP Fault 1b0 = Not Active 1b1 = Active 6 BUVLO_STAT R X Battery UVLO Status 1b0 = Not Active 1b1 = Active 5 RESERVED R X Reserved TS_STAT_1:0 R 2b00 TS Status 2b00 = Normal 2b01 = VTS < VHOT or VTS > VCOLD(charging suspended) 2b10 = VCOOL < VTS < VCOLD (Charging current reduced by value set by TS_Registers) 2b11 = VWARM > VTS > VHOT (Charging voltage reduced by value set by TS_Registers) 2 SAFETY_TMR_FAULT_F LAG RC 1b0 Safety Timer Expired Fault Cleared only after CE is toggled. 1b0 = Not Active 1b1 = Active 1 WAKE1_FLAG RC 1b0 Wake 1 Timer Flag 1b0 = Does not meet Wake 1 Condition 1b1 = Met Wake 1 Condition 4-3 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table 8-10. STAT1 Register Field Descriptions (continued) Bit 0 Field Type Reset Description WAKE2_FLAG RC 1b0 Wake 2 Timer Flag 1b0 = Does not meet Wake 2 Condition 1b1 = Met Wake2 Condition 8.5.1.3 FLAG0 Register (Offset = 2h) [Reset = X] FLAG0 is shown in Table 8-11. Return to the Table 8-7. Table 8-11. FLAG0 Register Field Descriptions Bit Field Type Reset Description 7 TS_FAULT RC X TS_Fault 1b0 = No TS Fault detected 1b1 = TS Fault detected 6 ILIM_ACTIVE_FLAG RC X ILIM Active 1b0 = NO ILIM Fault detected 1b1 = ILIM Fault detected 5 VDPPM_ACTIVE_FLAG RC X VDPPM FLAG 1b0 = VDPPM fault not detected 1b1 = VDPPM fault detected 4 VINDPM_ACTIVE_FLAG RC X VINDPM FLAG 1b0 = VINDPM fault not detected 1b1 = VINDPM fault detected 3 THERMREG_ACTIVE_FL RC AG X Thermal Regulation FLAG 1b0 = No thermal regulation detected 1b1 = Thermal regulation has occured 2 VIN_OVP_FAULT_FLAG RC X VIN_OVP FLAG 1b0 = VIN_OVP fault not detected 1b1 = VIN_OVP fault detected 1 BUVLO_FAULT_FLAG RC X Battery undervoltage FLAG 1b0 = Battery undervoltage fault not detected 1b1 = Battery undervoltage fault detected 0 BAT_OCP_FAULT RC X Battery overcurrent protection 1b0 = Battery overcurrent condition not detected 1b1 = Battery overcurrent condition detected 8.5.1.4 VBAT_CTRL Register (Offset = 3h) [Reset = 46h] VBAT_CTRL is shown in Table 8-12. Return to the Table 8-7. Table 8-12. VBAT_CTRL Register Field Descriptions Bit 7 6-0 Field Type Reset Description RESERVED R/W 1b0 Reserved VBATREG_6:0 R/W 7b1000110 Battery Regulation Voltage VBATREG= 3.5V + VBATREG_CODE * 10mV. Maximum programmable voltage = 4.65V 8.5.1.5 ICHG_CTRL Register (Offset = 4h) [Reset = 05h] ICHG_CTRL is shown in Table 8-13. Return to the Table 8-7. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 27 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table 8-13. ICHG_CTRL Register Field Descriptions Bit Field Type Reset Description 7 CHG_DIS R/W 1b0 Charge Disable 1b0 = Battery Charging Enabled 1b1 = Battery Charging Disabled 6-0 ICHG_6:0 R/W 7b0000101 For ICHG 35mA = 40+ ((ICHGCODE-31)*10)mA. Maximum programmable current = 800mA 8.5.1.6 CHARGECTRL0 Register (Offset = 5h) [Reset = 2Ch] CHARGECTRL0 is shown in Table 8-14. Return to the Table 8-7. Table 8-14. CHARGECTRL0 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 1b0 Reserved 6 IPRECHG R/W 1b0 Precharge current = x times of term 1b0 = Precharge is 2x Term 1b1 = Precharge is Term 5-4 ITERM_1:0 R/W 2b10 Termination current = % of Icharge 2b00 = Disable 2b01 = 5% of ICHG 2b10 = 10% of ICHG 2b11 = 20% of ICHG 3-2 VINDPM_1:0 R/W 2b11 VINDPM Level Selection 2b00 = 4.2 V 2b01 = 4.5 V 2b10 = 4.7 V 2b11 = Disabled 1-0 THERM_REG_1:0 R/W 2b00 Thermal Regulation Threshold 2b00 = 100C 2b11 = Disabled 8.5.1.7 CHARGECTRL1 Register (Offset = 6h) [Reset = 56h] CHARGECTRL1 is shown in Table 8-15. Return to the Table 8-7. Table 8-15. CHARGECTRL1 Register Field Descriptions Bit Field Type Reset Description 7-6 IBAT_OCP_1:0 R/W 2b01 Battery Discharge Current Limit 2b00 = 500mA 2b01 = 1000mA 2b10 = 1500mA 2b11 = Disabled 5-3 BUVLO_2:0 R/W 3b010 Battery Undervoltage LockOut Falling Threshold. 3b000 = 3.0V 3b001 = 3.0V 3b010 = 3.0V 3b011 = 2.8V 3b100 = 2.6V 3b101 = 2.4V 3b110 = 2.2V 3b111 = 2.0V CHG_STATUS_INT_MAS K R/W 1b1 Mask Charging Status Interrupt 1b0 = Enable Charging Status Interrupt anytime there is a charging status change. 1b1 = Mask Charging Status Interrupt 2 28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table 8-15. CHARGECTRL1 Register Field Descriptions (continued) Bit Field Type Reset Description 1 ILIM_INT_MASK R/W 1b1 Mask ILIM Fault Interrupt 1b0 = Enable ILIM Interrupt 1b1 = Mask ILIM Interrupt 0 VDPM_INT_MASK R/W 1b0 Mask VINDPM and VDPPM Interrupt 1b0 = Enable VINDPM and VDPPM Interrupt 1b1 = Mask VINDPM and VDPPM Interrupt 8.5.1.8 IC_CTRL Register (Offset = 7h) [Reset = 84h] IC_CTRL is shown in Table 8-16. Return to the Table 8-7. Table 8-16. IC_CTRL Register Field Descriptions Bit Field Type Reset Description 7 TS_EN R/W 1b1 TS Auto Function 1b0 = TS auto function disabled (Only charge control is disabled. TS monitoring is enabled) 1b1 = TS auto function enabled 6 VLOWV_SEL R/W 1b0 Precharge Voltage Threshold (VLOWV) 1b0 = 3V 1b1 = 2.8V 5 VRCH_0 R/W 1b0 Recharge Voltage Threshold 1b0 = 100mV 1b1 = 200 mV 4 2XTMR_EN R/W 1b0 Timer Slow 1b0 = The timer is not slowed at any time 1b1 = The timer is slowed by 2x when in any control other than CC or CV 3-2 SAFETY_TIMER_1:0 R/W 2b01 Fast Charge Timer 2b00 = 3 hour fast charge 2b01 = 6 hour fast charge 2b10 = 12 hour fast charge 2b11 = Disable safety timer 1-0 WATCHDOG_SEL_1:0 R/W 2b00 Watchdog Selection 2b00 = 160s default register values 2b01 = 160s HW_RESET 2b10 = 40s HW_RESET 2b11 = Disable watchdog function 8.5.1.9 TMR_ILIM Register (Offset = 8h) [Reset = 4Dh] TMR_ILIM is shown in Table 8-17. Return to the Table 8-7. Table 8-17. TMR_ILIM Register Field Descriptions Bit Field Type Reset Description 7-6 MR_LPRESS_1:0 R/W 2b01 Push button Long Press duration timer 2b00 = 5s 2b01 = 10s 2b10 = 15s 2b11 = 20s 5 MR_RESET_VIN R/W 1b0 Hardware reset condition 1b0 = Reset sent when long press duration is met 1b1 = Reset sent when long press duration is met and VIN_Powergood Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 29 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table 8-17. TMR_ILIM Register Field Descriptions (continued) Bit Field Type Reset Description 4-3 AUTOWAKE_1:0 R/W 2b01 Auto Wake Up Timer Restart 2b00 = 0.5s 2b01 = 1s 2b10 = 2s 2b11 = 4s 2-0 ILIM_2:0 R/W 3b101 Input Current Limit Setting 3b000 = 50mA 3b001 = 100mA(max.) 3b010 = 200mA 3b011 = 300mA 3b100 = 400mA 3b101 = 500mA(max.) 3b110 = 700mA 3b111 = 1100mA 8.5.1.10 SHIP_RST Register (Offset = 9h) [Reset = 11h] SHIP_RST is shown in Table 8-18. Return to the Table 8-7. Table 8-18. SHIP_RST Register Field Descriptions Bit Field Type Reset Description REG_RST R/W 1b0 Software Reset 1b0 = Do nothing 1b1 = Software Reset 6-5 EN_RST_SHIP_1:0 R/W 2b00 Shipmode Enable and Hardware Reset 2b00 = Do nothing 2b01 = Enable shutdown mode with wake on adapter insert only 2b10 = Enable shipmode with wake on button press or adapter insert 2b11 = Hardware Reset 4-3 PB_LPRESS_ACTION_1: R/W 0 2b10 Pushbutton long press action 2b00 = Do nothing 2b01 = Hardware Reset 2b10 = Enable shipmode 2b11 = Enable shutdown mode 2 WAKE1_TMR R/W 1b0 Wake 1 Timer Set 1b0 = 300ms 1b1 = 1s 1 WAKE2_TMR R/W 1b0 Wake 2 Timer Set 1b0 = 2s 1b1 = 3s 0 EN_PUSH R/W 1b1 Enable Push Button and Reset Function on Battery Only 1b0 = Disable 1b1 = Enable 7 8.5.1.11 SYS_REG Register (Offset = Ah) [Reset = 40h] SYS_REG is shown in Table 8-19. Return to the Table 8-7. 30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Table 8-19. SYS_REG Register Field Descriptions Bit Field Type Reset Description 7-5 SYS_REG_CTRL_2:0 R/W 3b010 SYS Regulation Voltgage 3b000 = Battery Tracking Mode 3b001 = 4.4V 3b010 = 4.5V 3b011 = 4.6V 3b100 = 4.7V 3b101 = 4.8V 3b110 = 4.9V 3b111 = Pass-Through (VSYS is VIN) RESERVED R/W 1b0 Reserved SYS_MODE_1:0 R/W 2b00 Sets how SYS is powered in any state, except SHIPMODE 2b00 = SYS powered from VIN if present or VBAT 2b01 = SYS powered from VBAT only, even if VIN present 2b10 = SYS disconnected and left floating 2b11 = SYS disconnected with pulldown 1 WATCHDOG_15S_ENAB LE R/W 1b0 I2C Watchdog 1b0 = Mode Disabled 1b1 = Do a HW reset after 15s if no I2C transaction after VIN plugged 0 VDPPM_DIS R/W 1b0 Disable VDPPM 1b0 = Enable VDPPM 1b1 = Disable VDPPM 4 3-2 8.5.1.12 TS_CONTROL Register (Offset = Bh) [Reset = 00h] TS_CONTROL is shown in Table 8-20. Return to the Table 8-7. Table 8-20. TS_CONTROL Register Field Descriptions Bit Field Type Reset Description 7-6 TS_HOT R/W 2b00 TS Hot threshold register 2b00 = Default 60C 2b01 = 65C 2b10 = 50C 2b11 = 45C 5-4 TS_COLD R/W 2b00 TS Cold threshold register 2b00 = Default 0C 2b01 = 3C 2b10 = 5C 2b11 = -3C 3 TS_WARM R/W 1b0 TS Warm threshold 1b0 = Default 45C 1b1 = Disabled 2 TS_COOL R/W 1b0 TS Cool threshold register 1b0 = Default 10C 1b1 = Disabled 1 TS_ICHG R/W 1b0 Fast charge current when decreased by TS function 1b0 = 0.5*ICHG 1b1 = 0.2*ICHG 0 TS_VRCG R/W 1b0 Reduced target battery voltage during Warm 1b0 = VBATREG -100mV 1b1 = VBATREG -200mV 8.5.1.13 MASK_ID Register (Offset = Ch) [Reset = C0h] MASK_ID is shown in Table 8-21. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 31 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Return to the Table 8-7. Table 8-21. MASK_ID Register Field Descriptions Bit Field Type Reset Description 7 TS_INT_MASK R/W 1b1 Mask TS 1b0 = Enable TS Interrupt 1b1 = Mask TS Interrupt 6 TREG_INT_MASK R/W 1b1 Mask TREG 1b0 = Enable TREG Interrupt 1b1 = Mask TREG Interrupt 5 BAT_INT_MASK R/W 1b0 Mask BATOCP and BUVLO 1b0 = Enable BOCP and BUVLO Interrupt 1b1 = Mask BOCP and BUVLO Interrupt 4 PG_INT_MASK R/W 1b0 Mask PG and VINOVP 1b0 = Enable PG and VINOVP Interrupt 1b1 = Mask PG and VINOVP Interrupt Device_ID R 4b0000 Device ID 4b0000 = BQ21080 3-0 32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information A typical application of the BQ21080 consists of the device configured as an I2C controlled single cell Li-ion battery charger and power path manager or battery applications such as smart watches and wireless headsets. A battery thermistor may be connected to the TS pin to allow the device to monitor the battery temperature and control charging as desired. The system designer may connect the TS/MR pin input to a push button to send interrupts to the host as a button is pressed or to allow the application end user to reset the system. 9.2 Typical Application SYS IN VBUS Regulated Load 10uF 1uF /INT SCL Device Control SDA BAT Host 1uF VIO + TS/MR – NTC BQ21080 GND Figure 9-1. Typical Application 9.2.1 Design Requirements The design requirements for the following design example are shown in Table 9-1. Table 9-1. Design Parameters PARAMETER VALUE IN supply voltage 5V Battery regulation voltage 4.2 V 9.2.2 Detailed Design Procedure Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 33 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 9.2.2.1 Input (IN/SYS) Capacitors Low ESR ceramic capacitors such as X7R or X5R are preferred for input decoupling capacitors and should be placed as close as possible to the supply and ground pins for the IC. Due to the voltage derating of the capacitors, it is recommended that 25-V rated capacitors are used for the IN and SYS pins which can normally operate at 5 V. After derating the minimum capacitance must be higher than 1 µF. 9.2.2.2 TS The ground connection for the NTC must be made as close as possible to the GND pin of the device or kelvin connected to it to minimize any error in TS measurement due to IR drops on the ground board lines. If the system designer does not wish to use the TS function for charging control, a 10-kΩ resistor must be connected from TS to ground. 9.2.2.3 Recommended Passive Components Table 9-2. Passive Components MIN NOM MAX UNIT CSYS Capacitance on SYS pin 1 10 100 μF CBAT Capacitance on BAT pin 1 1 - μF CIN IN input bypass capacitance 1 1 10 μF 34 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 9.2.3 Application Curves CIN = 1 µF, COUT = 10 µF, VIN = 5 V, VOUT = 3.8 V, ICHG = 10 mA (unless otherwise specified) VIN = 5 V VBAT = Floating VIN = 5 V Figure 9-2. Power Up with IN Supply Insertion with No Battery VIN = 0 V → 5 V VBAT = 3.8 V VBAT = 3.6 V Figure 9-3. Power Up from Shutdown Mode with VIN Supply Insertion MR_LPRESS = 00 (5s Long Press Timer) Figure 9-4. Power Up from Shipmode with VIN Insertion Figure 9-5. Power Up from Shipmode with /TSMR Button Press Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 35 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 MR_LPRESS = 00 (5s Long Press Timer) PB_LPRESS_ACTION = 01 (Hardware Reset) MR_LPRESS = 00 (5s Long Press Timer) PB_LPRESS_ACTION = 10 Figure 9-6. Hardware Reset with /TSMR Press Figure 9-8. Hardware Reset Through I2C Figure 9-7. Enter Shipmode with Push Button Long Press EN_RST_SHIP = 01 (enable shutdown with wake on adapter insert only) Figure 9-9. Shutdown Entry on VIN Removal 36 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 EN_RST_SHIP = 10 (enable shutdown with wake on adapter insert only) VIN = 0 V → 5 V → 0 V Figure 9-11. Power Good Interrupt on /INT Figure 9-10. Shipmode Entry on VIN Removal VIN = 0 V PB_LPRESS_ACTION = 11 (enable shutown mode) MR_LPRESS = 00 (5 seconds) SYS_REG_CTRL = 000 → 111 in steps Figure 9-13. SYS Regulation Sweep Figure 9-12. Shutdown Mode Entry with Push Button Long Press Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 37 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 SYS_MODE = 00 → 01 → 10 → 11 VIN = 5 V Figure 9-14. SYS Mode Sweep VIN = 5 V Figure 9-16. Wake2 Interrupt with VIN Present Figure 9-15. Wake1 Interrupt with VIN Present VIN = 5 V MR_LPRESS = 00 (5 seconds) PB_LPRESS_ACTION = Hardware Reset Figure 9-17. Long Press Interrupt with VIN Present VIN = 0 V VIN = 5 V Figure 9-18. Wake1 Interrupt without VIN 38 Figure 9-19. Wake2 Interrupt without VIN Present Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 VIN = 0 V MR_LPRESS = 00 (5 seconds) PB_LPRESS_ACTION = 11 (Hardware Reset) Figure 9-20. Long Press Interrupt without VIN Present Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 39 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 10 Power Supply Recommendations The BQ21080 requires the adapter or IN supply to be between 2.7 V and 5.5 V. The battery voltage must be higher than 3.15 V or VBUVLO to ensure proper operation. 40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 11 Layout 11.1 Layout Guidelines • • • To obtain optimal performance, the decoupling capacitor from IN to GND, the capacitor from SYS to GND and BAT to GND should be placed as close as possible to the device, with short trace runs to IN, SYS, BAT and GND.Have solid ground plane that is tied to the GND bump The pushbutton GND should be connected close to the device as possible. The high current charge paths into IN, SYS and BAT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. 11.2 Layout Example Bo
om Layer Top Layer GND 0402 IN 0402 /INT IN SYS SCL SYS SDA BAT TS/MR GND 0402 BAT Figure 11-1. Layout Example Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 41 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary 42 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 43 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 44 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 45 BQ21080 www.ti.com SLUSF49 – JANUARY 2023 46 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: BQ21080 PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ21080YBGR ACTIVE DSBGA YBG 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 B080 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of