BQ2201SNTR

bq2201 SRAM Nonvolatile Controller Unit Features General Description ➤ Power monitoring and switching for 3-volt battery-backup applications The CMOS bq2201 SRAM Nonvolatile Controller Unit provides all necessary functions for converting a standard CMOS SRAM into nonvolatile read/write memory. ➤ Write-protect control ➤ 3-volt primary cell inputs ➤ Les s than 10ns chip- e nable propagation delay ➤ 5% or 10% supply operation A precision comparator monitors the 5V VCC input for an out-of-tolerance condition. When out of tolerance is detected, a conditioned chip-enable output is forced inactive to writeprotect any standard CMOS SRAM. Pin Connections During a power failure, the external SRAM is switched from the V CC supply to one of two 3V backup supplies. On a subsequent power-up, the SRAM is write-protected until a power-valid condition exists. The bq2201 is footprint- and timingcompatible with industry standards with the added benefit of a chip-enable propagation delay of less than 10ns. Pin Names NC 1 16 NC VOUT 2 15 VCC VOUT Supply output BC1—BC2 3-volt primary backup cell inputs THS Threshold select input CE chip-enable active low input CECON Conditioned chip-enable output VOUT 1 8 VCC NC 3 14 NC BC2 2 7 BC1 BC2 4 13 BC1 THS 3 6 CECON NC 5 12 NC VCC +5-volt supply input VSS 4 5 CE THS 6 11 CECON VSS Ground NC 7 10 NC NC No Connect VSS 8 9 CE 8-Pin Narrow DIP or SOIC PN220101.eps 16-Pin SOIC PN2201E.eps Functional Description An external CMOS static RAM can be battery-backed using the VOUT and the conditioned chip-enable output pin from the bq2201. As VCC slews down during a power failure, the conditioned chip-enable output CE CON is forced inactive independent of the chip-enable input CE. If THS is tied to VSS, power-fail detection occurs at 4.62V typical for 5% supply operation. If THS is tied to VCC, power-fail detection occurs at 4.37V typical for 10% supply operation. The THS pin must be tied to VSS or VCC for proper operation. This activity unconditionally write-protects external SRAM as VCC falls to an out-of-tolerance threshold VPFD. VPFD is selected by the threshold select input pin, THS. If a memory access is in process during power-fail detection, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time tWPT, the CECON output is unconditionally driven high, write-protecting the memory. Oct. 1998 D 1 bq2201 A valid isolation signal requires CE low as VCC crosses both VPFD and VSO during a power-down. See Figure 2. Between these two points in time, CE must be brought to the point of (0.48 to 0.52)*VCC and held for at least 700ns. The isolation signal is invalid if CE exceeds 0.54*VCC at any point between VCC crossing VPFD and VSO. As the supply continues to fall past VPFD, an internal switching device forces VOUT to one of the two external backup energy sources. CECON is held high by the VOUT energy source. During power-up, VOUT is switched back to the VCC supply as VCC rises above the backup cell input voltage sourcing VOUT. The CECON output is held inactive for time t CER (120 ms maximum) after the supply has reached VPFD, independent of the CE input, to allow for processor stabilization. The appropriate battery is connected to VOUT and CECON immediately on subsequent application and removal of VCC. During power-valid operation, the CE input is fed through to the CECON output with a propagation delay of less than 10ns. Nonvolatility is achieved by hardware hookup, as shown in Figure 1. VPFD Energy Cell Inputs—BC1, BC2 Two primary backup energy source inputs are provided on the bq2201. The BC1 and BC2 inputs accept a 3V primary battery, typically some type of lithium chemistry. If no primary cell is to be used on either BC1 or BC2, the unused input should be tied to VSS. VCC VSO If both inputs are used, during power failure the VOUT output is fed only by BC1 as long as it is greater than 2.5V. If the voltage at BC1 falls below 2.5V, an internal isolation switch automatically switches VOUT from BC1 to BC2. 0.5 VCC CE 700ns To prevent battery drain when there is no valid data to retain, VOUT and CECON are internally isolated from BC1 and BC2 by either of the following: ■ Initial connection of a battery to BC1 or BC2, or ■ Presentation of an isolation signal on CE. TD220101.eps Figure 2. Battery Isolation Signal 5V VCC From Address Decoder VOUT VCC CE bq2201 BC1 CE CECON CMOS SRAM THS 3V Primary Cell VSS BC2 3V Primary Cell FG220101.eps Figure 1. Hardware Hookup (5% Supply Operation) Oct. 1998 D 2 bq2201 Absolute Maximum Ratings Symbol Parameter Value Unit Conditions VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to 7.0 V VT ≤ VCC + 0.3 TOPR 0 to +70 °C Commercial Operating temperature -40 to +85 °C Industrial “N” TSTG Storage temperature -55 to +125 °C TBIAS Temperature under bias -40 to +85 °C TSOLDER Soldering temperature 260 °C IOUT VOUT current 200 mA Note: For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Recommended DC Operating Conditions (TA = TOPR) Symbol VCC Parameter Minimum Typical Maximum Unit 4.75 5.0 5.5 V THS = VSS 4.50 5.0 5.5 V THS = VCC 0 0 0 V Supply voltage VSS Supply voltage VIL Input low voltage -0.3 - 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V VBC1, VBC2 Backup cell voltage 2.0 - 4.0 V THS Threshold select -0.3 - VCC + 0.3 V Note: Typical values indicate operation at TA = 25°C, VCC = 5V or VBC. Oct. 1998 D 3 Notes bq2201 DC Electrical Characteristics (TA = TOPR, VCC = 5V ± 10%) Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes - - ±1 µA 2.4 - - V IOH = -2.0mA VBC - 0.3 - - V VBC > VCC, IOH = -10µA IOL = 4.0mA ILI Input leakage current VOH Output high voltage VOHB VOH, BC supply VOL Output low voltage - - 0.4 V ICC Operating supply current - 3 5 mA VPFD 4.55 4.62 4.75 V Power-fail detect voltage THS = VSS 4.30 4.37 4.50 V THS = VCC VIN = VSS to VCC No load on VOUT and CECON. VSO Supply switch-over voltage - VBC - V ICCDR Data-retention mode current - - 100 nA VOUT1 VOUT voltage VCC - 0.2 - - V VCC > VBC, IOUT = 100mA VCC - 0.3 - - V VCC > VBC, IOUT = 160mA VBC - 0.3 - - V VCC < VBC, IOUT = 100µA VOUT data-retention current to additional memory not included. VOUT2 VOUT voltage VBC Active backup cell voltage - VBC2 - V VBC1 < 2.5V - VBC1 - V VBC1 > 2.5V IOUT1 VOUT current - - 160 mA VOUT > VCC - 0.3V IOUT2 VOUT current - 100 - µA VOUT > VBC - 0.2V Note: Typical values indicate operation at TA = 25°C, VCC = 5V or VBC. Oct. 1998 D 4 bq2201 Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V) Minimum Typical Maximum Unit CIN Symbol Input capacitance - - 8 pF Input voltage = 0V COUT Output capacitance - - 10 pF Output voltage = 0V Note: Parameter Conditions This parameter is sampled and not 100% tested. AC Test Conditions Parameter Test Conditions Input pulse levels 0V to 3.0V Input rise and fall times 5ns Input and output timing reference levels 1.5V (unless otherwise specified) Output load (including scope and jig) See Figure 3 5V 960 CECON 510 100pF FG220102.eps Figure 3. Output Load Oct. 1998 D 5 bq2201 Power-Fail Control (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit Notes tPF VCC slew, 4.75V to 4.25V 300 - - µs tFS VCC slew, 4.25V to VSO 10 - - µs tPU VCC slew, 4.25V to 4.75V 0 - - µs tCED Chip-enable propagation delay - 7 10 ns tCER Chip-enable recovery 40 80 120 ms Time during which SRAM is write-protected after VCC passes VPFD on power-up. tWPT Write-protect time 40 100 150 µs Delay after VCC slews down past VPFD before SRAM is write-protected. Note: Typical values indicate operation at TA = 25°C. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down Timing tPF 4.75 VPFD VCC tFS 4.25 VSO CE tWPT VOHB CECON TD220102.eps Oct. 1998 D 6 bq2201 Power-Up Timing tPU VCC 4.25 VSO 4.75 VPFD tCER CE CECON tCED VOHB tCED TD220103.eps Oct. 1998 D 7 bq2201 8-Pin DIP Narrow (PN) 8-Pin DIP Narrow (PN) Dimension A A1 B B1 C D E E1 e G L S Minimum 0.160 0.015 0.015 0.055 0.008 0.350 0.300 0.230 0.300 0.090 0.115 0.020 Maximum 0.180 0.040 0.022 0.065 0.013 0.380 0.325 0.280 0.370 0.110 0.150 0.040 All dimensions are in inches. 8-Pin SOIC Narrow (SN) 8-Pin SOIC Narrow (SN) Dimension A A1 B C D E e H L Minimum 0.060 0.004 0.013 0.007 0.185 0.150 0.045 0.225 0.015 Maximum 0.070 0.010 0.020 0.010 0.200 0.160 0.055 0.245 0.035 All dimensions are in inches. Oct. 1998 D 8 bq2201 S: 16-Pin SOIC 16-Pin S (SOIC) D Dimension Minimum A 0.095 A1 0.004 B 0.013 C 0.008 D 0.400 E 0.290 e 0.045 H 0.395 L 0.020 All dimensions are in inches. B e E H A C .004 L A1 Oct. 1998 D 9 Maximum 0.105 0.012 0.020 0.013 0.415 0.305 0.055 0.415 0.040 bq2201 Data Sheet Revision History Change No. Page No. 1 Note: Description Nature of Change Added industrial temperature range Was: THS tied to VOUT Is: THS tied to VCC 2 1, 3, 4 10% supply operation 3 1, 9, 11 Added 16-pin package option Change 1 = Sept. 1991 B changes from Sept. 1990 A. Change 2 = Aug. 1997 C changes from Sept. 1991 B. Change 3 = Oct. 1998 D changes from Aug. 1997 C. Oct. 1998 D 10 bq2201 Ordering Information bq2201 Temperature Range: blank = Commercial (0 to +70°C) N = Industrial (-40 to +85°C) Package Option: PN = 8-pin narrow plastic DIP SN = 8-pin narrow SOIC S = 16-pin SOIC Device: bq2201 Nonvolatile SRAM Controller Oct. 1998 D 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ2201SN-N ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2201 -N BQ2201SN-NTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2201 -N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of