bq24030-Q1
bq24031-Q1
www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009
SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC
Check for Samples: bq24030-Q1 bq24031-Q1
FEATURES
APPLICATIONS
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Qualified for Automotive Applications
Small 3.5-mm × 4.5-mm QFN Package
Designed for Single-Cell Li-Ion or
Li-Polymer-Based Portable Applications
Integrated Dynamic Power-Path Management
(DPPM) Feature Allowing AC Adapter or USB
Port to Simultaneously Power the System and
Charge the Battery
Power Supplement Mode Allows Battery to
Supplement USB or AC Input Current
Autonomous Power Source Selection (AC
Adapter or USB)
Integrated USB Charge Control With
Selectable 100-mA and 500-mA Maximum
Input Current Regulation Limits
Dynamic Total Current Management for USB
Supports up to 2-A Total Current
3.3-V Integrated LDO Output
Thermal Regulation for Charge Control
Charge Status Outputs for LED or System
Interface Indicates Charge and Fault
Conditions
Reverse Current, Short-Circuit, and Thermal
Protection
Power Good (AC Adapter and USB Port
Present) Status Outputs
Charge Voltage: 4.1 V or 4.2 V
Smart Phones and PDAs
MP3 Players
Digital Cameras
Handheld Devices
Internet Appliances
DESCRIPTION
The bqTINY™ III series of devices are highly
integrated Li-ion linear chargers and system
power-path management devices targeted at
space-limited portable applications. The bqTINY III
series offer integrated USB-port and dc supply (AC
adapter), power-path management with autonomous
power-source selection, power FETs and current
sensors, high accuracy current and voltage
regulation, charge status, and charge termination in a
single monolithic device.
The bqTINY III series powers the system while
independently charging the battery. This feature
reduces the charge and discharge cycles on the
battery, allows for proper charge termination, and
allows the system to run with an absent or defective
battery pack. This feature also allows for the system
to instantaneously turn on from an external power
source in the case of a deeply discharged battery
pack. The IC design is focused on supplying
continuous power to the system when available from
the AC, USB, or battery sources.
POWER FLOW DIAGRAM
AC Adapter
bq2403x
(See Note 2)
AC
VDC
USB Port
D+
D–
VBUS
GND
OUT
System
Q1
USB
40 mW
BAT
PACK+
+
PACK–
GND
Q3
Q2
(1)
See Figure 2 and Functional Block Diagram for detailed feature information.
(2)
P-FET back gate body diodes are disconnected to prevent body diode conduction.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
bqTINY is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
bq24030-Q1
bq24031-Q1
SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The power select pin (PSEL) defines which input source is to be used first (primary source is either AC or USB).
If the primary source is not available, then the IC automatically switches over to the secondary source (if
available) or the battery as the last option. If the PSEL is set low, the USB input is selected first and (if not
available) the AC line is selected (if available) but programmed to a USB input limiting rate (100 mA/500 mA
max). This feature allows the use of one input connector, where the host programs the PSEL pin according to
what source is connected (AC adapter or USB port).
The ISET1 pin programs the battery's fast-charge constant current level with a resistor. During normal AC
operation, the input supply provides power to both the OUT (system) and BAT pins. For peak or excessive loads
(typically when operating from the USB power, PSEL = low) that would cause the input source to enter current
limit (or Q3 – USB FET limiting current) and its source and system voltage (OUT pin) to drop, the dynamic
power-path management (DPPM) feature reduces the charging current attempting to prevent any further drop in
system voltage. This feature allows the selection of a lower current rated adapter based on the average load
(ISYS-AVG + IBAT-PGM), rather than a high peak transient load.
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
(3)
(4)
(5)
2
BATTERY
VOLTAGE (V)
OUT PIN FOR AC
INPUT CONDITIONS
(3)
4.2
Regulated to 6 V (5)
4.1
Regulated to 6 V (5)
PACKAGE
QFN – RHL
(2)
ORDERABLE
PART NUMBER
(4)
Reel of 3000
TOP-SIDE
MARKING
BQ24030IRHLRQ1
BQ24030
BQ24031IRHLRQ1
BQ24031
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
When power is applied via the USB pin (PSEL = low), the input voltage is switched straight through to the OUT pin, unless the USB
input current limit is active, and then the OUT pin voltage typically drops to the DPPM-OUT threshold or battery voltage (whichever is
higher).
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
If AC < VO(OUT-REG), the AC is connected to the OUT pin by a P-FET (Q1).
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www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Input voltage
AC (dc voltage with respect to VSS)
–0.3 V to 18 V
USB (dc voltage with respect to VSS)
–0.3 V to 7 V
BAT, CE, DPPM, ACPG, PSEL, OUT, ISET1, ISET2, STAT1,
STAT2, TS, USBPG (all dc voltages with respect to VSS)
–0.3 V to 7 V
LDO (dc voltage with respect to VSS)
–0.3 V to (VO(OUT) + 0.3 V)
TMR
–0.3 V to (VO(LDO) + 0.3 V)
AC
Input current
Output current
3.5 A
USB
1000 mA
OUT
4A
BAT
(2)
–4 A to 3.5 A
Output source current
(in regulation at 3.3-V LDO)
LDO
30 mA
Output sink current
ACPG, STAT1, STAT2, USBPG
15 mA
Storage temperature range, Tstg
–65°C to 150°C
Operating virtual-junction temperature range, TJ
–40°C to 125°C
Lead temperature (soldering, 10 seconds)
(1)
(2)
300°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
Negative current is defined as current flowing into the BAT pin.
RECOMMENDED OPERATING CONDITIONS
From AC input
VCC
Supply voltage
IAC
Input current, AC
IUSB
Input current, USB
TA
Operating ambient temperature
(1)
(2)
(1) (2)
From USB input (1)
MIN
MAX
4.35
16
V
4.35
6
V
2
0.5
–40
85
UNIT
A
°C
VCC is defined as the greater of AC or USB input.
Verify that power dissipation and junction temperatures are within limits at maximum VCC.
DISSIPATION RATINGS
(1)
PACKAGE
TA ≤ 40°C
POWER RATING
DERATING FACTOR
TA > 40°C
θJA
20-pin RHL (1)
1.81 W
21 mW/°C
46.87 °C/W
This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24030-Q1 bq24031-Q1
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bq24030-Q1
bq24031-Q1
SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Bias Currents
ICC(SPLY)
Active supply current, VCC
VVCC > VVCC(min)
1
2
mA
ICC(SLP)
Sleep current (current into
BAT pin)
V(AC) < V(BAT), V(USB) < V(BAT),
2.6 V ≤ VI(BAT) ≤ VO(BAT-REG),
Excludes load on OUT pin
2
5
μA
ICC(AS-STDBY)
AC standby current
VI(AC) ≤ 6 V, Total current into AC pin with chip disabled,
Excludes all loads, CE = low,
After t(CE-HOLDOFF) delay
200
μA
ICC(USB-STDBY)
USB standby current
Total current into USB pin with chip disabled, Excludes
all loads, CE = low,
After t(CE-HOLDOFF) delay
200
μA
ICC(BAT-STDBY)
BAT standby current
Total current into BAT pin with AC and/or USB present
and chip disabled, Excludes all loads (OUT and LDO),
CE = low, After t(CE-HOLDOFF) delay, 0°C ≤ TJ ≤ 85°C (1)
45
60
μA
IIB(BAT)
Charge done current, BAT
Charge finished, AC or USB supplying the load
1
5
μA
6.4
6.8
V
High AC Cutoff Mode
VCUT-OFF
Input AC cutoff voltage,
bq24035
VI(AC) > 6.8 V, AC FET (Q1) turns off, USB FET (Q3)
turns on if USB power present, otherwise BAT FET (Q2)
turns on
Output regulation voltage
Active only if AC or USB is present,
VI(OUT) ≥ VO(LDO) + (IO(LDO) × RDS(on))
6.1
LDO Output
VO(LDO)
3.3
Regulation accuracy (2)
IO(LDO)
Output current
RDS(on)
On resistance
C(OUT)
(3)
–5
V
5
%
20
mA
50
Ω
1
μF
6.0
6.3
V
OUT to LDO
Output capacitance
OUT Pin – Voltage Regulation (4)
VO(OUT-REG)
Output regulation voltage
VI(AC) ≥ 6 V + VDO
OUT Pin – DPPM Regulation
V(DPPM-SET)
DPPM set point (5)
VDPPM-SET < VOUT
2.6
5
V
I(DPPM-SET)
DPPM current source
AC or USB present
95
100
105
μA
SF
DPPM scale factor
V(DPPM-REG) = V(DPPM-SET) × SF
1.139
1.150
1.162
VI(AC) ≥ VCC(min), PSEL = high, II(AC) = 1 A,
(IO(OUT) + IO(BAT)), or no AC
300
475
VI(USB) ≥ VCC(min), PSEL = low, ISET2 = high,
II(USB) = 0.4 A, (IO(OUT) + IO(BAT)), or no AC
140
180
VI(USB) ≥ VCC(min), PSEL = low, ISET2 = low,
II(USB) = 0.08 A, (IO(OUT) + IO(BAT))
28
36
VI(BAT) ≥ 3 V, II(BAT)= 1 A, VCC < VI(BAT)
40
100
OUT Pin – FET (Q1, Q3, and Q2) Dropout Voltage (RDSon)
AC to OUT dropout
voltage (6)
V(ACDO)
V(USBDO)
V(BATDO)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
(7)
USB to OUT dropout
voltage
BAT to OUT dropout
voltage (discharging)
mV
mV
mV
This includes the quiescent current for the integrated LDO.
In standby mode (CE low) the accuracy is ±10%.
LDO output capacitor is not required, but one with a value of 0.1 μF is recommended.
When power is applied to the USB pin and PSEL is low, the USB input is switched straight through to the OUT pin (not regulated). This
voltage may drop to the DPPM-OUT threshold or battery voltage (which ever is higher) if the USB input current limit is active.
V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).
VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the
increase in current.
RDS(on) of USB FET Q3 is calculated by: (VUSB – VOUT) / (IOUT + IBAT) when II(USB) ≤ II(USB-MIN) (FET fully on, not in regulation).
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www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUT Pin – Battery Supplement Mode
VBSUP1
Enter battery supplement
mode (battery supplements
VI(BAT) > 2 V
OUT current in the
presence of input source
VBSUP2
Exit battery supplement
mode
VI(OUT) ≤
VI(BAT)
– 60 mV
V
VI(OUT) ≥
VI(BAT)
– 20 mV
VI(BAT) > 2 V
V
OUT Pin – Short Circuit
IOSH1
BAT to OUT short-circuit
recovery
Current source between BAT to OUT for short-circuit
recovery to VI(OUT) ≤ VI(BAT) – 200 mV
RSHAC
AC to OUT short-circuit
limit
RSHVSB
USB to OUT short-circuit
limit
10
mA
VI(OUT) ≤ 1 V
500
Ω
VI(OUT) ≤ 1 V
500
Ω
BAT Pin Charging – Precharge
V(LOWV)
Precharge to fast-charge
transition threshold
Voltage on BAT
TDGL(F)
Deglitch time for
fast-charge to precharge
transition (8)
tFALL = 100 ns, 10-mV overdrive,
VI(BAT) decreasing below threshold
IO(PRECHG)
Precharge range
1 V < VI(BAT) < V(LOWV), t < t(PRECHG),
IO(PRECHG) = (K(SET) × V(PRECHG))/RSET
V(PRECHG)
Precharge set voltage
1 V < VI(BAT) < V(LOWV), t < t(PRECHG)
230
100
2.9
3
3.1
22.5
10
V
ms
150
mA
250
270
mV
1000
1500
mA
BAT Pin Charging – Current Regulation
IO(BAT)
AC battery-charge
current (9)
VI(BAT) > V(LOWV), VI(OUT) – VI(BAT) > V(DO-MAX),
PSEL = high IOUT(BAT) = (K(SET) × V(SET)/RSET),
VI(OUT) > VO(OUT-REG) + V(DO-MAX)
RPBAT
BAT to OUT pullup
VI(BAT)< 1 V
1000
Ω
RPOUT
AC to OUT and USB to
OUT short-circuit pullup
VI(OUT) < 1 V
500
Ω
V(SET)
Battery charge current set
voltage (10)
Voltage on ISET1, VVCC ≥ 4.35 V,
VI(OUT) – VI(BAT) > V(DO-MAX), VI(BAT) > V(LOWV)
K(SET)
Charge current set factor,
BAT
100 mA ≤ IO(BAT) ≤ 1 A
10 mA ≤ IO(BAT) ≤ 100 mA
(11)
2.475
2.500
2.525
400
425
450
300
450
600
V
USB Pin Input Current Regulation
I(USB)
USB input current
VI(BAT) > V(LOWV), VI(USB) – VI(BAT) > V(DO-MAX),
ISET2 = low, PSEL = low, or no AC (12)
VI(BAT) > V(LOWV), VI(USB) – VI(BAT) > V(DO-MAX),
ISET2 = high, PSEL = low, or no AC (13)
100
mA
400
500
BAT Pin Charging Voltage Regulation, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤ 1 A
VO(BAT-REG)
Battery charge voltage
Battery charge voltage
regulation accuracy
(8)
(9)
(10)
(11)
(12)
(13)
bq24030
4.2
bg24031
4.1
TA = 25°C
V
–0.5
0.5
–1
1
%
All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.
For half-charge rate, V(SET) is 1.25 V ± 25 mV for bq24032A/38 only.
Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.
With the PSEL= low, the bqTINY III series defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY III series charges from the
AC input at the USB charge rate. In this configuration, the specification is 80 mA (min) and 100 mA (max).
With the PSEL= low, the bqTINY III series defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY III series charges from the
AC input at the USB charge rate. In this configuration, the specification is 400 mA (min) and 500 mA (max).
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24030-Q1 bq24031-Q1
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bq24030-Q1
bq24031-Q1
SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
150
mA
Charge Termination Detection
I(TERM)
Charge termination
detection range
VI(BAT) < V(RCH), I(TERM) = (K(SET) × V(TERM))/RSET
V(TERM-AC)
AC-charge termination
detection voltage,
measured on ISET1
VI(BAT) > V(RCH) , PSEL = high, ACPG = low
V(TAPER-USB)
USB-charge termination
detection voltage,
measured on ISET1
VI(BAT) > V(RCH),
PSEL = low or PSEL = high and ACPG = high
TDGL(TERM)
Deglitch time for
termination detection
tFALL = 100 ns, 10-mV overdrive,
ICHG increasing above or decreasing below threshold
10
235
250
265
mV
95
100
130
mV
22.5
ms
Temperature Sense Comparators
VLTF
High voltage threshold
Temperature fault at V(TS) > VLTF
2.465
2.500
2.535
V
VHTF
Low voltage threshold
Temperature fault at V(TS) < VHTF
0.485
0.500
0.515
V
ITS
Temperature sense current
source
94
100
106
μA
TDGL(TF)
Deglitch time for
temperature fault
detection (14)
R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing above
and below; 100-ns fall time, 10-mV overdrive
22.5
ms
Battery Recharge Threshold
VRCH
Recharge threshold
voltage
TDGL(RCH)
Deglitch time for recharge
detection (14)
VO(BAT-REG)
– 0.075
R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing below
threshold, 100-ns fall time, 10-mV overdrive
VO(BAT-REG)
– 0.100
VO(BAT-REG)
– 0.125
22.5
V
ms
STAT1, STAT2. ACPG, USBPG Open-Drain (OD) Outputs (15)
VOL
Low-level output saturation
voltage
ILKG
Input leakage current
IOL = 5 mA, External pullup resistor ≥ 1 kΩ required
1
0.25
V
5
μA
ISET2, CE Inputs
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
IIL
Low-level input current, CE
–1
IIH
High-level input current,
CE
IIL
Low-level input current,
ISET2
VISET2 = 0 V
IIH
High-level input current,
ISET2
VISET2 = VCC
IIL1
Low-level input current
IIH1
High-level input current
t(CE-HLDOFF)
Holdoff time, CE
CE going low only
VIL
Low-level input voltage
Falling high→low, 280 kΩ ± 10% applied when low
VIH
High-level input voltage
Input RPSEL sets external hysteresis
IIL
Low-level input current,
PSEL
IIH
High-level input current,
PSEL
0.4
V
μA
1
μA
μA
–20
6
3.3
40
μA
1
μA
15
μA
6.2
ms
PSEL Input
0.975
VIL + 0.01
–1
1
1.025
V
VIL + 0.024
V
μA
μA
(14) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
(15) See Charger Sleep mode for ACPG (VCC = VAC) and USBPG (VCC = VUSB) specifications.
6
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www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.313
0.360
0.414
s/Ω
100
kΩ
Timers
K(TMR)
R(TMR)
Timer set factor
(16)
t(CHG) = K(TMR) × R(TMR)
External resistor limits
t(PRECHG)
Precharge timer
I(FAULT)
Timer fault recovery pullup
from OUT to BAT
30
0.09 t(CHG)
0.10 t(CHG)
0.11 t(CHG)
1
s
kΩ
Charger Sleep Thresholds (ACPG and USBPG Thresholds, Low to Power Good)
V(SLPENT)
(17)
Sleep-mode entry
threshold
V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG), No t(BOOT-UP) delay
V(SLPEXIT)
(17)
Sleep-mode exit threshold
V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG), No t(BOOT-UP) delay
Deglitch time for sleep
mode (18)
R(TMR) = 50 kΩ, V(AC) or V(USB) or decreasing below
threshold, 100-ns fall time, 10-mV overdrive
t(DEGL)
VVCC ≤
VI(BAT)
+ 125 mV
VVCC ≥
VI(BAT)
+ 190 mV
V
V
22.5
ms
Start-Up Control and USB Boot-Up
t(BOOT-UP)
Boot-up time
On the first application of USB input power or AC input
with PSEL low
120
150
180
ms
50
μs
100
μs
100
μs
Switching Power Source Timing
tSW-BAT
Switching power source
from inputs (AC or USB) to
battery
Only AC power or USB power applied,
Measure from [xxPG: low to high to I(xx) > 5 mA],
xx = AC or USB I(OUT) = 100 mA, RTRM = 50 K
tSW-AC/USB
Switching from AC to USB,
or, USB to AC by input
source removal. (19)
Measure from
I(AC) < 5 mA to I(USB) > 5 mA or
I(USB) < 5 mA to I(AC) > 5 mA,
I(OUT) = 100 mA, RTMR = 50 kΩ,
ISET2 = high, ROUT > 15 Ω, VDPPM = 2.5 V
tSW-PSEL
Switching from AC to USB,
or USB to AC by toggling
PSEL
Measure from
I(AC) < 5 mA to I(USB) > 5 mA or
I(USB) < 5 mA to I(AC) > 5 mA,
I(OUT) = 100 mA, RTMR = 50 kΩ,
ISET2 = high, ROUT > 15 Ω, VDPPM = 2.5 V
50
Thermal Shutdown Regulation (20)
T(SHTDWN)
TJ(REG)
Temperature trip
TJ (Q1 and Q3 only)
155
°C
Thermal hysteresis
TJ (Q1 and Q3 only)
30
°C
Temperature regulation
limit
TJ (Q2)
115
Undervoltage lockout
Decreasing VCC
2.45
135
°C
UVLO
V(UVLO)
Hysteresis
2.50
2.65
27
V
mV
(16) To disable the fast-charge safety timer and charge termination, tie TMR to the LDO pin. Tying the TMR pin high changes the timing
resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed spectification. The TMR
pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become
active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by
the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum
time extension of 2.5 V ÷ 0.8 V × 100 = 310%.
(17) The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBPG = open drain).
(18) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
(19) The power handoff is implemented once the PG pin goes high (removed sources PG), which is when the removed source drops to the
battery voltage. If the battery voltage is critically low, the system may lose power unless the system takes control of the PSEL pin and
switches to the available power source prior to shutdown. The USB source often has less current available; so, the system may have to
reduce its load when switching from AC to USB.
(20) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
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DEVICE INFORMATION
USB
LDO
RHL PACKAGE
(TOP VIEW)
USBPG
STAT1
2
STAT2
3
18
ACPG
AC
4
17
OUT
BAT
5
16
OUT
BAT
6
15
OUT
ISET2
7
14
TMR
PSEL
8
13
DPPM
9 10
ISET1
CE
20 19
11 12
TS
VSS
1
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AC
4
I
Charge input voltage from AC adapter
ACPG
18
O
AC power-good status output (open drain)
BAT
5, 6
I/O
Battery input and output.
CE
9
I
Chip enable input (active high)
DPPM
13
I
Dynamic power-path management set point (account for scale factor)
ISET1
10
I/O
ISET2
7
I
Charge current set point for USB port (high = 500 mA, low = 100 mA)
LDO
1
O
3.3-V LDO regulator
OUT
15, 16, 17
O
Output terminal to the system
PSEL
8
I
Power source selection input (low for USB, high for AC)
STAT1
2
O
Charge status output 1 (open drain)
STAT2
3
O
Charge status output 2 (open drain)
TMR
14
I/O
Timer program input programmed by resistor. Disable fast-charge safety timer and termination by tying
TMR to LDO.
TS
12
I/O
Temperature sense input
USB
20
I
USB charge input voltage
USBPG
19
O
USB power-good status output (open-drain)
VSS
11
–
Ground input (the thermal pad on the underside of the package) There is an internal electrical connection
between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be
connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as
the primary ground input for the device. VSS pin must be connected to ground at all times.
8
Charge current set point for AC input and precharge and termination set point for both AC and USB
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FUNCTIONAL BLOCK DIAGRAM
Short-Circuit Recovery
500 W
BAT
Short-Circuit
Recovery
USB
Charge
Enable
100 mA /
500 mA
AC
VO(OUT)
OUT
VO(LDO)
Q1
1 kW
3.3-V LDO
Fault
Recovery
LDO
10 mA
VSET
500 W
+
VIO(AC)
AC Charge
Enable
Short-Circuit
Recovery
VI(IUSB- SNS)
VO(OUT)
Q2
Q3
+
VI(BAT)
BAT
VO(OUT- REG)
VI(IUSB- SNS)
USB
VI(ISET1)
ISET1
Reference, Bias, and UVLO
VI(IUSB- SNS)
UVLO
TMR
Oscillator
VI(BAT)
VI(BAT)
+
100 mA / 500 mA
VSET
VO(BAT- REG)
USB
Charge
Enable
+
VO(BAT- REG)
VI(ISET1)
VO(OUT)
DPPM
+
DPPM
I(DPPM) Scaling
BAT
Charge
Enable
VSET
VDPPM
TJ
+
+
DisableSleep
VI(BAT)
200 mV
TS
+
I(TS)
Thermal
Shutdown
+
VO(OUT)
TJ(REG)
V(HTF)
60 mV
+
+
1V
+
Fast Precharge
Suspend
+
1V
V(LTF)
280 kΩ
Power Source Selection
USB Charge Enable
PSEL
AC Charge Enable
CE
BAT Charge Enable
VO(BAT- REG)
Recharge
VBAT
Precharge
VBAT
Charge
Control
Timer
and
Display
Logic
500 mA / 100 mA
Fast Precharge
1C - 500 mA
C/S - 100 mA
ISET2
ACPG
V(SET)
VI(ISET1)
Term
USBPG
STAT1
Sleep (AC)
VBAT
VAC
VSS
STAT2
Sleep (USB)
VBAT
VUSB
*
Signal deglitched
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FUNCTIONAL DESCRIPTION
Charge Control
The bqTINY III series supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable
devices. See a typical charge profile, application circuit, and an operational flow chart in Figure 1 through
Figure 4, respectively.
Pre-Conditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Charge
Voltage
Minimum
Charge
Voltage
Charge
Complete
Charge
Current
Pre−
Conditioning
and Term
Detect
UDG−04087
Figure 1. Charge Profile
AC Adapter
VDC
4
AC
LDO
1
10 µF
GND
10 µF
OUT 15
10 µF
OUT 16
D+
D–
VBUS
20 USB
10 µF
14 TMR
RTMR
System
OUT 17
Battery Pack
PACK+
BAT
5
BAT
6
+
1 µF
7 ISET2
PACK–
GND
USB Port
2
STAT1
3
STAT2
19 USBPG
TS 12
18 ACPG
DPPM 13
9
CE
ISET1 10
8
PSEL
TEMP
RSET
RDPPM
VSS 11
Control and
Status Signals
Figure 2. Typical Application Circuit
10
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POR
SLEEP MODE
Vcc > V I(OUT)
checked at all
times?
No
Indicate SLEEP
MODE
Yes
V I(BAT) < V (LOWV)
Yes
Regulate
IO(PRECHG)
Reset and Start
t(PRECHG)timer
Indicate Charge−
In−Progress
?
No
Reset all timers,
Start t (CHG) timer
Regulate Current
or Voltage
Indicate Charge−
In−Progress
No
V I(OUT) V (RCH)
?
Turn off charge
Yes
Yes
Indicate DONE
Disable I (FAULT)
No
current
V I(OUT) < V (RCH)
?
Figure 3. Charge Control Operational Flow Chart
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Autonomous Power Source Selection, PSEL Control Pin
The PSEL pin selects the priority of the input sources (high = AC, low = USB). If that primary source is not
available (based on ACPG, USBPG signal), the secondary source is used. If neither input source is available,
then the battery is selected as the source. With the PSEL input high, the bqTINY III series attempts to charge
from the AC input. If the AC input is not present, then USB is selected. If both inputs are available, the AC
adapter has priority. With the PSEL input low, the bqTINY III series defaults to USB charging. If USB input is
grounded, then the bqTINY III series charges from the AC input at the USB charge rate (as selected by ISET2).
This feature can be used in system where AC and USB power source selection is done elsewhere. The PSEL
function is summarized in Table 1.
Table 1. Power Source Selection Function Summary
PSEL STATE
AC
MAXIMUM
CHARGE RATE
(1)
SYSTEM
POWER
SOURCE
USB BOOT-UP
FEATURE
Present (2)
Absent
AC
ISET2
AC
Enabled
Absent (3)
Present
USB
ISET2
USB
Enabled
Present
Present
USB
ISET2
USB
Enabled
Absent
Absent
N/A
N/A
Battery
Disabled
Present
Absent
AC
ISET1
AC
Disabled
Low
High
(1)
(2)
(3)
CHARGE
SOURCE
USB
Absent
Present
USB
ISET2
USB
Disabled
Present
Present
AC
ISET1
AC
Disabled
Absent
Absent
N/A
N/A
Battery
Disabled
Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and IOUT system load.
Present is defined as input being at a higher voltage than the BAT voltage (sources power good is low).
AC Absent is defined as AC input not present (ACPG is high) or Q1 turned off due to overvoltage in the bq24035.
Boot-Up Sequence
In order to facilitate the system start-up and USB enumeration, the bqTINY III series offers a proprietary boot-up
sequence. On the first application of power to the bqTINY III series, this feature enables the 100-mA USB charge
rate for a period of approximately 150 ms (t(BOOT-UP)) ignoring the ISET2 and CE inputs setting. At the end of this
period, the bqTINY III series implements CE and ISET2 inputs settings. Table 1 indicates when this feature is
enabled (see Figure 13).
Power-Path Management
The bqTINY III series powers the system while independently charging the battery. This features reduces the
charge and discharge cycles on the battery, allows for proper charge termination, and allows the system to run
with an absent or defective battery pack. This feature gives the system priority on input power, allowing the
system to power up with a deeply discharged battery pack. This feature works as follows (note that PSEL is
assumed high for this discussion).
AC Adapter
bq2403x
(See Note 2)
AC
VDC
USB Port
D+
D–
VBUS
GND
OUT
System
Q1
USB
40 mW
BAT
PACK+
+
PACK–
GND
Q3
Q2
Figure 4. Power-Path Management
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Case 1: AC Mode (PSEL = High)
System Power
In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see
Figure 4). For bq24030/31, Q1 acts as a switch as long as the AC input remains at or below 6 V (VO(OUT-REG)).
Once the AC voltage goes above 6 V, Q1 starts regulating the output voltage at 6 V. For bq24035, once the AC
voltage goes above VCUT-OFF (~6.4 V), Q1 turns off. For bq24032A/38, the output is regulated at 4.4 V from the
AC input. Note that switch Q3 is turned off for both devices. If the system load exceeds the capacity of the
supply, the output voltage drops down to the battery's voltage.
Charge Control
When AC is present, the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.
Dynamic Power-Path Management (DPPM)
This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,
or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V(DPPM-SET) × SF, due to a
limited amount of input current, then the battery charging current is reduced until the output voltage stops
dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current and
the battery is charged with the remaining current. No active control limits the current to the system; therefore, if
the system demands more current than the input can provide, the output voltage drops just below the battery
voltage and Q2 turns on which supplements the input current to the system. DPPM has three main advantages.
1. DPPM allows the designer to select a lower-power wall adapter, if the average system load is moderate
compared to its peak power. For example, if the peak system load is 1.75 A, average system load is 0.5 A,
and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A adapter
could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of
1.25 A, the smaller adapter’s voltage drops until the output voltage reaches the DPPM regulation voltage
threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets
its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system
load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value.
2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the
system current plus charge current exceed the supply’s current limit, then the output is pulled down to the
battery. Linear chargers dissipate the unused power (VIN – VOUT) × ILOAD. The current remains high (at
current limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is
less (VIN – V(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is
the same for both cases. The advantages include less power dissipation, lower system temperature, and
better overall efficiency.
3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by
reducing the noncritical charging load while maintaining the maximum power output of the adapter.
Note that the DPPM voltage, V(DPPM-REG), is programmed as follows:
V (DPPM−REG) + I (DPPM) R(DPPM) SF
(1)
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly
proportional to the programmed charging current. When the programmed charging current is reduced, due to
DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the
safety time. In normal operation, V(TMR) = 2.5 V; when the clock is slowed the voltage V(TMR) is reduced. For
example, if V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value (see
Figure 5 through Figure 8).
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Case 2: USB (PSEL = Low)
System Power
In this case, the system load is powered directly from the USB port through the internal switch Q3 (see
Figure 14). Note in this case, Q3 regulates the total current to the 100-mA or 500-mA level, as selected on the
ISET2 input. Switch Q1 is turned off in this mode. If the system and battery load is less than the selected
regulated limit, then Q3 is fully on and VOUT is approximately (V(USB) – V(USB-DO)). The systems power
management is responsible for keeping its system load below the USB current level selected (if the battery is
critically low or missing). Otherwise, the output drops to the battery voltage; therefore, the system should have a
low power mode for USB power application. The DPPM feature keeps the output from dropping below its
programmed threshold, due to the battery charging current, by reducing the charging current.
Charge Control
When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin
(0.1/0.5 A). The charge current to the battery is set by the ISET1 resistor (typically >0.5 A). Because the charge
current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage
or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until
VOUT stops dropping. If VOUT drops to the battery voltage, the battery is able to supplement the input current to
the system.
Dynamic Power-Path Management (DPPM)
The theory of operation is the same as described in Case 1, except that Q3 restricts the amount of input current
delivered to the output and battery instead of the input supply.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V (DPPM−REG) + I (DPPM) R(DPPM) SF
(2)
and
V (DPPM−REG) + V(DPPM−SET)
(3)
SF
where
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
Feature Plots
The voltage on the DPPM pin, V(DPPM-SET) is determined by the external resistor, R(DPPM). The output voltage
(V(OUT)) that the DPPM function regulates is V(DPPM-REG). For example, if R(DPPM) is 33 kΩ, then the V(DPPM-SET)
voltage on the DPPM pin is 3.3 V (I(DPPM-SET) = 100 μA, typical). The DPPM function attempts to keep V(OUT) from
dropping below the V(DPPM-REG) voltage, and is 3.795 V for this example (SF = 1.15, typical).
Figure 5 illustrates DPPM and battery supplement modes as the output current (IOUT) is increased, channel 1
(CH1) VAC = 5.4 V, channel 2 (CH2) VOUT, channel 3 (CH3) IOUT = 0 to 2.2 A to 0 A, channel 4 (CH4)
VBAT = 3.5 V, I(PGM-CHG) = 1 A. In typical operation, VOUT = 4.4 Vreg, through an AC adapter overload condition
and recovery. The AC input is set for ~5.1 V (1.5-A current limit), I(CHG) = 1 A, V(DPPM-SET) = 3.7 V,
V(DPPM-OUT) = 1.15 × V(DPPM-SET) = 4.26 V, VBAT = 3.5 V, PSEL = H, and USB input is not connected. The output
load is increased from 0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the IOUT load reaches
0.5 A, along with the 1-A charge current, the adapter starts to current limit, the output voltage drops to the
DPPM-OUT threshold of 4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout
voltage of the AC FET. The battery charge current is then adjusted back as necessary to keep the output voltage
from falling any further. Once the output load current exceeds the input current, the battery has to supplement
the excess current and the output voltage falls just below the battery voltage by the dropout voltage of the battery
FET. This is the battery supplement mode. When the output load current is reduced, the operation described is
reversed as shown. If V(DPPM-REG) was set below the battery voltage, during input current limiting, the output falls
directly to the battery's voltage.
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Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is
observed. If the output load exceeds the available USB current, the output instantly goes into the battery
supplement mode.
VAC
VOUT
VOUT Regulated at 4.4 V
VDPPM - OUT = 4.26 V, DPPM Mode
VOUT ≈ VBAT, BAT Supplement Mode
ICHG
IOUT
Figure 5. DPPM and Battery Supplement Modes
Figure 6 illustrates when PSEL is toggled low for 500 μs. Power transfers from AC to USB to AC [channel 1
(CH1) VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4
(CH4) VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. When the PSEL goes low (first division), the AC FET opens, and the
output falls until the USB FET turns on. Turning off the active source before turning on the replacement source is
referred to as break-before-make switching. The rate of discharge on the output is a function of system
capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the fourth
division, the output has reached steady-state operation at V(DPPM-REG) (charge current has been reduced due to
the limited USB input current). At the sixth division, the PSEL goes high and the USB FET turns off followed by
the AC FET turning on. The output returns to its regulated value, and the battery returns to its programmed
current level.
Break Before Make
VAC
VUSB
VOUT
VBAT
System Capacitance
Powering System
DPPM Mode
USB is Charging System Capacitance
Hi
PSEL
Low
Figure 6. Toggle PSEL Low
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Figure 7 illustrates when AC is removed, power transfers to USB [PSEL = H (AC primary source), channel 1
(CH1) VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4
(CH4) VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. The power transfer from AC to USB only takes place after the primary
source (AC) is considered bad (too low, VAC ≤ VBAT + 125 mV) indicated by the ACPG FET turning off (open
drain not shown). Thus, the output drops down to the battery voltage before the USB source is connected (sixth
division). The output starts to recover when the USB FET starts to limit the input current (seventh division) and
the output drops to the V(DPPM-REG) threshold.
USB Input Current Limit Is Reached
DPPM Mode
VUSB
VOUT
VAC
VBAT
AC Declared Not Present, USB Power Applied
Figure 7. Remove AC – Power Transfer to USB
Figure 8 illustrates when AC (low battery) is removed, power transfers to USB [PSEL = H, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT = 2.25 V, and I(PGM-CHG) = 1 A]. This figure is the same as when the battery has more capacity. Note that
the output drops to the battery voltage before switching to USB power. A resistor divider between AC and ground
tied to PSEL can toggle the power transfer earlier, if necessary.
VUSB
VOUT
DPPM Mode
VAC
VBAT
Figure 8. Remove AC (Low Battery) – Power Transfer to USB
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Figure 9 illustrates that when AC is applied, power transfers from USB to AC [PSEL = H, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. The charger is set for AC priority but is running off USB until AC is applied.
When AC is applied (first division) and the USB FET opens (second division), the AC FET closes (third division)
and the output recovers from the DPPM threshold (eighth division).
VAC
VUSB
VOUT
VBAT
Break Before Make
VOUT Returns to Regulation
Charging Current Returns to Ipgm
DPPM Mode
Figure 9. Apply AC – Power Transfer From USB to AC
Figure 10 illustrates when USB is removed, power transfers from USB to AC [PSEL = L, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT = 3.5 V, and I(PGM-CHG) = 1 A]. The USB source is removed (second division) and the output drops to the
battery voltage (declares USB bad, fourth division) and switches to AC (in USB mode) and recovers similar to the
figure that is switching to USB power. This power transfer occurs with PSEL low, which means that the AC input
is regulated as if it were a USB.
AC is Applied (USB Mode)
VAC
AC Hits USB (ISET2) limit
DPPM Mode
VOUT
VUSB
VBAT
USB Declared not Present
Figure 10. Remove USB – Power Transfer From USB to AC
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Figure 11 illustrates when the battery is absent, power transfers to USB [PSEL = H, channel 1 (CH1)
VAC = 5.4 V, channel 2 (CH2) V(USB) = 5 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A, channel 4 (CH4)
VBAT, I(PGM-CHG) = 1 A]. Note the saw-tooth waveform due to cycling between charge done and refresh (new
charge).
VAC
VUSB
VOUT
VBAT
BAT PIN Capacitance Discharging to Refresh Threshold
Charging (Step) Followed by Charge Done
Figure 11. Battery Absent – Power Transfer to USB
Figure 12 illustrates when a battery is inserted for power up [channel 1 (CH1) VAC = 0 V, channel 2 (CH2)
VUSB = 0 V, channel 3 (CH3) VOUT, output current IOUT = 0.25 A for VOUT > 2 V, channel 4 (CH4) VBAT = 3.5 V,
and C(DPPM) = 0 pF]. When there are no power sources and the battery is inserted, the output tracks the battery
voltage if there is no load ( 1 V × 500 Ω/ (VIN – VOUT)} such that the pullup
resistor is able to lift the output voltage above 1 V, for the input FETs to be turned back on.
If the output drops 200 mV below the battery voltage, the battery FET is considered in short circuit and it turns
off. To recover from this state, there is a 10-mA ± 8-mA current source from the battery to the output. Once the
output load is reduced, such that the current source can pick up the output within 200 mV of the battery, the FET
turns back on (As Vout increases in voltage the current source's drive drops toward 2 mA).
If the short is removed and the minimum system load is still too large [R < (VBat – 200 mV / 2 mA)], the
short-circuit protection can be temporarily defeated. The battery short-circuit protection can be disabled
(recommended only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V
for a few microseconds should be enough to recover.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24030-Q1 bq24031-Q1
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This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the
BAT input voltage rises much faster than the OUT voltage (VOUT < VBAT – 200 mV), with most any capacitive load
on the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and
ground slows the VDPPM rise time during power up, and delays the short-circuit protection. Too large a
capacitance on this pin (too much of a delay) could allow too-high currents if the output were shorted to ground.
The recommended capacitance is 1 nF to 10 nF. The VDPPM rise time is a function of the 100-µA DPPM current
source, the DPPM resistor, and the capacitor added.
24
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Product Folder Link(s): bq24030-Q1 bq24031-Q1
bq24030-Q1
bq24031-Q1
www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009
APPLICATION INFORMATION
Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A
0.1-μF ceramic capacitor, placed in close proximity to AC and USB to VSS pins, works well. In some applications
depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-μF
ceramic capacitor to each input.
The bqTINY III series only requires a small output capacitor for loop stability. A 0.1-μF ceramic capacitor placed
between the OUT and VSS pin is usually sufficient.
The integrated LDO requires a maximum 1-μF ceramic capacitor on its output. The output does not require a
capacitor for a steady-state load but 0.1-μF minimum capacitance is recommended.
It is recommended to install a minimum 33-μF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).
Thermal Considerations
The bqTINY III series is packaged in a thermally enhanced MLP package. The package includes a QFN thermal
pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB
design guidelines for this package are provided in the application report QFN/SON PCB Attachment (SLUA271).
The power pad should be tied to the VSS plane. The most common measure of package thermal performance is
thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the package
surface (ambient).
The mathematical expression for θJA is:
T * TA
q JA + J
P
(10)
where
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 11:
P + ƪǒV IN * V OUTǓ
ǒI OUT ) I BATǓƫ ) ƪǒV OUT * VBATǓ
ǒIBATǓƫ
(11)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above V(LOWV)). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the
minimum battery voltage because the system board and charging device does not have time to reach a
maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This
theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage
and charger's power-pad temperature.
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24030-Q1 bq24031-Q1
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SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com
PCB Layout Considerations
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from input terminals to VSS and the output filter
capacitors from OUT to VSS should be placed as close as possible to the bqTINY III series, with short trace
runs to both signal and VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high-current charge paths into AC and USB and from the BAT and OUT pins must be sized appropriately
for the maximum charge current in order to avoid voltage drops in these traces.
• The bqTINY III series is packaged in a thermally enhanced MLP package. The package includes a QFN
thermal pad to provide an effective thermal contact between the device and the printed-circuit board. Full
PCB design guidelines for this package are provided in the application report QFN/SON PCB Attachment
(SLUA271).
26
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24030-Q1 bq24031-Q1
bq24030-Q1
bq24031-Q1
www.ti.com.................................................................................................................................................... SLUS793B – APRIL 2008 – REVISED OCTOBER 2009
NOTE: Page numbers for previous revisions may be different from current version.
Changes from Revision A (December 2008) to Revision B ........................................................................................... Page
•
Changed t(CE-HLDOFF) spec from 4 ms MIN and 6 ms MAX .................................................................................................... 6
•
Changed "safety timer" to "fast-charge safety timer" and added to footnote explanation for R(TMR). ................................... 7
•
Changed "safety-timer" to "fast-charge safety timer" for TMR Description. ......................................................................... 8
•
Changed text string "all safety timers" to "the fast-charge safety timer (does not disable or reset the pre-charge
safety timer)" in the Charge Timer Operation paragraph. .................................................................................................. 21
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24030-Q1 bq24031-Q1
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27
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24031IRHLRQ1
ACTIVE
VQFN
RHL
20
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
BQ24031
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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