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bq24091, bq24090
bq24092, bq24093, bq24095
SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
bq2409x 1A, Single-Input, Single Cell Li-Ion and Li-Pol Battery Charger
1 Features
2 Applications
•
•
•
•
•
1
•
•
Charging
– 1% Charge Voltage Accuracy
– 10% Charge Current Accuracy
– Pin Selectable USB 100-mA and 500-mA
Maximum Input Current Limit
– Programmable Termination and Precharge
Threshold
Protection
– 6.6 V Over-Voltage Protection
– Input Voltage Dynamic Power Management
– 125°C Thermal Regulation; 150°C Thermal
Shutdown Protection
– OUT Short-Circuit Protection and ISET Short
Detection
– Operation Over JEITA Range via Battery
NTC – ½ Fast-Charge-Current at Cold, 4.06V
at Hot, bq24092/3
– Fixed 10-Hour Safety Timer
System
– Automatic Termination and Timer Disable
Mode (TTDM) for Absent Battery Pack With
Thermistor
– Status Indication – Charging/Done
– Available in Small 10-Pin MSOP Package
Smart Phones
PDAs
MP3 Players
Low-Power Handheld Devices
3 Description
The bq2409x series of devices are highly integrated
Li-ion and Li-Pol linear chargers devices targeted at
space-limited portable applications. The devices
operate from either a USB port or AC adapter. The
high input voltage range with input overvoltage
protection supports low-cost unregulated adapters.
The bq2409x has a single power output that charges
the battery. A system load can be placed in parallel
with the battery as long as the average system load
does not keep the battery from charging fully during
the 10-hour safety timer.
The battery is charged in three phases: conditioning,
constant current and constant voltage. In all charge
phases, an internal control loop monitors the IC
junction temperature and reduces the charge current
if an internal temperature threshold is exceeded.
Device Information(1)
PART NUMBER
bq2409x
PACKAGE
BODY SIZE (NOM)
HVSSOP (10)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
1.5kW
bq2409x
Adaptor
1 IN
DC+
OUT 10
1.5kW
GND
1mF
1kW
2 ISET
TS 9
3 VSS
CHG 8
System Load
Battery Pack
++
1mF
4 PRETERM ISET2 7
OR
5 PG
NC 6
VDD
2kW
TTDM
USB Port
ISET/100/500mA
VBUS
GND
GND
D+
D+
D-
Disconnect after Detection
D-
Host
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24091, bq24090
bq24092, bq24093, bq24095
SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
1
1
1
2
4
4
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions ...................... 6
Thermal Information .................................................. 6
Dissipation Ratings .................................................. 6
Electrical Characteristics........................................... 6
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 22
10 Application and Implementation........................ 25
10.1 Application Information.......................................... 25
10.2 Typical Application ................................................ 25
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 28
12.3 Thermal Considerations ........................................ 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
14 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
Changes from Revision F (December 2014) to Revision G
•
Page
Changed bq24095 VO(REG) value From: 4.20 V To: 4.35 V in the Device Options table ....................................................... 4
Changes from Revision E (September 2013) to Revision F
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision D (December 2012) to Revision E
•
Page
Deleted the MARKING column from the ORDERING INFORMATION table, and added table note 1.................................. 4
Changes from Revision C (May 2012) to Revision D
Page
•
Added bq24095 to the ORDERING INFORMATION table..................................................................................................... 4
•
Changed bq24090/2 to bq24090/2/5 for TS pin description in Pin Functions table. .............................................................. 5
•
Changed the KISET entry in the Elect Characteristics table .................................................................................................... 7
•
Deleted " Line Regulation" typical characteristics graph ..................................................................................................... 11
•
Changed "Current Regulation Over Temperature" graph to "Load Regulation - bq24095" graph....................................... 11
Changes from Revision B (June 2010) to Revision C
•
2
Page
Changed all instances of Li-ion To: Li-ion and Li-Pol............................................................................................................. 1
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bq24092, bq24093, bq24095
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
Changes from Revision A (February 2010) to Revision B
Page
•
Changed the device number on the front page circuit From: bq24090 To: bq2409x ............................................................ 1
•
Changed the ORDERING INFORMATION table Marking column From: Product Preview To: bq24092 and bq24093........ 4
Changes from Original (January 2010) to Revision A
Page
•
Changed VDO(IN-OUT), MAX value From: 500 mV To: 520 mV in the Elect Characteristics table ........................................... 7
•
Changed IPRE-TERM MAX value From: 79 µA to 81µA in the Elect Characteristics table ......................................................... 8
•
Changed VCLAMP(TS) MIN value From: 1900 mV to 1800 mV in the Elect Characteristics table ............................................. 9
Copyright © 2010–2015, Texas Instruments Incorporated
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3
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
www.ti.com
5 Description (continued)
The charger power stage and charge current sense functions are fully integrated. The charger function has high
accuracy current and voltage regulation loops, charge status display, and charge termination. The pre-charge
current and termination current threshold are programmed via an external resistor. The fast charge current value
is also programmable via an external resistor.
6 Device Options
PART
NUMBER
VO(REG)
VOVP
JEITA
TS/CE
PG
PACKAGE
bq24090
4.20 V
6.6 V
No
10 kΩ NTC
Yes
10 PIN 5x3mm2
bq24091
4.20 V
6.6 V
No
100 kΩ NTC
Yes
10 PIN 5x3mm2
bq24092
4.20 V
6.6 V
Yes
10 kΩ NTC
Yes
10 PIN 5x3mm2
bq24093
4.20 V
6.6 V
Yes
100 kΩ NTC
Yes
10 PIN 5x3mm2
bq24095
4.35 V
6.6 V
No
10 kΩ NTC
Yes
10 PIN 5x3mm2
7 Pin Configuration and Functions
DGQ Package
10 Pins
Top View
bq2409x
1 IN
OUT 10
2 ISET
TS 9
3 VSS
CHG 8
4 PRETERM ISET2 7
5 PG
NC 6
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CHG
8
O
Low (FET on) indicates charging and Open Drain (FET off) indicates no Charging or Charge complete.
IN
1
I
Input power, connected to external DC supply (AC adapter or USB port). Expected range of bypass
capacitors 1μF to 10μF, connect from IN to VSS.
ISET
2
I
Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast charge current
value. Range is 10.8k (50mA) to 540 Ω (1000mA).
ISET2
7
I
Programming the Input/Output Current Limit for the USB or Adaptor source:
High = 500mAmax, Low = ISET, FLOAT = 100mA max.
NC
6
NA
OUT
10
O
Battery Connection. System Load may be connected. Average load should not be excessive, allowing
battery to charge within the 10 hour safety timer window. Expected range of bypass capacitors 1μF to
10μF.
PG
5
O
Low (FET on) indicates the input voltage is above UVLO and the OUT (battery) voltage.
PRE-TERM
4
I
Programs the Current Termination Threshold (5 to 50% of Iout which is set by ISET) and Sets the PreCharge Current to twice the Termination Current Level.
Do not make a connection to this pin (for internal use) – Do not route through this pin
Expected range of programming resistor is 1k to 10kΩ (2k: Ipgm/10 for term; Ipgm/5 for precharge)
4
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bq24092, bq24093, bq24095
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
Pin Functions (continued)
PIN
NAME
NO.
Thermal PAD
and Package
—
I/O
DESCRIPTION
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the
device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit
board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be
connected to ground at all times
TS
9
I
Temperature sense pin connected to bq24090/2/5 -10k at 25°C NTC thermistor & bq24091/3 -100k at
25°C NTC thermistor, in the battery pack. Floating TS Pin or pulling High puts part in TTDM “Charger”
Mode and disable TS monitoring, Timers and Termination. Pulling pin Low disables the IC. If NTC
sensing is not needed, connect this pin to VSS through an external 10 kΩ/100kΩ resistor. A 250kΩ from
TS to ground will prevent IC entering TTDM mode when battery with thermistor is removed.
VSS
3
–
Ground terminal
8 Specifications
8.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
Input Voltage (2)
MIN
MAX
UNIT
IN (with respect to VSS)
–0.3
12
V
OUT (with respect to VSS)
–0.3
7
V
PRE-TERM, ISET, ISET2, TS, CHG, PG, ASI, ASO
(with respect to VSS)
–0.3
7
V
Input Current
IN
1.25
A
Output Current (Continuous)
OUT
1.25
A
Output Sink Current
CHG
15
mA
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
8.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±3000
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2010–2015, Texas Instruments Incorporated
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
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8.3 Recommended Operating Conditions (1)
MIN
MAX
3.5
12
V
4.45
6.45
V
1.0
A
IN voltage range
VIN
IN operating voltage range, Restricted by VDPM and VOVP
UNIT
IIN
Input current, IN pin
IOUT
Current, OUT pin
1.0
A
TJ
Junction temperature
0
125
°C
RPRE-TERM
Programs precharge and termination current thresholds
1
10
kΩ
RISET
Fast-charge current programming resistor
0.540
49.9
kΩ
RTS
10kΩ NTC thermistor range without entering BAT_EN or TTDM
1.66
258
kΩ
(1)
Operation with VIN less than 4.5V or in drop-out may result in reduced performance.
8.4 Thermal Information
bq2409x
THERMAL METRIC (1)
DGQ
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
71.2
RθJC(top)
Junction-to-case (top) thermal resistance
53.9
RθJB
Junction-to-board thermal resistance
45.2
ψJT
Junction-to-top characterization parameter
3.5
ψJB
Junction-to-board characterization parameter
44.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
19.2
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Dissipation Ratings (1)
(1)
(2)
°C/W
(2)
PACKAGE
RθJA
RθJC
TA ≤ 25°C
POWER RATING
DERATING FACTOR
TA > 25°C
5x3mm MSOP
52°C/W
48°C/W
1.92 W
19.2 mW/°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2×3 via matrix
8.6 Electrical Characteristics
over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Undervoltage lock-out Exit
VIN: 0V → 4V Update based on sim/char
3.15
3.3
3.45
V
VHYS_UVLO
Hysteresis on VUVLO_RISE falling
VIN: 4V→0V,
VUVLO_FALL = VUVLO_RISE –VHYS-UVLO
175
227
280
mV
VIN-DT
Input power good detection threshold
is VOUT + VIN-DT
(Input power good if VIN > VOUT + VIN-DT);
VOUT = 3.6V, VIN: 3.5V → 4V
30
80
145
mV
VHYS-INDT
Hysteresis on VIN-DT falling
VOUT = 3.6V, VIN: 4V → 3.5V
31
mV
tDGL(PG_PWR)
Deglitch time on exiting sleep.
Time measured from VIN: 0V → 5V 1μs rise-time to
PG = low, VOUT = 3.6V
45
μs
tDGL(PG_NO-
Deglitch time on VHYS-INDT power
down. Same as entering sleep.
Time measured from VIN: 5V → 3.2V 1μs fall-time to
PG = OC, VOUT = 3.6V
29
ms
PWR)
VOVP
Input over-voltage protection threshold
VIN: 5V → 7V
tDGL(OVP-SET)
Input over-voltage blanking time
VIN: 5V → 7V
113
μs
VHYS-OVP
Hysteresis on OVP
VIN: 7V → 5V
95
mV
Deglitch time exiting OVP
Time measured from VIN: 7V → 5V 1μs fall-time to
PG = LO
30
μs
UVLO
tDGL(OVP-REC)
6
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6.5
6.65
6.8
V
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: bq24091 bq24090 bq24092 bq24093 bq24095
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bq24092, bq24093, bq24095
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
Electrical Characteristics (continued)
over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
VIN-DPM
IIN-USB-CL
TEST CONDITIONS
USB/Adaptor low input voltage
protection. Restricts lout at VIN-DPM
MIN
TYP
MAX
Feature active in USB mode; Limit Input Source
Current to 50mA; VOUT = 3.5V; RISET = 825Ω
4.34
4.4
4.46
Feature active in Adaptor mode; Limit Input Source
Current to 50mA; VOUT = 3.5V; RISET = 825Ω
4.24
4.3
4.36
UNIT
V
USB input I-Limit 100mA
ISET2 = Float; RISET = 825Ω
85
92
100
USB input I-Limit 500mA
ISET2 = High; RISET = 825Ω
430
462
500
280
mA
ISET SHORT CIRCUIT TEST
RISET_SHORT
Highest Resistor value considered a
fault (short). Monitored for Iout>90mA
Riset: 600Ω → 250Ω, IOUT latches off. Cycle power to
Reset.
tDGL_SHORT
Deglitch time transition from ISET
short to Iout disable
Clear fault by cycling IN or TS/BAT_EN
IOUT_CL
Maximum OUT current limit Regulation VIN = 5V, VOUT = 3.6V, VISET2 = Low, RISET:
(Clamp)
600Ω → 250Ω, Iout latches off after tDGL-SHORT
500
1
1.05
Ω
ms
1.4
A
0.85
V
BATTERY SHORT PROTECTION
VOUT(SC)
OUT pin short-circuit detection
threshold/ precharge threshold
VOUT:3V → 0.5V, no deglitch
VOUT(SC-HYS)
OUT pin Short hysteresis
Recovery ≥ VOUT(SC) + VOUT(SC-HYS); Rising, no
Deglitch
IOUT(SC)
Source current to OUT pin during
short-circuit detection
0.75
0.8
77
10
15
mV
20
mA
QUIESCENT CURRENT
IOUT(PDWN)
Battery current into OUT pin
VIN = 0V
1
IOUT(DONE)
OUT pin current, charging terminated
VIN = 6V, VOUT > VOUT(REG)
6
IIN(STDBY)
Standby current into IN pin
TS = LO, VIN ≤ 6V
Active supply current, IN pin
TS = open, VIN = 6V, TTDM – no load on OUT pin,
VOUT > VOUT(REG), IC enabled
ICC
μA
125
μA
0.8
1.0
mA
BATTERY CHARGER FAST-CHARGE
Battery regulation voltage
(bq24090/1/2/3)
VIN = 5.5V, IOUT = 25mA, (VTS-45°C≤ VTS ≤ VTS-0°C)
4.16
4.2
4.23
Battery regulation voltage (bq24095)
VIN = 5.5V, IOUT = 25mA
4.30
4.35
4.40
VO_HT(REG)
Battery hot regulation Voltage,
bq24092/3
VIN = 5.5V, IOUT = 25mA, VTS-60°C≤ VTS ≤ VTS-45°C
4.02
4.06
4.1
IOUT(RANGE)
Programmed Output “fast charge”
current range
VOUT(REG) > VOUT > VLOWV; VIN = 5V, ISET2=Lo,
RISET = 540 to 10.8kΩ
10
VDO(IN-OUT)
Drop-Out, VIN – VOUT
Adjust VIN down until IOUT = 0.5A, VOUT = 4.15V,
RISET = 540 , ISET2=Lo (adaptor mode); TJ ≤ 100°C
IOUT
Output “fast charge” formula
VOUT(REG) > VOUT > VLOWV; VIN = 5V, ISET2 = Lo
VOUT(REG)
KISET
KISET
Fast charge current factor for
bq24090, 91, 92, 93
Fast charge current factor for
bq24095
325
V
V
1000
mA
520
mV
KISET/RISET
A
RISET = KISET /IOUT; 50 < IOUT < 1000 mA
510
540
565
RISET = KISET /IOUT; 25 < IOUT < 50 mA
480
527
580
RISET = KISET /IOUT; 10 < IOUT < 25 mA
350
520
680
RISET = KISET /IOUT; 50 < IOUT < 1000 mA
510
560
585
RISET = KISET /IOUT; 25 < IOUT < 50 mA
480
557
596
RISET = KISET /IOUT; 10 < IOUT < 25 mA
350
555
680
2.4
2.5
2.6
AΩ
AΩ
PRECHARGE – SET BY PRETERM PIN
VLOWV
Pre-charge to fast-charge transition
threshold
tDGL1(LOWV)
Deglitch time on pre-charge to fastcharge transition
70
μs
tDGL2(LOWV)
Deglitch time on fast-charge to precharge transition
32
ms
IPRE-TERM
Refer to the Termination Section
%PRECHG
Pre-charge current, default setting
VOUT < VLOWV; RISET = 1080Ω;
RPRE-TERM= High Z
Pre-charge current formula
RPRE-TERM = KPRE-CHG (Ω/%) × %PRE-CHG (%)
Copyright © 2010–2015, Texas Instruments Incorporated
18
20
22
V
%IOUTCC
RPRE-TERM/KPRE-CHG%
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
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Electrical Characteristics (continued)
over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
KPRE-CHG
TEST CONDITIONS
% Pre-charge Factor
MIN
TYP
MAX
UNIT
VOUT < VLOWV, VIN = 5V, RPRE-TERM = 2k to 10kΩ;
RISET = 1080Ω , RPRE-TERM = KPRE-CHG × %IFAST-CHG,
where %IFAST-CHG is 20 to 100%
90
100
110
Ω/%
VOUT < VLOWV, VIN = 5V, RPRE-TERM = 1k to 2kΩ; RISET
= 1080Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG, where
%IFAST-CHG is 10% to 20%
84
100
117
Ω/%
9
10
11
%IOUT-
TERMINATION – SET BY PRE-TERM PIN
Termination Threshold Current, default VOUT > VRCH; RISET = 1k;
setting
RPRE-TERM= High Z
%TERM
KTERM
CC
Termination Current Threshold
Formula
RPRE-TERM = KTERM (Ω/%) × %TERM (%)
182
200
216
% Term Factor
VOUT > VRCH, VIN = 5V, RPRE-TERM = 2k to 10kΩ ;
RISET = 750Ω KTERM × %IFAST-CHG, where %IFAST-CHG
is 10 to 50%
VOUT > VRCH, VIN = 5V, RPRE-TERM = 1k to 2kΩ ; RISET
= 750Ω KTERM × %Iset, where %Iset is 5 to 10%
174
199
224
71
75
81
IPRE-TERM
Current for programming the term. and
pre-chg with resistor. ITerm-Start is the
RPRE-TERM = 2k, VOUT = 4.15V
initial PRE-TERM current.
%TERM
Termination current formula
tDGL(TERM)
Deglitch time, termination detected
ITerm-Start
Elevated PRE-TERM current for, tTermStart, during start of charge to prevent
recharge of full battery,
tTerm-Start
Elevated termination threshold initially
active for tTerm-Start
RPRE-TERM/ KTERM
Ω/%
μA
RTERM/ KTERM%
29
80
85
ms
92
1.25
μA
min
RECHARGE OR REFRESH
Recharge detection threshold –
Normal Temp
VIN = 5V, VTS = 0.5V, VOUT: 4.25V → VRCH
VO(REG)
-0.120
VO(REG)-0.095
VO(REG)0.070
V
Recharge detection threshold – Hot
Temp
VIN = 5V, VTS = 0.2V, VOUT: 4.15V → VRCH
VO(REG)
-0.130
VO(REG)-0.105
VO(REG)0.080
V
tDGL1(RCH)
Deglitch time, recharge threshold
detected
VIN = 5V, VTS = 0.5V, VOUT: 4.25V → 3.5V in 1μs;
tDGL(RCH) is time to ISET ramp
29
ms
tDGL2(RCH)
Deglitch time, recharge threshold
detected in OUT-Detect Mode
VIN = 5V, VTS = 0.5V, VOUT = 3.5V inserted; tDGL(RCH)
is time to ISET ramp
3.6
ms
VRCH
BATTERY DETECT ROUTINE
VREG-BD
VOUT Reduced regulation during
battery detect
IBD-SINK
Sink current during VREG-BD
tDGL(HI/LOW
REG)
VO(REG)
-0.450
VIN = 5V, VTS = 0.5V, Battery Absent
VO(REG)-0.400
7
Regulation time at VREG or VREG-BD
VO(REG)350
10
25
V
mA
ms
VBD-HI
High battery detection threshold
VIN = 5V, VTS = 0.5V, Battery Absent
VO(REG)
-0.150
VO(REG)-0.100
VO(REG)0.050
V
VBD-LO
Low battery detection threshold
VIN = 5V, VTS = 0.5V, Battery Absent
VREG-BD
+0.50
VREG-BD +0.1
VREG-BD
+0.15
V
BATTERY CHARGING TIMERS AND FAULT TIMERS
tPRECHG
Pre-charge safety timer value
Restarts when entering Pre-charge; Always enabled
when in pre-charge.
1700
1940
2250
s
tMAXCH
Charge safety timer value
Clears fault or resets at UVLO, TS/BAT_EN disable,
OUT Short, exiting LOWV and Refresh
34000
38800
45000
s
BATTERY-PACK NTC MONITOR (Note 1); TS pin: 10k and 100k NTC
INTC-10k
NTC bias current, bq24090/2/5
VTS = 0.3V
48
50
52
μA
INTC-100k
NTC bias current, bq24091/3
VTS = 0.3V
4.8
5.0
5.2
μA
INTC-DIS-10k
10k NTC bias current when Charging
is disabled, bq24090/2/5
VTS = 0V
27
30
34
μA
INTC-DIS-100k
100k NTC bias current when Charging
is disabled, bq24091/3
VTS = 0V
4.4
5.0
5.8
μA
8
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
Electrical Characteristics (continued)
over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VTS: Set to 1.525V
4
5
6.5
μA
INTC is reduced prior to entering
TTDM to keep cold thermistor from
entering TTDM, bq24091/3
VTS: Set to 1.525V
1.1
1.5
1.9
μA
VTTDM(TS)
Termination and timer disable mode
Threshold – Enter
VTS: 0.5V → 1.7V; Timer Held in Reset
1550
1600
1650
mV
VHYS-TTDM(TS)
Hysteresis exiting TTDM
VTS: 1.7V → 0.5V; Timer Enabled
VCLAMP(TS)
TS maximum voltage clamp
VTS = Open (Float)
1800
1950
INTC-FLDBK-10k
INTC is reduced prior to entering
TTDM to keep cold thermistor from
entering TTDM, bq24090/2/5
INTC-FLDBK-100k
tDGL(TTDM)
100
Deglitch exit TTDM between states
Deglitch enter TTDM between states
VTS_I-FLDBK
TS voltage where INTC is reduce to
keep thermistor from entering TTDM
CTS
Optional Capacitance – ESD
INTC adjustment (90 to 10%; 45 to 6.6uS) takes
place near this spec threshold. VTS: 1.425V →
1.525V
ms
μs
1475
mV
0.22
μF
Low temperature CHG Pending
VHYS-0°C
Hysteresis at 0°C
Charge pending to low temp charging;
VTS: 1.5V → 1V
VTS-10°C
Low temperature, half charge,
bq24092/3
Normal charging to low temp charging;
VTS: 0.5V → 1V
VHYS-10°C
Hysteresis at 10°C, bq24092/3
Low temp charging to normal CHG;
VTS: 1.0V → 0.5V
VTS-45°C
High temperature at 4.1V
Normal charging to high temp CHG;
VTS: 0.5V → 0.2V
VHYS-45°C
Hysteresis at 45°C
High temp charging to normal CHG;
VTS: 0.2V → 0.5V
VTS-60°C
High temperature Disable, bq24092/3
High temp charge to pending;
VTS: 0.2V → 0.1V
VHYS-60°C
Hysteresis at 60°C, bq24092/3
Charge pending to high temp CHG;
VTS: 0.1V → 0.2V
tDGL(TS_10C)
Deglitch for TS thresholds: 10C,
bq24092/3
Normal to Cold Operation; VTS: 0.6V → 1V
50
Cold to Normal Operation; VTS: 1V → 0.6V
12
tDGL(TS)
Deglitch for TS thresholds: 0/45/60C.
Battery charging
VTS-EN-10k
Charge Enable Threshold, (10k NTC)
VTS: 0V → 0.175V;
VTS-DIS_HYS-10k
HYS below VTS-EN-10k to Disable, (10k
NTC)
VTS: 0.125V → 0V;
VTS-EN-100k
Charge Enable Threshold, bq24090/2
VTS: 0V → 0.175V;
VTS-DIS_HYS-
HYS below VTS-EN-100k to Disable,
bq24091/3
VTS: 0.125V → 0V;
1230
1255
86
765
790
278
815
178
293
186
ms
ms
96
12
140
150
mV
mV
30
88
mV
mV
11.5
80
mV
mV
10.7
170
mV
mV
35
263
mV
8
VTS-0°C
100k
mV
2000
57
Low Temp Charging to Pending;
VTS: 1.0V → 1.5V
1205
UNIT
mV
mV
160
mV
50
mV
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
125
°C
TJ(OFF)
Thermal shutdown temperature
155
°C
TJ(OFF-HYS)
Thermal shutdown hysteresis
20
°C
LOGIC LEVELS ON ISET2
VIL
Logic LOW input voltage
Sink 8 μA
VIH
Logic HIGH input voltage
Source 8 μA
1.4
IIL
Sink current required for LO
VISET2= 0.4V
2
IIH
Source current required for HI
VISET2= 1.4V
VFLT
ISET2 Float Voltage
V
9
μA
V
1.1
575
0.4
900
8
μA
1225
mV
LOGIC LEVELS ON CHG AND PG
VOL
Output LOW voltage
ISINK = 5 mA
ILEAK
Leakage current into IC
V CHG = 5V, V PG = 5V
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0.4
V
1
μA
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8.7 Typical Characteristics
SETUP: bq2409x typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated)
8.7.1 Power Up, Power Down, OVP, Disable and Enable Waveforms
Vin
Vin
5V/div
5V/div
Vchg
2V/div
2V/div
Vchg
Vpg
2V/div
Vpg
Viset
2V/div
Viset 2V/div
2V/div
t - time - 20ms/div
Figure 1. OVP 8V Adaptor - Hot Plug
t - time - 100ms/div
Figure 2. OVP from Normal Power-Up
Operation – VIN 0V → 5V → 6.8V → 5V
Vpg
Vpg
2V/div
5V/div
Vchg
Vchg
2V/div
2V/div
Vout
2V/div
500mV/div
Vts
Viset
Battery Detect Mode
Vin
2V/div
5V/div
t - time - 50ms/div
10kΩ resistor from TS to GND.
10kΩ is shorted to disable the IC.
Figure 3. TS Enable and Disable
t - time - 20ms/div
Fixed 10kΩ resistor, between TS and GND.
Figure 4. Hot Plug Source w/ No Battery –
Battery Detection
Vout
Vin
2V/div
Vchg
Vout
500mV/div
Viset
1 Battery Detect Cycle
1V/div
5V/div
1V/div
Viset
1V/div
Vts
1V/div
Vts
Entered TTDM
2V/div
t - time - 5ms/div
Figure 5. Battery Removal – GND Removed 1st, 42 Ω Load
10
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t - time - 10ms/div
Figure 6. Battery Removal With OUT and
TS Disconnect 1st, With 100 Ω Load
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
8.7.2 Protection Circuits Waveforms
Vchg
Vin
2V/div
2V/div
Vchg
Vin
2V/div
2V/div
Short Detected in 100mA
mode and Latched Off
Viset
500mV/div
500mV/div
V_0.1 W_OUT
20mV/div
Viset
20mV/div
V_0.1W_OUT
t - time - 500ms/div
t - time - 5ms/div
CH4: Iout (0.2A/Div)
Figure 7. ISET Shorted Prior to USB Power-Up
Vin
Vout
Figure 8. DPM – USB Current Limits – Vin Regulated to
4.4V
2V/div
1V/div
Enters
Thermal
Regulation
Exits
Thermal
Regulation
Vin
1V/div
Viset
1V/div
Viset
Vchg
1V/div
5V/div
Vpg
V_0.1W_OUT
5V/div
50mV/div
t - time - 20ms/div
t - time - 1s/div
The IC temperature rises to 125°C and enters thermal regulation.
Charge current is reduced to regulate the IC at 125°C. VIN is
reduced, the IC temperature drops, the charge current returns to the
programmed value.
Figure 9. Thermal Regulation – Vin increases PWR/Iout
Reduced
VIN swept from 5V to 3.9V to 5V
VBAT = 4V
Figure 10. Entering and Exiting Sleep Mode
4.2
546
K iset
544
4.199
Vreg @ 25°C
Low to High Currents
(may occur in recharge to fast charge transion)
540
Kiset - W
VOUT - Output Voltage - V
542
538
High to Low Currents
(may occur in Voltage Regulation - Taper Current)
536
534
532
4.198
Vreg @ 85°C
4.197
4.196
4.195
Vreg @ 0°C
4.194
4.193
530
4.192
528
0
.15
0.2
0.4
IO - Output Current - A
0.6
Figure 11. KISET for Low and High Currents
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0.8
0
0.2
0.4
0.6
IO - Output Current - A
0.8
1
Figure 12. Load Regulation Over Temperature
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Protection Circuits Waveforms (continued)
4.360
Vreg @ 85°C
4.358
VO - Output Voltage - V
4.356
4.354
Vreg @ 25°C
4.352
4.350
4.348
4.346
4.344
Vreg @ 0°C
4.342
4.340
0
0.2
0.4
0.6
IO - Output Current - A
0.8
1
Figure 13. Load Regulation – bq24095
12
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
9 Detailed Description
9.1 Overview
The bq2409x is a highly-integrated family of single cell Li-Ion and Li-Pol chargers. The charger can be used to
charge a battery, power a system or both. The charger has three phases of charging: Pre-charge to recover a
fully discharged battery, fast-charge constant current to supply the buck charge safely and voltage regulation to
safely reach full capacity. The charger is very flexible, allowing programming of the fast-charge current and Precharge/Termination Current. This charger is designed to work with a USB connection or Adaptor (DC out). The
charger also checks to see if a battery is present.
The charger also comes with a full set of safety features: JEITA Temperature Standard, Over-Voltage Protection,
DPM-IN, Safety Timers, and ISET short protection. All of these features and more are described in detail below.
The charger is designed for a single power path from the input to the output to charge a single cell Li-Ion or LiPol battery pack. Upon application of a 5VDC power source the ISET and OUT short checks are performed to
assure a proper charge cycle.
If the battery voltage is below the LOWV threshold, the battery is considered discharged and a preconditioning
cycle begins. The amount of precharge current can be programmed using the PRE-TERM pin which programs a
percent of fast charge current (10 to 100%) as the precharge current. This feature is useful when the system load
is connected across the battery “stealing” the battery current. The precharge current can be set higher to account
for the system loading while allowing the battery to be properly conditioned. The PRE-TERM pin is a dual
function pin which sets the precharge current level and the termination threshold level. The termination "current
threshold" is always half of the precharge programmed current level.
Once the battery voltage has charged to the VLOWV threshold, fast charge is initiated and the fast charge current
is applied. The fast charge constant current is programmed using the ISET pin. The constant current provides the
bulk of the charge. Power dissipation in the IC is greatest in fast charge with a lower battery voltage. If the IC
reaches 125°C the IC enters thermal regulation, slows the timer clock by half and reduce the charge current as
needed to keep the temperature from rising any further. Figure 14 shows the charging profile with thermal
regulation. Typically under normal operating conditions, the IC’s junction temperature is less than 125°C and
thermal regulation is not entered.
Once the cell has charged to the regulation voltage the voltage loop takes control and holds the battery at the
regulation voltage until the current tapers to the termination threshold. The termination can be disabled if desired.
The CHG pin is low (LED on) during the first charge cycle only and turns off once the termination threshold is
reached, regardless if termination, for charge current, is enabled or disabled.
Further details are mentioned in the Feature Description section.
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Overview (continued)
VO(REG)
PreConditioning
Phase
Thermal
Regulation
Phase
Current
Regulation
Phase
Voltage Regulation and
Charge Termination
Phase
DONE
IO(OUT)
FAST-CHARGE
CURRENT
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
Battery
Voltage,
V(OUT)
Battery Current,
I(OUT)
Charge
Complete
Status,
Charger
Off
VO(LOWV)
I(TERM)
IO(PRECHG)
T(THREG)
0A
Temperature, Tj
T(PRECHG)
T(CHG)
DONE
Figure 14. Charging Profile With Thermal Regulation
14
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SLUS968G – JANUARY 2010 – REVISED AUGUST 2015
9.2 Functional Block Diagram
Internal Charge
Current Sense
w/ Multiple Outputs
IN
OUT
80 mV
OUT
+
_
Input
Power
Detect
IN
OUT
+
_
+
_
+
-
IN-DPMREF
Charge
Pump
IOUT x 1.5 V
540 AW
OUTREGREF
TJ°C
+
_
FAST CHARGE
125°CREF
PRE-CHARGE
ISET
IN
+
_
1.5V
Pre-CHG Reference
+
_
USB100/500REF
USB Sense
Resistor
o
TJ C
+
_
Term Reference
+
_
150oCREF
Thermal Shutdown
75mA +
X2 Gain (1: 2)
Term:Pre-CHGX2
PRE-TERM
Increased from 75mA to 85mA for
1st minute of charge.
IN
+
_
+
CHG
OVPREF
+
_
OUT
VTERM_EN
Charge
Pump
+
_
ON:
OFF:
ISET2 (LO = ISET, HI = USB500,
0.9V Float
On During
1st Charge Only
CHARGE
CONTROL
FLOAT = USB100)
PG
VCOLD-10 C
o
+
_
o
+
_
VHOT-45 C
HI = Half CHG (JEITA)
HI = 4.06Vreg (JEITA)
VCOLD-FLT
+
_
+
_
VHOT-FLT
LO = TTDM MODE
HI = Suspend CHG
TS
VTTDM
TS - bq24090
VCE
+
_
+
_
HI=CHIP DISABLE
VDISABLE
+
_
Cold Temperature
Sink Current
= 45mA _ VCLAMP = 1.4V
Disable
Sink Current
= 20mA
+
5mA
+
_
45mA
Bq24090 is as shown
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9.3 Feature Description
9.3.1 Power-Down or Undervoltage Lockout (UVLO)
The bq2409x family is in power down mode if the IN pin voltage is less than UVLO. The part is considered
“dead” and all the pins are high impedance. Once the IN voltage rises above the UVLO threshold the IC will
enter Sleep Mode or Active mode depending on the OUT pin (battery) voltage.
9.3.2 UVLO
The bq2409x family is in power down mode if the IN pin voltage is less than VUVLO. The part is considered “dead”
and all the pins are high impedance.
9.3.3 Power-Up
The IC is alive after the IN voltage ramps above UVLO (see sleep mode), resets all logic and timers, and starts
to perform many of the continuous monitoring routines. Typically the input voltage quickly rises through the
UVLO and sleep states where the IC declares power good, starts the qualification charge at 100mA, sets the
input current limit threshold base on the ISET2 pin, starts the safety timer and enables the CHG pin. See
Figure 15.
9.3.4 Sleep Mode
If the IN pin voltage is between than VOUT+VDT and UVLO, the charge current is disabled, the safety timer
counting stops (not reset) and the PG and CHG pins are high impedance. As the input voltage rises and the
charger exits sleep mode, the PG pin goes low, the safety timer continues to count, charge is enabled and the
CHG pin returns to its previous state. See Figure 16.
9.3.5 New Charge Cycle
A new charge cycle is started when a good power source is applied, performing a chip disable/enable (TS pin),
exiting Termination and Timer Disable Mode (TTDM), detecting a battery insertion or the OUT voltage dropping
below the VRCH threshold. The CHG pin is active low only during the first charge cycle, therefore exiting TTDM or
a dropping below VRCH will not turn on the CHG pin FET, if the CHG pin is already high impedance.
16
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VSS
1.8V
Disabled
4.06 V
HOT
Operation
Normal
Operation
4.06 V
HOT
Operation
HOT
Fault
Disabled
Normal
Operation
Cold
Operation
Cold
Fault
LDO
Mode
Cold
Fault
tDGL(TTDM)
Enter
Normal
Operation
Cold
Operation
t < tDGL(IS)
Normal
Operation
LDO
Mode
tDGL(TTDM)
Enter
tDGL(TTDM)
Exit
LDO
t < tDGL(TTDM)
Exit
LDOHYS
tDGL(TS)
tDGL(TS)
tDGL(TS1_IOC)
Cold to Normal
0°C
0°CHYS
tDGL(TS_IOC)
Rising
tDGL(TS_IOC)
Falling
10°C
10°CHYS
tDGL(TS)
tDGL(TS)
tDGL(TS)
45°CHYS
45°C
tDGL(TS)
tDGL(TS)
60°CHYS
Dots Show Threshold Trip Points
fllowed by a deglitch time before
transitioning into a new mode.
60°C
EN
DISHYS
0V
Drawing Not to Scale
t
Figure 15. TS Battery Temperature Bias Threshold and Deglitch Timers
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Apply Input
Power
Is power good?
VBAT +VDT < VIN < VOVP
& VUVLO < VIN
No
Turn on PG FET
PG pin LOW
Yes
Is chip enabled?
VTS > VEN
No
Yes
Set Input Current Limit to 100 mA
and Start Charge
Perform ISET & OUT short tests
Remember ISET2 State
Set charge current
based on ISET2 truth
table.
Return to
Charge
Figure 16. bq2409x Power-Up Flow Diagram
9.3.6 Overvoltage-Protection (OVP) – Continuously Monitored
If the input source applies an overvoltage, the pass FET, if previously on, turns off after a deglitch, tBLK(OVP). The
timer ends and the CHG and PG pin goes to a high impedance state. Once the overvoltage returns to a normal
voltage, the PG pin goes low, timer continues, charge continues and the CHG pin goes low after a 25ms
deglitch. PG pin is optional on some packages
9.3.7 Power Good Indication (PG)
After application of a 5V source, the input voltage rises above the UVLO and sleep thresholds (VIN>VBAT+VDT),
but is less than OVP (VIN
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