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bq24120, bq24123, bq24125
SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
bq2412x Single-Chip Switched-Mode, Li-Ion, and Li-Polymer Charge-Management
IC With Enhanced EMI Performance (bqSWITCHER™)
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Enhanced EMI Performance
Integrated Power FETs For Up To 2-A Charge
Rate
Suitable For 1-, 2-, or 3-Cell Li-Ion and Li-Polymer
Battery Packs
Synchronous Fixed-Frequency PWM Controller
Operating at 1.1 MHz With 0% to 100% Duty
Cycle
High-Accuracy Voltage and Current Regulation
Status Outputs For LED or Host Processor
Interface Indicates Charge-In-Progress, Charge
Completion, Fault, and AC-Adapter Present
Conditions
20-V Absolute Maximum Voltage Rating on IN and
OUT Pins
Accurate High-Side Battery Current Sensing
Battery Temperature Monitoring
Automatic Sleep Mode for Low Power
Consumption
Reverse Leakage Protection Prevents Battery
Drainage
Thermal Shutdown and Protection
Built-In Battery Detection
Available in 20-pin 3.5-mm × 4.5-mm VQFN
Package
Handheld Products
Portable Media Players
Industrial and Medical Equipment
Portable Equipment
Portable DVD Players
3 Description
The bqSWITCHER™ series are highly integrated Liion
and
Li-polymer
switched-mode
charge
management devices targeted at a wide range of
portable applications. The bqSWITCHER™ series
offers integrated synchronous PWM controller and
power FETs, high-accuracy current and voltage
regulation, charge preconditioning, charge status, and
charge termination, in a small, thermally enhanced
QFN package.
The bqSWITCHER charges the battery in three
phases: conditioning, constant current, and constant
voltage. Charge is terminated based on userselectable minimum current level. A programmable
charge timer provides a safety backup for charge
termination. The bqSWITCHER automatically restarts
the charge cycle if the battery voltage falls below an
internal threshold. The bqSWITCHER automatically
enters sleep mode when VCC supply is removed.
Device Information
PART NUMBER
bq2412x
PACKAGE
VQFN (20)
(1)
BODY SIZE (NOM)
3.50 mm × 4.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical 1-Cell Application
LO
BQ24120
VIN
CIN
10 mF
1.5 KW
1.5 KW
Adapter
Present
1.5 KW
Done
Charge
3
IN
OUT 1
4
IN
OUT 20
6
VCC
2
STAT1 PGND 18
19 STAT2
CTTC
5
PG
7
TTC
16 CE
0.1 mF
10 VSS
0.1 mF
PGND 17
13 NC
RSNS
10mH
COUT
10mF
0.1W
Battery
Pack
Pack+
Pack-
MMBZ18VALT1
(See Note)
103AT
SNS 15
BAT 14
ISET1 8
ISET2 9
7.5 KW R
ISET1
7.5 KW
R ISET2
VTSB
9.31 KW
R T1
442 KW
RT2
TS 12
VTSB 11
0.1 mF
0.1 mF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24120, bq24123, bq24125
SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
5
5
5
8
9
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 21
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
9.3 System Examples ................................................... 26
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
11.3 Thermal Considerations ........................................ 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision G (August 2008) to Revision H
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: bq24120 bq24123 bq24125
bq24120, bq24123, bq24125
www.ti.com
SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
5 Device Options
PART NUMBER
CHARGE REGULATION
VOLTAGE (V)
(1) (2)
BQ24120RHLR / BQ24120RHLT
4.2 V
(2)
Stand-alone
4.2 V / 8.4 V
BQ24123RHLR / BQ24123RHLT
(1)
INTENDED
APPLICATION
2.1 V to 15.5 V
Externally programmable
The RHL package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel
T - taped and reeled in quantities of 250 devices per reel
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes.
6 Pin Configuration and Functions
2
1
20 19
3
18
4
17
5
16
6
15
7
14
8
13
11 12
STAT2
PGND
PGND
CE
SNS
BAT
CELLS
TS
VTSB
9 10
VSS
STAT1
IN
IN
PG
VCC
TTC
ISET1
ISET2
OUT
OUT
RHL Package
20-Pin VQFN
Top View
Pin Functions
PIN
NAME
I/O
DESCRIPTION
bq24120
bq24123
bq24125
BAT
14
14
14
I
Battery voltage sense input. Bypass it with a capacitor to VSS if there are long
inductive leads to battery.
CE
16
16
16
I
Charger enable input. This active low input, if set high, suspends charge and
places the device in the low-power sleep mode. Do not pull up this input to VTSB.
I
Available on parts with selectable output voltage. Ground or float for single-cell
operation (4.2 V). For two-cell operation (8.4 V) pull up this pin with a resistor to
VIN.
13
I
Output voltage analog feedback adjustment. Connect the output of a resistive
voltage divider powered from the battery terminals to this node to adjust the
output battery voltage regulation.
Charger input voltage. Bypass it with a 10μF capacitor from IN to PGND.
CELLS
13
FB
IN
3, 4
3, 4
3, 4
I
ISET1
8
8
8
I/O
Charger current set point 1 (fast charge). Use a resistor to ground to set this
value.
ISET2
9
9
9
I/O
Charge current set point 2 (precharge and termination), set by a resistor
connected to ground.
N/C
13
–
No connection. This pin must be left floating in the application.
1
1
1
O
20
20
20
O
Charge current output inductor connection. Connect a zener TVS diode between
OUT pin and PGND to clamp the voltage spike to protect the power MOSFETs
during abnormal conditions.
5
5
5
O
OUT
PG
Power-good status output (open drain). The transistor turns on when a valid VCC
is detected. It is turned off in the sleep mode. PG can be used to drive a LED or
communicate with a host processor.
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: bq24120 bq24123 bq24125
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SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
bq24120
bq24123
bq24125
PGND
17,18
17,18
17,18
SNS
15
15
15
I
Charge current-sense input. Battery current is sensed via the voltage drop
developed on this pin by an external sense resistor in series with the battery pack.
A 0.1μF capacitor to VSS is required.
STAT1
2
2
2
O
Charge status 1 (open-drain output). When the transistor turns on indicates
charge in process. When it is off and with the condition of STAT2 indicates
various charger conditions (See Table 1)
STAT2
19
19
19
O
Charge status 2 (open-drain output). When the transistor turns on indicates
charge is done. When it is off and with the condition of STAT1 indicates various
charger conditions (See Table 1)
TS
12
12
12
I
Temperature sense input. This input monitors its voltage against an internal
threshold to determine if charging is allowed. Use an NTC thermistor and a
voltage divider powered from VTSB to develop this voltage. (See Figure 9)
TTC
7
7
7
I
Timer and termination control. Connect a capacitor from this node to VSS to set
the bqSWITCHER timer. When this input is low, the timer and termination
detection are disabled.
I
Analog device input. A 0.1μF capacitor to VSS is required.
VCC
6
6
6
VSS
10
10
10
VTSB
11
11
11
Exposed
Thermal
Pad
Pad
Pad
Power ground input
Analog ground input
O
TS internal bias regulator voltage. Connect capacitor (with a value between a
0.1μF and 1μF) between this output and VSS.
There is an internal electrical connection between the exposed thermal pad and
VSS. The exposed thermal pad must be connected to the same potential as the
VSS pin on the printed circuit board. The power pad can be used as a star ground
connection between VSS and PGND. A common ground plane may be used. VSS
pin must be connected to ground at all times.
Pad
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (with respect to VSS)
MAX
UNIT
20
V
IN, VCC
Input voltage (with respect to VSS and PGND)
STAT1, STAT2, PG, CE, CELLS, SNS, BAT
–0.3
20
V
OUT
–0.7
20
V
7
V
VTSB
3.6
V
ISET1, ISET2
3.3
V
TS, TTC
Voltage difference between SNS and BAT inputs (VSNS - VBAT)
±1
V
Output sink
STAT1, STAT2, PG
10
mA
Output current (average)
OUT
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
2.2
A
300
°C
TA
Operating free-air temperature
–40
85
°C
TJ
Junction temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
±2000
(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: bq24120 bq24123 bq24125
bq24120, bq24123, bq24125
www.ti.com
SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
7.3 Recommended Operating Conditions
MIN
Supply voltage, VCC and IN (Tie together)
4.35
Operating junction temperature range, TJ
(1)
(2)
NOM
(1)
MAX
16.0
–40
UNIT
(2)
V
125
°C
The IC continues to operate below Vmin, to 3.5 V, but these conditions are not tested, and are not specified.
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the IN or OUT pins. A tight layout
minimizes switching noise.
7.4 Thermal Information
bq2412x
THERMAL METRIC
(1)
RHL (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
39.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.3
°C/W
RθJB
Junction-to-board thermal resistance
15.8
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
15.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VCC > VCC(min), PWM switching
IVCC(VCC)
VCC supply current
Battery discharge sleep current, (SNS,
BAT, OUT pins)
I(SLP)
10
VCC > VCC(min), PWM NOT switching
5
VCC > VCC(min), CE = HIGH
315
0°C ≤ TJ ≤ 65°C, VI(BAT) = 4.2 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
3.5
0°C ≤ TJ ≤ 65°C, VI(BAT) = 8.4 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
5.5
0°C ≤ TJ ≤ 65°C, VI(BAT) = 12.6 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
7.7
mA
μA
μA
VOLTAGE REGULATION
VOREG
Output voltage, bq24123
Output voltage, bq24120
VIBAT
CELLS = Low, in voltage regulation
4.2
CELLS = High, in voltage regulation
8.4
Operating in voltage regulation
4.2
Feedback regulation REF for bq24125 only
IIBAT = 25 nA typical into pin
(W/FB)
2.1
TA = 25°C
Voltage regulation accuracy
V
–0.5%
0.5%
–1%
1%
150
2000
–10%
10%
CURRENT REGULATION - FAST CHARGE
IOCHARGE
VLOWV ≤ VI(BAT) < VOREG,
V(VCC) - VI(BAT) > V(DO-MAX)
Output current range of converter
100 mV ≤ VIREG≤ 200 mV,
V
VIREG
(1)
Voltage regulated across R(SNS) Accuracy
IREG
+
mA
(1)
1V
RSET1
1000,
Programmed Where
5 kΩ ≤ RSET1 ≤ 10 kΩ, Select RSET1 to
program VIREG,
VIREG(measured) = IOCHARGE ×RSNS
(–10% to 10% excludes errors due to RSET1
and R(SNS) tolerances)
Inductor peak current should be less than 2.6 A. Use equations 12, 13, 15, 18, and 19 to make sure the peak inductor current is less
than 2.6 A.
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: bq24120 bq24123 bq24125
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SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
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Electrical Characteristics (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
V(ISET1)
Output current set voltage
V(LOWV) ≤ VI(BAT) ≤ VO(REG),
V(VCC) ≥ VI(BAT) + V (DO-MAX)
K(ISET1)
Output current set factor
VLOWV ≤ VI(BAT) < VO(REG) ,
V(VCC) ≥ VI(BAT) + V(DO-MAX)
MIN
TYP
1
1000
MAX
UNIT
V
V/A
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
VLOWV
Precharge to fast-charge transition voltage
threshold, BAT
t
Deglitch time for precharge to fast charge
transition
IOPRECHG
V(ISET2)
K(ISET2)
Precharge current set factor
68
71.4
75
%VO(REG)
Rising voltage;
tRISE, tFALL = 100 ns, 2-mV overdrive
20
30
40
ms
Precharge range
VI(BAT) < VLOWV, t < tPRECHG
15
200
mA
Precharge set voltage, ISET2
VI(BAT) < VLOWV, t < tPRECHG
10 mV ≤ VIREG-PRE ≤ 100 mV,
V
VIREG-PRE
6
Voltage regulated across RSNS-Accuracy
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IREG*PRE
100
mV
1000
V/A
(1)
+ 0.1V
RSET2
1000,
–20%
Where
1.0 kΩ ≤ RSET2 ≤ 10 kΩ, Select RSET2
to program VIREG-PRE,
VIREG-PRE (Measured) = IOPRE-CHG × RSNS
(–20% to 20% excludes errors due to RSET2
and RSNS tolerances)
20%
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: bq24120 bq24123 bq24125
bq24120, bq24123, bq24125
www.ti.com
SLUS688H – MARCH 2006 – REVISED NOVEMBER 2015
Electrical Characteristics (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
mA
CHARGE TERMINATION (CURRENT TAPER) DETECTION
ITERM
Charge current termination detection range
VI(BAT) > VOREG- VRCH
VTERM
Charge termination detection set voltage,
ISET2
VI(BAT) > VOREG- VRCH
K(ISET2)
Termination current set factor
tdg-TERM
15
100
mV
1000
Charger termination accuracy
VI(BAT) > VOREG- VRCH
Deglitch time for charge termination
Both rising and falling,
2-mV overdrive tRISE, tFALL = 100 ns
–20%
V/A
20%
20
30
40
ms
TEMPERATURE COMPARATOR AND VTSB BIAS REGULATOR
%LTF
Cold temperature threshold, TS, % of bias
VLTF = VO(VTSB) × % LTF/100
72.8%
73.5%
74.2%
%HTF
Hot temperature threshold, TS, % of bias
VHTF = VO(VTSB) × % HTF/100
33.7%
34.4%
35.1%
%TCO
Cutoff temperature threshold, TS, % of
bias
VTCO = VO(VTSB) × % TCO/100
28.7%
29.3%
29.9%
0.5%
1.0%
1.5%
20
30
40
LTF hysteresis
tdg-TS
Deglitch time for temperature fault, TS
Both rising and falling,
2-mV overdrive tRISE, tFALL = 100 ns
VO(VTSB)
TS bias output voltage
VCC > VIN(min),
I(VTSB) = 10 mA 0.1 μF ≤ CO(VTSB) ≤ 1 μF
VO(VTSB)
TS bias voltage regulation accuracy
VCC > IN(min),
I(VTSB) = 10 mA 0.1 μF ≤ CO(VTSB) ≤ 1 μF
ms
3.15
–10%
V
10%
BATTERY RECHARGE THRESHOLD
VRCH
tdg-RCH
Recharge threshold voltage
Below VOREG
75
100
125
mV/cell
Deglitch time
VI(BAT) < decreasing below threshold,
tFALL = 100 ns 10-mV overdrive
20
30
40
ms
STAT1, STAT2, AND PG OUTPUTS
VOL(STATx)
Low-level output saturation voltage, STATx
IO = 5 mA
0.5
VOL(PG)
Low-level output saturation voltage, PG
IO = 10 mA
0.1
V
CE , CELLS INPUTS
VIL
Low-level input voltage
IIL = 5 μA
VIH
High-level input voltage
IIH = 20 μA
0
0.4
1.3
VCC
V
TTC INPUT
tPRECHG
Precharge timer
tCHARGE
Programmable charge timer range
t(CHG) = C(TTC) × K(TTC)
Charge timer accuracy
0.01 μF ≤ C(TTC) ≤ 0.18 μF
KTTC
Timer multiplier
CTTC
Charge time capacitor range
VTTC_EN
TTC enable threshold voltage
1440
1800
25
-10%
2160
s
572
minutes
10%
2.6
0.01
V(TTC) rising
min/nF
0.22
200
μF
mV
SLEEP COMPARATOR
VSLP-ENT
Sleep-mode entry threshold
VSLP-EXIT
Sleep-mode exit hysteresis,
tdg-SLP
2.3 V ≤ VI(OUT) ≤ VOREG, for 1 or 2 cells
VCC ≤ VIBAT
+5 mV
VCC ≤ VIBAT
+75 mV
VI(OUT) = 12.6 V, RIN = 1kΩ,
bq24125 (2)
VCC ≤ VIBAT
–4 mV
VCC ≤ VIBAT
+73 mV
40
160
2.3 V ≤ VI(OUT)≤ VOREG
VCC decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive,
PMOS turns off
Deglitch time for sleep mode
VCC decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive,
STATx pins turn off
V
mV
μs
5
20
30
40
3.50
ms
UVLO
VUVLO-ON
(2)
IC active threshold voltage
VCC rising
3.15
3.30
IC active hysteresis
VCC falling
120
150
V
mV
For bq24125 only. RIN is connected between IN and PGND pins and needed to ensure sleep entry.
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Electrical Characteristics (continued)
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM
Internal P-channel MOSFET on-resistance
Internal N-channel MOSFET on-resistance
fOSC
7 V ≤ VCC ≤ VCC(max)
400
4.5 V ≤ VCC ≤ 7 V
500
7 V ≤ VCC ≤ VCC(max)
130
4.5 V ≤ VCC ≤ 7 V
mΩ
150
Oscillator frequency
1.1
Frequency accuracy
–9%
MHz
9%
DMAX
Maximum duty cycle
100%
DMIN
Minimum duty cycle
tTOD
Switching delay time (dead time)
20
ns
tsyncmin
Minimum synchronous FET on time
60
ns
0%
Synchronous FET minimum current-off
threshold (3)
50
400
mA
BATTERY DETECTION
IDETECT
Battery detection current during time-out
fault
VI(BAT) < VOREG – VRCH
IDISCHRG1
Discharge current
tDISCHRG1
Discharge time
IWAKE
tWAKE
2
mA
VSHORT < VI(BAT) < VOREG – VRCH
400
μA
VSHORT < VI(BAT) < VOREG – VRCH
1
s
Wake current
VSHORT < VI(BAT) < VOREG – VRCH
2
mA
Wake time
VSHORT < VI(BAT) < VOREG – VRCH
0.5
s
IDISCHRG2
Termination discharge current
Begins after termination detected,
VI(BAT) ≤ VOREG
400
μA
tDISCHRG2
Termination time
262
ms
OUTPUT CAPACITOR
COUT
Required output ceramic capacitor range
from SNS to PGND, between inductor and
RSNS
CSNS
Required SNS capacitor (ceramic) at SNS
pin
4.7
10
μF
47
μF
0.1
PROTECTION
Threshold over VOREG to turn off P-channel
MOSFET, STAT1, and STAT2 during charge
or termination states
110
117
2.6
3.6
4.5
A
Short-circuit voltage threshold, BAT
VI(BAT) falling
1.95
2
2.05
V/cell
ISHORT
Short-circuit current
VI(BAT) ≤ VSHORT
TSHTDWN
Thermal trip
VOVP
OVP threshold voltage
ILIMIT
Cycle-by-cycle current limit
VSHORT
35
%VO(REG)
65
165
Thermal hysteresis
(3)
121
mA
°C
10
N-channel always turns on for approximately 60 ns and then turns off if current is too low.
7.6 Dissipation Ratings
PACKAGE
RHL
(1)
8
(1)
ΘJA
ΘJC
TA < 40°C
POWER RATING
DERATING FACTOR
ABOVE TA = 40°C
46.87°C/W
2.15°C/W
1.81 W
0.021 W/°C
This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
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7.7 Typical Characteristics
See Figure 17 for a 1-cell application test circuit schematic and Figure 21 for the standalone cells application test circuits
schematic.
100
100
VI = 5 V
90
Efficiency - %
Efficiency - %
90
VI = 9 V
Vbat = 8.4 V
Vbat = 4.2 V
80
VI = 16 V
70
60
VI = 16 V
80
70
60
50
50
0
1
Charge Current Ibat - A
2
0
1
Charge Current Ibat - A
Figure 2. Efficiency 2-Cells
Figure 1. Efficiency 1-Cell
CH3
1.38 A
CH3
200 mA/div
2
CH3 = Inductor Current
CH3
500 mA
CH3
500 mA/div
CH3 = Inductor Current
CH1 = BAT
CH1
8.4 V
CH1
5 V/div
CH1 = BAT
CH1
2 V/div
CH1
3.8 V
CH2 = OUT
CH2 = OUT
CH2
5 V/div
CH2
16 V
CH2
9V
CH2
10 V/div
t = Time = 400 ns/div
t - Time = 400 ns/div
Figure 3. Switching Waveforms in Fast Charge Mode
CH1 = BAT
CH1
2 V/div
Figure 4. Switching Waveforms in Voltage Regulation Mode
CH1
4.2 V
CH3 = Inductor Current
CH3
200 mA/div
CH3
480 mA
CH1 = BAT
CH1
2 V/div
CH1
3.8 V
CH3 = Inductor Current
CH3
1.3 A
CH2 = OUT
CH2
5V
CH2
2 V/div
CH2 = OUT
CH2
5V
CH3
500 mA/div
20 ns
35 ns
CH2
5 V/div
t = Time = 1 ms/div
t = Time = 50 ns/div
Figure 5. Dead Time
Figure 6. Soft Start Waveforms
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Typical Characteristics (continued)
See Figure 17 for a 1-cell application test circuit schematic and Figure 21 for the standalone cells application test circuits
schematic.
60
50
Level [dBμV]
40
30
20
10
0
-10
30M
50M
70M
100M
Frequency [Hz]
200M
300M
500M
700M
1G
16 V, 1 A
Figure 7. Typical Radiated EMI Performance Measured on EVM
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8 Detailed Description
8.1 Overview
The bqSWITCHER supports a precision Li-ion or Li-polymer charging system for single cell or two cell
applications. See Figure 16 and Figure 8 for a typical charge profile.
The bq2412X has enhanced EMI performance that helps minimize the number of components needed to meet
the FCC-B Standard. The rise time of the OUT pin was slowed down to minimize the radiated EMI.
Precharge
Phase
Voltage Regulation and
Charge Termination Phase
Current Regulation Phase
Regulation V oltage
Regulation Current
Charge Voltage
VLOW
VSHORT
Charge Current
Precharge
and Termination
ISHORT
UDG-04037
Programmable
Safety Timer
Precharge
Timer
Figure 8. Typical Charging Profile
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8.2 Functional Block Diagram
Protection PMOS FET is OFF when not charging
or in SLEEP to prevent discharge of battery
when IN < BAT
Rsns
Sense FET
IN
Poff VCC PG
CHARGE
SLEEP
10
Synch
V(150 mA)
VCC-6V
PGND
VCC
Sense FET
Vuvlo UVLO/POR
POR
Icntrl
6V
VTSB
VTSB
Co
10 F
Temp
VCC
TG
VCC-6V
V(3.6A)
2.1V
Pack-
PGND
VCC
PkILim
Voltage
Reference
+
H
OUT
Isynch
BG
TG
Pack+
Lo
OUT
IN
VIN
I
VCC/10
RAMP
(Vpp=VCC/10)
Gate
Drive
to FB
FB
SPIN
ONLY
BG
SYNCH
VCC-6V
OSC
Q S
MOD
MOD
RAMP
Q R
VCC
OVP
PkILim or OVP
TIMEOUT F AULT
SUSPEND
TERM
UVLO/POR
SNS
VCC
*
TIMEOUT
COMPENSA TION
+
-
Ibat Reg
+
-
1k
PG
SUSPEND
SLEEP
VCC
BAT
+
-
+
CLAMP
VCC
VCC
UVLO/
POR
1V
50 mV
VTSB
CE
CE
BAT
Vbat Reg
+
-
CONTROL
LOGIC
SNS+
VCC
LowV
FB
SPIN
20uA
20uA
Term_Det
TERM
SLEEP
SUSPEND
1C
Vreg
VSHORT
Wake
+
-
ISET1
FASTCHG
Disable
WAKE
PkILim
VTSB
FB
1V
DISCHARGE
CELLS (bq24123)
FB (bq24125)
N/C (bq24120)
2C
BAT
BAT_PRS_
disch
CHARGE
VCC
2.1V
Vrch
(STATE
MACHINE)
VCC
BAT
Charge
RSET1
PRE-CHARGE
STAT1
SYNCH
Charge
0.1V
Discharge
SLEEP
SNS
+
1k
-
Vovp
OVP
BAT
OVP
STAT2
2.1V
TERM
VCC
Vrch 30ms
Dgltch
DSABL_TERM
0.25V
1V
TTC
TIMER CLK
Term &
Timer
Disable
0.75V
TIMER
FF CHAIN
0.5V
PRE-CHG
TIMEOUT
VSS
RESET
FAST CHG
TIMEOUT
30ms
Dgltch
BAT_PRS_dischg
BAT
ISET2
PRE-CHG
Disable
RSET2
+
-
FASTCHG
Disable
VTSB
0.1V
LowV
VSHORT
+
-
30ms
dgltch
Term_Det
VTSB
TS
LTF
SUSPEND
TS
SPIN
TEMP
SUSPEND
HTF
TCO
bqSWITCHER
bq2410x
*Patent Pending #36889
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8.3 Feature Description
8.3.1 PWM Controller
The bq2412X provides an integrated fixed 1MHz frequency voltage-mode controller with Feed-Forward function
to regulate charge current or voltage. This type of controller is used to help improve line transient response,
thereby simplifying the compensation network used for both continuous and discontinuous current conduction
operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that
provides enough phase boost for stable operation, allowing the use of small ceramic capacitors with very low
ESR. There is a 0.5V offset on the bottom of the PWM ramp to allow the device to operate between 0% to 100%
duty cycle.
The internal PWM gate drive can directly control the internal PMOS and NMOS power MOSFETs. The high-side
gate voltage swings from VCC (when off), to VCC-6 (when on and VCC is greater than 6V) to help reduce the
conduction losses of the converter by enhancing the gate an extra volt beyond the standard 5V. The low-side
gate voltage swings from 6V, to turn on the NMOS, down to PGND to turn it off. The bq2412X has two back to
back common-drain P-MOSFETs on the high side. An input P-MOSFET prevents battery discharge when IN is
lower than BAT. The second P-MOSFET behaves as the switching control FET, eliminating the need of a
bootstrap capacitor.
Cycle-by-cycle current limit is sensed through the internal high-side sense FET. The threshold is set to a nominal
3.6A peak current. The low-side FET also has a current limit that decides if the PWM Controller will operate in
synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side NMOS
before the current reverses, preventing the battery from discharging. Synchronous operation is used when the
current of the low-side FET is greater than 100mA to minimize power losses.
8.3.2 Temperature Qualification
The bqSWITCHER continuously monitors battery temperature by measuring the voltage between the TS pin and
VSS pin. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop
this voltage. The bqSWITCHER compares this voltage against its internal thresholds to determine if charging is
allowed. To initiate a charge cycle, the battery temperature must be within the V(LTF)-to-V(HTF) thresholds. If
battery temperature is outside of this range, the bqSWITCHER suspends charge and waits until the battery
temperature is within the V(LTF)-to-V(HTF) range. During the charge cycle (both precharge and fast charge), the
battery temperature must be within the V(LTF)-to-V(TCO) thresholds. If battery temperature is outside of this range,
the bqSWITCHER suspends charge and waits until the battery temperature is within the V(LTF)-to-V(HTF) range.
The bqSWITCHER suspends charge by turning off the PWM and holding the timer value (that is, timers are not
reset during a suspend condition). Note that the bias for the external resistor divider is provided from the VTSB
output. Applying a constant voltage between the V(LTF)-to-V(HTF) thresholds to the TS pin disables the
temperature-sensing feature.
VO(VTSB) ´ RTHCOLD ´ RTHHOT ´
1 - 1
VLTF
VHTF
RT2 =
RTHHOT ´
(
VO(VTSB)
-1
VHTF
VO(VTSB)
-1
VLTF
RT1 =
1 +
1
RT2 RTHCOLD
)
- RTHCOLD ´
(
VO(VTSB)
-1
VLTF
)
Where:
VLTF = VO(VTSB) ´ % LTF¸100 / 100
VHTF = VO(VTSB) ´ % HTF¸100 / 100
(1)
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Feature Description (continued)
VCC
Charge Suspend
Charge Suspend
V(LTF)
V(HTF)
V(TCO)
Temperature Range
to Initiate Charge
Charge Suspend
Temperature Range
During Charge Cycle
Charge Suspend
VSS
Figure 9. TS Pin Thresholds
8.3.3 Battery Preconditioning (Precharge)
On power up, if the battery voltage is below the VLOWV threshold, the bqSWITCHER applies a precharge current,
IPRECHG, to the battery. This feature revives deeply discharged cells. The bqSWITCHER activates a safety timer,
tPRECHG, during the conditioning phase. If the VLOWV threshold is not reached within the timer period, the
bqSWITCHER turns off the charger and enunciates FAULT on the STATx pins. In the case of a FAULT
condition, the bqSWITCHER reduces the current to IDETECT. IDETECT is used to detect a battery replacement
condition. Fault condition is cleared by POR or battery replacement.
The magnitude of the precharge current, IO(PRECHG), is determined by the value of programming resistor, R(ISET2),
connected to the ISET2 pin.
K (ISET2) V (ISET2)
I O(PRECHG) +
R(ISET2) R(SNS)
ǒ
Ǔ
where
•
•
•
•
RSNS is the external current-sense resistor
V(ISET2) is the output voltage of the ISET2 pin
K(ISET2) is the V/A gain factor
V(ISET2) and K(ISET2) are specified in the Electrical Characteristics table.
(2)
8.3.4 Battery Charge Current
The battery charge current, IO(CHARGE), is established by setting the external sense resistor, R(SNS), and the
resistor, R(ISET1), connected to the ISET1 pin.
In order to set the current, first choose R(SNS) based on the regulation threshold VIREG across this resistor. The
best accuracy is achieved whe the VIREG is between 100mV and 200mV.
V IREG
R (SNS) +
I OCHARGE
(3)
If the results is not a standard sense resistor value, choose the next larger value. Using the selected standard
value, solve for VIREG. Once the sense resistor is selected, the ISET1 resistor can be calculated using the
following equation:
K
´V
RISET1 = ISET1 ISET1
RSNS ´ ICHARGE
(4)
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Feature Description (continued)
8.3.5 Battery Voltage Regulation
The voltage regulation feedback occurs through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bqSWITCHER monitors the battery-pack voltage between the BAT and VSS pins. The
bqSWITCHER is offered in a fixed single-cell voltage version (4.2 V) and as a one-cell or two-cell version
selected by the CELLS input. A low or floating input on the CELLS selects single-cell mode (4.2 V) while a highinput through a resistor selects two-cell mode (8.4 V).
8.3.6 Charge Termination And Recharge
The bqSWITCHER monitors the charging current during the voltage regulation phase. Once the termination
threshold, ITERM, is detected, the bqSWITCHER terminates charge. The termination current level is selected by
the value of programming resistor, R(ISET2), connected to the ISET2 pin.
K (ISET2) V TERM
I TERM +
R(ISET2) R(SNS)
ǒ
Ǔ
where
•
•
•
•
R(SNS) is the external current-sense resistor
VTERM is the output of the ISET2 pin
K(ISET2) is the A/V gain factor
VTERM and K(ISET2) are specified in the Electrical Characteristics table
(5)
As a safety backup, the bqSWITCHER also provides a programmable charge timer. The charge time is
programmed by the value of a capacitor connected between the TTC pin and GND by the following formula:
t CHARGE + C(TTC) K(TTC)
where
•
•
A
•
•
•
•
C(TTC) is the capacitor connected to the TTC pin
K(TTC) is the multiplier
(6)
new charge cycle is initiated when one of the following conditions is detected:
The battery voltage falls below the VRCH threshold.
Power-on reset (POR), if battery voltage is below the VRCH threshold
CE toggle
TTC pin, described as follows.
In order to disable the charge termination and safety timer, the user can pull the TTC input below the VTTC_EN
threshold. Going above this threshold enables the termination and safety timer features and also resets the timer.
Tying TTC high disables the safety timer only.
8.3.7 Sleep Mode
The bqSWITCHER enters the low-power sleep mode if the VCC pin is removed from the circuit. This feature
prevents draining the battery during the absence of VCC.
8.3.8 Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 1. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates that the
open-drain transistor is turned off.
Table 1. Status Pins Summary
STAT1
STAT2
Charge-in-progress
CHARGE STATE
ON
OFF
Charge complete
OFF
ON
Charge suspend, timer fault, overvoltage, sleep mode, battery absent
OFF
OFF
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PG Output
The open-drain PG (power good) indicates when the AC-to-DC adapter (that is, VCC) is present. The output turns
on when sleep-mode exit threshold, VSLP-EXIT, is detected. This output is turned off in the sleep mode. The PG pin
can be used to drive an LED or communicate to the host processor.
8.3.10
CE Input (Charge Enable)
The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the
charge and a high-level VCC signal disables the charge. A high-to-low transition on this pin also resets all timers
and fault conditions. Note that the CE pin should not be tied to VTSB. This may create power-up issues.
8.3.11 Timer Fault Recovery
As shown in Figure 16, bqSWITCHER provides a recovery method to deal with timer fault conditions. The
following summarizes this method.
Condition 1 VI(BAT) above recharge threshold (VOREG - VRCH) and timeout fault occurs.
Recovery method: bqSWITCHER waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the
recharge threshold, the bqSWITCHER clears the fault and enters the battery absent detection routine. A POR or
CE toggle also clears the fault.
Condition 2 Charge voltage below recharge threshold (VOREG – VRCH) and timeout fault occurs
Recovery method: Under this scenario, the bqSWITCHER applies the IDETECT current. This small current is used
to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the battery voltage goes above the recharge threshold, then the bqSWITCHER disables the IDETECT
current and executes the recovery method described in Condition 1. Once the battery falls below the recharge
threshold, the bqSWITCHER clears the fault and enters the battery absent detection routine. A POR or CE toggle
also clears the fault.
8.3.12 Output Overvoltage Protection (Applies to All Versions)
The bqSWITCHER provides a built-in overvoltage protection to protect the device and other components against
damages if the battery voltage gets too high, as when the battery is suddenly removed. When an overvoltage
condition is detected, this feature turns off the PWM and STATx pins. The fault is cleared once VIBAT drops to the
recharge threshold (VOREG - VRCH).
8.3.13 Battery Detection
For applications with removable battery packs, bqSWITCHER provides a battery absent detection scheme to
reliably detect insertion and/or removal of battery packs.
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POR or VRCH
Detection routine runs on power up
and if VBAT drops below refresh
threshold due to removing battery
or discharging battery.
Yes
Enable
I(DETECT)
for t(DETECT)
VI(BAT)
VO(REG)
−VRCH
Yes
BATTERY
ABSENT
Figure 10. Battery Detection for bq2412x ICs
The voltage at the BAT pin is held above the battery recharge threshold, VOREG – VRCH, by the charged battery
following fast charging. When the voltage at the BAT pin falls to the recharge threshold, either by a load on the
battery or due to battery removal, the bqSWITCHER begins a battery absent detection test. This test involves
enabling a detection current, IDISCHARGE1, for a period of tDISCHARGE1 and checking to see if the battery voltage is
below the short circuit threshold, VSHORT. Following this, the wake current, IWAKE is applied for a period of tWAKE
and the battery voltage is checked again to ensure that it is above the recharge threshold. The purpose of this
current is to attempt to close an open battery pack protector, if one is connected to the bqSWITCHER.
Passing both of the discharge and charge tests indicates a battery absent fault at the STAT pins. Failure of either
test starts a new charge cycle. For the absent battery condition, typically the voltage on the BAT pin rises and
falls between 0V and VOVP thresholds indefinitely.
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VBAT
Battery
Connected
VOREG
No
Battery
Detected
2V/cell
No
Battery
Detected
Yes
Battery
Detected
IWAKE
IBAT
- IDISCHRG1
t DISCHRG1
tWAKE
t DISCHRG1
Figure 11. Battery Detect Timing Diagram
8.3.13.1 Battery Detection Example
In order to detect a no battery condition during the discharge and wake tests, the maximum output capacitance
should not exceed the following:
a. Discharge (IDISCHRG1 = 400 μA, tDISCHRG1 = 1s, VSHORT = 2V)
I
´t
CMAX _ DIS = DISCHRG1 DISCHRG1
VOREG - VSHORT
CMAX _ DIS =
400 mA ´ 1 s
4.2 V - 2 V
CMAX _ DIS = 182 mF
(7)
b. Wake (IWAKE = 2 mA, tWAKE = 0.5 s, VOREG – VRCH = 4.1V)
IWAKE ´ t WAKE
CMAX _ WAKE =
(VOREG - VRCH ) - 0 V
CMAX _ WAKE =
2 mA ´ 0.5 s
(4.2 V - 0.1 V ) - 0 V
CMAX _ WAKE = 244 mF
(8)
Based on these calculations the recommended maximum output capacitance to ensure proper operation of the
battery detection scheme is 100 μF which will allow for process and temperature variations.
Figure 12 shows the battery detection scheme when a battery is inserted. Channel 3 is the output signal and
Channel 4 is the output current. The output signal switches between VOREG and GND until a battery is inserted.
Once the battery is detected, the output current increases from 0A to 1.3A, which is the programmed charge
current for this application.
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Figure 12. Battery Detection Waveform When a Battery is Inserted
Figure 13 shows the Battery Detection scheme when a battery is removed. Channel 3 is the output signal and
Channel 4 is the output current. When the battery is removed, the output signal goes up due to the stored energy
in the inductor and it crosses the VOREG – VRCH threshold. At this point the output current goes to 0A and the IC
terminates the charge process and turns on the IDISCHG2 for tDISCHG2. This causes the output voltage to fall down
below the VOREG – VRCHG threshold triggering a Battery Absent condition and starting the Battery Detection
scheme.
Figure 13. Battery Detection Waveform When a Battery is Removed
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8.3.14 Current Sense Amplifier
BQ2412X family offers a current sense amplifier feature that translates the charge current into a DC voltage.
Figure 14 is a block diagram of this feature.
OUT
ICHARGE
SNS
RSNS
+
KISET2
BAT
+
-
+
FASTCHG
Disable
ISET2
RISET2
Figure 14. Current Sense Amplifier
The voltage on the ISET2 pin can be used to calculate the charge current. Equation 9 shows the relationship
between the ISET2 voltage and the charge current:
VISET2 ´ K (ISET2)
ICHARGE =
RSNS ´ RISET2
(9)
This feature can be used to monitor the charge current during the current regulation phase (Fastcharge only) and
the voltage regulation phase. The schematics for the application circuit for this waveform is shown in Figure 21
CH3 = Inductor Current
CH3
500 mA/div
CH1 = ISET2
CH3
0A
CH1
200 mV/div
CH1
0V
CH2
16 V
CH2 = OUT
CH2
10 V/div
t = Time = 200 ms/div
Figure 15. Current Sense Amplifier
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8.4 Device Functional Modes
Figure 16 shows the operational flow chart for a typical charge operation.
POR
Check for battery
Presence
Battery
Detected?
No
Indicate BATTERY
ABSENT
Yes
Suspend charge
TS pin
in LTF to HTF
range?
No
Indicate CHARGE
SUSPEND
Yes
VBAT
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