BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168
SLUSAO0H – NOVEMBER 2011 – REVISED JULY 2022
BQ2416xx 2.5-A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with
Power Path Management and I2C Interface
1 Features
3 Description
•
The BQ24160, BQ24160A, BQ24161, BQ24161B,
BQ24163, and BQ24168 are highly integrated singlecell Li-ion battery charger and system power path
management devices targeted for space-limited,
portable applications with high-capacity batteries.
The single-cell charger has dual inputs which allow
operation from either a USB port or a higher-power
input supply (that is, AC adapter or wireless charging
input) for a versatile solution. The two inputs are fully
isolated from each other and are easily selectable
using the I2C interface.
•
•
•
•
•
•
High-efficiency switched-mode charger with
separate power path control
– Instantly start up system from a deeply
discharged battery or no battery
Compatible with MaxLife™ technology for faster
charging when used in conjunction with BQ27530
Dual input, integrated FET charger for up to 2.5-A
charging
– 20-V input rating, with overvoltage protection
(OVP)
• 6.5 V for USB input up to 1.5 A
• 10.5 V for IN input (BQ24160, BQ24160A,
BQ24161, BQ24163) up to 2.5 A
• 6.5 V for IN input (BQ24168) up to 2.5 A
Safe and accurate battery management functions
– 1% battery regulation accuracy
– 10% charge current accuracy
Charge parameters programmed using I2C
interface
Voltage-based, NTC monitoring input
– JEITA compatible (BQ24160, BQ24160A,
BQ24161B, BQ24163, BQ24168)
Available in small 2.8-mm × 2.8-mm 49-ball WCSP
or 4-mm × 4-mm VQFN-24 packages
2 Applications
•
•
•
•
The power path management feature allows the
BQ2416xx to power the system from a highefficiency DC-DC converter while simultaneously and
independently charging the battery. The power path
management architecture enables the system to run
with a defective or absent battery pack and enables
instant system turnon even with a totally discharged
battery or no battery.
Device Information
PART NUMBER
BQ2416xx
(1)
PACKAGE(1)
BODY SIZE (NOM)
VQFN (24)
4.00 mm × 4.00 mm
DSBGA (49)
2.80 mm × 2.80 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Handheld products
Portable media players
Portable equipment
Netbook and portable internet devices
Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168
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SLUSAO0H – NOVEMBER 2011 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 Handling Ratings.........................................................7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................8
7.5 Electrical Characteristics.............................................8
7.6 Typical Characteristics.............................................. 11
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................26
8.5 Programming............................................................ 27
8.6 Register Maps...........................................................29
9 Application and Implementation.................................. 34
9.1 Application Information............................................. 34
9.2 Typical Application.................................................... 34
10 Power Supply Recommendations..............................38
10.1 Requirements for SYS Output................................ 38
10.2 Requirements for Charging.....................................38
11 Layout........................................................................... 39
11.1 Layout Guidelines................................................... 39
11.2 Layout Example...................................................... 40
12 Device and Documentation Support..........................41
12.1 Device Support....................................................... 41
12.2 Receiving Notification of Documentation Updates..41
12.3 Support Resources................................................. 41
12.4 Trademarks............................................................. 41
12.5 Electrostatic Discharge Caution..............................41
12.6 Glossary..................................................................41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (November 2015) to Revision H (July 2022)
Page
• Changed ITERM specification...............................................................................................................................8
Changes from Revision F (July 2014) to Revision G (November 2015)
Page
• Deleted hyperlink to unpublished application note SLUA727........................................................................... 26
Changes from Revision E (November 2013) to Revision F (January 2014)
Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Changed the Ordering Information table to the Device Comparison Table........................................................ 4
• Changed to VBAD_SOURCE include values for "During Bad Source Detection".................................................... 8
• Changed the Functional Block Diagram. Changed the device numbers above D+/D- and PSEL....................14
• Changed the PWM Controller in Charge Mode section to include the soft-start function.................................15
• Changed the Battery Charging Process section. New text added starting with "The BQ2416xx monitors the
charging current..".............................................................................................................................................16
• Changed the Input Source Connected section................................................................................................. 17
• Changed the Input Source Connected section................................................................................................. 19
• Added the Reverse Boost (Boost Back) Prevention Circuit section................................................................. 25
Changes from Revision D (November 2012) to Revision E (November 2013)
Page
• Added Feature: Compatible with MaxLife Technology for Faster Charging When Used in Conjunction with
BQ27530.............................................................................................................................................................1
• Changed From: QFN-24 Package To: VQFN-24 Package throughout the data sheet....................................... 1
Changes from Revision C (October 2012) to Revision D (November 2012)
Page
• Changed the Ordering Information table to include the WSCP package for BQ24161BRGR and
BQ24161BYFF................................................................................................................................................... 4
2
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SLUSAO0H – NOVEMBER 2011 – REVISED JULY 2022
Changes from Revision B (September 2012) to Revision C (October 2012)
Page
• Changed the Ordering Information table to include BQ24160A......................................................................... 4
Changes from Revision A (March 2012) to Revision B (September 2012)
Page
• Changed the Ordering Information table to include BQ24161B......................................................................... 4
• Changed text From: "battery FET (Q6)" To: "battery FET (Q4)" in the Battery Only Connected section..........18
• Changed From: VWARM < VTS < VHOT To: VWARM > VTS > VHOT, and Changed From: VCOLD < VTS < VCOOL To:
VCOLD > VTS > VCOOL in the External NTC Monitoring (TS) section................................................................. 21
• Changed Figure 11-1 ....................................................................................................................................... 40
Changes from Revision * (November 2011) to Revision A (March 2012)
Page
• Changed the USB Pin numbers in the YFF pachkage for bq24160/3 From: A5-A6 To: A5-A7.......................... 4
• Changed VBATREG - Voltage regulation accuracy ...............................................................................................8
• Changed Figure 9-1 .........................................................................................................................................34
• Changed Figure 9-2 .........................................................................................................................................34
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SLUSAO0H – NOVEMBER 2011 – REVISED JULY 2022
5 Device Comparison Table
USB OVP
IN OVP
USB DETECTION
TIMERS
(Safety and
Watchdog)
NTC
MONITORING
VBATSHRT/
IBATSHRT
VMINSYS
BQ24160
6.5V
10.5V
D+/D–
Yes
JEITA
3.0V
50mA
3.5V
BQ24160A
6.5V
10.5V
D+/D–
No
JEITA
3.0V
50mA
3.5V
BQ24161
6.5V
10.5V
PSEL (0=1.5A,
1=100mA)
Yes
Standard
2.0V
50mA
3.5V
BQ24161B
6.5V
10.5V
PSEL (0=1.5A,
1=500mA)
Yes
JEITA
3.0V
50mA
3.5V
BQ24163
6.5V
10.5V
D+/D–
Yes
JEITA
2.0V
50mA
3.2V
BQ24168
6.5V
6.5V
PSEL (0=1.5A,
1=100mA)
No
JEITA
2.0V
50mA
3.5V
PART NUMBER(1) (2)
(1)
(2)
Each of the above are available in as YFF and RGE packages with the following options:
R - tabed and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
20
19
19
21
20
22
21
BQ24160
BQ24163
23
22
3
24
23
SCL
BOOT
BOOT
2
PMIDI
PMIDI
D+
IN
IN
18 SW
USB
USB
1
PMIDU
PMIDU
D-
CD
CD
24
6 Pin Configuration and Functions
N.C.
1
18 SW
17 PGND
PSEL
2
17 PGND
16 SGND
SCL
3
15 PGND
SDA
4
16 SGND
BQ24161
BQ24161B
BQ241618
15 PGND
SDA
4
PGND
5
14 SYS
GND
5
14 SYS
DRV
6
13 SYS
DRV
6
13 SYS
BAT
12 BAT
11
10 BGATE
STAT
TS
8
/BATGD
9
7
12 BAT
TS
BAT
9
STAT
11
8
INT
10 BGATE
7
Figure 6-1. RGE Package VQFN 24 Pins Top View
4
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SLUSAO0H – NOVEMBER 2011 – REVISED JULY 2022
BQ24161
BQ24161B
BQ24168
(Top View)
BQ24160
BQ24163
(Top View)
1
2
3
4
5
A
IN
IN
IN
IN
B
PMIDI
PMIDI
PMIDI
C
SW
SW
D
PGND
E
6
7
IN
USB
USB
USB
PMIDI
PMIDI
PMIDU
PMIDU
PMIDU
SW
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PSEL
N.C.
CD
SDA
SCL
BOOT
SYS
SYS
SYS
SYS
BGATE
INT
DRV
BAT
BAT
BAT
BAT
TS
STAT
PGND
2
3
7
USB
USB
USB
A
IN
IN
IN
PMIDI
PMIDU
PMIDU
PMIDU
B
PMIDI
PMIDI
SW
SW
SW
SW
SW
C
SW
PGND
PGND
PGND
PGND
PGND
PGND
D
PGND
D+
D-
CD
SDA
SCL
BOOT
E
SYS
SYS
SYS
SYS
BGATE
INT
DRV
F
G
5
1
6
4
F
BAT
BAT
BAT
BAT
TS
STAT
PGND
G
Figure 6-2. YFF Package WCSP 49 Pins Top View
Table 6-1. Pin Functions
PIN
NAME
NO.
BQ24160, 3
NO.
BQ24161, 1B, 8
I/O
DESCRIPTION
YFF
RGE
YFF
RGE
G1-G4
11, 12
G1-G4
11, 12
I/O
Battery Connection – Connect to the positive terminal of the battery. Additionally, bypass BAT
to GND with at least a 1-μF capacitor.
BGATE
F5
10
F5
10
O
External Discharge MOSFET Gate Connection – BGATE drives an external P-Channel
MOSFET to provide a very low-resistance discharge path. Connect BGATE to the gate of the
external MOSFET. BGATE is low during high impedance mode and when no input is connected.
BOOT
E7
19
E7
19
I
High Side MOSFET Gate Driver Supply – Connect a 0.01-µF ceramic capacitor (voltage rating
> 10 V) from BOOT to SW to supply the gate drive for the high side MOSFETs.
CD
E4
24
E4
24
I
IC Hardware Chip Disable Input – Drive CD high to place the BQ2416xx in high-z mode. Drive
CD low for normal operation. Do not leave CD unconnected.
D+
E2
2
—
—
I
D–
E3
1
—
—
I
D+ and D– Connections for USB Input Adapter Detection – When a charge cycle is initiated
by the USB input, and a short is detected between D+ and D–, the USB input current limit is set
to 1.5 A. If a short is not detected, the USB100 mode is selected. The D+/D– detection has no
effect on the IN input.
DRV
F7
6
F7
6
O
Gate Drive Supply – DRV is the bias supply for the gate drive of the internal MOSFETs.
Bypass DRV to PGND with a 1-μF ceramic capacitor. DRV may be used to drive external loads
up to 10 mA. DRV is active whenever the input is connected and VSUPPLY > VUVLO and VSUPPLY
> (VBAT + VSLP)
A1- A4
21
A1- A4
21
I
Input power supply – IN is connected to the external DC supply (AC adapter or alternate
power source). Bypass IN to PGND with at least a 1-μF ceramic capacitor.
F6
7
F6
7
O
Status Output – INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete or the charger
is disabled. When a fault occurs, a 128-μs pulse is sent out as an interrupt for the host. INT
is enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail
through a 100-kΩ resistor to communicate with the host processor.
D1-D7,
E1, G7
5, 15,
16, 17
D1-D7,
E1, G7
5, 15,
16, 17
—
Ground terminal – Connect to the thermal pad (for VQFN only) and the ground plane of the
circuit.
BAT
IN
INT
PGND
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Table 6-1. Pin Functions (continued)
PIN
NAME
NO.
BQ24161, 1B, 8
I/O
DESCRIPTION
YFF
RGE
YFF
RGE
PMIDI
B1-B4
20
B1-B4
20
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power
Input – Bypass PMIDI to GND with at least a 4.7-μF ceramic capacitor. Use caution when
connecting an external load to PMIDI. The PMIDI output is not current limited. Any short on
PMIDI will damage the IC.
PMIDU
B5-B7
23
B5-B7
23
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for USB Input –
Bypass PMIDU to GND with at least a 4.7-μF ceramic capacitor. Use caution when connecting
an external load to PMIDU. The PMIDU output is not current limited. Any short on PMIDU will
damage the IC.
PSEL
—
—
E2
2
SCL
E6
3
E6
3
I
I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
SDA
E5
4
E5
4
I/O
I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
STAT
G6
8
G6
8
O
Status Output – STAT is an open-drain output that signals charging status and fault interrupts.
STAT pulls low during charging. STAT is high impedance when charging is complete or the
charger is disabled. When a fault occurs, a 128-μs pulse is sent out as an interrupt for the host.
STAT is enabled /disabled using the EN_STAT bit in the control register. Pull STAT up to a logic
rail thruogh an LED for visual indication or through a 10-kΩ resistor to communicate with the
host processor.
USB Source Detection Input – Drive PSEL high to indicate that a USB source is connected
to the USB input. When PSEL is high, the IC starts up with a 100 mA (BQ24161/8) or 500
mA (BQ24161B) input current limit for USB. Drive PSEL low to indicate that an AC Adapter is
connected to the USB input. When PSEL is low, the IC starts up with a 1.5 A input current limit
for USB. PSEL has no effect on the IN input. Do not leave PSEL unconnected.
SW
C1-C7
18
C1-C7
18
O
Inductor Connection – Connect to the switched side of the external inductor.
SYS
F1-F4
13, 14
F1-F4
13,14
I
System Voltage Sense and Charger FET Connection – Connect SYS to the system output at
the output bulk capacitors. Bypass SYS locally with at least 10 μF. A 47-μF bypass capacitor is
recommended for optimal transient response.
G5
9
G5
9
I
Battery Pack NTC Monitor – Connect TS to the center tap of a resistor divider from DRV to
GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA
compatibility (160, 161B, 163, 168 only). TS faults are reported by the I2C interface. See the
NTC Monitor section for more details on operation and selecting the resistor values. Connect TS
to DRV to disable the TS function.
A5-A7
22
A5-A7
22
I
USB Input Power Supply – USB is connected to the external DC supply (AC adapter or USB
port). Bypass USB to PGND with at least a 1-μF ceramic capacitor.
—
Pad
—
Pad
—
TS
USB
Thermal
Pad
6
NO.
BQ24160, 3
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There is an internal electrical connection between the exposed thermal pad and the PGND pin
of the device. The thermal pad must be connected to the same potential as the PGND pin on
the printed circuit board. Do not use the thermal pad as the primary ground input for the device.
PGND pin must be connected to ground at all times.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
–2
20
V
PMIDI, PMIDU, BOOT
–0.3
20
V
SW
–0.7
12
V
SDA, SCL, SYS, BAT, STAT, BGATE, DRV, TS, D+, D–, INT, PSEL, CD
–0.3
7
V
–0.3
7
V
IN, USB
Pin voltage range (with
respect to VSS)
BOOT to SW
Output current (continuous)
Input current (continuous)
Output sink current
SW
4.5
A
SYS, BAT
3.5
A
IN
2.75
A
USB
1.75
A
STAT
10
mA
INT
1
mA
Operating free-air temperature range
–40
85
Junction temperature, TJ
–40
125
Lead temperature (soldering, 10 s)
300
(1)
°C
°C
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
–65
150
°C
2
kV
500
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
VUSB
MIN
MAX
IN voltage range
4.2
18
IN operating voltage range (BQ24160/1/3)
4.2
10
IN operating voltage range (BQ24168)
4.2
6
USB voltage range
4.2
18
USB operating range
4.2
6
UNIT
V
V
IIN
Input current, IN input
2.5
A
IUSB
Input current USB input
1.5
A
ISYS
Output Current from SW, DC
3
A
2.5
A
IBAT
TJ
Charging
Discharging, using internal battery FET
Operating junction temperature range
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0
2.5
A
125
°C
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7.4 Thermal Information
BQ2416xx
THERMAL METRIC(1)
49 PINS (YFF)
24 PINS (RGE)
UNIT
θJA
Junction-to-ambient thermal resistance
49.8
32.6
°C/W
θJCtop
Junction-to-case (top) thermal resistance
0.2
30.5
°C/W
θJB
Junction-to-board thermal resistance
1.1
3.3
°C/W
ψJT
Junction-to-top characterization parameter
1.1
0.4
°C/W
ψJB
Junction-to-board characterization parameter
6.6
9.3
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
2.6
°C/W
(1)
For more information about traditional and new thermal metrics, see The IC Package Thermal Metrics Application Report.
7.5 Electrical Characteristics
Circuit of Figure 9-1, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY >
VBAT+VSLP, TJ = -40°C – 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VUVLO < VSUPPLY < VOVP and
VSUPPLY > VBAT+VSLP
PWM switching
ISUPPLY
Supply current for control (VIN or VUSB)
IBATLEAK
Leakage current from BAT to the Supply
0°C < TJ < 85°C, VBAT = 4.2V, VUSB = VIN = 0V
IBAT_HIZ
Battery discharge current in High Impedance mode,
(BAT, SW, SYS)
0°C< TJ < 85°C, VBAT = 4.2V, VSUPPLY = 5V or 0V,
SCL, SDA = 0 V or 1.8V, High-Z Mode
15
PWM NOT switching
mA
5
0°C < TJ < 85°C, High-Z Mode
175
μA
5
μA
55
μA
POWER-PATH MANAGEMENT
Charge Enabled, VBAT < VMINSYS
VSYS(REG)
System regulation voltage
BQ24160, 1, 1B, 8
3.60
3.7
3.3
3.4
3.5
VBATREG
+ 1.5%
VBATREG
+ 3.0%
VBATREG
+ 4.17%
BQ24160, 1, 1B, 8
3.4
3.5
3.62
V
BQ24163
3.1
3.2
3.3
V
BQ24163
Battery FET turned off (Charge Disabled, TS Fault or
Charging Terminated)
3.82
V
VMINSYS
Minimum system regulation voltage
Charge enabled, VBAT < VMINSYS,
Input current limit or VINDPM active
VBSUP1
Enter supplement mode threshold
VBAT > 2.5V
VBAT
–30mV
V
VBSUP2
Exit supplement mode threshold
VBAT > 2.5V
VBAT
–10mV
V
ILIM(discharge)
Current limit, discharge or supplement mode
Current monitored in internal FET only.
7
A
tDGL(SC1)
Deglitch time, SYS short circuit during discharge or
supplement mode
Measured from (VBAT – VSYS) = 300mV to BAT highimpedance
250
μs
tREC(SC1)
Recovery time, SYS short circuit during discharge or
supplement mode
60
ms
Battery range for BGATE and supplement mode
operation
2.5
4.5
V
BATTERY CHARGER
RON(BAT-SYS)
VBATREG
37
57
RGE pkg
50
70
Measured from BAT to SYS,
VBAT = 4.2V
Charge Voltage
Operating in voltage regulation, Programmable range
Voltage regulation accuracy
Fast charge current range
VBATSHRT ≤ VBAT < VBAT(REG) programmable range
Fast charge current accuracy
0°C to 125°C
VBATSHRT
Battery short circuit threshold
100mV Hysteresis
IBATSHRT
Battery short circuit current
VBAT < VBATSHRT
tDGL(BATSHRT)
Deglitch time for battery short circuit to fastcharge
transition
ICHARGE
ITERM
8
YFF pkg
Internal battery charger MOSFET on-resistance
Termination charge current accuracy
4.44
1%
550
2500
–10%
+10%
BQ24161, 3, 8
1.9
2.0
2.1
BQ24160, 1B
2.9
3.0
3.1
50
32
+40%
ITERM = 100mA
–20%
+20%
ITERM ≥ 150mA
–15%
Both rising and falling, 2mV overdrive, tRISE, tFALL = 100ns
VRCH
Recharge threshold voltage
Below VBATREG
mA
V
ms
–40%
Deglitch time for charge termination
V
mA
ITERM = 50mA
tDGL(TERM)
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–1%
mΩ
+15%
32
ms
120
mV
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7.5 Electrical Characteristics (continued)
Circuit of Figure 9-1, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY >
VBAT+VSLP, TJ = -40°C – 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tDGL(RCH)
Deglitch time
VBAT falling below VRCH, tFALL=100ns
32
ms
VDETECT
Battery detection threshold
During battery detection source cycle
3.3
V
During battery detection sink cycle
3.0
2.5
mA
250
ms
IDETECT
Battery detection current before charge done (sink
current)
Termination enabled (EN_TERM = 1)
tDETECT
Battery detection time
Termination enabled (EN_TERM = 1)
VIH
PSEL, CD Input high logic level
VIL
PSEL, CD Input low logic level
1.3
V
0.4
V
INPUT CURRENT LIMITING
IIN_USB
Input current limit threshold (USB input)
USB charge mode, VUSB = 5V,
DC Current pulled from SW
IUSBLIM = USB100
90
95
100
IUSBLIM = USB500
450
475
500
IUSBLIM = USB150
135
142.5
150
IUSBLIM = USB900
800
850
900
IUSBLIM = USB800
700
750
800
IUSBLIM = 1.5A
1250
1400
1500
IINLIM = 1.5A
IIN_IN
Input current limit threshold (IN input)
IN charge mode, VIN = 5V,
DC Current pulled from SW
1.35
1.5
1.65
IINLIM = 2.5A
2.3
2.5
2.8
VIN_DPM
Input based DPM threshold range
Charge mode, programmable via I2C, both inputs
4.2
4.76
–2
+2%
VIN_DPM threshold accuracy
mA
A
V
VDRV BIAS REGULATOR
VDRV
Internal bias regulator voltage
IDRV
DRV output current
VDO_DRV
DRV Dropout voltage (VSUPPLY – VDRV)
VSUPPLY > 5.45V
5
5.2
5.45
10
V
mA
ISUPPLY = 1A, VSUPPLY = 5V, IDRV = 10mA
450
mV
0.4
V
1
µA
STATUS OUTPUT ( STAT, INT)
VOL
Low-level output saturation voltage
IO = 10mA, sink current
IIH
High-level leakage current
VSTAT = VINT = 5V
VUVLO
IC active threshold voltage
VIN rising
3.6
3.8
VUVLO_HYS
IC active hysteresis
VIN falling from above VUVLO
120
150
VSLP
Sleep-mode entry threshold, VSUPPLY-VBAT
2.0V ≤VBAT ≤VBATREG, VIN falling
VSLP_EXIT
Sleep-mode exit hysteresis
2.0V ≤VBAT ≤VBATREG
Deglitch time for supply rising above VSLP+VSLP_EXIT
Rising voltage, 2mV over drive, tRISE = 100ns
PROTECTION
VBAD_SOURCE Bad source detection threshold
tDGL(BSD)
VBOVP
40
100
mV
100
175
mV
30
VOVP hysteresis
ms
VIN_DPM
– 80 mV
V
During Bad Source Detection
VIN_DPM
+ 80 mV
V
32
IN, VIN Rising (BQ24160/1/1B/3)
IN, VIN Rising (BQ24168)
VOVP(HYS)
0
40
Deglitch on bad source detection
Input supply OVP threshold voltage
V
mV
After Bad Source Detection completes
USB, VUSB Rising
VOVP
4
ms
6.3
6.5
6.7
10.3
10.5
10.7
6.3
6.5
6.7
1.025 ×
VBATREG
1.05 ×
Supply falling from VOVP
100
V
mV
1.075 ×
VBATREG
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger during charge
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
1
% of
VBATREG
tDGL(BOVP)
Battery OVP deglitch
BOVP fault shown in register once tDGL(BOVP) expires.
Buck converter shut down immediately when VBAT >
VBATOVP
1
ms
VBATUVLO
Battery undervoltage lockout threshold
VBAT rising, 100mV hysteresis
ILIMIT
Cycle-by-cycle current limit
VSYS shorted
TSHTDWN
Thermal trip
2.5
4.1
4.9
V
V
5.6
165
Thermal hysteresis
TREG
VBATREG
A
°C
10
Thermal regulation threshold
Charge current begins to cut off
Safety timer accuracy
(BQ24160/1/1B/3 Only)
120
–20%
°C
20%
PWM
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7.5 Electrical Characteristics (continued)
Circuit of Figure 9-1, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY >
VBAT+VSLP, TJ = -40°C – 125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
Internal top reverse blocking MOSFET on-resistance
TYP
MAX
IIN_LIMIT = 500mA, Measured from USB to PMIDU
TEST CONDITIONS
MIN
95
175
IIN_LIMIT = 500mA, Measured from IN to PMIDI
45
80
Internal top N-channel Switching MOSFET onresistance
Measured from PMIDU to SW
100
175
Measured from PMIDI to SW
65
110
Internal bottom N-channel MOSFET on-resistance
Measured from SW to PGND
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
1.35
UNIT
mΩ
mΩ
65
115
mΩ
1.50
1.65
MHz
95%
0%
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling
VHYS(HOT)
Hysteresis on high threshold
VTS rising
VWARM
High temperature threshold
VTS falling
VHYS(WARM)
Hysteresis on high threshold
VTS rising
VCOOL
Low temperature threshold
VTS falling
VHYS(COOL)
Hysteresis on low threshold
VTS rising
VCOLD
Low temperature threshold
VTS falling
VHYS(COLD)
Hysteresis on low threshold
VTS rising
TSOFF
TS Disable threshold
VTS rising, 2%VDRV hysteresis
tDGL(TS)
Deglitch time on TS change
29.7
30
30.5
1
37.9
38.3
39.6
1
56
56.5
56.9
1
59.5
60
60.4
1
70
73
50
%VDRV
%VDRV
%VDRV
%VDRV
%VDRV
ms
D+/D– DETECTION (bq24160)
VD+_SRC
D+ Voltage Source
ID+_SRC
D+ Connection Check Current Source
ID-_SINK
D- Current Sink
ID_LKG
0.5
50
Leakage Current into D+/D-
0.6
7
100
0.7
V
14
µA
150
µA
D–, switch open
–1
1
µA
D+, switch open
–1
1
µA
VD+_LOW
D+ Low Comparator Threshold
0.8
VD-_LOWdatref
D- Low Comparator Threshold
250
400
mV
V
RD-_DWN
D- Pulldown for Connection Check
14.25
24.8
kΩ
BATGD OPERATION
VBATGD
Good Battery threshold
Deglitch for good battery threshold
3.6
VBAT rising to HIGH-Z mode, DEFAULT Mode Only
3.8
3.9
32
V
ms
I2C COMPATIBLE INTERFACE
VIH
Input low threshold level
VPULL-UP = 1.8V, SDA and SCL
VIL
Input low threshold level
VPULL-UP = 1.8V, SDA and SCL
0.4
VOL
Output low threshold level
IL = 10mA, sink current
0.4
IBIAS
High-Level leakage current
VPULL-UP = 1.8V, SDA and SCL
tWATCHDOG
Watchdog timer timeout
(BQ24160/1/3 Only)
10
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1.3
V
1
30
V
V
μA
s
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
7.6 Typical Characteristics
60
50
40
60
50
40
30
30
VIN = 5 V
VIN = 7 V
VIN = 9 V
20
10
0
0.1
1
SYS loaded
VUSB = 5 V
VUSB = 6 V
10
0
0.1
3
System Current (A)
Charge Disabled
IN2500 ILIM
20
VBATREG = 3.6 V
Charge Disabled
USB1500 ILIM
SYSREG Regulation
MINSYS Regulation
4.208
3.75
3.7
3.65
3.6
3.55
4.206
4.204
4.202
4.2
4.198
4.196
3.5
4.194
3.45
4.192
0
50
Temperature (°C)
100
4.19
150
50
75
Temperature (°C)
No load
100
125
G004
Termination Disabled
Figure 7-4. Battery Regulation vs Temperature
700
6.7
USB100 Current Limit
USB500 Current Limit
6.6
6.5 V OVP Threshold (V)
USB Input Current Limit (mA)
25
VBATREG = 4.2 V
Figure 7-3. SYSREG and MINSYS Regulation vs Temperature
500
400
300
200
100
0
−50
0
G003
VBAT = 3 V
600
G002
VBATREG = 3.6 V
Figure 7-2. USB Efficiency
3.8
3.4
−50
SYS loaded
2
4.21
Battery Regulation (V)
SYSREG and MINSYS Regulation (V)
Figure 7-1. IN Efficiency
3.9
3.85
1
System Current (A)
G001
Falling Edge
Rising Edge
6.5
6.4
6.3
6.2
6.1
0
50
Temperature (°C)
100
150
G005
USB100 and USB500 current limit VUSB = 5 V VBAT = 3.6 V
Figure 7-5. USB Input Current Limit vs Temperature
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6
−50
0
50
Temperature (°C)
100
150
G006
USB input and IN input (BQ24168)
Figure 7-6. 6.5-V OVP Threshold vs Temperature
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7.6 Typical Characteristics (continued)
10.7
2.09
2.08
Charge Current (A)
10.5 V OVP Threshold (V)
10.6
2.1
Falling Edge
Rising Edge
10.5
10.4
10.3
10.2
2.07
2.06
2.05
2.04
2.03
2.02
10.1
10
−50
2.01
0
50
Temperature (°C)
100
150
2
2
2.5
3
3.5
Battery Voltage (V)
G007
Figure 7-7. 10.5-V OVP Threshold vs Temperature
ICHARGE = 2 A
VIN = 5 V
4
4.5
G008
VBATREG = 4.44 V
Figure 7-8. Charge Current vs Battery Voltage
0.055
IBATSHRT (A)
0.054
0.053
0.052
0.051
0.05
0
0.5
1
1.5
2
Battery Voltage (V)
2.5
3
G009
Figure 7-9. IBATSHRT vs Battery Voltage
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8 Detailed Description
8.1 Overview
The BQ24160/BQ24160A/BQ24161/BQ24161B/BQ24163/BQ24168 devices are highly integrated single-cell
Li-Ion battery chargers and system power path management devices targeted for space-limited, portable
applications with high-capacity batteries. The dual-input, single-cell charger operates from either a USB port
or alternate power source (that is, wall adapter or wireless power input) for a versatile solution.
The power path management feature allows the BQ2416xx to power the system from a high-efficiency DC-DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current
limit. This allows proper charge termination and enables the system to run with a defective or absent battery
pack. Additionally, this enables instant system turnon even with a totally discharged battery or no battery. The
power-path management architecture also permits the battery to supplement the system current requirements
when the adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The 2.5-A
current capability allows for GSM phone calls as soon as the adapter is plugged in regardless of the battery
voltage. The charge parameters are programmable using the I2C interface.
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8.2 Functional Block Diagram
PMIDU
PMIDI
5.2-V Reference
DRV
IN
Q1
USB
5A
+
BOOT
CbC Current
Limit
IN IINLIM
USB IUSBLIM
IN VINDPM
DC-DC CONVERTER
PWM LOGIC,
COMPENSATION
AND
BATTERY FET CONTROL
USB VINDPM
VSYS(REG)
Q2
IBAT(REG)
SW
VBAT(REG)
DIE Temp
Regulation
Q3
PGND
VSUPPLY
IBAT
Termination Comparator
OVP Comparators
+
VINOVP
Enable Linear
Charge
Sleep Comparators
+
Hi-Z Mode
SDA
2
I C
Interface
SCL
VBAT
BQ24160, 60A, 3
VSYS
VDRV
VBSUP
VBOVP Comparator
VBAT
VBATOVP
1.5A/USB100
DISABLE
TS COLD
BQ24161, 1B, 8
1C/0.5C
PSEL
BQ24160/2/3
+
TS COOL
+
VBATREG – 0.14V
STAT
TS WARM
+
D–
BGATE
+
D+
USB
Adapter
Detection
Circuitry
Hi-Z Mode
+
CD
VBAT
VBATGD
VBATSC Comparator
VBAT
Enable
VBATSHRT
IBATSHRT
Supplement Comparator
Good Battery
Circuit
+
VIN
VBAT + VSLP
VSYSREG Comparator
VSYS
VMINSYS
+
+
BAT
Recharge Comparator
VBATREG – 0.12V
VBAT
+
VUSB
VBAT + VSLP
Start Recharge
Cycle
Q4
+
VIN
+
VUSBOVP
SYS
+
+
+
VUSB
References
SUPPLY_SEL
Termination
Reference
DISABLE
TS HOT
CHARGE
CONTROLLER
with Timers (160/1/3)
INT
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8.3 Feature Description
8.3.1 Charge Mode Operation
8.3.1.1 Charge Profile
The internal battery MOSFET is used to charge the battery. When the battery is above the MINSYS voltage, the
internal FET is on to maximize efficiency and the PWM converter regulates the charge current into the battery.
When battery is less than MINSYS, the SYS is regulated to VSYS(REG) and battery is charged using the battery
FET to regulate the charge current. There are 5 loops that influence the charge current:
• Constant current loop (CC)
• Constant voltage loop (CV)
• Thermal-regulation loop
• Minimum system-voltage loop (MINSYS)
• Input-voltage dynamic power-management loop (VIN-DPM)
During the charging process, all five loops are enabled and the one that is dominant takes control. The
BQ2416xx supports a precision Li-ion or Li-polymer charging system for single-cell applications. The Dynamic
Power Path Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup
is enabled even for a missing or deeply discharged battery. Figure 8-1 shows a typical charge profile including
the minimum system output voltage feature.
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Current
Regulation
Threshold
System Voltage
VSYS
V BATSHORT
Battery
Voltage
Charge Current
Termination
Current
Threshold
I BATSHORT
50mA Precharge to
Close Pack Protector
Linear Charge
to Maintain
Minimum
System
Voltage
Battery FET is ON
Battery
FET
is OFF
Figure 8-1. Typical BQ2416xx Charging Profile
8.3.1.2 PWM Controller in Charge Mode
The BQ2416xx provides an integrated, fixed-frequency 1.5-MHz voltage-mode controller to power the system
and supply the charge current. The voltage loop is internally compensated and provides enough phase margin
for stable operation, allowing the use of small ceramic capacitors with low ESR. When starting up, the BQ2416xx
uses a "soft-start" function to help limit inrush current. When coming out of High Impedance mode, the
BQ2416xx starts up with the input current limit set to 40% of the value programmed in the I2C register. After 80
ms, the input current limit threshold steps up in 256-µs steps. The steps are 40% to 50%, then 50% to 60%, then
60% to 70%, then 70% to 80%, and finally 80% to 100%. After the final step, soft start is complete and will not be
restarted until the BQ2416xx enters High Impedance mode.
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The input scheme for the BQ2416xx prevents battery discharge when the supply voltages are lower than VBAT
and also isolates the two inputs from each other. The high-side N-MOSFET (Q1/Q2) switches to control the
power delivered to the output. The DRV LDO provides a supply for the gate drive for the low side MOSFET,
while a bootstrap circuit (BST) with an external bootstrap capacitor is used to boost up the gate drive voltage for
Q1 and Q2.
Both inputs are protected by a cycle-by-cycle current limit that is sensed through the high-side MOSFETs for Q1
and Q2. The threshold for the current limit is set to a nominal 5-A peak current. The inputs also utilize an input
current limit that limits the current from the power source.
8.3.2 Battery Charging Process
Assuming a vaild input source is attached to IN or USB, as soon as a deeply discharged or shorted battery is
attached to the BAT pin, (VBAT < VBATSHRT), the BQ2416xx applies IBATSHRT to close the pack protector switch
and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is linearly
regulated and the system output is regulated to VSYS(REG). Once the battery rises above VBATSHRT, the charge
current is regulated to the value set in the I2C register. The battery FET is linearly regulated to maintain the
system voltage at VSYS(REG). Under normal conditions, the time spent in this region is a very short percentage
of the total charging time, so the linear regulation of the charge current does not affect the overall charging
efficiency for very long. If the die temperature does rise, the thermal regulation circuit reduces the charge current
to maintain a die temperature less than 120°C. If the current limit for the SYS output is reached (limited by
the input current limit, or VIN_DPM), the SYS output drops to the VMINSYS output voltage. When this happens,
the charge current is reduced to provide the system with all the current that is needed while maintaining the
minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the
output to fall to the battery voltage and enter supplement mode. (See the Dynamic Power Path Management
section for more details.)
Once the battery is charged enough so that the system voltage begins to rise above VSYS(REG), the battery FET
is turned on fully and the battery is charged with the full programmed charge current set by the I2C interface,
ICHARGE. The slew rate for the fast-charge current is controlled to minimize current and voltage overshoot during
transients. The charge current is regulated to ICHARGE until the battery is charged to the regulation voltage. As
the battery voltage rises above VRCH, the battery regulation loop is activated. This may result in a small step
down in the charge current as the loops transition between the charge current and charge voltage loops. As the
battery voltage charges up to the regulation voltage, VBATREG, the charge current is tapered down as shown in
Figure 8-1 while the SYS output remains connected to the battery. The voltage between the BAT and PGND pins
is regulated to VBATREG. The BQ2416xx is a fixed single-cell voltage version, with adjustable regulation voltage
(3.5 V to 4.44 V), programmed using the I2C interface.
The BQ2416xx monitors the charging current during the voltage-regulation phase. If the battery voltage is above
the recharge threshold and the charge current has naturally tapered down to and remains below termination
threshold, ITERM, (without disturbance from events like supplement mode) for 32 ms, the charger terminates
charge, turns off the battery charging FET and enters battery detection. Termination is disabled when the charge
current is reduced by a loop other than the voltage regulation loop or the input current limit is set to 100 mA.
For example, when the BQ2416xx is in half charge due to TS function, reverse boost protection is active,
LOW_CHG bit is set, or the thermal regulation, VINDPM or input current loops are active, termination will not
occur. This prevents false termination events. During termination, the system output is regulated to the VSYS(REG)
and supports the full current available from the input and the battery supplement mode is available. (See the
Dynamic Power Path Management section for more details.) The termination current level is programmable.
When setting the termination threshold less than 150mA, the reverse boost protection may trip falsely with load
transients and very fully charged batteries. This will prevent termination while in the reverse boost protection and
may extend charge time. To disable the charge current termination, the host sets the charge termination bit (TE)
of charge control register to 0, refer to I2C section for details.
A new charge cycle is initiated if CD is low when either
1. VSUPPLY rises above UVLO while a battery with VBAT < VBATREG - VRCH is attached or
2. a battery with VBAT < VBATREG - VRCH is attached while VSUPPLY is above UVLO.
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With VSUPPLY above UVLO and V(BAT) < VBOVP, a recharge cycle is initiated when one of the following
conditions is detected:
1.
2.
3.
4.
The battery voltage falls below the VBAT(REG)-VRCH threshold.
CE bit toggle or RESET bit toggle
Supplement mode event occurs
CD pin or HI-Z bit toggle
VBAT(REG) should never be programmed less than VBAT. If the battery is ever 5% above the regulation threshold,
the battery OVP circuit shuts the PWM converter off immediately and the battery FET is turned on to discharge
the battery to safe operating levels. If the battery OVP condition exists for the 1ms deglitch, a battery OVP fault
is reported in the I2C status registers. The battery OVP fault is cleared when the battery voltage discharges
below VRCH or if the IC enters hi-impedance mode (HZ_MODE=1 or CD=1). Always write BQ2416xx to high
impedance mode before changing VBATREG to clear BOVP condition to ensure proper operation.
If the battery voltage is ever greater than VBATREG (for example, when an almost fully charged battery enters
the JEITA WARM state due to the TS pin) but less than VBOVP, the reverse boost protection circuitry may
activate as explained later in this data sheet. If the battery is ever above VBOVP, the buck converter turns off and
the internal battery FET is turned on. This prevents further overcharging of the battery and allows the battery
to discharge to safe operating levels. The battery OVP event does not clear until the battery voltage falls below
VRCH.
8.3.3 Battery Detection
When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT
is pulled from VBAT for tDETECT to verify there is a battery. If the battery voltage remains above VDETECT for
the full duration of tDETECT, a battery is determined to present and the IC enters “Charge Done”. If VBAT falls
below VDETECT, a “Battery Not Present” fault is signaled and battery detection continues. The next cycle of
battery detection, the BQ2416xx turns on IBATSHORT for tDETECT. If VBAT rises to VDETECT, the current source is
turned offand after tDETECT, the battery detection continues through another current sink cycle. Battery detection
continues until charge is disabled or a battery is detected. Once a battery is detected, the fault status clears and
a new charge cycle begins. Battery detection is not run when termination is disabled.
8.3.4 Dynamic Power Path Management (DPPM)
The BQ2416xx features a SYS output that powers the external system load connected to the battery. This output
is active whenever a source is connected to IN, USB or BAT. The following sections discuss the behavior of SYS
with a source connected to the supply or a battery source only.
8.3.5 Input Source Connected
When a valid input source is connected to IN or USB and the BQ2416xx is NOT in High Impedance mode, the
buck converter enters soft-start and turns on to power the load on SYS. The STAT/INT pin outputs a 128-µs
interrupt pulse to alert the host that an input has been connected. The FAULT bits indicate a normal condition,
and the Supply Status register indicates that a new supply is connected. The CE bit (bit 1) in the control register
(0x02) indicates whether a charge cycle is initiated. By default, the BQ2416xx ( CE = 0) enables a charge cycle
when a valid input source is connected. When the CE bit is '1' and a valid input source is connected, the battery
FET is turned off and the SYS output is regulated to the VSYS(REG) programmed by the VBATREG threshold in the
I2C register. A charge cycle is initiated when the CE bit is written to a 0 value (cleared).
When the CE bit is a 0 and a valid source is connected to IN or USB, the buck converter starts up using
soft-start. A charge cycle is initiated 64 ms after the buck converter iniates startup. When VBAT is high enough
that VSYS > VSYS(REG), the battery FET is turned on and the SYS output is connected to BAT. If the SYS voltage
falls to VSYS(REG), it is regulated to that point to maintain the system output even with a deeply discharged or
absent battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET
linearly regulates the charge current into the battery. The current from the supply is shared between charging
the battery and powering the system load at SYS. The dynamic power-path management (DPPM) circuitry of
the BQ2416xx monitors the current limits continuously, and if the SYS voltage falls to the VMINSYS voltage, it
adjusts charge current to maintain the minimum system voltage and supply the load on SYS. If the charge
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current is reduced to zero and the load increases further, the BQ2416xx enters battery-supplement mode. During
supplement mode, the battery FET is turned on and the battery supplements the system load.
When an input is connected with no battery attached and termination enabled, the startup process proceeds as
normal until the termination deglitch times out. After this, the BQ2416xx enters battery detection and waits for a
battery to be connected. Once a battery is connected and passes battery detection, a new charge cycle begins.
Once the battery is applied, the HZMODE bit or CD pin must be toggled before writing the BATREG to a higher
voltage and beginning a new charge cycle. Failure to do this can result in SYS unexpectedly regulating to 15%
above VBATREG.
2000
mA
1800 mA
ISYS
800 mA
0 mA
1500
IIN
mA
~850 mA
0mA
1A
IBAT
0mA
-200 mA
VSYS(REG)
VMINSYS
DPPM loop active
VOUT
~3.1V
Supplement
Mode
Figure 8-2. Example DPPM Response (VSupply = 5 V, VBAT = 3.1 V, 1.5 A Input Current Limit)
8.3.6 Battery Only Connected
When a battery with voltage greater than VBATUVLO is connected with no input source, the battery FET is turned
on similar to supplement mode. In this mode, the current is not regulated; however, there is a short circuit
current limit. If the short circuit limit is reached, the battery FET is turned off for the deglitch time (tDGL(SC1)).
After the recovery time (tREC(SC1)), the battery FET is turned on to test and see if the short has been removed.
If it has not, the FET turns off and the process repeats until the short is removed. This process is to protect
the internal FET from over current. If an external FET is used for discharge, the external FET's body diode
prevents the load on SYS from being disconnected from the battery. If the battery voltage is less than VBATUVLO,
the internal battery FET (Q4) remains off and BAT is high-impedance. This prevents further discharging of
deeply-discharged batteries.
8.3.7 Battery Discharge FET (BGATE)
The BQ2416xx contains a MOSFET driver to drive the gate of an external discharge FET between the battery
and the system output. This external FET provides a low impedance path when supplying the system from
the battery. Connect BGATE to the gate of the external discharge MOSFET. BGATE is on under the following
conditions:
1. No input supply connected.
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2. HZ_MODE bit = 1
3. CD pin = 1
8.3.8 DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT< VBATGD before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface and the safety timer has not expired.
3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I2C
communication is established
In DEFAULT mode, the I2C registers are reset to the default values. The 27-minute safety timer (no timer for
BQ24168) is reset and starts when DEFAULT mode is entered. The default value for VBATREG is 3.6 V, and
the default value for ICHARGE is 1 A. The input current limit for the IN input is set to 1.5 A. The input current
limit for the USB input is determined by the D+/D– detection (BQ24160/3) or PSEL (BQ24161/1B/8). PSEL and
D+/D– detection have no effect on the IN input. Default mode is exited by programming the I2C interface. Once
I2C communication is established, PSEL has no effect on the USB input. Note that if termination is enabled and
charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.
8.3.9 Safety Timer and Watchdog Timer (BQ24160/BQ24161/BQ24161B/BQ24163 only)
At the beginning of charging process, the BQ24160/1/1B/3 starts the safety timer. This timer is active during the
entire charging process. If charging has not terminated before the safety timer expires, charging is disabled, the
charge parameters are reset to the default values and the CE bit is written to a “1”. The length of the safety timer
is selectable using the I2C interface. A single 128-μs pulse is sent on the STAT and INT outputs and the STATx
bits of the status registers are updated in the I2C. In DEFAULT mode, the safety timer can be reset and a new
charge cycle initiated by input supply power on reset, removing/inserting battery or toggling the CD pin. In HOST
mode, the CE bit is set to a '1' when the safety timer expires. The CE bit must be cleared to a '0' in order to
resume charging and clear the safety timer fault. The safety timer duration is selectable using the TMR_X bits in
the Safety Timer Register/ NTC Monitor register. Changing the safety timer duration resets the safety timer. This
function prevents continuous charging of a defective battery. During the fast charge (CC) phase, several events
increase the timer duration by 2× if the EN_2X_TMR bit is set in the register.
1.
2.
3.
4.
5.
6.
7.
The system load current reduces the available charging current.
The input current needed for the fast charge current is limited by the input current loop.
The input current is reduced because the VINDPM loop is preventing the supply from crashing.
The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG).
The LOW_CHG bit is set.
The battery voltage is less than VBATSHORT.
The battery has entered the JEITA WARM or COLD state via the TS pin
During these events, the timer is slowed by half to extend the timer and prevent any false timer faults. Starting a
new charge cycle by VSUPPLY POR or removing/replacing the battery or resuming a charge by toggling the CE
or HZ_MODE bits, resets the safety timer. Additionally, thermal shutdown events cause the safety timer to reset.
In addition to the safety timer, the BQ24160/1/1B/3 contain a watchdog timer that monitors the host through the
I2C interface. Once a read/write is performed on the I2C interface, a 30-second timer (tWATCHDOG) is started.
The 30-second timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit
(TMR_RST) in the control register. The TMR_RST bit is automatically set to “0” when the 30-second timer is
reset. This process continues until the battery is fully charged or the safety timer expires. If the 30-second timer
expires, the IC enters DEFAULT mode where the default register values are loaded, the safety timer restarts at
27 minutes and charging continues. The I2C may be accessed again to reinitialize the desired values and restart
the watchdog timer. The watchdog timer flow chart is shown in Figure 8-3.
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Start Safety Timer
Safety timer expired?
Yes
Safety timer
fault
No
Charge Done?
ICHG < ITERM
Yes
STAT = Hi
Update STAT
bits
Yes
STAT = Hi
Update STAT
bits
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
No
No
I2C Read/Write
performed?
Yes
Start 30 second
watchdog timer
Charge Done?
ICHG < ITERM
Reset 30 second
watchdog timer
No
Yes
Safety timer
fault
Safety timer expired?
No
Charging suspended
Fault indicated in
STAT registers
No
30s timer expired?
Yes
No
Yes
Received SW watchdog
RESET?
Reset to default
values in I2C
register
Restart 27min
safety timer
Figure 8-3. The Watchdog Timer Flow Chart for BQ2416xx
8.3.10 D+, D– Based Adapter Detection for the USB Input (D+, D–, BQ24160/0A/3)
The BQ24160/0A/3 contain a D+, D– based adapter detection circuit that is used to program the input current
limit for the USB input during DEFAULT mode. D+, D– detection is only performed in DEFAULT mode unless
forced by the D+, D–_EN bit in host mode. Writing to register 2 during detection stops the detection routine.
By default the USB input current limit is set to 100 mA. When a voltage higher than UVLO is applied to the
USB input, the BQ24160/0A/3 performs a charger source identification to determine if it is connected to an SDP
(USB port) or CDP/DCP (dedicated charger). The first step is D+, D- line connection detection as described in
BC1.2. Primary detection begins 10 ms after the connection detection complete. The primary detection complies
with the method described in BC1.2. During primary detection, the D+, D- lines are tested to determine if the
port is an SDP or CDP/DCP. If a CDP/DCP is detected the input current limit is increased to 1.5 A, if an SDP
is detected the current limit remains at 100 mA, until changed via the I2C interface. These two steps require at
least 90 ms to complete but if they have not completed within 500 ms, the D+, D- detection routine selects 100
mA for the unknown input source. Secondary detection as described in BC1.2 is not performed.
Automatic detection is performed only if VD+ and VD– are less than 0.6 V to avoid interfering with the USB
transceiver which may also perform D+, D– detection when the system is running normally. However, D+, D–
can be initiated at any time by the host by setting the D+, D– EN bit in the Control/Battery Voltage Register
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to 1. After detection is complete the D+, D– EN bit is automatically reset to 0 and the detection circuitry is
disconnected from the D+, D– pins to avoid interference with USB data transfer.
When a command is written to change the input current limit in the I2C, this overrides the current limit selected
by D+/D– detection. D+, D– detection has no effect on the IN input.
8.3.11 USB Input Current Limit Selector Input (PSEL, BQ24161/161B/168 only)
The BQ24161, BQ24161B, and BQ24168 contain a PSEL input that is used to program the input current limit for
USB during DEFAULT mode. Drive PSEL high to indicate that a USB source is connected to the USB input and
program the 100 mA (BQ24161/8) or 500 mA (BQ24161B) current limit for USB. Drive PSEL low to indicate that
an AC adapter is connected to the USB input. When PSEL is low, the IC starts up with a 1.5-A current limit for
USB. PSEL has no effect on the IN input. Once an I2C write is done, the PSEL has no effect on the input current
limit until the watchdog timer expires.
8.3.12 Hardware Chip Disable Input (CD)
The BQ2416xx contains a CD input that is used to disable the IC and place the BQ2416xx into high-impedance
mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the
BQ2416xx into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving
CD high during HOST mode resets the safety timer and places the BQ2416xx into high impedance mode. The
CD pin has precedence over the I2C control.
8.3.13 LDO Output (DRV)
The BQ2416xx contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10-mA external loads to power the STAT LED or the USB transceiver
circuitry. The maximum value of the DRV output is 5.45 V; ideal for protecting voltage sensitive USB circuits from
high voltage fluctuations in the supply. The LDO is on whenever a supply is connected to the IN or USB inputs of
the BQ2416xx. The DRV is disabled under the following conditions:
1. VSUPPLY < UVLO
2. VSUPPLY < VSLP
3. Thermal Shutdown
8.3.14 External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the BQ2416xx provides a flexible, voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging. The BQ24160, BQ24160A, BQ24161B, BQ24163, and BQ24168 enable the
user to easily implement the JEITA standard for charging temperature while the BQ24161 only monitors the hot
and cold cutoff temperatures and leaves the JEITA control to the host. The JEITA specification is shown in.
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1°C
0.5°C
Portion of spec not covered by TS
Implementation on BQ24160
4.25 V
4.15 V
4.1 V
T1
(0°C)
T2
(10°C)
T3
T4
(45°C) (50°C)
T5
(60°C)
Figure 8-4. Charge Current During TS Conditions
To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC
< 0°C), the cool battery threshold (0°C < TNTC < 10°C), the warm battery threshold (45°C < TNTC ≤ 60°C) and
the hot battery threshold (TNTC > 60°C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT
thresholds. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VWARM
> VTS > VHOT, the battery regulation voltage is reduced by 140 mV from the programmed regulation threshold.
When VCOLD > VTS > VCOOL, the charging current is reduced to half of the programmed charge current.
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 8-11. The resistor values
are calculated using the following equations:
é 1
1 ù
VDRV ´ RCOLD ´ RHOT ´ ê
ú
V
V
ë COLD
HOT û
RLO =
éV
ù
é V
ù
RHOT ´ ê DRV - 1ú - RCOLD ´ ê DRV - 1ú
ë VHOT
û
ë VCOLD
û
(1)
VDRV
-1
VCOLD
RHI =
1
1
+
RLO RCOLD
(2)
Where:
VCOLD = 0.60 × VDRV
VHOT = 0.30 × VDRV
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature.
For the BQ24160, BQ24161B, BQ24163, and BQ24168, the WARM and COOL thresholds are not independently
programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using the
following equations:
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RCOOL =
SLUSAO0H – NOVEMBER 2011 – REVISED JULY 2022
RLO ´ 0.564 ´ RHI
RLO - RLO ´ 0.564 - RHI ´ 0.564
RW ARM =
(3)
RLO ´ 0.383 ´ RHI
RLO - RLO ´ 0.383 - RHI ´ 0.383
VBAT(REG) 1 x Charge/
DISABLE -140 mV 0.5 x Charge
TS COLD
TS COOL
(4)
VDRV
+
+
TS WARM +
VDRV
TS HOT
RHI
+
TS
PACK+
TEMP
BQ2416x
RLO
PACK-
Figure 8-5. TS Circuit
8.3.15 Thermal Regulation and Protection
During the charging process, to prevent chip overheating, the BQ2416xx monitors the junction temperature, TJ,
of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG.
The charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once
the charge current is reduced, the system current is reduced while the battery supplements the load to supply
the system. This may cause a thermal shutdown of the BQ2416xx if the die temperature rises too high. At any
state, if TJ exceeds TSHTDWN, the BQ2416xx suspends charging and disables the buck converter. During thermal
shutdown mode, the buck converter is turned off, all timers are suspended, and a single 128-μs pulse is sent on
the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new
charging cycle begins when TJ falls below TSHTDWN by approximately 10°C.
8.3.16 Input Voltage Protection in Charge Mode
8.3.16.1 Sleep Mode
The BQ2416xx enters the low-power sleep mode if the voltage on VSUPPLY falls below the sleep-mode entry
threshold, VBAT+VSLP, and VSUPPLY is higher than the undervoltage lockout threshold, VUVLO. This feature
prevents draining the battery during the absence of VSUPPLY. When VSUPPLY < VBAT+ VSLP, the BQ2416xx turns
off the PWM converter, turns the battery FET on and drives BGATE to GND, sends a single 128-μs pulse on the
STAT and INT outputs and updates the STATx and FAULT_x bits in the status registers. Once VSUPPLY > VBAT+
VSLP, the STATx and FAULT_x bits are cleared and the device initiates a new charge cycle.
8.3.16.2 Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage decreases. Once the supply drops to VIN_DPM (default 4.2 V for both inputs),
the input current limit is reduced to prevent further supply droop. When the IC enters this mode, the charge
current is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature provides
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IC compatibility with adapters with different current capabilities without a hardware change. Figure 8-6 shows the
VIN–DPM behavior to a current-limited source. In this figure the input source has a 750-mA current limit and the
charging is set to 750 mA. The SYS load is then increased to 1.2 A.
Adapter Voltage Falls due
to Adapter Current Limit
VIN
5 V Adapter
rated for 750 mA
Input Current Reduced by VINDPM function
to Prevent Adapter from Crashing
IIN
VSYS
750 mA Charging
750 mA Charging
IBAT
ISYS
Supplement Mode
1.2 A Load Step
Figure 8-6. BQ24160 VIN-DPM
8.3.16.3 Bad Source Detection
When a source is connected to IN or USB, the BQ2416xx runs a Bad Source Detection procedure to determine
if the source is strong enough to provide some current to charge the battery. A current sink is turned on (30
mA for USB input, 75 mA for the IN input) for 32 ms. If the source is valid after the 32 ms (VBADSOURCE <
VSUPPLY < VOVP), the buck converter starts up and normal operation continues. If the supply voltage falls below
VBAD_SOURCE during the detection, the current sink shuts off for two seconds and then retries, a single 128-μs
pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers and the
battery/supply status registers are updated. The detection circuits retry continuously until either a new source
is connected to the other input or a valid source is detected after the detection time. If during normal operation
the source falls to VBAD_SOURCE, the BQ2416xx turns off the PWM converter, turns the battery FET on, sends
a single 128-μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status
registers, and the battery/supply status registers are updated. Once a good source is detected, the STATx and
FAULT_x bits are cleared and the device returns to normal operation.
If two supplies are connected, the supply with precedence is checked first. If the supply detection fails once,
the device switches to the other supply for two seconds and then retries. This allows the priority supply to settle
if the connection was jittery or the supply ramp was too slow to pass detection. If the priority supply fails the
detection a second time, it is locked out and lower priority supply is used. Once the bad supply is locked out, it
remains locked out until the supply voltage falls below UVLO. This prevents continuously switching between a
weak supply and a good supply.
8.3.16.4 Input Overvoltage Protection
The built-in input overvoltage protection to protect the device and other downstream components against
damage from overvoltage on the input supply (voltage from VUSB or VIN to PGND). During normal operation,
if VSUPPLY > VOVP, the BQ2416xx turns off the PWM converter, turns the battery FET and BGATE on, sends a
single 128-μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers
and the battery/supply status registers are updated. Once the OVP fault is removed, the STATx and FAULT_x
bits are cleared and the device returns to normal operation.
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To allow operation with some unregulated adapters, the OVP circuit is not active during Bad Source Detection.
This provides some time for the current sink to pull the unregulated adapter down into an acceptable range. If
the adapter voltage is high at the end of the detection, the startup of the PWM converter does not occur. The
OVP circuit is active during normal operation, so if the system standby current plus the charge current is not
enough to pull down the source, operation is suspended.
8.3.16.5 Reverse Boost (Boost Back) Prevention Circuit
A buck converter has two operating modes, continuous conduction mode (CCM) and discontinuous conduction
mode (DCM). In DCM, the inductor current ramps down to zero during the switching cycle while in CCM the
inductor maintains a DC level of current. Transitioning from DCM to CCM during load transients, slows down the
converter's transient response for those load steps, which can result in the SYS rail drooping. To achieve the
fastest possible transient reponse for this charger, this charger's synchronous buck converter is forced to run in
CCM even at light loads when the buck converter would typically revert to DCM. The challenge that presents
itself when forcing CCM with a charger is that the output of the buck converter now has a power source. Thus,
if the battery voltage, V(BAT), is ever greater than VBATREG, the inductor current goes fully negative and pushes
current back to the input supply. This effect causes the input source voltage to rise if the input source cannot
sink current. The input over-voltage protection circuit protects the IC from damage however some input sources
may be damaged if the voltage rises. To prevent this, this charger has implemented a reverse boost prevention
circuit. When reverse current is sensed that is not a result of the supplement comparator tripping, this circuit
disables the internal battery FET and changes the feedback point to VSYSREG for 1 ms. After the 1-ms timeout,
the BATFET is turned on again and the battery is tested to see if it is higher than VBATREG (negative current).
The reverse current protection is only active when VBOVP > VBAT > VBATREG - VRCH. Having VBOVP > VBAT >
VBATREG - VRCH results in an approximately 100-mV, 1000-Hz ripple on SYS as seen in Figure 8-7. The most
common trigger for reverse boost prevention is a load transient on SYS that requires the charger to enter battery
supplement mode. When the IC enters reverse boost prevention, the IC stops charging or exits charge done
which may result in the battery never reaching full charge. With termination enabled and ITERM > 150 mA
or with a high line impedance to the battery, the likelihood of activating the reverse boost prevention circuit is
small and even when activated, the charger typically exits reverse boost prevention as the battery relaxes. With
termination enabled and ITERM < 150 mA or with a low impedance battery, the likelihood of activating the
reverse boost prevention circuit by a load transient or even the inductor ripple current is higher. In either case,
the IC resumes charging until VBAT drops below VBATREG - VRCH, resulting in the battery always charging to
at least 0.97 of full charge. If full charge is required with ITERM < 150 mA then the recommended solution to
ensure full charge is as follows
1.
SET the charger’s enable no battery operation bit ( EN_NOBATOP) = 1 to disable the reverse boost
prevention circuits. Brief, low-amplitude voltage pulses on IN may be observed as the IC enters boost back to
resolve instances where VBAT is greater than the VBATREG, for example when exiting supplement mode. The
I2C communication software must ensure that VBATREG is never written below VBAT. The IC automatically
rewrites the VBATREG register to the default value of 3.6 V when existing HOST mode. For JEITA enabled ICs,
the IC automatically lowers the voltage reference to 0.98 of the VBATREG value. The software must account
for these instances as well.
2.
Disable the charger’s termination function and TS functions and use a gas gauge to control termination
and TS through its independent voltage and current measurements.
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Figure 8-7. V(SYS) When Reverse Boost Prevention Circuit is Active
8.3.17 Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for BQ2416xx. STAT is pulled low during charging
when EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is
high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 8-1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
Table 8-1. STAT Pin Summary
CHARGE STATE
Charge in progress and EN_STAT=1
Other normal conditions
STAT AND INT BEHAVIOR
Low
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault,
watchdog expiration, sleep mode, battery temperature fault (TS), battery fault
(OVP or absent), thermal shutdown
128-µs pulse, then High Impedance
8.3.18 Good Battery Monitor
The BQ2416xx contains a good battery monitor circuit that places the BQ2416xx into high-z mode if the battery
voltage is above the BATGD threshold while in DEFAULT mode. This function is used to enable compliance
to the battery charging standard that prevents charging from an un-enumerated USB host while the battery is
above the good battery threshold. If the BQ2416xx is in HOST mode, it is assumed that USB host has been
enumerated and the good battery circuit has no effect on charging.
8.4 Device Functional Modes
The state machine of the BQ2416x automatically changes primary states (Off, sleep, HiZ, charge disabled,
charging, charge done, battery OVP, fault) based on data in the I2C registers, IN and USB pin voltages, BAT
pin voltage and current flow, TS pin voltage, CD pin voltage and status of the safety timer. The BAT and TS pin
voltages as well as current flow into the IN and USB pins, out of SYS pin and into/out of the BAT pin determine
the charging sub-states, including conditioning, constant current (CC), CC with reduced charge current, constant
voltage (CV) with reduced charge current.
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8.5 Programming
8.5.1 Serial Interface Description
The BQ2416xx uses an I2C-compatible interface to program charge parameters. I2C is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All I2C-compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A
host device, usually a microcontroller or a digital signal processor, controls the bus. The host is responsible for
generating the SCL signal and device addresses. The host also generates specific conditions that indicate the
START and STOP of data transfer. A target device receives and/or transmits data on the bus under control of the
host device.
The BQ2416xx device works as a target and supports the following data transfer modes, as defined in the
I2C Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to
the battery charging solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as battery voltage remains
above 2.5 V (typical). The I2C circuitry is powered from VBUS when a supply is connected. If the VBUS supply
is not connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above
2.5 V with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The BQ2416xx devices only support 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (6Bh).
8.5.1.1 F/S Mode Protocol
The host initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 8-8. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 8-8. START and STOP Condition
The host then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the host ensures that data is valid. A valid data condition requires the
SDA line to be stable during the entire high period of the clock pulse (see Figure 8-9). All devices recognize the
address sent by the host and compare it to their internal fixed addresses. Only the target device with a matching
address generates an acknowledge (see Figure 8-10) by pulling the SDA line low during the entire high period of
the ninth SCL cycle. Upon detecting this acknowledge, the host knows that communication link with a target has
been established.
DATA
CLK
Data Line
Stable
Data Valid
Chang
of Data
Allowed
Figure 8-9. Bit Transfer on the Serial Interface
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The host generates further SCL cycles to either transmit data to the target (R/W bit 1) or receive data from
the target (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the host or by the target, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the host generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 8-11). This releases the bus and stops the communication
link with the addressed target. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the host needs sending a STOP condition to prevent the
target I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Host
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 8-10. Acknowledge on the I2C Bus
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgment
Signal From Target
MSB
Sr
Address
R/W
SCL
S
or
Sr
ACK
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
Figure 8-11. Bus Protocol
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8.6 Register Maps
8.6.1 Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
READ/WRITE
B7 (MSB)
TMR_RST
Read/Write
FUNCTION
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
(BQ24160/1/3 only)
B6
STAT_2
Read only
B5
STAT_1
Read only
B4
STAT_0
Read only
000- No Valid Source Detected
001- IN Ready (shows preferred source when both connected)
010- USB Ready (shows preferred source when both connected)
011- Charging from IN
100- Charging from USB
101- Charge Done
110- NA
111- Fault
B3
SUPPLY_SEL
Read/Write
0-IN has precedence when both supplies are connected
1-USB has precedence when both supplies are connected (default 0)
B2
FAULT_2
Read only
B1
FAULT_1
Read only
B0 (LSB)
FAULT_0
Read only
000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
011- Watchdog Timer Expired (BQ24160/1/1B/3 only)
100- Safety Timer Expired (BQ24160/1/1B/3 only)
101- IN Supply Fault
110- USB Supply Fault
111- Battery Fault
SUPPLY_SEL Bit (Supply Precedence Selector)
The SUPPLY_SEL bit selects which supply has precedence when both supplies are present. In cases where both supplies are
connected, they must remain isolated from each other which means only one is allowed to charge the battery. Write a 1 to
SUPPLY_SEL to select the USB input to have precedence. Write a 0 to select the IN input.Note the following behavior when
switching the SUPPLY_SEL bit with both supplies attached:
•
•
•
The BQ2416xx returns to high impedance mode
The input supply is switched
The BQ2416xx begins a full startup cycle starting with bad adapter detection then proceeding to soft-start
Similarly, if charging from the non-preferred supply when the preferred supply is attached, the BQ2416xx follows the same
procedure.
STAT_x and FAULT_x Bits
The STAT_x show the current status of the device and are updated dynamically as the IC changes state. The FAULT_x bits show
faults that have occurred and are only cleared by reading the bits, assuming the fault no longer exists. If multiple faults occur, the
first one is the one that is shown.
8.6.2 Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
NAME
READ/WRITE
B7 (MSB)
INSTAT1
Read Only
B6
INSTAT0
Read Only
B5
USBSTAT1
Read Only
B4
USBSTAT0
Read Only
B3
OTG_LOCK
Read/Write
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FUNCTION
00-Normal
01-Supply OVP
10-Weak Source Connected (No Charging)
11- VIN TS temp > TCOLD (Charge current reduced by half, BQ24160 only)
11 – TWARM < TS temp < THOT (Charge voltage reduced by 140 mV, BQ24160 only)
B0 (LSB)
LOW_CHG
Read/ Write
0 – Charge current as programmed in Register 0x05
1 – Charge current is half programmed value in Register 0x05
(default 0)
2xTMR_EN Bit (2x Timer Enable)
The 2xTMR_EN bit is used to slow down the timer when charge current is reduced by the system load. When 2xTMR_EN is a
1, the safety timer is slowed to half speed effectively doubling the timer time. The conditions that activate the 2x timer are: Input
Current Limit, VINDPM, Thermal Regulation, LOW_CHG, BATSHRT and TS Cool. When 2xTMR_EN is a 0, the timer operates at
normal speed in all conditions.
LOW_CHG Bit (Low Charge Mode Enable)
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The LOW_CHG bit is used to reduce the charge current from the programmed value. This feature is used by systems where
battery NTC is monitored by the host and requires a reduced charge current setting or by systems that need a “preconditioning”
current for low battery voltages. Write a 1 to this bit to charge at half of the programmed charge current (BQ24160/1/3/8). Write a
0 to this bit to charge at the programmed charge current.
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9 Application and Implementation
9.1 Application Information
A typical application circuit using the BQ24160 with a smartphone's GSM power amplifier (PA) powered directly
from the battery is shown in Figure 9-1. A typical application circuit using the BQ24161 with a smartphone's
GSM PA powered from the SYS rail, to allow for calls even with a deeply discharged battery, is shown in
Figure 9-2. Each circuit shows the minimum capacitance requirements for each pin and typical recommended
inductance value of 1.5 µH. The TS resistor divider for configuring the TS function for the battery's specific
thermistor can be computed from equations Equation 1 and Equation 2. The resistor on STAT is sized per the
LED current requirements. All other configuration settings for VINDPM, input current limit, charge current and
charge voltage are made in EEPROM registers using I2C commands. Options for sizing the inductor outside the
1.5 µH recommended value and additional SYS pin capacitance are explained in the next section.
9.2 Typical Application
ADAPTER
1.5 mH
IN
SW
PMIDI
1 mF
VBUS
D+
DGND
BOOT
USB
SYS
10 mF
PMIDU
1 mF
System
Load
0.01 mF
4.7 mF
PGND
4.7 mF
BGATE
DRV
BAT
1 mF
VDRV
1 mF
STAT
GSM
PA
PACK+
TS
TEMP
VSYS
(1.8V)
D+
DPACK-
BQ24160
HOST
INT
SDA
GPIO1
SCL
SCL
SDA
Figure 9-1. BQ24160, Shown with no External Discharge FET, PA Connected to Battery
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ADAPTER
1.5 mH
IN
SW
PMIDI
1 mF
System
Load
0.01 mF
4.7 mF
BOOT
USB
VBUS
D+
DGND
SYS
PMIDU
1 mF
10 mF
PGND
4.7 mF
BGATE
DRV
1 mF
VDRV
1 mF
STAT
USB PHY
GSM
PA
BAT
PACK+
TS
TEMP
VSYS
(1.8V)
PSEL
PACK-
HOST
BQ24161
INT
SDA
GPIO1
SCL
SCL
SDA
Figure 9-2. BQ24161, Shown with External Discharge FET, PA Connected to System for GSM Call
Support with a Deeply Discharged or No Battery
9.2.1 Design Requirements
MIN
Supply voltage, VIN
Input voltage from ac adapter
4.2
USB voltage, VUSB
Input voltage from USB or equivalent supply
System voltage, VSYS
Voltage output at SYS terminal (depends on VBAT voltage and
status of VINDPM)
Battery voltage, VBAT
Voltage output at VBAT terminal (registers set via I2C
communication)
Supply current, IIN(MAX)
Maximum input current from ac adapter input (registers set via
I2C communication)
1.5
Supply current, IUSB(MAX)
Maximum input current from USB input (registers set via I2C
communication)
0.1
Fast charge current,
ICHRG(MAX)
Battery charge current (registers set via I2C communication)
Operating junction temperature range, TJ
TYP
MAX
UNIT
10
V
4.2
6
V
3.3
VBATRE
G+4.17%
V
4.44
V
2.5
A
1.5
A
0.550
2.5
A
-40
125
°C
2
4.2
0.5
9.2.2 Detailed Design Procedure
9.2.2.1 Output Inductor and Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The BQ2416xx is designed to work with 1.5-µH to 2.2-µH inductors.
The chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2-µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5-µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use Equation 5 to calculate the peak current.
æ %
ö
IPEA K = ILOAD(MAX) ´ ç1+ RIPPP LE ÷
2
è
ø
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The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due
to the high currents possible with the BQ2416xx, a thermal analysis must also be done for the inductor. Many
inductors have a 40°C temperature-rise rating. The DC component of the current can cause a 40°C temperature
rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used
adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5-A DC load with
peaks at 2.5 A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7 A:
ITEMPRISE = ILOAD + D ´ (IPEAK - ILOAD ) = 1.5A + 0.2 × (2.5A - 1 .5A ) = 1.7A
(6)
The BQ2416xx provides internal loop compensation. Using this scheme, the BQ2416xx is stable with 10 µF to
200 µF of local capacitance on the SYS output. The capacitance on the SYS rail can be higher if distributed
amongst the rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10 µF
and 47 µF is recommended for local bypass to SYS. A 47-µF bypass capacitor is recommended for optimal
transient response.
9.2.3 Application Curves
USB500
925-mA Charge Setting
Figure 9-3. USB Plug-In with Battery Connected
Figure 9-5. Adapter Detection USB
1500-mA ILIM
1300-mA Charge Setting
Figure 9-4. IN Plug-in with Battery Connected
Termination Enabled
Figure 9-6. Battery Insert During Battery Detection
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Termination Enabled
MINSYS Operation USB1500
200-mA to 1400-mA Load Step on SYS
Figure 9-7. Battery Pull During Charging
Figure 9-8. Load Transient into DPPM
VUSB
5 V/div
VSYS
5 V/div
VBAT
VSTAT/INT
1 V/div
5 V/div
VSW
IUSB
500 mA/div
1 A/div
IBAT
IBAT
500 mA/div
10 ms/div
4 ms/div
MINSYS Operation USB500
200-mA to 1400-mA Load Step on SYS
Figure 9-10. OVP Fault USB Input
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Figure 9-9. Load Transient into Supplement Mode
60
50
40
30
60
50
40
30
VIN = 5 V
VIN = 7 V
VIN = 9 V
20
10
0
0.1
1
SYS loaded
0
0.1
1
System Current (A)
G001
VBATREG = 3.6 V
Figure 9-11. IN Efficiency
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VUSB = 5 V
VUSB = 6 V
10
3
System Current (A)
Charge Disabled
IN2500 ILIM
20
Charge Disabled
USB1500 ILIM
SYS loaded
2
G002
VBATREG = 3.6 V
Figure 9-12. USB Efficiency
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10 Power Supply Recommendations
10.1 Requirements for SYS Output
In order to provide an output voltage on SYS, the BQ2416xx requires either a power supply between 4.2 V
and 6.0 V for USB input on all versions, 4.2 V and 6.0 V for IN input on BQ24168 and 4.2 V and 10.0 V on
the remaining versions with at least 100-mA current rating connected to IN or USB or a single-cell LiIon battery
with voltage > VBATUVLO connected to BAT. The source current rating needs to be at least 2.5 A in order for the
charger's buck converter to provide maximum output power to SYS.
10.2 Requirements for Charging
In order for charging to occur, the source voltage as measured at the IC's USB or IN pins (factoring in cable/
trace losses from the source) must be greater than the VINDPM threshold (but less than the maximum values
above) and the source's current rating must be higher than the buck converter needs to provide the load on
SYS. For charging at a desired charge current of ICHRG, VUSBorINx IUSBorIN x η > VSYS x (ISYS+ ICHRG) where η is
the efficiency estimate from Figure 7-1 or Figure 7-2 and VSYS = VBAT when VBAT charges above VMINSYS. The
charger limits IUSBorIN to that input's current limit setting. With ISYS = 0 A, the charger consumes maximum power
at the end of CC mode, when the voltage at the BAT pin is near VBATREG but ICHRG has not started to taper off
toward ITERM.
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11 Layout
11.1 Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 11-1 provides a sample layout for the high
current paths of the BQ2416xx. A list of layout guidelines follows.
•
•
•
•
•
•
•
•
•
To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the BQ2416xx
Minimize the amount of inductance between BAT and the postive connection of the battery terminal. If a large
parasitic board inductance on BAT is expected, increase the bypass capacitance on BAT.
Place 4.7-µF input capacitor as close to PMID_ pin and PGND pin as possible to make high frequency
current loop area as small as possible. Place 1-µF input capacitor GNDs as close to the respective PMID cap
GND and PGND pins as possible to minimize the ground difference between the input and PMID_.
The traces from the input connector to the inputs of the BQ2416xx should be as wide as possible to minimize
the impedance in the line. Although the VINDPM feature will allow operation from input sources having high
resistances(impedances), the BQ2416xx input pins (IN and USB) have been optimized to connect to input
sources with no more than 350 mΩ of input resistance, including cables and PCB traces
The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
Place all decoupling capacitors close to their respective IC pins and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high-current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach
is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces
noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With
this small layout and a single ground plane, there is no ground-bounce issue, and having the components
segregated minimizes coupling between signals.
The high-current charge paths into IN, USB, BAT, SYS and from the SW pins must be sized appropriately
for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance because the board conducts heat away from the
IC.
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11.2 Layout Example
WCSP
VQFN
Figure 11-1. Recommended BQ2416xx PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
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change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
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not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168
41
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
BQ24160ARGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 125
BQ
24160A
Samples
BQ24160ARGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
0 to 125
BQ
24160A
Samples
BQ24160RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24160
Samples
BQ24160RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24160
Samples
BQ24160YFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24160
Samples
BQ24160YFFT
ACTIVE
DSBGA
YFF
49
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24160
Samples
BQ24161BRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24161B
Samples
BQ24161BRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24161B
Samples
BQ24161BYFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
BQ24161B
Samples
BQ24161RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24161
Samples
BQ24161RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24161
Samples
BQ24161YFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24161
Samples
BQ24161YFFT
ACTIVE
DSBGA
YFF
49
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24161
Samples
BQ24163RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24163
Samples
BQ24163RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24163
Samples
BQ24163YFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24163
Samples
BQ24163YFFT
ACTIVE
DSBGA
YFF
49
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24163
Samples
BQ24168RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24168
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
16-Jul-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
BQ24168RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
24168
Samples
BQ24168YFFR
ACTIVE
DSBGA
YFF
49
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24168
Samples
BQ24168YFFT
ACTIVE
DSBGA
YFF
49
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24168
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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