BQ24180YFFT

bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and Accessory Power Connection Check for Samples: bq24180 FEATURES • 1 • 2 • • • • • • • Charge Faster than Linear Chargers From Current Limited Input Sources High-Accuracy Voltage and Current Regulation – Input Current Regulation Accuracy: ±5% (100mA, 500mA) – Charge Voltage Regulation Accuracy: ±0.5% (25°C), ±1% (0–125°C) – Charge Current Regulation Accuracy: ±5% Accessory Power Output (DCOUT) Input Voltage Based Dynamic Power Management Safety Limit Register for Maximum Charge Voltage and Current Limiting High-Efficiency Mini-USB/AC Battery Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs 20-V Absolute Maximum and 16.5V Operation Input Voltage Rating Built-in Input Current Sensing and Limiting • • • • • • • Integrated Power FETs for Up to 1.5-A Charge Rate Programmable Charge Parameters through I2C™ compatible Interface (up to 3.4 Mbps) Synchronous Fixed-Frequency PWM Controller Operating at 3 MHz With 0% to 99.5% Duty Cycle Safety Timer and Software Watchdog Reverse Leakage Protection Prevents Battery Drainage Thermal Regulation and Protection Status Outputs for Charging and Faults 25-Pin WCSP Package APPLICATIONS • • • Mobile Phones and Smart Phones Portable Media Players Handheld Devices DESCRIPTION The bq24180 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters is programmable using an I2C compatible interface. The bq24180 integrates a synchronous PWM controller, power MOSFETs, input current sensing and overvoltage protection, high-accuracy current and voltage regulation, and charge termination, into a small WCSP package. POWER FOR ACCESSORY C8 1 µF SYSTEM VBUS C1 1 µF RSNS 68 mW DCOUT VBUS SW C4 10 nF PMID C3 4.7 µF C2 10 µF BOOT TEMP PACK + PGND HOST bq24180 CSIN PACK - CSOUT DRV C7 1 µF VBUS D+ D- VBUS C5 0.1 µF PSEL TS USB PHY GND C6 1 µF VAUX R1 10 kW R2 10 kW R4 10 kW CD INT Hardware Disable STAT SCL SDA R3 4 kW 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Phillips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) The bq24180 charges the battery in three phases: conditioning, constant current and constant voltage. Charge current is programmable using the I2C interface. Additionally, the input current can be limited to a host programmable threshold to maintain maximum charge current from current-limited sources, such as USB ports. Charge is terminated based on user-selectable minimum current level. A software watchdog provides a safety backup for I2C interface while a safety timer prevents overcharging the battery. During normal operation, bq24180 automatically restarts the charge cycle if the battery voltage falls below an internal threshold and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge status is reported to the host using the I2C interface. During the charging process, the bq24180 monitors its junction temperature (TJ) and reduces the charge current if TJ increases to 125°C. The bq24180 is available in 25-pin WCSP package. ORDERING INFORMATION VOVP I2C ADDRESS bq24180YFFR 16.5 V 6B bq24180YFFT 16.5 V 6B PART NUMBER (1) (2) (1) (2) The YFF package is available in the following options: R – taped and reeled in quantities of 3,000 devices per reel. T – taped and reeled in quantities of 250 devices per reel. This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) LIMITS UNIT Supply voltage range (with respect to PGND) VBUS –2 to 20 V Input voltage range (with respect to and PGND) SCL, SDA, PSEL, CSIN, CSOUT, DRV, DCOUT, INT –0.3 to 7 V PMID, STAT –0.3 to 20 SW, BOOT –0.7 to 20 Output voltage range (with respect to and PGND) Voltage difference between CSIN and CSOUT inputs (VCSIN –VCSOUT) Voltage difference between BOOT and SW inputs (VBOOT –VSW) Output sink Output current Output current (average) V ±7 V –0.3 to 7 V INT 5 STAT 10 DCOUT 1.5 A DRV 10 mA 2 A TA Operating free-air temperature range –30 to +85 °C TJ Junction temperature range –40 to +125 °C Tstg Storage temperature –45 to +150 °C (1) (2) 2 SW mA Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 DISSIPATION RATINGS (1) PACKAGE RqJA RqJC TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C WCSP-25 60°C/W (1) 1.57°C/W 540 mW 5.4 mW/°C Using JEDEC 2s2p PCB standard. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VBUS MAX 4.0 Operating junction temperature range, TJ (1) NOM 16 0 UNIT (1) V 125 °C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight layout minimizes switching noise. ELECTRICAL CHARACTERISTICS Circuit of Figure 2, VVBUS = 5V, HZ_MODE=0, CD=0, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS VVBUS > VVBUS(min), PWM switching 10 mA IVBUS VVBUS supply current for control VVBUS > VVBUS(min), PWM NOT switching 5 mA 0°C< TJ < 85°C, EN=0 or HZ_MODE=1 650 µA IVBUS_LEAK Leakage current from battery to VBUS pin 0°C< TJ < 85°C, VCSOUT = 4.2 V, No input connected 5 µA IBAT_DCOUT Battery Current when using DCOUT DCOUT = enabled, VBAT = 4.2V, DCOUT_ILIM=1A, IDCOUT=750mA 800 µA 0°C< TJ < 85°C, VCSOUT = 4.2 V, No Input connected, DCOUT disabled SCL,SDA=0V or 1.8V 30 µA IBAT_HIZ Battery discharge current in High Impedance mode, (CSIN, CSOUT, SW pins) 0°C< TJ < 85°C, VCSOUT = 4.2 V, High Impedance mode, DCOUT disabled, VVBUS = 5V, SCL,SDA=0V or 1.8V 60 µA V VOLTAGE REGULATION VOREG Output charge voltage programmable range Voltage regulation accuracy Operating in voltage regulation, programmable 3.5 4.44 –0.5% 0.5% –1% 1% 550 1550 VICHRG = 37.4 mV to 44.2 mV –3.5% 3.5% VICHRG > 44.2 mV –3.0% 3.0% TA = 25°C CURRENT REGULATION - FAST CHARGE IOCHARGE Output charge current programmable range Regulation accuracy for charge current across RSNS VIREG = IOCHARGE × RSNS VPRECHG ≤ VCSOUT < VOREG, VVBUS>VSLP, RSNS = 68 mΩ, Programmable mA PSEL, CD LOGIC LEVEL VIL Input low threshold level PSEL, CD falling VIH Input high threshold level PSEL, CD rising 1.2 0.4 25 V V CHARGE TERMINATION DETECTION ITERM Termination charge current VCSOUT > VOREG–VRCH , VVBUS>VSLP, RSNS = 68 MΩ, Programmable ITERM_dgl Deglitch time for charge termination Both rising and falling, 2-mV over- drive, tRISE, tFALL = 100 ns Regulation accuracy for termination current across RSNS VIREG_TERM = IOTERM × RSNS 200 30 ms VTERM = 1.7 mV –40% 40% VTERM = 3.4 mV to 6.8 mV –16% 16% VTERM = 6.8 mV to 13.6 mV –11% 11% VTERM ≥ 13.6 mV –5.5% 5.5% Battery Detection sink current before charge done mA –550 µA INPUT BASED DYNAMIC POWER MANAGEMENT Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 3 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 2, VVBUS = 5V, HZ_MODE=0, CD=0, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS The threshold when input based DPM loop kicks in VIN_DPM MIN Charge mode, programmable DPM loop kick-in threshold tolerance TYP MAX UNIT 4.15 4.71 V –2% 2% FAULTY ADAPTER PROTECTION VVBUS (MIN) Faulty adapter threshold 3.6 Deglitch time for Faulty adapter 4.0 30 Hysteresis for faulty adapter protection VVBUS Rising 100 Current source for faulty adapter protection tINT 3.8 20 Detection Interval 30 V ms 200 mV 40 mA 2 s INPUT CURRENT LIMITING IIN_LIMIT USB charge mode, current pulled from PMID Input current limiting threshold IIN_LIMIT = 100 mA 90 95 100 IIN_LIMIT = 500 mA 450 475 500 IIN_LIMIT = 800 mA 700 755 800 mA DCOUT RDCOUT DCOUT Pass FET on-resistance IDCOUT = 500 mA 2 ILIM_DCOUT DCOUT current limit programmable range tDGL_DCOUT Deglitch time from DCOUT current-limit event to DCOUT latch-off ILIM_DCOUT 350 Programmable via I C mΩ 1400 mA 14.5 Programmable via I2C DCOUT current limit range 300 ILIM_DCOUT = 350mA 270 ILIM_DCOUT = 750mA 650 750 ILIM_DCOUT = 1050mA 800 1050 ILIM_DCOUT = 1400mA 1050 1400 100 120 ms 350 mA BATTERY RECHARGE THRESHOLD VRCH Recharge threshold voltage Below VOREG Deglitch time VCSOUT decreasing below threshold, tFALL = 100 ns, 10-mV overdrive 150 130 mV ms STAT OUTPUTS VOL(STAT) VOL(INT) Low-level output saturation voltage, STAT IO = 10 mA, sink current High-level leakage current Voltage on STAT pin is 5V 0.5 V 1 µA Low-level output saturation voltage, INT IO = 1 mA, sink current 0.4 V High-level leakage current Voltage on INT pin is 5V 1 µA I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS VOL Output low threshold level IO = 10 mA, sink current 0.4 V Input low threshold level V(pull-up) = 1.8 V, SDA and SCL 0.4 V Input high threshold level V(pull-up) = 1.8 V, SDA and SCL I(bias) Input bias current V(pull-up) = 1.8 V, SDA and SCL 1 µA fSCL SCL clock frequency 1.2 V 3.4 MHz SLEEP COMPARATOR VSLP Sleep-mode entry threshold, VBUS-VCSOUT 2.3 V ≤ VCSOUT ≤ VOREG, VVBUS falling VSLP-EXIT Sleep-mode exit hysteresis 2.3 V ≤ VCSOUT < VOREG Deglitch time for VBUS rising above VSLP+VSLP_EXIT Rising voltage, 2-mV over drive, tRISE = 100 ns 0 40 100 mV 140 200 260 mV 30 ms UVLO VUVLO IC active threshold voltage VVBUS rising 3.05 3.3 VUVLO_HYS IC active hysteresis VVBUS falling from above VUVLO 120 150 3.55 V Internal top reverse blocking MOSFET on-resistance IIN_LIMIT = 500 mA, Measured from VVBUS to PMID 110 210 mΩ Internal top N-channel Switching MOSFET on-resistance Measured from PMID to SW 130 250 mΩ mV PWM 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 2, VVBUS = 5V, HZ_MODE=0, CD=0, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER Internal bottom N-channel MOSFET on-resistance fOSC TEST CONDITIONS MIN Measured from SW to PGND Oscillator frequency Maximum duty cycle DMIN Minimum duty cycle MAX UNIT 125 210 mΩ 3.0 Frequency accuracy DMAX TYP –10% MHz 10% 99.5% 0 Synchronous mode to non-synchronous mode transition current threshold (1) Low-side MOSFET cycle-by-cycle current sensing VDRV Internal bias voltage regulator IDRV = 10 mA IDRV DRV Output Current External load on DRV VDO_DRV DRV Dropout Voltage (VVBUS – VDRV) 100 5 5.2 mA 5.45 10 IVBUS = 1A, VVBUS = 5 V, IDRV = 10 mA 340 VUVLO < VVBUS VCOLD or VTSVIN(MIN), the device continues the startup sequence. If VVBUS VOVP, the bq24180 latches off the PWM converter, a single 128µs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. Once the OVP fault is removed, the STATx and FAULT_x bits are cleared and the device returns to normal operation. Charge Status Outputs (STAT, INT) The STAT and INT outputs are used to indicate operation conditions for bq24180. STAT and INT are pulled low during charging when EN_STAT bit in the control register (00H) is set to “1”. When charge is complete or disabled, INT and STAT are high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT and INT during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication. INT is available for connecting to the logic rail for host communication. Table 1. STAT Pin Summary CHARGE STATE STAT and INT BEHAVIOR Charge in progress and EN_STAT=1 Low Other normal conditions Open-drain Charge mode faults: Timer fault, sleep mode, VBUS over voltage, VBUS UVLO, thermal shutdown 128-µs pulse, then open-drain Control Bits in Charge Mode CE Bit (Charge Enable) The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge. RESET Bit Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 23 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com The bit of RESET in control register is used to reset all the charge parameters. Write ‘1” to RESET bit to reset all the charge parameters to default values and RESET bit is automatically cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge starts and it is not recommended to set RESET bit when charging or boosting in progress. Output Inductor and Capacitor Selection Guidelines The bq24180 provides internal loop compensation. With this scheme, best stability occurs when LC resonant frequency, of, is approximately 40 kHz (20 kHz to 80 kHz). Equation 1 can be used to calculate the value of the output inductor, LOUT, and output capacitor, COUT. 1 ¦o = 2p ´ LOUT ´ COUT (1) To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7µF and 47µF is recommended for COUT, refer to the application section for components selection. Selecting Current Sense Resistor Both the termination current range and charge current range are depending on the sensing resistor (RSNS). The termination current step (IOTERM_STEP) can be calculated using Equation 2: V IOTERM_STEP = ITERM0 RSNS (2) Table 2 shows the termination current settings with two sensing resistors. Table 2. Termination Current Settings for 68mΩ and 100mΩ Sense Resistors BIT VITERM (mV) ITERM (mA) RSNS = 68 mΩ ITERM (mA) RSNS = 100 mΩ VITERM2 6.8 100 68 VITERM1 3.4 50 43 VITERM0 1.7 25 17 Offset 1.7 25 17 The charge current step (IOCHARGE_STEP) can be calculated using Equation 3: V IOCHARG E_STEP = ICHRG0 R SNS (3) Table 3 shows the charge current settings with two sensing resistors. Table 3. Charge Current Settings for 68 mΩ and 100 mΩ Sense Resistors 24 BIT VIREG (mV) IOCHARGE (mA) RSNS = 68 mΩ IOCHARGE (mA) RSNS = 100 mΩ VICHRG3 54.4 800 544 VICHRG2 27.2 400 272 VICHRG1 13.6 200 136 VICHRG0 6.8 100 68 Offset 37.4 550 374 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 SERIAL INTERFACE DESCRIPTION I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The bq24180 device works as a slave and is compatible with the following data transfer modes, as defined in the I2C Bus™ Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as battery voltage remains above 2.5 V (typical). The I2C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is not connected, the I2C circuitry is powered from the battery through CSOUT. The battery voltage must stay above 2.5V with no input connected in order to maintain proper operation. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as the HS-mode. The bq24150/1 device only supports 7-bit addressing. The device 7-bit address is defined as ‘1101011’ (6BH). F/S Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 33. All I2C -compatible devices should recognize a start condition. DATA CLK START Condition STOP Condition Figure 33. START and STOP Condition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 34). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 34) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. DATA CLK Data Line Stable; Data Valid Charge of Data Allowed Figure 34. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 25 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 35). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in this section will result in FFh being read out. Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master Clock Pulse for Acknowledgement START Condition Figure 35. Acknowledge on the I2C Bus Figure 36. Bus Protocol F/S Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation. 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in this section results in FFh being read out. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 27 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com REGISTER DESCRIPTION blank paragraph for spacer Status/Control Register (READ/WRITE) – Memory location: 00, Reset state: x1xx 0xxx BIT NAME Read/Write FUNCTION B7(MSB) TMR_RST Read/Write Write: TMR_RST function, write "1" to reset the watchdog timer (auto clear) Read: 0 – PSEL indicates low, 1- PSEL indicates high B6 EN_STAT Read/Write 1-Enable STAT function, 0-Disable STAT function (default 1) B5 STAT2 Read only B4 STAT1 Read only B3 NA Read only B2 FAULT_3 Read only B1 FAULT_2 Read only B0(LSB) FAULT_1 Read only 00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault NA Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011- Faulty Adapter or VBUSVSHORT), the maximum values for battery regulation voltage and charge current can be programmed many times until any writing to other register locks the safety limits. Programmed values exclude higher values from memory locations 02 (battery regulation voltage), and from memory location 04 (Fast charge current). If host accesses (write command) to some other register before Safety limit register, the default values hold! • • blank paragraph for spacer NTC Monitor Register (READ/WRITE) – Memory location: 07, Reset state: 100X 0000 BIT NAME Read/Write FUNCTION B7(MSB) 2XTMR_EN Read/Write 1 – Timer slowed by 2x when in thermal regulation or VIN_HIGH protection, 0 – Timer not slowed at any time (default 1) B6 TMR_1 Read/Write B5 TMR_2 Read/Write Safety Timer Time Limit 00 – 27 minute fast charge, 01 – 3 hour fast charge, 10 – 6 hour fast charge, 11 – Disable safety timers (default 00) B4 NA Read/Write NA B3 TS_/EN Read/Write 1 – TS function disabled, 0 – TS function enabled (default 0) B2 TS_FAULT2 Read only B1 TS_FAULT1 Read only B0(LSB) TS_FAULT0 Read only TS Fault Mode: 000 – TS temp < 5°C or TS temp > 55°C, 010 – Normal, No TS fault, 011 – 45°C < TS temp < 55°C, 100–111 – TS Open 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 POWER TOPOLOGIES System Load After Sensing Resistor One of the simple high-efficiency topologies connects the system load directly across the battery pack, as shown in Figure 37. The input voltage has been converted to a usable system voltage with good efficiency from the input. When the input power is on, it supplies the system load and charges the battery pack at the same time. When the input power is off, the battery pack powers the system directly. SW VBUS Isns L1 VIN + - Isys Rsns Ichg bq24180 C1 PMID + PGND C4 C3 System Load BAT C2 Figure 37. System Load After Sensing Resistor The advantages: • When the AC adapter is disconnected, the battery pack powers the system load with minimum power dissipations. Consequently, the time that the system runs on the battery pack can be maximized. • It saves the external path selection components and offers a low-cost solution. • Dynamic power management (DPM) can be achieved. The total of the charge current and the system current can be limited to a desired value by adjusting charge current. When the system current increases, the charge current drops by the same amount. As a result, no potential over-current or over-heating issues are caused by excessive system load demand. • The total of the input current can be limited to a desired value by setting input current limit value. So USB specifications can be met easily. • The supply voltage variation range for the system can be minimized. • The input current soft-start can be achieved by the generic soft-start feature of the IC. Design considerations and potential issues: • If the system always demands a high current (but lower than the regulation current), the charging never terminates. Thus, the battery is always charged, and the lifetime may be reduced. • Because the total current regulation threshold is fixed and the system always demands some current, the battery may not be charged with a full-charge rate and thus may lead to a longer charge time. • If the system load current is large after the charger has been terminated, the voltage drop across the battery impedance may cause the battery voltage to drop below the refresh threshold and start a new charge. The charger would then terminate due to low charge current. Therefore, the charger would cycle between charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold, resulting in a much slower cycling. • In a charger system, the charge current is typically limited to about 10mA, if the sensed battery voltage is below 2V short circuit protection threshold. This results in low power availability at the system bus. If an external supply is connected and the battery is deeply discharged, below the short circuit protection threshold, the charge current is clamped to the short circuit current limit. This then is the current available to the system during the power-up phase. Most systems cannot function with such limited supply current, and the battery supplements the additional power required by the system. Note that the battery pack is already at the depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown. • If the battery is below the short circuit threshold and the system requires a bias current budget lower than the short circuit current limit, the end-equipment will be operational, but the charging process can be affected depending on the current left to charge the battery pack. Under extreme conditions, the system current is Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 31 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 • www.ti.com close to the short circuit current levels and the battery may not reach the fast-charge region in a timely manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process. Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the application possible. For instance, if the battery pack voltage is too low, highly depleted, or totally dead or even shorted, the system voltage is clamped by the battery and it cannot operate even if the input power is on. System Load Before Sensing Resistor The second circuit is very similar to first one; the difference is that the system load is connected before the sense resistor, as shown in Figure 38. Isys SW VBUS Isns L1 VIN + - Rsns Ichg bq24180 C1 PMID + PGND C4 C3 System Load BAT C2 Figure 38. System Load Before Sensing Resistor The advantages of system load before sensing resistor to system load after sensing resistor: • The charger controller is based only on the current goes through the current-sense resistor. So, the constant current fast charge and termination functions work well, and are not affected by the system load. This is the major advantage of it. • A depleted battery pack can be connected to the charger without the risk of the safety timer expiration caused by high system load. • The host charger can disable termination and keep the converter running to keep battery fully charged, or let the switcher terminate when the battery is full and then run off of the battery via the sense resistor. Design considerations and potential issues: • The total current is limited by the IC input current limit, or peak current protection, or the thermal regulation but not the charge current setting. The charge current does not drop when the system current load increases until the input current limit is reached. This solution is not applicable if the system requires a high current. • Efficiency declines when discharging through the sense resistor to the system. DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUITS Systems Design Specifications: • VBUS = 5 V • V(BAT) = 4.2 V (1-Cell) • I(charge) = 1.25 A • Inductor ripple current = 30% of fast charge current 1. Determine the inductor value (LOUT) for the specified charge current ripple: L OUT = VBAT ´ (VBUS - VBAT) VBUS ´ f ´ D IL , the worst case is when battery voltage is as close as to half of the input voltage. 32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 LOUT = 2.5 ´ (5 - 2.5) 5 ´ (3 ´ 106 ) ´ 1.25 ´ 0.3 (4) LOUT = 1.11 mH Select the output inductor to standard 1 mH. Calculate the total ripple current with using the 1-mH inductor: DIL = DIL = VBAT ´ (VBUS - VBAT) VBUS ´ f ´ LOUT (5) 2.5 ´ (5 - 2.5) 5 ´ (3 ´ 106 ) ´ (1 ´ 10-6 ) (6) ΔIL = 0.42 A Calculate the maximum output current: DIL ILPK = IOUT + 2 ILPK = 1.25 + (7) 0.42 2 (8) ILPK = 1.46 A Select 2.5mm by 2.0mm 1-mH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers are shown as following. Table 4. Inductor Part Numbers PART NUMBER INDUCTANCE SIZE MANUFACTURER LQM2HPN1R0MJ0 1 mH 2.5 x 2.0 mm muRata MIPS2520D1R0 1 mH 2.5 x 2.0 mm FDK MDT2520-CN1R0M 1 mH 2.5 x 2.0 mm TOKO CP1008 1 mH 2.5 x 2.0 mm Inter-Technical 2. Determine the output capacitor value COUT using 40 kHz as the resonant frequency: fo = 1 2p ´ COUT = COUT = LOUT ´ COUT (9) 1 4p2 ´ f02 ´ LOUT 1 (10) 4p2 ´ (40 ´ 103 )2 ´ (1 ´ 10-6 ) (11) COUT = 15.8 mF Select two 0603 X5R 6.3V 10-mF ceramic capacitors in parallel i.e., muRata GRM188R60J106M. 3. Determine the sense resistor using the following equation: V(RSNS) R(SNS) = I(CHARGE) (12) The maximum sense voltage across sense resistor is 85 mV. In order to get a better current regulation accuracy, V(RSNS) should equal 100mV, and calculate the value for the sense resistor. 85mV R(SNS) = 1.25A (13) R(SNS) = 68 mΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 33 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com This is a standard value. If it is not a standard value, then choose the next close value and calculate the real charge current. Calculate the power dissipation on the sense resistor: P(RSNS) = I(CHARGE) 2 × R(SNS) P(RSNS) = 1252 × 0.068 P(RSNS) = 0.106 W Select 0805 0.25-W 68-mΩ 2% sense resistor, i.e. Sosomu RL122OT-R068-G or RL0816T-R068-F 68-mΩ, 0.125W, 0603, 1%. PCB LAYOUT CONSIDERATION It is important to pay special attention to the PCB layout. The following provides some guidelines: • To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed as close as possible to the bq24180. The output inductor should be placed close to the IC and the output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper layout to minimize high frequency current path loop is critical (see Figure 39). The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the RSNS(R1) back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers (do not route the sense leads through a high-current path, see Figure 40). • Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths. • The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for small-signal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue, and having the components segregated minimizes coupling between signals. • The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. • Place 4.7mF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. Place 1mF input capacitor as close to VBUS pin and PGND pin as possible to make high frequency current loop area as small as possible (see Figure 41). L1 VBUS R1 SW V BAT High Frequency BAT V IN PMID C1 Current Path PGND C3 C2 Figure 39. High Frequency Current Path 34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 bq24180 www.ti.com SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 Charge Current Direction R SNS To Inductor To Capacitor and battery Current Sensing Direction CSOUT must be as large as possible to avoid error when using DCOUT To CSIN and CSOUT pin Figure 40. Sensing Resistor PCB Layout VBUS Vin+ PMID SW 1uF Vin4.7uF PGND Figure 41. Input Capacitor Position and PCB Layout Example PACKAGE SUMMARY WCSP PACKAGE (Top View) CHIP SCALE PACKAGE (Top Side Symbol For bq24180) VBUS VBUS BOOT SCL SDA PMID PMID PMID INT CD SW SW SW PSEL STAT PGND PGND PGND DCOUT DCOUT CSIN TS DRV CSOUT CSOUT D TI YMLLLLS bq24180 E 0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code CHIP SCALE PACKAGING DIMENSIONS TM The bq24180 devices are available in a 20-bump chip scale package (YFF, NanoFree ). The package dimensions are: · D = 2.2 ± 0.05 mm · E = 2.4 ± 0.05 mm Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 35 bq24180 SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010 www.ti.com REVISION HISTORY Changes from Original (February 2010) to Revision A • 36 Page Changed ±7 to "-0.3 to 7 V" for "Voltage difference between BOOT and SW inputs (VBOOT –VSW)" parameter of the Absolute Maximum Ratings table. .................................................................................................................................. 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq24180 PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ24180YFFR ACTIVE DSBGA YFF 25 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM 0 to 125 BQ24180 Samples BQ24180YFFT ACTIVE DSBGA YFF 25 250 RoHS & Green SNAGCU Level-1-260C-UNLIM 0 to 125 BQ24180 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of