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bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
bq24188 2A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery
Charger with Power Path Management and USB-OTG Support
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
Charge Time Optimizer (Enhanced CC/CV
Transition) for Faster Charging
Integrated FETs for Up to 2A Charge Rate at 5%
Accuracy and 93% Peak Efficiency
Boost Capability to Supply 5V at 1A at IN for USB
OTG Supply
Integrated 17mΩ Power Path MOSFET and
optional BGATE control to Maximize Battery Life
and Instantly Startup From a Deeply Discharged
Battery or No Battery
30V Input Rating with Over-Voltage Protection
Supports 5V USB2.0/3.0 and 12V USB Power
Delivery
Small Solution Size In a 2.4mm x 2.4mm 36-ball
WCSP or 4mm x 4mm QFN-24 Package
– Total Charging Solution Can be 50mm2 or less
with WCSP
Safe and Accurate Battery Management
Functions Programmed Using I2C Interface
– Charge Voltage, Current, Termination
Threshold, Input Current Limit, VIN_DPM
Threshold
– Voltage-based, JEITA Compatible NTC
Monitoring Input
– Thermal Regulation Protection for Input
Current Control
– Thermal Shutdown and Protection
Smartphone and Tablets
Handheld Products
Power Banks and External Battery Packs
Small Power Tools
Portable Media Players and Gaming
3 Description
The bq24188 is a highly integrated single cell Li-Ion
battery charger and system power path management
device that supports operation from either a USB port
or wall adapter supply. The power path feature allows
the bq24188 to power the system from a high
efficiency DC to DC converter while simultaneously
and independently charging the battery. The power
path also permits the battery to supplement the
system current requirements when the adapter
cannot. Many features are programmable using the
I2C interface. To support USB OTG applications, the
bq24188 is configurable to boost the battery voltage
to 5V and supply up to 1A at the input. The battery is
charged with three phases: precharge, constant
current and constant voltage. Thermal regulation
prevents the die temperature from exceeding 125°C.
Additionally, a JEITA compatible battery pack
thermistor monitoring input (TS) is included to prevent
the battery from charging outside of its safe
temperature range.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
bq24188
DSBGA (36)
2.40 mm × 2.40 mm
bq24188
QFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Application Schematic
Charge Time Optimizer Effect
SW
Charge Cycle 4000mAh Battery 2A Charge Rate
D+
D-
PGND
4.2
BOOT
2.5
`
PMID
3
4.4
System
Load
GND
4
3.8
SYS
More Energy
Delivered to
the Battery
in the Same
Time
Voltage (V)
`
D+
DBAT
CD
HOST
1.5
3.2
3
bq24188
INT
PACK+
TS
2.8
0.5
TEMP
2.6
VDRV
V I/O
3.4
2
1
SDA
SCL
3.6
Charge Current (A) / Efficiency
IN
VBUS
PACK-
2.4
0
2000
VBAT_CTO
4000
6000
Time (sec)
VBAT_Traditional
8000
IBAT_CTO
0
10000 11000
IBAT_Traditional
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Application Schematic ..........................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
1
1
1
1
2
3
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information ................................................. 6
Electrical Characteristics........................................... 6
Switching Characteristics ........................................ 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 15
9.5 Programming........................................................... 26
9.6 Register Descriptions .............................................. 29
10 Applications and Implementation...................... 36
10.1 Application Information.......................................... 36
10.2 Typical Applications .............................................. 36
11 Power Supply Recommendations ..................... 41
11.1 Requirements for SYS Output .............................. 41
11.2 Requirements for Charging ................................... 41
12 Layout................................................................... 42
12.1 Layout Guidelines ................................................. 42
12.2 Layout Example .................................................... 42
13 Device and Documentation Support ................. 44
13.1
13.2
13.3
13.4
Documentation Support .......................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
14 Mechanical, Packaging, and Orderable
Information ........................................................... 44
5 Revision History
Changes from Original (December 2014) to Revision A
Page
•
Changed minimum capacitance for DRV pin from 1 µF to 2.2 µF ........................................................................................ 4
•
Changed absolute max voltage for DRV, SYS from 5.0 V to 5.5 V ....................................................................................... 5
•
Added specifications to Electrical Characteristics table pertaining to RGE package............................................................. 6
•
Added separate lines for IINLIM current for YFF and RGE packages. ..................................................................................... 8
•
Changed VDO_DRV spec MAX voltage from "500 mV" to "450 mV" ......................................................................................... 8
•
Added footnote to the Electrical Characteristics table for the ILIM(DISCH) specification: "Continuous and periodic pulse
currents from BAT to SYS are limited by output current specifications in the Absolute Max Ratings table" ....................... 10
•
Changed the DRV bypass capacitor in the Typical Application circuit diagrams from 1 µF to 2.2 µF ................................ 36
2
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SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
6 Device Comparison Table
PART
NUMBER
OVP
CE BIT DEFAULT
D+/D–
DETECTION
TIMERS (SAFETY and
WATCHDOG)
NTC
MONITORING
OTG
BOOST
I2C
ADDRESS
bq242188
14
1
(Charge Disabled)
NO
YES
JEITA
YES
6B
7 Pin Configuration and Functions
36-Ball 2,4mm x 2,4mm WCSP (YFF)
bq24188 Top View
1
2
A
PGND
PGND
B
PMID
C
3
4
5
PGND
PGND
PGND
PGND
SW
SW
SW
SW
SW
IN
IN
IN
IN
CD
BOOT
D
SDA
SCL
N.C.
PSEL
TS
DRV
E
STAT
INT
SYS
SYS
SYS
SYS
F
AGND
BGATE
BAT
BAT
BAT
BAT
6
SW
SW
PGND
PGND
AGND
IN
24-Terminal 4mm × 4mm QFN (RGE)
bq24188 Top View
24
23
22
21
20
19
PMID
1
18 IN
BOOT
2
17 SDA
DRV
3
16 SCL
bq24188
7
8
9
10
11
12
AGND
13 STAT
BGATE
SYS 6
INT
14 PSEL
BAT
TS 5
BAT
15 N.C.
SYS
CD 4
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3
bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
www.ti.com
Pin Functions
PIN
NAME
PIN NUMBER
bq24188
I/O
DESCRIPTION
YFF
RGE
F1
12, 20
F3-F6
8, 9
I/O
Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1μF of
ceramic capacitance. See Application section for additional details.
F2
11
O
External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a
very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low
during high impedance mode or when no input is connected. If no external FET is required, leave BGATE
disconnected. Do not connect BGATE to GND.
C6
2
I
High Side MOSFET Gate Driver Supply. Connect 0.033µF of ceramic capacitance (voltage rating > 10V) from
BOOT to SW to supply the gate drive for the high side MOSFET.
C5
4
I
IC Hardware Disable Input. Drive CD high to place the bq24188 in high-z mode. Drive CD low for normal
operation. CD is pulled low internally with 100kΩ
D+
–
–
I
D–
–
–
I
D6
3
O
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND
with at least a 10-V or higher rated, +/-10%, X5R or better 2.2 μF ceramic capacitor. DRV may be used to
drive external loads up to 10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN >
(VBAT + VSLP).
C1-C4
18, 19
I
DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to
PGND with at least a 4.7μF of ceramic capacitance.
AGND
BAT
Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
BGATE
BOOT
CD
DRV
IN
INT
D+ and D– Connections for USB Input Adapter Detection. When a source is initially connected to the input
during DEFAULT mode, and a short is detected between D+ and D–, the input current limit is set to 1.5A. If a
short is not detected, the USB100 mode is selected.
E2
10
O
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low
during charging. INT is high impedance when charging is complete, disabled or the charger is in high
impedance mode. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is enabled
/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through a 100kΩ resistor
to communicate with the host processor.
A1-A6
21,22
–
Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
B1
1
I
High Side Bypass Connection. Connect at least 1µF of ceramic capacitance from PMID to PGND as close to
the PMID and PGND terminals as possible.
D4
14
I
Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit. Drive PSEL high to
select USB100, drive PSEL low to select 1.5A mode.
SCL
D2
16
I
I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor. Do not leave floating.
SDA
D1
17
I/O
I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
PGND
PMID
PSEL
STAT
SW
E1
13
O
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low
during charging. STAT is high impedance when charging is complete, disabled or the charger is high
impedance mode. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is
enabled /disabled using the EN_STAT bit in the control register. Connect STAT to a logic rail using an LED
for visual indication or through a 100kΩ resistor to communicate with the host processor.
B2-B6
23, 24
O
Inductor Connection. Connect to the switched side of the external inductor. The inductance must be between
1.5µH and 2.2µH.
E3-E6
6, 7
I
System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with at least 10μF of ceramic capacitance. The SYS rail must have at least
20µF of total capacitance for stable operation. See Application section for additional details.
D5
5
I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is
connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS faults are
reported by the I2C interface. Pull TS high to VDRV to disable the TS function if unused. See the NTC Monitor
section for more details on operation and selecting the resistor values.
–
–
–
There is an internal electrical connection between the exposed thermal pad and the PGND terminal of the
device. The thermal pad must be connected to the same potential as the PGND terminal on the printed circuit
board. Do not use the thermal pad as the primary ground input for the device. PGND terminal must be
connected to ground at all times.
SYS
TS
Thermal PAD
4
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SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
8 Specifications
8.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Terminal Voltage Range (with
respect to PGND)
MIN
MAX
IN
–1.3
30
BOOT, PMID
–0.3
30
SW
–0.7
20
BAT, BGATE, CD, INT, PSEL, SDA, SCL, STAT, TS
–0.3
5.0
DRV, SYS
–0.3
5.5
–0.3
5
BOOT to SW
Output Current (Continuous)
Output Current (VBAT+VSLP
PWM NOT switching
6.5
mA
RGE Package: VUVLO < VIN < VOVP and VIN>VBAT+VSLP
PWM NOT switching
6.65
0°C< TJ < 85°C, VIN = 5V, High-Z Mode
250
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 5V,
SCL, SDA = 0V or 1.8V, High-Z Mode
15
YFF Package: 0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0V,
SCL, SDA = 0V or 1.8V
77
RGE Package: 0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0V,
SCL, SDA = 0V or 1.8V
80
INPUT CURRENTS
VUVLO < VIN < VOVP and VIN>VBAT+VSLP
PWM switching
IIN
Supply current for control
Battery discharge current in
High Impedance mode, (BAT,
SW, SYS)
IBAT_HIZ
15
μA
μA
POWER-PATH MANAGEMENT
VSYSREG(LO)
System Regulation Voltage
VBAT < VMINSYS
VMINSYS
+ 80mV
VMINSYS
+ 100mV
VMINSYS
+ 120mV
V
VSYSREG(HI)
System Regulation Voltage
Battery FET turned off, no charging,
VBAT > 3.5V
VBATREG
+1.4%
VBATREG
+1.6%
VBATREG
+1.77%
V
VMINSYS
Minimum System Voltage
Regulation Threshold
VBAT + VDO(SYS_BAT) < 3.5V
3.44
3.5
3.55
V
tDGL(MINSYS_CMP)
Deglitch time, VMINSYS
comparator rising
VBSUP1
Enter supplement mode
threshold
VBSUP2
8
ms
VBAT > VBUVLO
VBAT –
20mV
V
Exit supplement mode
threshold
VBAT > VBUVLO
VBAT –
5mV
V
ILIM(DISCH)
Current Limit, Discharge or
Supplement Mode (1)
VLIM(BGATE) = VBAT – VSYS
9
A
tDGL(SC1)
Deglitch Time, OUT Short
Circuit during Discharge or
Supplement Mode
Measured from IBAT = 7A to FET off
250
μs
tREC(SC1)
Recovery time, OUT Short
Circuit during Discharge or
Supplement Mode
2
s
Battery Range for BGATE
Operation
(1)
6
6
2.5
4.5
V
Continuous and periodic pulse currents from BAT to SYS are limited by output current specifications in the Absolute Maximum Ratings
table.
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SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
Electrical Characteristics (continued)
Circuit of Figure 7, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
YFF
17
25
RGE
32
47
UNIT
BATTERY CHARGER
RON(BAT-SYS)
VBATREG
Internal battery charger
MOSFET on-resistance
Measured from BAT to SYS,
VBAT = 4.2V, High-Z mode
Charge Voltage
Operating in voltage regulation, Programmable Range
RGE Package Voltage
Regulation Accuracy
3.5
4.44
TJ = 0°C to 50°C
-0.5%
0.5%
RGE Package Voltage
Regulation Accuracy
TJ = 0°C to 85°C
-0.7%
0.7%
YFF Package Voltage
Regulation Accuracy
TJ = 0°C to 85°C
-0.75%
0.75%
RGE and YFF Package
Voltage Regulation Accuracy
TJ = 0°C to 125°C
-1.0%
1.0%
YFF Package Voltage
Regulation Accuracy
TJ = 25°C
-29.2
28.1
YFF Package Voltage
Regulation Accuracy
TJ = 0°C to 85°C
-32.0
29.3
YFF Package Voltage
Regulation Accuracy
TJ = 0°C to 125°C
-40.2
29.3
Fast Charge Current Range
VBATSHRT ≤ VBAT < VBAT(REG)
500
2000
ICHARGE
Fast Charge Current
Accuracy
500 mA ≤ ICHARGE ≤ 1A
–10%
10%
ICHARGE > 1000 mA
–5%
VBATSHRT
Battery short circuit threshold
VBATSHRT_HYS
Hysteresis for VBATSHRT
Battery voltage falling
Deglitch time for battery short
to fastcharge transition
VBAT rising or falling
IBATSHRT
Battery short circuit charge
current
VBAT < VBATSHRT
ITERM
Termination charge current
1.9
ITERM ≤ 50 mA
50 mA <
ITERM
< 200 mA
ITERM ≥ 200 mA
tDGL(TERM)
Deglitch time for charge
termination
Both rising and falling, 2-mV over-drive,
tRISE, tFALL=100ns
VRCH
Recharge threshold voltage
Below VBATREG
tDGL(RCH)
Deglitch time
VBAT falling below VRCH, tFALL=100ns
VDET(SRC1)
Battery detection voltage
threshold
(TE = 1)
VDET(SRC2)
VDET(SNK)
33.5
V
mV
mA
5%
2
2.1
V
100
mV
1
ms
50
66.5
–30%
30%
–15%
15%
–15%
10%
32
100
mΩ
120
mA
ms
150
mV
32
ms
During current source (Turn IBATSHRT off)
VRCH
V
During current source (Turn IBATSHRT on)
VRCH
– 200mV
V
During current sink
VBATSHRT
V
IDETECT
Battery detection current
before charge done (sink
current)
Termination enabled (TE = 1)
7
mA
tDETECT(SRC)
Battery detection time
(sourcing current)
Termination enabled (TE = 1)
2
s
tDETECT(SNK)
Battery detection time (sinking
Termination enabled (TE = 1)
current)
250
ms
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bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
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Electrical Characteristics (continued)
Circuit of Figure 7, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT LIMITING
IINLIM
Input current limiting threshold
Input based DPM threshold
range
VIN_DPM
USB charge mode, VIN = 5V, Current
pulled from SW
IINLIM=USB100
90
95
100
IINLIM=USB500
450
475
500
IINLIM=USB150
125
140
150
IINLIM=USB900
800
850
900
IINLIM=1.5A
1425
1500
1575
IINLIM=2A, YFF
Package
1850
2000
2150
IINLIM=2A, RGE
Package
1850
2000
2200
IINLIM=2.5A, YFF
Package
2300
2500
2700
IINLIM=2.5A, RGE
Package
2225
2500
2825
Charge mode, programmable via I2C
VIN_DPM threshold Accuracy
4.2
11.6
–3%
3%
mA
V
VDRV BIAS REGULATOR
VDRV
Internal bias regulator voltage
IDRV
DRV Output Current
VDO_DRV
DRV Dropout Voltage
(VIN – VDRV)
VIN>5V
4.3
4.8
5.3
V
10
mA
IIN = 1A, VIN = 4.2V, IDRV = 10mA
450
mV
0.4
V
1
µA
0.4
V
0
STATUS OUTPUT (STAT, INT)
VOL
Low-level output saturation
voltage
IO = 10 mA, sink current
IIH
High-level leakage current
V STAT = VINT = 5V
INPUT PINS (CD, PSEL)
VIL
Input low threshold
VIH
Input high threshold
RPULLDOWN
CD pull-down resistance
Deglitch for CD and PSEL
8
1.4
V
CD Only
100
kΩ
CD or PSEL rising/falling
100
µs
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SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
Electrical Characteristics (continued)
Circuit of Figure 7, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.3
3.4
UNIT
PROTECTION
VUVLO
IC active threshold voltage
VIN rising
VUVLO_HYS
IC active hysteresis
VIN falling from above VUVLO
3.2
300
VBATUVLO
Battery Undervoltage Lockout
threshold
VBAT falling, 100mV Hysteresis
2.4
2.6
V
VSLP
Sleep-mode entry threshold,
VIN-VBAT
2.0 V < VBAT < VBATREG, VIN falling
40
120
mV
tDGL(BAT)
Deglitch time, BAT above
VBATUVLO before SYS starts to
rise
VSLP_HYS
Sleep-mode exit hysteresis
VIN rising above VSLP
tDGL(VSLP)
Deglitch time for supply rising
above VSLP+VSLP_HYS
Rising voltage, 2-mV over drive, tRISE=100ns
VOVP
Input supply OVP threshold
voltage
N rising, 100mV hysteresis
13.6
14
14.4
V
VBATGD
Good Battery Monitor
Threshold
VIN Rising
3.51
3.7
3.89
V
tDGL(BUCK_OVP)
Deglitch time, VIN OVP in
Buck Mode
IN falling below VOVP
VBOVP
Battery OVP threshold voltage VBAT threshold over VOREG to turn off charger during charge
VBOVP_HYS
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
tDGL(BOVP)
BOVP Deglitch
Battery entering/exiting BOVP
ICbCLIMIT
Cycle-by-cycle current limit
VSYS shorted
TSHTDWN
Thermal trip
0
1.2
40
Thermal regulation threshold
190
mV
ms
30
1.03 ×
VBATREG
1.05 ×
VBATREG
ms
1.07 ×
VBATREG
V
% of
VBATREG
1
8
4.1
Input current begins to cut off
Safety Timer Accuracy
100
ms
30
Thermal hysteresis
TREG
V
mV
4.5
ms
4.9
A
150
°C
10
°C
125
–20%
°C
20%
PWM
Internal top MOSFET onresistance
YFF Package: Measured from IN to SW
75
120
mΩ
RGE Package: Measured from IN to SW
80
135
mΩ
RDSON_Q2
Internal bottom N-channel
MOSFET on-resistance
YFF Package: Measured from SW to PGND
75
115
mΩ
RGE Package: Measured from SW to PGND
80
135
mΩ
fOSC
Oscillator frequency
1.5
1.65
MHz
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
RDSON_Q1
1.35
95
%
0
BATTERY-PACK NTC MONITOR (1)
VHOT
High temperature threshold
VTS falling, 2% VDRV Hysteresis
27.3
30
32.6
%VDRV
VWARM
Warm temperature threshold
VTS falling, 2% VDRV Hysteresis
36.0
38.3
41.2
%VDRV
VCOOL
Cool temperature threshold
VTS rising, 2% VDRV Hysteresis
54.7
56.4
58.1
%VDRV
VCOLD
Low temperature threshold
VTS rising, 2% VDRV Hysteresis
58.2
60
61.8
%VDRV
TSOFF
TS Disable threshold
VTS rising, 4% VDRV Hysteresis
80
85
%VDRV
tDGL(TS)
Deglitch time on TS change
Applies to VHOT, VWARM, VCOOL and VCOLD
50
ms
I2C COMPATIBLE INTERFACE
VIH
Input low threshold level
VPULL-UP=1.8V, SDA and SCL
VIL
Input low threshold level
VPULL-UP=1.8V, SDA and SCL
0.4
VOL
Output low threshold level
IL=5mA, sink current
0.4
V
IBIAS
High-Level leakage current
VPULL-UP=1.8V, SDA and SCL
1
μA
tWATCHDOG
1.3
30
tI2CRESET
V
50
s
700
ms
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Electrical Characteristics (continued)
Circuit of Figure 7, VUVLO < VIN < VOVP AND VIN > VBAT+ VSLP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
µA
4.5
V
5.2
V
OTG BOOST SUPPLY
Quiescent current during
boost mode (BAT pin)
3.3V (VBAT – 1V), the
bq24188 begins switching and regulates IN up to 5V. If VIN does not rise to within 1V of VBAT within 8ms, an
over-current event is detected and boost mode is exited and a boost mode over-current event is announced, the
BOOST_EN bit is reset to ‘0’ and the STAT_x and FAULT_x bits in the Status/ Control register are updated.
9.4.18.3 Burst Mode during Light Load
In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. During
boost mode, the PWM converter is turned off when the device reaches minimum duty cycle and the output
voltage rises to VBURST(ENT) threshold. This corresponds to approximately a 75mA inductor current. The converter
then restarts when VIN falls to VBURST(EXT). See Figure 37 in the Typical Operating Characteristics for an example
waveform.
9.4.18.4 Watchdog Timer in Boost Mode
During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Write
a “1” to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets the
EN_BOOST bit to 0, signals the fault pulse on the STAT and INT terminals. The FAULT_x bits read "Low Supply
Fault" as this is a higher priority fault than the WD timer.
9.4.18.5 STAT/ INT During Boost Mode
During boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128µs pulse is sent
out to notify the host of the error condition.
9.4.18.6 Protection in Boost Mode
9.4.18.6.1
Output Over-Voltage Protection
The bq24188 contains integrated over-voltage protection on the IN terminal. During boost mode, if an overvoltage condition is detected (VIN > VBOOSTOVP), after deglitch tDGL(BOOST_OVP), the IC turns off the PWM converter,
resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on STAT and INT. The converter
does not restart when VIN drops to the normal level until the EN_BOOST bit is reset to 1.
9.4.18.6.2
Output Over-Current Protection
The bq24188 contains over current protection to prevent the device and battery damage when IN is overloaded.
When an over-current condition occurs, the cycle-by-cycle current limit limits the current from the battery to the
load. If the overload condition lasts for 8ms, the overload fault is detected. When an overload condition is
detected, the bq24188 turns off the PWM converter, resets EN_BOOST bit to 0, sets the fault status bits and
sends out the fault pulse on STAT and INT. The boost operation starts only after the fault is cleared and the
EN_BOOST bit is reset to 1 using the I2C.
9.4.18.6.3
Battery Voltage Protection
During boost mode, when the battery voltage is below the minimum battery voltage threshold, VBATUVLO, the IC
turns off the PWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on
STAT and INT. Once the battery voltage returns to the acceptable level, the boost starts only after the
EN_BOOST bit is set to 1. Proper operation below 3.3V down to the VBATUVLOis not specified.
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9.5 Programming
9.5.1 Serial Interface Description
The bq24188 uses an I2C compatible interface to program charge parameters. I2C is a 2-wire serial interface
developed by NXP (formerly Philips Semiconductor, see I2C-Bus Specification, Version 5, October 2012). The
bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O
terminals, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the
bus. The master is responsible for generating the SCL signal and device addresses. The master also generates
specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits
data on the bus under control of the master device.
The bq24188 device works as a slave and supports the following data transfer modes, as defined in the I2C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from IN when a supply is connected. If the
IN supply is not connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must
stay above VBATUVLO with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is defined as
‘1101011’ (0x6Bh).
To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the transaction takes longer than
tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
9.5.2 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 15. All I2C -compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 15. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 16). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 17) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
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Programming (continued)
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 16. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1. In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 15). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
Clock Pulse for
Acknowledgement
START
Condition
Figure 17. Acknowledge on the I2C Bus
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Programming (continued)
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
ACK
ACK
Sr
or
P
Figure 18. Bus Protocol
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9.6 Register Descriptions
9.6.1 Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 00xx 0xxx
Figure 19. Status/Control Register
B7(MSB)
0
R/W
B6
0
R/W
B5
X
R
B4
X
R
B3
0
R/W
B2
X
R
B1
X
R
B0(LSB)
X
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
BIT
FEILD (1)
(2)
TYPE
DESCRIPTION
B7(MSB)
TMR_RST
R/W
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
B6
EN_BOOST
R/W
0-Charger Mode
1-Boost Mode (default 0)
B5
STAT_1
R
B4
STAT_0
R
B3
EN_SHIPMODE
R/W
B2
FAULT_2
R
B1
FAULT_1
R
B0(LSB)
FAULT_0
R
(1)
(2)
00-Ready
01-Charge in progress
10-Charge done
11-Fault
0-Normal Operation
1-Ship Mode Enabled (default 0)
000-Normal
001-VIN > VOVP or Boost Mode OVP
010- Low Supply connected (VIN TS temp > TCOLD (Charge current reduced by half)
11 – TWARM < TS temp < THOT (Charge voltage reduced by 100mV)
0 – 4.2V
1 – 10.1V
(Default 0)
BOOST_ILIM Bit (Boost current limit setting)
The BOOST_ILIM bit programs the cycle by cycle current limit threshold for boost operation. The 1 A
setting sets the low side cycle by cycle current limit to 4 A (typ). This ensures that at least 1 A can be
supplied from the boost converter over the entire battery range. The 500 mA setting sets the current limit
to 2 A (typ) to ensure at least 500 mA available from the boost converter. See the Output Over-Current
Protection section for more details.
VINDPM_OFF Bit (VINDPM offset setting)
The VINDPM_OFF bit programs the offset for the VINDPM function. The 4.2 V setting is intended to work
with a standard 5V output adapter. The 10.1 V setting supports 12 V adapters and the 12 V output for the
new USB Power Delivery specification (USB PD).
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The bq24188EVM evaluation module (EVM) is a complete charger module for evaluating the bq24188. The
application curves were taken using the bq24188. See Related Documentation .
10.2 Typical Applications
10.2.1
bq24188 Typical Application
1.5 µH
PMID
SW
10 µF
1 µF
System
Load
0.033 µF
BOOT
SYS
IN
VBUS
D+
10 µF
DGND
Optional FET
4.7 µF
BGATE
DRV
BAT
DRV
DRV
1 µF
2.2 µF
PGND
STAT
5.62 k
PACK+
TS
1.5 k
TEMP
VI/O
(1.8V)
12.4 k
PSEL
USB PHY
PACK-
1.5 k
HOST
bq24188
INT
GPIO
SDA
SDA
SCL
SCL
CD
GPIO
Figure 26. bq24188 Typical Application Circuit
36
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Typical Applications (continued)
10.2.1.1 Design Requirements
Table 2. Design Requirements
DESIGN PARAMATER
EXAMPLE VALUE
Input Voltage Range
4.75 V to 5.25 V nominal, withstand 28 V
Input Current Limit
1500 mA
Input DPM Threshold
4.25 V
Fast Charge Current
2000 mA
Battery Charge Voltage
4.2 V
Termination Current
50 mA
10.2.1.2 Detailed Design Procedure
The parameters are configurable using the EVM software.
The typical application circuit shows the minimum capacitance requirements for each pin. Options for sizing the
inductor outside the 1.5 μH recommended value and additional SYS pin capacitance are explained in the next
section. The resistors on STAT and INT are sized per each LED's current requirements. The TS resistor divider
for configuring the TS function to work with the battery's specific thermistor can be computed from Equation 1
and Equation 2. The external battery FET is optional.
10.2.2 bq24188 Typical Application – External Discharge FET
1 .5 µH
PMID
SW
1 µF
0 .033 µF
System
Load
47 µF
10 µF
BOOT
SYS
IN
VBUS
D+
D-
PGND
GND
4 .7 µF
BGATE
DRV
BAT
VDRV
2.2 µF
1 µF
STAT
PACK +
TS
TEMP
V SYS
( 1 .8 V )
D+
D–
PACK -
HOST
bq24188
INT
GPIO 1
SDA
SDA
SCL
SCL
CD
Figure 27. bq24188 Typical Application Circuit
10.2.3 Output Inductor and Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24188 is designed to work with 1.5 µH to 2.2 µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2 µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5 µH inductor provides a good tradeoff between size and efficiency.
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Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use Equation 5 to calculate the peak current.
æ %
ö
IPEAK = ILOAD(MAX) ´ ç 1 + RIPPPLE ÷
2
è
ø
(5)
The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to
the high currents possible with the bq24188, a thermal analysis must also be done for the inductor. Many
inductors have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise
above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted
for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at
2.5A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D × (IPEAK – ILOAD) = 1.5 A + 0.2 × (2.5 A – 1.5 A) = 1.7 A
The internal loop compensation of the bq24188 is designed to be stable with 10 µF to 150 µF of local
capacitance but requires at least 20 µF total capacitance on the SYS rail (10 µF local + ≥ 10 µF distributed). The
capacitance on the SYS rail can be higher than 150 µF if distributed amongst the rail. To reduce the output
voltage ripple, a ceramic capacitor with the capacitance between 10 µF and 47 µF is recommended for local
bypass to SYS. If greater than 100 µF effective capacitance is on the SYS rail, place at least 10 µF bypass on
the BAT terminal. Pay special attention to the DC bias characteristics of ceramic capacitors. For small case
sizes, the capacitance can be derated as high as 70% at workable voltages. All capacitances specified in this
datasheet are effective capacitance, not capacitor value.
10.2.4 Application Curves
VBAT = 3.8V
VREG = 4.2V
Figure 28. Startup With No Battery
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VIN = 5V
ICHG = 0.5V
Figure 29. Battery Detection
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Figure 31. Default Start-Up - bq24188
(D+/D– Shorted)
Figure 30. Battery Removal
VBATREG = 3.6V
VSYS = 3.68V
Figure 32. Default Start-Up - bq24188
(D+/D– Not Shorted)
VBATREG = 3.6V
VBAT = 3.4V
VIN = 5V
Step from 100mA to 3.3A
Figure 34. VSYS Transient With Supplement Mode
VIN = 5.5V
Step from 100mA to 3.3A
Figure 33. VSYS Transient Without Supplement Mode
VBATREG = 3.6V
VBAT = 3.4V
VIN = 5V
Step from 100mA to 3.3A
Figure 35. VSYS Transient With Supplement Mode
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Figure 36. Boost Startup No Load
Figure 37. Boost Burst Mode During Light Load
Figure 38. Boost Startup 1A Load
Figure 39. Boost Transient Response
VBAT = 3.6V
ICHG = 2A
ISYS = 0A
Figure 40. Input OVP Event with INT
40
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VBATREG = 4.2V
ILIM = 0.5A
VDPM = 4.36V
Figure 41. Startup, 4.2V
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11 Power Supply Recommendations
11.1 Requirements for SYS Output
In order to provide an output voltage on SYS, the bq24188 requires either a power supply between 4.2 V and 6.0
V input on all versions, 4.2 and 14 V on bq24188 with at least 100 mA current rating connected to IN; or, a
single-cell Li-Ion battery with voltage > VBATUVLO connected to BAT. The source current rating needs to be at
least 2.5 A in order for the buck converter of the charger to provide maximum output power to SYS.
11.2 Requirements for Charging
In order for charging to occur the source voltage measured at the IN terminals of the IC, factoring in cable/trace
losses from the source, must be greater than the VINDPM threshold, but less than the maximum values shown
above. The current rating of the source must be higher than the buck converter needs to provide the load on
SYS. For charging at a desired charge current of ICHRG, VIN x IIN x η > VSYS x (ISYS+ ICHRG) where η is the
efficiency estimate from Figure 2 or Figure 3 and VSYS = VBAT when VBAT charges above VMINSYS. The
charger limits IIN to the current limit setting of that input. With ISYS = 0 A, the charger consumes maximum
power at the end of CC mode, when the voltage at the BAT terminal is near VBATREG but ICHRG has not
started to taper off toward ITERM.
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12 Layout
12.1 Layout Guidelines
The following provides some guidelines:
• Place 1µF input capacitor as close to PMID terminal and PGND terminal as possible to make high frequency
current loop area as small as possible.
• Connect the GND of the PMID and IN caps as close as possible.
• Place 4.7µF input capacitor as close to IN terminal and PGND terminal as possible to make high frequency
current loop area as small as possible.
• The local bypass capacitor from SYS to GND should be connected between the SYS terminal and PGND of
the IC. The intent is to minimize the current path loop area from the SW terminal through the LC filter and
back to the PGND terminal.
• Place all decoupling capacitors close to their respective IC terminal and as close as to PGND as possible. Do
not place components such that routing interrupts power stage currents. All small control signals should be
routed away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias.
Two vias per capacitor for power-stage capacitors and one via per capacitor for small-signal components. It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results.
• The high-current charge paths into IN, BAT, SYS and from the SW terminals must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND terminals should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
12.2 Layout Example
It is important to pay special attention to the PCB layout. Figure 42 provides a sample layout for the high current
paths of the bq24188YFF. Figure 43 provides a sample layout for the high current paths of the bq24188RGE.
PMID
PMID and IN
Cap Gnds
close together
PGND
SW
IN cap close
to IN pin
BOOT
Thermal vias
connect to
PGND
SYS cap
close to
SYS pins
BAT cap close
to BAT pins
Figure 42. Recommended bq24188 PCB Layout for WCSP Package
sp
42
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Layout Example (continued)
PGND
SW
PMID
PMID and IN
Cap Gnds
BOOT
Close together
SYS Cap
IN Cap
Close to
Close to
SYS Pins
IN Pin
BAT Cap
Thermal
Close to
Vias connect
BAT Pins
To GND
Figure 43. Recommended bq24188 PCB Layout for QFN Package
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
User's Guide for WCSP Packaged bq24260, bq24261 and bq24262A 3-A Battery Charger Evaluation Module,
SLUUAB0.
User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A Battery Charger Evaluation Module,
SLUUAV8.
3A, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger Evaluation Module,
http://www.ti.com/tool/bq24261evm-611.
Host-Controlled Single-Input, Single Cell
http://www.ti.com/tool/bq24261evm-079.
Switchmode
Li-Ion
Battery
Charger
Evaluation
Module,
EVM Software, SLUC519
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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22-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24188YFFR
ACTIVE
DSBGA
YFF
36
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24188
BQ24188YFFT
ACTIVE
DSBGA
YFF
36
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ24188
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
BQ24188YFFR
DSBGA
YFF
36
3000
180.0
8.4
BQ24188YFFT
DSBGA
YFF
36
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.54
2.54
0.76
4.0
8.0
Q1
2.54
2.54
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24188YFFR
DSBGA
YFF
36
3000
182.0
182.0
20.0
BQ24188YFFT
DSBGA
YFF
36
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0036
DSBGA - 0.625 mm max height
SCALE 4.500
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
BALL TYP
0.30
0.12
0.05 C
2 TYP
SYMM
F
D: Max = 2.485 mm, Min =2.425 mm
E
D
2
TYP
C
B
36X
A
0.4 TYP
E: Max = 2.485 mm, Min =2.425 mm
SYMM
1
2
3
4
5
6
0.3
0.2
0.015
C A
B
0.4 TYP
4222008/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0036
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
36X ( 0.23)
1
2
3
4
5
6
A
(0.4) TYP
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
( 0.23)
METAL
0.05 MAX
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222008/A 03/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0036
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
36X ( 0.25)
1
2
4
3
5
6
A
(0.4)
TYP
METAL
TYP
B
C
SYMM
D
E
F
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222008/A 03/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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