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bq24232HA
SLUSCG4 – MAY 2016
bq24232HA USB-Friendly Lithium-Ion Battery Charger and Power-Path Management IC
•
•
•
•
•
•
•
•
2 Applications
•
•
The battery is charged in three phases: conditioning,
constant current, and constant voltage. In all charge
phases, an internal control loop monitors the IC
junction temperature and reduces the charge current
if the internal temperature threshold is exceeded.
The charger power stage and charge current sense
functions are fully integrated. The charger function
has high-accuracy current and voltage regulation
loops, charge status display, and charge termination.
The input current limit and charge current are
programmable using external resistors.
Device Information(1)
PART NUMBER
bq24232HA
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Bluetooth™ Devices
Low-Power Handheld Devices
Typical Application Circuit
R5
1.5 kΩ
3 Description
R6
1.5 kΩ
SYSTEM
Adaptor
DC+
IN
OUT
C1
1 μF
GND
C2
4.7μF
VSS
bq24232HA
EN 2
EN 1
TS
CE
BAT
PACK +
TEMP
TMR
C3
4.7 μF
IT E R M
The bq24232HA device is a highly integrated Li-ion
linear charger and system power-path management
device targeted at space-limited portable applications.
The device operates from either a USB port or ac
adapter and supports charge currents between 25
mA and 500 mA. The high-input-voltage range with
input overvoltage protection supports low-cost,
unregulated adapters. The USB input current limit
accuracy and start-up sequence allow the
bq24232HA to meet USB-IF inrush current
specification. Additionally, the input dynamic power
management (VIN – DPM) prevents the charger from
crashing poorly designed or incorrectly configured
USB sources.
PACKAGE
VQFN (16)
PACK -
R1
3.57 kΩ
IS E T
•
CH G
•
•
Fully Compliant USB Charger
– Selectable 100-mA and 500-mA Maximum
Input Current
– 100-mA Maximum Current Limit Ensures
Compliance to USB-IF Standard
– Input-based Dynamic Power Management
(VIN – DPM) for Protection Against Poor USB
Sources
28-V Input Rating With Overvoltage Protection
Integrated Dynamic Power-Path Management
(DPPM) Function Simultaneously and
Independently Powers the System and Charges
the Battery
Supports up to 500-mA Charge Current With
Current Monitoring Output (ISET)
Programmable Input Current Limit up to 500 mA
for Wall Adapters
Programmable Termination Current
Programmable Precharge and Fast-Charge Safety
Timers
Reverse Current, Short-Circuit, and Thermal
Protection
NTC Thermistor Input
Proprietary Start-Up Sequence Limits Inrush
Current
Status Indication – Charging/Done, Power Good
Small 3 mm × 3 mm 16-Lead QFN Package
PGOOD
•
1
The bq24232HA features dynamic power-path
management (DPPM) that powers the system while
simultaneously and independently charging the
battery. The DPPM circuit reduces the charge current
when the input current limit causes the system output
to fall to the DPPM threshold, thus supplying the
system load at all times while monitoring the charge
current separately. This feature reduces the number
of charge and discharge cycles on the battery, allows
for proper charge termination, and enables the
system to run with a defective or absent battery pack.
Additionally, this enables instant system turn-on even
with a totally discharged battery. The power-path
management architecture also permits the battery to
supplement the system current requirements when
the adapter cannot deliver the peak system currents,
enabling the use of a smaller adapter.
IL IM
1 Features
R2
3.06 kΩ
R4
56 .2 kΩ
R3
4 .32 kΩ
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24232HA
SLUSCG4 – MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 26
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Power Supply Recommendations...................... 29
9.1 Requirements for OUT Output ................................ 29
9.2 USB Sources and Standard AC Adapters .............. 29
9.3 Half-Wave Adapters ................................................ 29
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
10.3 Thermal Considerations ........................................ 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Application and Implementation ........................ 25
11
12
13
19
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
2
DATE
REVISION
NOTES
May 2016
*
Initial release.
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bq24232HA
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SLUSCG4 – MAY 2016
5 Pin Configuration and Functions
ISET
ITERM
TMR
IN
RGT Package
16-Pin VQFN
Top View
16 15
14
13
BAT
2
11
OUT
BAT
3
10
OUT
CE
4
9
CHG
5
6
7
8
VSS
ILIM
PGOOD
12
EN1
1
EN2
TS
Pin Functions
PIN
I/O
DESCRIPTION
1
I
External NTC Thermistor Input. Connect the TS input to the NTC thermistor in the battery pack. TS monitors a 10-kΩ
NTC thermistor. For applications that do not utilize the TS function, connect a 10-kΩ fixed resistor from TS to VSS to
maintain a valid voltage level on TS.
BAT
2, 3
I/O
CE
4
I
EN2
5
I
EN1
6
I
PGOOD
7
O
Open-drain Power Good Status Indication Output. PGOOD pulls to VSS when a valid input source is detected.
PGOOD is high-impedance when the input power is not within specified limits. Connect PGOOD to the desired logic
voltage rail using a 1-kΩ – 100-kΩ resistor, or use with an LED for visual indication.
VSS
8
—
Ground. Connect to the thermal pad and to the ground rail of the circuit.
CHG
9
O
Open-Drain Charging Status Indication Output. CHG pulls to VSS when the battery is charging. CHG is high
impedance when charging is complete and when charger is disabled.
OUT
10, 11
O
System Supply Output. OUT provides a regulated output when the input is below the OVP threshold and above the
regulation voltage. When the input is out of the operation range, OUT is connected to VBAT. Connect OUT to the
system load. Bypass OUT to VSS with a 4.7-μF to 47-μF ceramic capacitor.
ILIM
12
I
Adjustable Current Limit Programming Input. Connect a 3.06-kΩ to 7.8-kΩ resistor from ILIM to VSS to program the
maximum input current (EN2 = 1, EN1 = 0). The input current includes the system load and the battery charge
current. Leaving ILIM unconnected disables all charging. In USB100/500 mode (EN2 = 0, EN1 = 0/1), ILIM can be
left floating.
IN
13
I
Input Power Connection. Connect IN to the connected to external DC supply (AC adapter or USB port). The input
operating range is 4.35 V to 6.6 V. The input can accept voltages up to 26 V without damage but operation is
suspended. Connect bypass capacitor 1 μF to 10 μF to VSS.
TMR
14
I
Timer Programming Input. TMR controls the precharge and fast-charge safety timers. Connect TMR to VSS to
disable all safety timers. Connect a 18-kΩ to 72-kΩ resistor between TMR and VSS to program the timers a desired
length. Leave TMR unconnected to set the timers to the 5-hour fast charge and 30-minute precharge default timer
values.
ITERM
15
I
Termination Current Programming Input. Connect a 0-Ω to 15-kΩ resistor from ITERM to VSS to program the
termination current. Leave ITERM unconnected to set the termination current to the internal default 10% threshold.
ISET
16
I/O
Fast-Charge Current Programming Input. Connect a 1.8-kΩ to 36-kΩ resistor from ISET to VSS to program the fastcharge current level. Charging is disabled if ISET is left unconnected. While charging, the voltage at ISET reflects the
actual charging current and can be used to monitor charge current. See the Charge Current Translator section for
more details.
—
An internal electrical connection exists between the exposed thermal pad and the VSS pin of the device. The thermal
pad must be connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad
as the primary ground input for the device. The VSS pin must be connected to ground at all times.
NAME
TS
Thermal Pad
NO.
Charger Power Stage Output and Battery Voltage Sense Input. Connect BAT to the positive terminal of the battery.
Bypass BAT to VSS with a 4.7-μF to 47-μF ceramic capacitor.
Charge Enable Active-Low Input. Connect CE to a high logic level to disable battery charging. OUT is active and
battery supplement mode is still available. Connect CE to a low logic level to enable the battery charger. CE is
internally pulled down with ~285 kΩ. Do not leave CE unconnected to ensure proper operation.
Input Current Limit Configuration Inputs. Use EN1 and EN2 control the maximum input current and enable USB
compliance. See EN1/EN2 Settings for the description of the operation states. EN1 and EN2 are internally pulled
down with ~285 kΩ. Do not leave EN1 or EN2 unconnected to ensure proper operation.
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Table 1. EN1/EN2 Settings
EN2
EN1
0
0
MAXIMUM INPUT CURRENT INTO IN PIN
100 mA, USB100 mode
0
1
500 mA, USB500 mode
1
0
Set by an external resistor from ILIM to VSS
1
1
Standby (USB suspend mode)
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage
II
Input current
IO
Output current (continuous)
Output sink current
(1)
MIN
MAX
IN (with respect to VSS
–0.3
28
OUT (with respect to VSS)
–0.3
7
BAT (with respect to VSS)
–0.3
5
EN1, EN2, CE, TS, ISET, PGOOD, CHG, ILIM, TMR, TD,
ITERM (with respect to VSS)
–0.3
7
V
IN
600
OUT
1700
BAT (discharge mode)
1700
CHG, PGOOD
mA
mA
15
mA
TJ
Junction temperature
–40
150
Tstg
Storage temperature
–65
150
(1)
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over junction temperature range –5°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
VI
MIN
MAX
IN voltage
4.35
26
UNIT
V
IN operating voltage
4.35
10.2
V
IIN
Input current, IN pin
500
mA
IOUT
Current, OUT pin
1500
mA
IBAT
Current, BAT pin (discharging)
1500
mA
ICHG
Current, BAT pin (charging)
500
mA
RILIM
Maximum input current programming resistor
3.1
7.8
kΩ
RISET
Fast-charge current programming resistor
1.8
36
kΩ
RTMR
Timer programming resistor
18
72
kΩ
RITERM
Termination programming resistor
0
15
kΩ
TJ
Junction temperature
–5
125
°C
4
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SLUSCG4 – MAY 2016
6.4 Thermal Information
bq24232HA
THERMAL METRIC (1)
RGT (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
44.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.2
°C/W
RθJB
Junction-to-board thermal resistance
17.2
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
17.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over junction temperature range –5°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.3
MAX
UNIT
INPUT
UVLO
Undervoltage lockout
VIN: 0 V → 4 V
3.2
Vhys(UVLO)
Hysteresis on UVLO
VIN: 4 V → 0 V
200
VIN(DT)
Input power detection
threshold
Input power detected when VIN > VBAT + VIN(DT)
VBAT = 3.6 V, VIN: 3.5 V → 4 V
Vhys(INDT)
Hysteresis on VIN(DT)
VBAT = 3.6 V, VIN: 4 V → 3.5 V
20
VOVP
Input overvoltage protection
threshold
('230) VIN: 5 V → 7 V
('232) VIN: 5 V → 11 V
Vhys(OVP)
Hysteresis on OVP
('230) VIN: 7 V → 5V
110
('232) VIN: 11 V → 5 V
213
3.4
V
300
mV
95
152
mV
6.4
6.6
6.8
10.2
10.5
10.8
55
mV
V
mV
ILIM, TEST ISET SHORT CIRCUIT
ISC
Current source
VSC
VIN > UVLO and VIN > VBAT+VIN(DT)
1.3
mA
VIN > UVLO and VIN > VBAT+VIN(DT)
502
mV
QUIESCENT CURRENT
IBAT(PDWN)
Sleep current into BAT pin
IIN(STDBY)
Standby current into IN pin
ICC
Active supply current, IN pin
CE = LO or HI, input power not
detected, no load on OUT pin
TJ= -5°C to 55°C
6.5
TJ= -5°C to 85°C
9.5
EN1= HI, EN2=HI, VIN = 6 V, TJ= 85°C
50
EN1= HI, EN2=HI, VIN = 10 V, TJ= 85°C
200
CE = LO, VIN = 6 V, no load on OUT pin,
VBAT > VBAT(REG), (EN1, EN2) ≠ (HI, HI)
1.5
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μA
μA
mA
5
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Electrical Characteristics (continued)
over junction temperature range –5°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
136
237.5
mV
62.5
mV
V
POWER PATH
VDO(IN-OUT)
VIN – VOUT
VIN = 4.3 V, IIN = 500 mA, VBAT = 4.2 V
VDO(BAT-OUT)
VBAT – VOUT
IOUT = 500 mA, VIN = 0 V, VBAT > 3 V
VO(REG)
OUT pin voltage regulation
VIN > VOUT + VDO (IN-OUT)
IINmax
Maximum input current
KILIM
Maximum input current
factor
4.35
4.5
4.6
EN1 = LO, EN2 = LO
90
95
100
EN1 = HI, EN2 = LO
450
475
500
EN2 = HI, EN1 = LO
ILIM = 200 mA to 500 mA
KILIM/RILIM
1380
IINmax
Programmable input current
limit range
EN2 = HI, EN1 = LO, RILIM = 3.06 kΩ to 7.8 kΩ
200
VIN-DPM
Input voltage threshold
when input current is
reduced
EN2 = LO, EN1 = X
4.3
VDPPM
Output voltage threshold
when charging current is
reduced
VBSUP1
Enter battery supplement
mode
VBSUP2
Exit battery supplement
mode
Output short-circuit
detection threshold, poweron
VIN > UVLO and VIN > VBAT+VIN(DT)
VO(SC1)
VIN > UVLO and VIN > VBAT+VIN(DT)
VO(SC2)
Output short-circuit
detection threshold,
supplement mode VBAT –
VOUT > VO(SC2) indicates
short circuit
6
VO(REG) –
180 mV
VBAT = 3.6 V, RILIM = 1.5 kΩ, RLOAD = 10 Ω →2 Ω
VBAT = 3.6 V, RILIM = 1.5 kΩ, RLOAD = 2 Ω →10 Ω
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1571
4.35
VO(REG) –
100 mV
mA
A
1700
AΩ
500
mA
4.63
V
VO(REG) –
30 mV
V
VOUT ≤
VBAT –50
mV
V
VOUT ≥
VBAT–20
mV
V
0.8
0.9
1
200
242
300
V
mV
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bq24232HA
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SLUSCG4 – MAY 2016
Electrical Characteristics (continued)
over junction temperature range –5°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
8.15
11
mA
1.6
1.8
2
V
4.25
4.31
4.35
V
2.9
3
3.1
V
500
mA
BATTERY CHARGER
IBAT(SC)
Source current for BAT pin
short-circuit detection
VBAT = 1.5 V
VBAT(SC)
BAT pin short-circuit
detection threshold
VBAT rising
VBAT(REG)
Battery charge voltage
VLOWV
Precharge to fast-charge
transition threshold
VIN > UVLO and VIN > VBAT + VIN(DT)
Battery fast-charge current
range
VBAT(REG) > VBAT > VLOWV, VIN = 5 V, CE = LO, EN1 = LO, EN2 =
HI
Battery fast-charge current
CE = LO, EN1= LO, EN2 = HI,
VBAT > VLOWV, VIN = 5 V, IINmax > ICHG, no load on OUT pin,
thermal loop and DPM loop not active
KISET
Fast-charge current factor
25 mA ≥ ICHG≥ 500 mA
KIPRECHG
Precharge current factor
2.5 mA ≥ IPRECHG≥ 30 mA
ICHG
ITERM
Termination comparator
threshold for termination
detection
ITERM
Termination current
threshold factor
IBIAS(ITERM)
Current for external
termination-setting resistor
KITERM
K factor for termination
detection threshold
(externally set)
25
KISET/RISET
A
797
870
975
AΩ
AΩ
70
88
106
CE = LO, (EN1,EN2) ≠ (LO,LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPM loop and thermal loop
not active
0.09 ×
ICHG
0.1 × ICHG
0.11 ×
ICHG
CE = LO, (EN1,EN2) = (LO,LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPM loop and thermal loop
not active
0.027 ×
ICHG
0.033 ×
ICHG
0.040 ×
ICHG
ITERM = 0% to 50% of ICHG
A
KITERM × RITERM / RISET
72
75
78
CE = LO, (EN1,EN2) ≠ (LO,LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPM loop and thermal loop
not active
0.024
0.030
0.036
CE = LO, (EN1,EN2) = (LO,LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPM loop and thermal loop
not active
0.009
0.010
0.011
VBAT(REG)
–140 mV
VBAT(REG)
–100 mV
VBAT(REG)
–60 mV
5
7.5
10
VRCH
Recharge detection
threshold
VIN > UVLO and VIN > VBAT+VIN(DT)
IBAT(DET)
Sink current for battery
detection
VBAT=2.5 V
A
μA
A
V
mA
BATTERY-PACK NTC MONITOR (1)
INTC
NTC bias current
VIN > UVLO and VIN > VBAT+VIN(DT)
VHOT
High-temperature trip point
Battery charging, VTS Falling
VHYS(HOT)
Hysteresis on high trip point
Battery charging, VTS Rising from VHOT
VCOLD
Low-temperature trip point
Battery charging, VTS Rising
VHYS(COLD)
Hysteresis on low trip point
Battery charging, VTS Falling from VCOLD
VDIS(TS)
TS function disable
threshold
TS unconnected
72
75
79
μA
270
300
330
mV
2000
2100
30
mV
2200
300
mV
mV
VIN – 200
mV
V
125
°C
155
°C
20
°C
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
TJ(OFF)
Thermal shutdown
temperature
TJ(OFF-HYS)
Thermal shutdown
hysteresis
(1)
TJ rising
These numbers set trip points of 0°C and 50°C while charging, with 3°C hysteresis on the trip points, with a Vishay Type 2 curve NTC
with an R25 of 10 kΩ.
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Electrical Characteristics (continued)
over junction temperature range –5°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC LEVELS ON EN1, EN2, CE, TD
VIL
Logic LOW input voltage
0
0.4
VIH
Logic HIGH input voltage
1.4
6.0
V
V
IIL
Input sink current
VIL = 0 V
1
μA
IIH
Input source current
VIH = 1.4 V
10
μA
ISINK = 5 mA
0.4
V
LOGIC LEVELS ON PGOOD, CHG
VOL
Output LOW voltage
6.6 Timing Requirements
over junction temperature range –5°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
tDGL(PGOOD)
Deglitch time, input power
detected status
tDGL(OVP)
Input overvoltage blanking time
tREC(OVP)
Input overvoltage recovery time
Time measured from VIN: 0 V → 5-V
1-μs rise time to PGOOD = LO
Time measured from VIN: 11 V → 5-V
1-μs fall time to PGOOD = LO
2
ms
50
μs
2
ms
250
μs
60
ms
POWER PATH
tDGL(SC2)
Deglitch time, supplement mode
short circuit
tREC(SC2)
Recovery time, supplement
mode short circuit
BATTERY CHARGER
tDGL1(LOWV)
Deglitch time on precharge to
fast-charge transition
25
ms
tDGL2(LOWV)
Deglitch time on fast-charge to
precharge transition
25
ms
tDGL(TERM)
Deglitch time, termination
detected
25
tDGL(RCH)
Deglitch time, recharge
threshold detected
tDGL(NO-IN)
Delay time, input power loss to
charger turnoff
VBAT = 3.6 V. Time measured from
VIN: 5 V → 3 V 1-μs fall time
ms
62.5
ms
20
ms
BATTERY CHARGING TIMERS
tPRECHG
Precharge safety timer value
TMR = floating
1440
1800
2160
s
tMAXCHG
Charge safety timer value
TMR = floating
14400
18000
21600
s
tPRECHG
Precharge safety timer value
18 kΩ < RTMR < 72 kΩ
RTMR × KTMR
s
tMAXCHG
Charge safety timer value
18 kΩ < RTMR < 72 kΩ
10×RTMR ×KTMR
s
KTMR
Timer factor
36
48
60
s/kΩ
BATTERY-PACK NTC MONITOR (1)
tDGL(TS)
(1)
8
Deglitch time, pack temperature
fault detection
Battery charging, VTS Falling
50
ms
These numbers set trip points of 0°C and 50°C while charging, with 3°C hysteresis on the trip points, with a Vishay Type 2 curve NTC
with an R25 of 10 kΩ.
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6.7 Typical Characteristics
Typical Application Circuit, EN1 = 0, EN2 = 1, TA = 25°C, unless otherwise noted.
0.3
250
0.3
Dropout Voltage - VIN-VOUT
IBAT - mA
200
150
100
50
0.2
0.2
0.1
0.1
0.0
0
120
0
125
130
135
140
TA - Free-Air Temperature - °C
0
145
25
100
50
75
TJ - Junction Temperature - °C
125
IL = 500 mA
Figure 2. Dropout Voltage vs Temperature
60
4.45
50
4.43
40
VO - Output Voltage - V
Dropout Voltage - VBAT-VOUT
Figure 1. Thermal Regulation
VBAT = 3 V
30
VBAT = 3.9 V
20
4.40
4.38
4.35
4.33
10
4.30
0
0
50
75
100
25
TJ - Junction Temperature - °C
125
0
IL = 500 mA
Figure 3. Dropout Voltage vs Temperature
75
100
125
IL = 500 mA
Figure 4. Output Regulation Voltage vs Temperature
10.70
VOVP - Output Voltage Threshold - V
VBAT - Regulation Voltage - V
50
VIN = 5 V
4.210
4.205
4.200
4.195
4.190
4.185
4.180
0
25
TJ - Junction Temperature - °C
25
50
75
100
125
150
TJ - Junction Temperature - °C
10.65
10.60
VI Rising
10.55
10.50
10.45
VI Falling
10.40
10.35
10.30
10.25
10.20
0
25
75
50
100
TJ - Junction Temperature - °C
125
10.5 V
Figure 5. Battery Regulation Voltage vs Temperature
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Figure 6. Overvoltage Protection Threshold vs Temperature
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Typical Characteristics (continued)
Typical Application Circuit, EN1 = 0, EN2 = 1, TA = 25°C, unless otherwise noted.
310
800
IBAT - Fast Charge Current - A
ILIM - Input Current - mA
700
600
500
USB500
400
300
200
USB100
305
300
295
290
285
100
0
280
5
6
7
8
9
VI - Input Voltage - V
10
3
3.2
3.4
3.6
3.8
4
VBAT - Battery Voltage - V
4.2
RISET = 3.3 kΩ
Figure 7. Input Current Limit Threshold vs Input Voltage
Figure 8. Fast-Charge Current vs Battery Voltage
31.5
IBAT - Precharge Current - A
31
30.5
30
29.5
29
28.5
2
2.2
2.4
2.6
2.8
VBAT - Battery Voltage - V
3
RISET = 3.3 kΩ
Figure 9. Precharge Current vs Battery Voltage
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7 Detailed Description
7.1 Overview
The bq24232HA device is an integrated Li-ion linear charger and system power-path management device
targeted at space-limited portable applications. The device powers the system while simultaneously and
independently charging the battery. This feature reduces the number of charge and discharge cycles on the
battery, allows for proper charge termination, and enables the system to run with a defective or absent battery
pack. It also allows instant system turnon even with a totally discharged battery. The input power source for
charging the battery and running the system can be an AC adapter or a USB port. The devices feature dynamic
power-path management (DPPM), which shares the source current between the system and battery charging
and automatically reduces the charging current if the system load increases. When charging from a USB port,
the input dynamic power management (VIN – DPM) circuit reduces the input current limit if the input voltage falls
below a threshold, preventing the USB port from crashing. The power-path architecture also permits the battery
to supplement the system current requirements when the adapter cannot deliver the peak system currents.
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7.2 Functional Block Diagram
250 mV
VO (SC1)
VBAT
OUT- SC1
tDGL(SC2)
OUT- SC 2
Q1
IN
OUT
EN2
Short Detect
225 mV
Precharge
2. 25
. V
Fastcharge
VIN-LOW
USB100
USB500
ILIM
V REF-ILIM
USB-susp
ISET
TJ
TJ (REG)
Short Detect
VDPPM
VOUT
VO (REG)
Q2
VBAT(REG)
EN2
EN1
BAT
V OUT
CHARGEPUMP
I BIAS-ITERM
40 mV
Supplement
V LOWV
225 mV
ITERM
VBAT(SC)
VRCH
tDGL(RCH)
tDGL2(LOWV)
tDGL(TERM)
VIN
tDGL1(LOWV)
ITERM- floating
~3 V
BAT-SC
VBAT+VIN-DT
t DGL (NO-IN)
t DGL(PGOOD)
VUVLO
I NTC
V HOT
Charge Control
TS
t DGL (TS )
V COLD
V OVP
t BLK (OVP)
VDIS(TS)
EN1
EN2
USB Suspend
CE
Halt timers
CHG
VIPRECHG
V CHG
I
VISET
Dynamically
Controlled
Oscillator
Reset timers
PGOOD
Fast- Charge
Timer
Timer fault
TMR
Pre -Charge
Timer
~100 mV
Timers disabled
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7.3 Feature Description
7.3.1 Undervoltage Lockout
The bq24232HA remains in power-down mode when the input voltage at the IN pin is below the undervoltage
lockout (UVLO) threshold.
During the power-down mode, the host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1
FET connected between IN and OUT pins is off, and the status outputs CHG and PGOOD are high impedance.
The Q2 FET that connects BAT to OUT is ON. During power-down mode, the VOUT(SC2) circuitry is active and
monitors for overload conditions on OUT.
7.3.2 Power On
When VIN exceeds the UVLO threshold, the bq24232HA powers up. While VIN is below VBAT + VIN(DT), the host
commands at the control inputs (CE, EN1, and EN2) are ignored. The Q1 FET connected between IN and OUT
pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT to
OUT is ON. During this mode, the VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.
When VIN rises above VBAT + VIN(DT), PGOOD is low to indicate that the valid power status and the CE, EN1, and
EN2 inputs are read. The device enters standby mode whenever (EN1, EN2) = (1, 1) or if an input overvoltage
condition occurs. In standby mode, Q1 is OFF and Q2 is ON. During standby mode, the VOUT(SC2) circuitry is
active and monitors for overload conditions on OUT.
When the input voltage at IN is within the valid range: VIN > UVLO AND VIN > VBAT + VIN(DT) AND VIN < VOVP, and
the EN1 and EN2 pins indicate that the USB suspend mode is not enabled [(EN1, EN2) ≠ (HI, HI)], all internal
timers and other circuit blocks are activated. The device checks for short circuits at the ISET and ILIM pins. If no
short conditions exists, the device switches on the input FET Q1 with a 100-mA current limit to check for a short
circuit at OUT. If VOUT rises above VSC, the FET Q1 switches to the current-limit threshold set by EN1, EN2, and
RILIM and the device enters normal operation where the system is powered by the input source (Q1 is on), and
the device continuously monitors the status of CE, EN1, and EN2 as well as the input voltage conditions.
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Feature Description (continued)
Begin Startup
I IN (MAX) 100 mA
PGOOD = Hi -Z
CHG = Hi -Z
Q2 ON
V OUT short ?
V UVLO VOVP
Hi impedance
Table 4. CHG Status Indicator
CHARGE STATE
CHG OUTPUT
Charging
Low (first charge cycle)
Charging terminated
Hi impedance until power or CE is toggled
Recharging after termination
Hi impedance
Carging suspended by thermal loop
Low (first charge cycle)
Safety timers expired
Flashing at 2Hz
IC disabled or no valid input power
Hi impedance
7.4.1.5.1 Timer Fault
If the precharge timer expires before the battery voltage reaches VLOWV, the bq24232HA indicates a fault
condition. Additionally, if the battery current does not fall to ITERM before the fast-charge timer expires, a fault is
indicated. The CHG output flashes at approximately 2 Hz to indicate a fault condition.
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7.4.2 Explanation of Deglitch Times and Comparator Hysteresis
Figures not to scale
VOVP
VOVP - Vhys(OVP)
VIN
Typical Input Voltage
Operating Range
t < tDGL(OVP)
VBAT + VIN(DT)
VBAT + VIN(DT) - Vhys(INDT)
UVLO
UVLO - Vhys(UVLO)
PGOOD
tDGL(PGOOD)
tDGL(OVP)
tDGL(NO-IN)
tDGL(PGOOD)
Figure 16. Power Up, Power Down
tDGL1(LOWV)
VBAT
VLOWV
t < tDGL1(LOWV)
tDGL1(LOWV)
tDGL2(LOWV)
ICHG
Fast-Charge
Fast-Charge
IPRE-CHG
t < tDGL2(LOWV)
Pre-Charge
Pre-Charge
Figure 17. Pre- To Fast-Charge, Fast- To Precharge Transition – TDGL1(LOWV), TDGL2(LOWV)
VBAT
VRCH
Re-Charge
t < tDGL(RCH)
tDGL(RCH)
Figure 18. Recharge – TDGL(RCH)
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Turn
Q2 OFF
Force
Q2 ON
tREC(SC2)
Turn
Q2 OFF
tREC(SC2)
Force
Q2 ON
VBAT - VOUT
Recover
VO(SC2)
t < tDGL(SC2)
tDGL(SC2)
tDGL(SC2)
t < tDGL(SC2)
Figure 19. Out Short-Circuit – Supplement Mode
VCOLD
VCOLD - Vhys(COLD)
t < tDGL(TS)
VTS
Suspend
Charging
tDGL(TS)
Resume
Charging
VHOT - Vhys(HOT)
VHOT
Figure 20. Battery Pack Temperature Sensing – TS Pin. Battery Temperature Increasing
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The bq24232HA device power the system while simultaneously and independently charging the battery. The
input power source for charging the battery and running the system can be an AC adapter or a USB port. The
devices feature dynamic power-path management (DPPM), which shares the source current between the system
and battery charging and automatically reduces the charging current if the system load increases. When
charging from a USB port, the input dynamic power management (VIN – DPM) circuit reduces the input current
limit if the input voltage falls below a threshold, preventing the USB port from crashing. The power-path
architecture also permits the battery to supplement the system current requirements when the adapter cannot
deliver the peak system currents.
The bq24232HA can be configured as host controlled for selecting different input current limits based on the
input source connected; or, as a fully stand-alone device for applications that do not support multiple types of
input sources.
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8.2 Typical Application
See Figure 21 for the design example schematic.
VIN = VUVLO to VOVP , IFASTCHG = 200 mA, IIN(MAX) = 500 mA, 25-mA Termination Current, ISET mode (EN1 = 0,
EN2 = 1), Battery Temperature Charge Range 0°C to 50°C, 7.5-hour Fast Charge Safety Timer.
R5
1.5 kΩ
R6
1.5 kΩ
Adaptor
DC+
IN
CH G
PGOOD
SYSTEM
OUT
C1
1 μF
GND
C2
4.7μF
VSS
bq24232HA
EN 2
EN 1
TS
CE
BAT
PACK -
R1
3.57 kΩ
IS E T
IT E R M
TEMP
TMR
IL IM
PACK +
C3
4.7 μF
R2
3.06 kΩ
R4
56 .2 kΩ
R3
4 .32 kΩ
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Figure 21. Using the bq24232HA in a Stand-Alone Charger Application
8.2.1 Design Requirements
•
•
•
•
•
•
Supply voltage = 5 V
Fast-charge current of approximately 200 mA; ISET - pin 16
Input Current Limit =500 mA; ILIM - pin 12
Termination Current = 25 mA - pin 15 (bq24232HA)
Safety timer duration, Fast charge = 7.5 hours; TMR – pin 14
TS – Battery Temperature Sense = 10 kΩ NTC (103AT-2)
8.2.2 Detailed Design Procedure
8.2.2.1 Calculations
8.2.2.1.1 Program The Fast-Charge Current (ISET):
RISET = KISET / ICHG
KISET = 870 AΩ from the Electrical Characteristics table.
RISET = 870 AΩ/0.2 A = 4.35kΩ
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Typical Application (continued)
Select the closest standard value, which for this case is 4.32 kΩ. Connect this resistor between ISET (pin 16)
and VSS.
8.2.2.1.2 Program The Input Current Limit (ILIM)
RILIM = KILIM / II_MAX
KILIM = 1530 AΩ from the Electrical Characteristics table.
RISET = 1530 AΩ / 0.5 A = 3.06 kΩ
Select the closest standard value, which for this case is 3.06 kΩ. Connect this resistor between ILIM (pin 12) and
VSS.
8.2.2.1.3 Program The Termination Current Threshold (ITERM, bq24232HA)
RITERM = RISET × ITERM / KITERM
KITERM = 0.03 A from Electrical Characteristics table
RITERM = 4.32 kΩ × 0.025 A/0.03 A = 3.6 kΩ
Select the closest standard value, which for this case is 3.57 kΩ. Connect this resistor between ITERM (pin 15)
and VSS
8.2.2.1.4 Program 7.5-hour Fast-Charge Safety Timer (TMR)
RTMR = tMAXCHG / (10 × KTMR )
KTMR = 48 s/kΩ from the Electrical Characteristics table.
RTMR = (7.5 hr × 3600 s/hr) / (10 × 48 s/kΩ) = 56.25 kΩ
Select the closest standard value, which for this case is 56.2 kΩ. Connect this resistor between TMR (pin 2) and
VSS.
8.2.2.2 TS Function
Use a 10-kΩ NTC thermistor in the battery pack (103AT). To disable the temperature sense function, use a fixed
10-kΩ resistor between the TS (pin 1) and VSS. Pay close attention to the linearity of the chosen NTC so that it
provides the desired hot and cold turnoff thresholds.
8.2.2.3
CHG and PGOOD
LED Status: connect a 1.5-kΩ resistor in series with a LED between OUT and CHG and OUT and PGOOD.
Processor Monitoring Status: connect a pullup resistor (approximately 100 kΩ) between the processor’s power
rail and CHG and PGOOD.
8.2.2.4 Selecting IN, OUT, and BAT Pin Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin,
input, output, and battery pins. Using the values shown on the application diagram is recommended. After
evaluation of these voltage signals with real system operational conditions, the user can determine if capacitance
values can be adjusted toward the minimum recommended values (dc load application) or higher values for fast,
high-amplitude, pulsed load applications. Note, if the application is designed with high input voltage sources (bad
adapters or wrong adapters), the capacitor needs to be rated appropriately. Ceramic capacitors are tested to 2x
their rated values so a 16-V capacitor may be adequate for a 30-V transient (verify the tested rating with
capacitor manufacturer).
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Typical Application (continued)
8.2.3 Application Curves
VIN
5 V/div
VOUT
4.4 V
VCHG
5 V/div
1 V/div
VBAT
4V
2 V/div
VBAT
Battery Inserted
VPGOOD
Battery Detection Mode
Battery Supplying Load
Mandatory Precharge
200 mA/div
IBAT
Charging Initiated
IBAT
100 mA/div
Fastcharge
400 ms/div
4 ms/div
RLOAD = 25Ω
Figure 22. Adapter Plug-In With Battery Connected
VCHG
2 V/div
VBAT
Figure 23. Battery Detection -- Insertion
ILOAD
500 mA/div
IBAT
200 mA/div
200 mA/div
Battery Removed
Battery Detection Mode
IBAT
2 V/div
VOUT
4.4 V
400 ms/div
200 mV/div
400 ms/div
RLOAD = 25Ω To 9Ω
Figure 24. Battery Detection -- Removal
500 mA/div
ILOAD
IBAT
Figure 25. Entering and Exiting DPPM Mode
VCE
5 V/div
VCHG
Supplement Mode
5 V/div
500 mA/div
VBAT
3.6V
VOUT
4.4 V
500 mV/div
200 mV/div
IBAT
VBAT
3.9 V
Mandatory Precharge
100 mA/div
10 ms/div
2 ms/div
RLOAD = 25Ω To 4.5Ω
Figure 26. Entering and Exiting Battery Supplement Mode
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Figure 27. Charger ON/OFF Using CE
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Typical Application (continued)
10 V/div
VIN
IBAT
200 mA/div
VOUT
4.4 V
VBAT
4.2 V
200 mV/div
40 ms/div
RLOAD = 25Ω
Figure 28. OVP Fault VIN = 6 V to 15 V
9 Power Supply Recommendations
9.1 Requirements for OUT Output
In order to provide an output voltage on SYS, the bq24232HA requires a power supply between 4.35 V and 10 V
to fully charge a battery. The supply must have at least 100 mA current rating connected to IN; or, a single-cell
Li-Ion battery with voltage around 2.2 V connected to BAT. The source current rating needs to be at least 1.5 A
in order to provide maximum output current to SYS.
9.2 USB Sources and Standard AC Adapters
In order for charging to occur the source voltage measured at the IN terminals of the IC, factoring in cable/trace
losses from the source, must be greater than the VINDPM threshold (in USB mode), but less than the maximum
values shown above. The current rating of the source must be higher than the load requirements for OUT in the
application. For charging at a desired charge current of ICHRG, IIN > (ISYS+ ICHRG). The charger limits IIN to
the current limit setting of EN1/EN2.
9.3 Half-Wave Adapters
Some low-cost adapters implement a half rectifier topology, which causes the adapter output voltage to fall below
the battery voltage during part of the cycle. To enable operation with low-cost adapters under those conditions,
the bq24232HA keeps the charger on for at least 20 ms (typical) after the input power puts the part in sleep
mode. This feature enables use of external low-cost adapters using 50-Hz networks.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) must be placed as close as possible to the bq24232HA, with
short trace runs to both IN, OUT, and GND (thermal pad).
All low-current GND connections must be kept separate from the high-current charge or discharge paths from
the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
The high current charge paths into the IN pin and from the OUT pin must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces.
The bq24232HA is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed-circuit board (PCB); this thermal pad is
also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. Full
PCB design guidelines for this package are provided in the application report entitled: QFN/SON PCB
Attachment (SLUA271).
10.2 Layout Example
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10.3 Thermal Considerations
The bq24232HA is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed-circuit board (PCB). The power pad must be
directly connected to the Vss pin. Full PCB design guidelines for this package are provided in the application
report entitled: QFN/SON PCB Attachment (SLUA271). The most common measure of package thermal
performance is thermal impedance (RθJA ) measured (or modeled) from the chip junction to the air surrounding
the package surface (ambient). The mathematical expression for RθJA is:
RθJA = (TJ – T) / P
where
•
•
•
TJ = Chip junction temperature
T = Ambient temperature
P = Device power dissipation
(10)
Factors that can greatly influence the measurement and calculation of RθJA include:
1.
2.
3.
4.
5.
Whether the device is board mounted
Trace size, composition, thickness, and geometry
Orientation of the device (horizontal or vertical)
Volume of the ambient air surrounding the device under test and airflow
Whether other surfaces are in close proximity to the device being tested
Due to the charge profile of Li-ion batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. Typically, after fast charge begins, the pack voltage
increases to about 3.4 V within the first 2 minutes. The thermal time constant of the assembly typically takes a
few minutes to heat up so when doing maximum power dissipation calculations, 3.4 V is a good minimum voltage
to use. This is easy to verify, with the system and a fully discharged battery, by plotting temperature on the
bottom of the PCB under the IC (pad must have multiple vias), the charge current and the battery voltage as a
function of time. The fast-charge current starts to taper off if the part goes into thermal regulation.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged:
P = [V(IN) – V(OUT)] × I(OUT) + [V(OUT) – V(BAT)] × I(BAT)
(11)
The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is
recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage
and nominal ambient temperatures) and use the feature for nontypical situations such as hot environments or
higher than normal input source voltage. With that said, the IC still performs as described, if the thermal loop is
always active.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
Application report QFN/SON PCB Attachment, SLUA271
11.3 Trademarks
Bluetooth is a trademark of Bluetooth SIG, Inc..
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24232HARGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-5 to 125
4232HA
BQ24232HARGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-5 to 125
4232HA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of