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bq24311
SLUSBT8 – JULY 2014
bq24311 Overvoltage and Overcurrent Protection IC and
Li+ Charger Front-End Protection IC
1
1 Features
•
•
•
•
•
•
•
Provides Protection for Three Variables:
– Input Overvoltage, with Rapid Response in < 1
μs
– User-Programmable Overcurrent with Current
Limiting
– Battery Overvoltage
30 V Maximum Input Voltage
Supports up to 0.3 A Input Current
Robust Against False Triggering Due to Current
Transients
Thermal Shutdown
Enable Input
Status Indication – Fault Condition
3 Description
The bq24311 is a highly integrated circuit designed to
protect Li-ion batteries from charging circuit failures.
The IC continuously monitors the input voltage, input
current, and battery voltage. The input overvoltage
protection immediately removes power from the
charging circuit by turning off an internal switch. The
input protection limits the system current at the userprogrammable value, and if the overcurrent persists,
switches the pass element OFF after a blanking
period. Additionally, the IC also monitors its own die
temperature and switches off if it becomes too hot.
The IC can be controlled by a processor and also
provides status information about fault conditions to
the host.
Device Information
2 Applications
•
•
•
•
•
Mobile Phones and Smart Phones
PDAs
MP3 Players
Low-Power Handheld Devices
Bluetooth™ Headsets
PART NUMBER
PACKAGE
BODY SIZE (NOM)
bq24311
WSON (8)
2.00mm x 2.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Application Information
AC Adapter
VDC
1 IN
OUT 8
1 mF
1 mF
GND
bq24080
Charger IC
bq24311DSG
SYSTEM
VBAT 6
VSS
ILIM
FAULT 4
2
7
CE 5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Application Information.........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
9
9
Application and Implementation ........................ 12
9.1 Typical Application Circuit ....................................... 12
10 Power Supply Requirements ............................. 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Trademarks ........................................................... 18
12.2 Electrostatic Discharge Caution ............................ 18
12.3 Glossary ................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
Detailed Description .............................................. 8
5 Revision History
2
Date
Revision
Notes
June
*
Initial release.
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6 Pin Configuration and Functions
DSG PACKAGE
(TOP VIEW)
IN 1
8
OUT
VSS 2
7
ILIM
NC 3
6
VBAT
FAULT 4
5
CE
Pin Functions
PIN
NAME
IN
DSG
I/O
DESCRIPTION
Input power, connect to external DC supply. Connect external 1μF ceramic capacitor
(minimum) to VSS.
1
I
8
O
Output pin to the charging system. Connect external 1 μF ceramic capacitor (minimum) to
VSS.
VBAT
6
I
Battery voltage sense input. Connect to pack positive pin through a resistor.
ILIM
7
I/O
Input overcurrent threshold programming. Connect a resistor to VSS to set the overcurrent
threshold.
CE
5
I
Chip enable input. Active low. When CE = High, the input FET is off. Internally pulled down.
FAULT
4
O
Device status, open-drain output. FAULT = Low indicates that the input FET Q1 has been
turned on due to input overvoltage, input overcurrent, battery overvoltage, or thermal
shutdown.
VSS
2
–
Ground pin
NC
3
OUT
Thermal PAD
This pin may have internal circuits used for test purposes. Do not make any external
connections at these pins for normal operation.
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin
of the device. The thermal pad must be connected to the same potential as the VSS pin on
the printed circuit board. Do not use the thermal pad as the primary ground input for the
device. The VSS pin must be connected to ground at all times.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage
MIN
MAX
IN (with respect to VSS)
–0.3
30
OUT (with respect to VSS)
–0.3
12
ILIM, FAULT, CE, VBAT (with respect to VSS)
–0.3
7
UNIT
V
Input current
IN
0.5
Output current
OUT
0.5
A
Output sink current
FAULT
15
mA
150
°C
Junction temperature, TJ
(1)
–40
A
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.2 Handling Ratings
Tstg
Storage temperature range
VESD
(1)
(2)
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
Electrostatic discharge
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
MIN
MAX
UNIT
–65
150
°C
–2000
2000
V
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
Input voltage range
3
26
UNIT
V
IIN
Input current, IN pin
50
300
mA
IOUT
Output current, OUT pin
50
300
mA
RILIM
OCP Programming resistor
83.3
500
kΩ
TJ
Junction temperature
–40
125
°C
7.4 Thermal Information
THERMAL METRIC (1)
DSG
8 PINS
RθJA
Junction-to-ambient thermal resistance
86.3
RθJCtop
Junction-to-case (top) thermal resistance
116.9
RθJB
Junction-to-board thermal resistance
56.1
ψJT
Junction-to-top characterization parameter
8.1
ψJB
Junction-to-board characterization parameter
56.4
RθJCbot
Junction-to-case (bottom) thermal resistance
25.9
(1)
4
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over junction temperature range –40°C to 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IN
V(UVLO)
Undervoltage lock-out, input power
detected threshold
CE = Low, VIN increasing from 0 V to 3 V
2.6
2.7
2.8
V
V(UVLO_HYS)
Hysteresis on UVLO
CE = Low, VIN decreasing from 3 V to 0 V
200
260
300
mV
IDD
Operating current
CE = Low, No load on OUT pin,
VIN = 5 V, R(ILIM) = 200 kΩ
400
500
μA
I(STDBY)
Standby current
CE = High, VIN = 5 V
65
95
μA
CE = Low, VIN = 5 V, IOUT = 0.125 A
21
35
mV
5.71
5.85
6.00
V
20
60
110
mV
300
mA
INPUT TO OUTPUT CHARACTERISTICS
V(DO)
Drop-out voltage IN to OUT
INPUT OVERVOLTAGE PROTECTION
V(OVP)
Input overvoltage protection threshold
CE = Low, VIN increasing from 5V to 7.5 V
VHYS-OVP
Hysteresis on OVP
CE = Low, VIN decreasing from 7.5 V to 5 V
INPUT OVERCURRENT PROTECTION
Input overcurrent protection threshold
range
I(OCP)
Input overcurrent protection threshold
50
CE = Low, RILIM = 200 kΩ,
3 V ≤ VIN < VOVP
TJ = 0°C to 85°C
110
125
135
TJ = 0°C to 125°C
110
125
140
mA
BATTERY OVERVOLTAGE PROTECTION
V(BOVP)
Battery overvoltage protection
threshold
CE = Low, VIN > 4.4 V
4.30
4.35
4.4
V
V(HYS-BOVP)
Hysteresis on V(BOVP)
CE = Low, VIN > 4.4 V
200
275
320
mV
I(VBAT)
Input bias current on VBAT pin
VBAT = 4.4 V, TJ = 25°C
10
nA
150
°C
THERMAL PROTECTION
TJ(OFF)
Thermal shutdown temperature
TJ(OFF-HYS)
Thermal shutdown hysteresis
140
20
°C
LOGIC LEVELS ON CE
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
0.4
V
IIL
Low-level input current
VCE = 0 V
1
μA
IIH
High-level input current
VCE = 1.8 V
15
μA
V
LOGIC LEVELS ON FAULT
VOL
Output low voltage
I(SINK) = 5 mA
0.2
V
I(HI-Z)
Leakage current, FAULT pin HI-Z
V(FAULT) = 5 V
10
μA
7.6 Timing Requirements
MIN
tDGL(PGOOD)
Deglitch time, input power detected status
(1)
tPD(OVP)
Input OV propagation delay
tON(OVP)
Recovery time from input overvoltage
condition
tBLANK(OCP)
Blanking time, input overcurrent detected
tREC(OCP)
Recovery time from input overcurrent
condition
tDGL(BOVP)
Deglitch time, battery overvoltage detected
(1)
CE = Low. Time measured from VIN 0 V → 5 V 1
μs rise-time, to output turning ON
TYP
MAX
8
CE = Low
ms
1
CE = Low, Time measured from
VIN 7.5 V → 5 V, 1μs fall-time
CE = Low, VIN > 4.4 V. Time measured from
V(VBAT) rising from 4.1 V to 4.4 V to FAULT going
low.
UNIT
μs
8
ms
176
μs
64
ms
176
μs
Not tested in production. Specified by design.
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7.7 Typical Characteristics
Test conditions (unless otherwise noted) for typical operating performance: VIN = 5 V, CIN = 1 μF, COUT = 1 μF,
R(ILIM) = 200 kΩ, R(BAT) = 100 kΩ, TA = 25°C, V(PU) = 3.3 V (see Figure 11 for the Typical Application Circuit)
35
2.75
VIN Increasing
VDD at 125 mA (mV)
31
VUVLO, VHYS-UVLO - V
2.65
2.6
2.55
2.5
29
27
25
23
21
19
VIN Decreasing
2.45
2.4
-50
VIN = 5 V
VIN = 4 V
33
2.7
17
15
-30
-10
10
30
50
70
Temperature - °C
90
110
0
130
Figure 1. Undervoltage Lockout vs Free-Air Temperature
20
40
60
80
Temperature (qC)
100
120
140
D002
Figure 2. Dropout Voltage (In to Out) vs Free-Air
Temperature
350
5.88
300
5.86
5.84
IOCP (mA)
VOVP, VHYS-OVP - V
250
VIN Increasing
5.82
200
150
100
5.8
50
VIN Decreasing
5.78
-50
0
-30
-10
10
30
50
70
90
110
0
130
100
200
Temperature - °C
128
4.4
127
4.35
126
4.3
125
124
122
4.1
50
Temperature (qC)
100
150
6
4.05
-50
D002
Figure 5. Input Overcurrent Protection vs Free-Air
Temperature
600
D002
V(BOVP) (VVBAT Increasing)
4.2
4.15
0
500
4.25
123
121
-50
400
Figure 4. Input Overcurrent Protection vs ILIM Resistance
V(BOVP) (V)
IOCP (mA)
Figure 3. Overvoltage Threshold Protection vs Free-Air
Temperature
300
RILIM (k:)
Bat-OVP Recovery (VVBAT Decreasing)
-30
-10
10
30
50
70
o
Temperature ( C)
90
110
130
Figure 6. Battery Overvoltage Protection vs Free-Air
Temperature
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Typical Characteristics (continued)
2.5
900
I(DD (/CE = Low)
I(STDBY (/CE = High)
800
700
IDD, Standby (PA)
IVBAT (nA)
2
1.5
1
600
500
400
300
200
0.5
100
0
-50
-30
-10
10
30
50
70
o
Temperature ( C)
90
110
130
0
0
Figure 7. Leakage Current (VBAT Pin) vs Free-Air
Temperature
5
10
15
20
VIN (V)
25
30
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D002
Figure 8. Supply Current vs Input Voltage
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8 Detailed Description
8.1 Overview
The bq24311 is a highly integrated circuit designed to protect Li-ion batteries from charging circuit failures. The
IC continuously monitors the input voltage, input current, and battery voltage. The input overvoltage protection
immediately removes power from the charging circuit by turning off an internal switch. The input protection limits
the system current at the user-programmable value, and if the overcurrent persists, switches the pass element
OFF after a blanking period. Additionally, the IC also monitors its own die temperature and switches off if it
becomes too hot.
8.2 Functional Block Diagram
Q1
IN
Charge Pump,
Bandgap,
Bias Gen
OUT
VBG
ISNS
ILIM
ILIMREF
Current limiting
loop
OFF
OCP comparator
ILIMREF - Δ
t BLANK(OCP)
ISNS
FAULT
VIN
VBG
COUNTERS,
CONTROL,
AND STATUS
OVP
VIN
CE
VBG
t DGL(PGOOD)
UVLO
VBAT
THERMAL
SHUTDOW
VBG
t DGL(BOVP)
VSS
Figure 9. Simplified Block Diagram
8
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8.3 Feature Description
8.3.1 Power Down
The device remains in power down mode when the voltage at the IN pin is below the undervoltage threshold
VUVLO. The FET Q1 connected between IN and OUT pins is off, and the status output, FAULT, is set to Hi-Z.
8.3.2 Power-On Reset
The device resets when the voltage at the IN pin exceeds the UVLO threshold. All internal counters and other
circuit blocks are reset. The IC then waits for duration tDGL(PGOOD) for the input voltage to stabilize. If, after
tDGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The IC has a soft-start feature
to control the inrush current which minimizes the ringing at input during power up, as shown in Figure 15 (ringing
occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant
circuit). Because of the deglitch time at power-on, if the input voltage rises rapidly to beyond the OVP threshold,
the device will not switch on at all, instead it will go into protection mode and indicate a fault on the FAULT pin,
as shown in Figure 16.
8.4 Device Functional Modes
8.4.1 Operation
The device continuously monitors the input voltage, input current, and battery voltage as described in detail in the
following sections.
8.4.1.1 Input Overvoltage Protection
If the input voltage rises above VOVP, the internal FET Q1 is turned off, removing power from the circuit. As
shown in Figure 17, the response is rapid, with the FET turning off in less than a microsecond. The FAULT pin is
driven low. When the input voltage returns below VOVP – VHYS-OVP (but is still above VUVLO), the FET Q1 is turned
on again after a deglitch time of tON(OVP) to ensure that the input supply has stabilized. Figure 18 shows the
recovery from input OVP.
8.4.1.2 Input Overcurrent Protection
If the load current tries to exceed the IOCP threshold, the device limits the current for a blanking period,
tBLANK(OCP). If the load current returns to less than IOCP before tBLANK(OCP) times out, the device continues to
operate. However, if the overcurrent situation persists for tBLANK(OCP), the FET Q1 is turned off for a duration of
tREC(OCP), and the FAULT pin is driven low. The FET is then turned on again after tREC(OCP) and the current is
monitored all over again. Each time an OCP fault occurs, an internal counter is incremented. If 15 OCP faults
occur in one charge cycle, the FET is turned off permanently, as shown in Figure 19. The counter is cleared
either by removing and re-applying input power, or by disabling and re-enabling the device with the CE pin.
Figure 19 and Figure 20 show what happens in an overcurrent fault.
To prevent the input voltage from spiking up due to the inductance of the input cable, Q1 is turned off slowly,
resulting in a “soft-stop”, as shown in Figure 22.
8.4.1.3 Battery Overvoltage Protection
The battery overvoltage threshold V(BOVP) is internally set to 4.35V. If the battery voltage exceeds the V(BOVP)
threshold, the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on once the battery
voltage drops to V(BOVP) – VHYS-BOVP (see Figure 22 and Figure 23). Each time a battery overvoltage fault occurs,
an internal counter is incremented. If 15 such faults occur in one charge cycle, the FET is turned off permanently,
as shown in Figure 23. The counter is cleared either by removing and re-applying input power, or by disabling
and re-enabling the device with the CE pin. In the case of a battery overvoltage fault, Q1 is switched OFF
gradually, resulting in a soft-stop (see Figure 22).
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Device Functional Modes (continued)
8.4.1.4 Thermal Protection
If the junction temperature of the device exceeds TJ(OFF), the FET Q1 is turned off, and the FAULT pin is driven
low. The FET is turned back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS).
8.4.1.5 Enable Function
The IC has an enable pin which can be used to enable or disable the device. When the CE pin is driven high, the
internal FET is turned off. When the CE pin is low, the FET is turned on if other conditions are safe. The OCP
counter and the Bat-OVP counter are both reset when the device is disabled and re-enabled. The CE pin has an
internal pulldown resistor and can be left floating. Note that the FAULT pin functionality is also disabled when the
CE pin is high.
8.4.1.6 Fault Indication
The FAULT pin is an active-low open-drain output. It is in a high-impedance state when operating conditions are
safe, or when the device is disabled by setting CE high. With CE low, the FAULT pin goes low whenever any of
these events occurs:
• Input overvoltage
• Input overcurrent
• Battery overvoltage
• IC Overtemperature
10
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Device Functional Modes (continued)
Power Down
All IC functions OFF
FAULT = HiZ
Any State
if V(IN) < V (UVLO),
go to Power Down
No
V(IN) > V(UVLO) ?
Any State
if CE = Hi,
go to Reset
Yes
Reset
Timers reset
Counters reset
FAULT = HiZ
FET off
No
CE = Low ?
V(IN) < V(OVP) ?
No
Turn off FET
FAULT = Low
No
CE = Hi ?
Yes
Go to Reset
Yes
No
I < IOCP ?
No
Turn off FET
FAULT = Low
Incr OCP counter
Wait tREC(OCP)
count V(UVLO) – V(HYS-UVLO) + RDS(on) x I(ACCESSORY). Within this
voltage range, the reverse current capability is the same as the forward capability, 0.5 A. It should be noted that
there is no overcurrent protection in this direction.
IN
Q1
OUT
VOUT
Charge Pump,
Bandgap,
Bias Gen
Figure 14.
14
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Typical Application Circuit (continued)
9.1.3 Application Curves
2 V/div
5 V/div
V(IN)
2 V/div
2 V/div
V(OUT)
V(IN)
V(OUT)
FAULT
5 V/div
50 mA/div
I(OUT)
Time 2 ms/div
Time 2 ms/div
Figure 16. OVP at Power-On
V(IN)
2 V/div
V(IN)
V(IN)
V(OUT)
V(OUT)
V(OUT)
5 V/div 50 mA/div
2 V/div
2 V/div
2 V/div
Figure 15. Normal Power-On Showing Soft-Start
5 V/div
FAULT
FAULT
I(OUT)
FAULT
Time 2 ms/div
Time 20 ms/div
VIN = 5 V to 12 V
VIN = 15 V to 5 V
tr = 20 μs
2 V/div
V(IN)
2 V/div
2 V/div
2 V/div
V(IN)
tr = 400 μs
Figure 18. Recovery from OVP
Figure 17. OVP Response for Input Step
V(OUT)
V(OUT)
5 V/div 50 mA/div
5 V/div 50 mA/div
tr = 50 μs
VIN = 0 V to 10 V
ROUT = 50 Ω
I(OUT)
FAULT
I(OUT)
FAULT
Time 2 ms/div
Time 200 ms/div
OCP Counter Counts to 15 Before Switching OFF the Device
Figure 19. OCP, Powering Up into a Short Circuit on OUT
Pin
Figure 20. OCP, Zoom-in on the First Cycle of Figure 19
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2 V/div
I(OUT)
2 V/div
V(IN)
FAULT
5 V/div
2 V/div
Typical Application Circuit (continued)
5 V/div 50 mA/div
2 V/div
V(OUT)
V(BAT)
V(OUT)
FAULT
Time 100 ms/div
Time 2 ms/div
Figure 21. OCP, ROUT Switches from 130 Ω to 30 Ω, Shows
Current Limiting and Soft-Stop
Figure 22. BAT-OVP, V(VBAT) Steps from 4.3 V to 4.4 V,
Shows tDGL(BAT-OVP) and Soft-Stop
1 V/div
2 V/div
V(OUT)
V(BAT)
5 V/div
FAULT
Time 100 ms/div
Figure 23. BAT-OVP, V(VBAT) Steps from 3.9V to 4.4V,
Shows BAT-OVP Counter
10 Power Supply Requirements
In a typical application, the system is powered by a USB port or USB wall adapter.
The minimum input voltage, where the protector starts to pass current assuming VBAT is acceptable, could be
2.7 V. The maximum supported input voltage is up to 5.85 V; the overvoltage protection kicks in at 5.85 V and
the maximum input voltage rating is 30 V input rating.
16
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11 Layout
11.1 Layout Guidelines
•
•
•
This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages.
Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of
PCB traces satisfy the design rules for high voltages.
The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should
be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly
under the IC. This copper pad should be connected to the ground plane with an array of thermal vias.
CIN and COUT should be located close to the IC. Other components like RILIM and RBAT should also be located
close to the IC.
11.2 Layout Example
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12 Device and Documentation Support
12.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: bq24311
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
BQ24311DSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
BQ24311DSGT
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SHN
Samples
SHN
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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