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BQ24618RGER

BQ24618RGER

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VFQFN24_EP

  • 描述:

    Charger IC Lithium-Ion/Polymer 24-VQFN (4x4)

  • 数据手册
  • 价格&库存
BQ24618RGER 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 bq24618 Stand-Alone USB-Friendly Synchronous Switched-Mode Li-Ion or Li-Polymer Battery Charger With System Power Selector and Low Iq 1 Features 2 Applications • • • • • • • • • • • • • • • USB-Friendly 4.7-V to 28-V Input Operating Range Stand-Alone Charge Controller to Support 1 to 6 Li-Ion or Li-Polymer Battery Cells Up to 10-A Charge Current and Adapter Current 600-kHz NMOS-NMOS Synchronous Buck Converter High-Accuracy Voltage and Current Regulation – ±0.5% Charge Voltage Accuracy – ±3% Charge Current Accuracy – ±3% Adapter Current Accuracy Integration – Automatic System Power Selection From Adapter or Battery – Internal Loop Compensation – Internal Soft Start – Dynamic Power Management Safety Protection – Input Overvoltage Protection – Battery Thermistor Sense Hot/Cold Charge Suspend – Battery Detection – Reverse-Protection Input FET – Programmable Safety Timer – Charge Overcurrent Protection – Battery Short Protection – Battery Overvoltage Protection – Thermal Shutdown Status Outputs – Adapter Present – Charger Operation Status Charge Enable Pin 6-V Gate Drive for Synchronous Buck Converter 30-ns Driver Dead-Time and 99.5% Maximum Effective Duty Cycle Energy Star Low Quiescent Current Iq – < 15-µA Off-State Battery Discharge Current – < 1.5-mA Off-State Input Quiescent Current • • • Tablet PCs Smart Phones Portable Media Players, Navigation Devices, Notebooks and Ultra-Mobile PCs Personal Digital Assistants Handheld Terminals Industrial and Medical Equipment 3 Description The bq24618 device is highly integrated Li-ion or Lipolymer switched-mode battery-charge controller. The bq24618 offers a constant-frequency synchronous switching PWM controller with highaccuracy charge current and voltage regulation, charge preconditioning, termination, adapter current regulation and charge status monitoring. The bq24618 operates from either a USB port or AC adapter and supports charge currents up to 10 A. The device charges the battery in three phases: preconditioning, constant current, and constant voltage. Charge is terminated when the current reaches a minimum user-selectable level. A programmable charge timer provides a safety backup for charge termination. The bq24618 automatically restarts the charge cycle if the battery voltage falls below an internal threshold, and enters a lowquiescent current sleep mode when the input voltage falls below the battery voltage. Device Information(1) PART NUMBER bq24618 PACKAGE VQFN (24) BODY SIZE (NOM) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic ADAPTER SYSTEM ACP ACDRV ACN BATDRV HIDRV CE VREF ISET1 ISET2 ACSET VREF ADAPTER STAT1 STAT2 PG TS PH bq2461x 1 LODRV Battery pack SRP SRN VFB TTC 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 8 1 1 1 2 3 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 8 Typical Characteristics ............................................ 12 Detailed Description ............................................ 15 8.1 Overview ................................................................. 15 8.2 Functional Block Diagram ....................................... 16 8.3 Feature Description................................................. 17 8.4 Device Functional Modes........................................ 26 9 Application and Implementation ........................ 27 9.1 Application Information............................................ 27 9.2 Typical Application .................................................. 27 10 Power Supply Recommendations ..................... 33 11 Layout................................................................... 33 11.1 Layout Guidelines ................................................. 33 11.2 Layout Example .................................................... 34 12 Device and Documentation Support ................. 35 12.1 12.2 12.3 12.4 12.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 35 35 35 35 35 13 Mechanical, Packaging, and Orderable Information ........................................................... 35 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2011) to Revision B • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Changes from Original (October 2010) to Revision A Page • Changed descriptions for PH and BTST pins......................................................................................................................... 5 • Corrected Equation 8 ........................................................................................................................................................... 22 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 5 Device Comparison Table bq24600 bq24610 bq24616 bq24617 bq24618 bq24650 Li-Ion/Li-Polymer Li-Ion/Li-Polymer Li-Ion/Li-Polymer Li-Ion/Li-Polymer Li-Ion/Li-Polymer Li-Ion/Li-Polymer 1 to 6 1 to 6 1 to 6 1 to 5 1 to 6 1 to 6 2.1 to 26 2.1 to 26 2.1 to 26 2.1 to 22 2.1 to 26 2.1 to 26 5 to 28 5 to 28 5 to 28 5 to 24 4.7 to 28 5 to 28 Input overvoltage (V) 32 32 32 26 32 32 Maximum battery charging current (A) 10 10 10 10 10 10 1200 600 600 600 600 600 JEITA charging temperature profile No No Yes No No No DPM No IIN DPM IIN DPM IIN DPM IIN DPM VIN DPM Cell chemistry Number of cells in series (minimum to maximum, 4.2 V/cell) Charge voltage (minimum to maximum) (V) Input voltage range (minimum to maximum) (V) Switching frequency (kHz) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 3 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 6 Pin Configuration and Functions VCC BATDRV BTST HIDRV PH LODRV RGE Package 24-Pin VQFN Top View 24 23 22 21 20 19 ACN 1 18 REGN ACP 2 17 GND 16 ACSET ACDRV 3 TS 6 13 SRN 7 8 9 10 11 12 VFB 14 SRP ISET1 5 VREF STAT1 STAT2 15 ISET2 PG 4 TTC CE Pin Functions PIN NAME DESCRIPTION NO. ACDRV 3 AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to source of the ACFET is used to slow down the ON and OFF times. ACN 1 Adapter current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to GND for commonmode filtering. ACP 2 Adapter current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to GND for common-mode filtering. ACSET 16 Adapter current set input. The voltage on the ACSET pin programs the input current regulation set point during Dynamic Power Management (DPM). BATDRV 23 Battery-to-system MOSFET driver output. Gate drive for the battery-to-system load BAT PMOS power FET to isolate the system from the battery to prevent current flow from the system to the battery, while allowing a low-impedance path from battery to system. Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical to allow a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times. BTST 22 PWM high-side driver positive supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky diode from REGN to BTST. CE 4 Charge enable active HIGH logic input. HI enables charge. LO disables charge. It has an internal 1-MΩ pulldown resistor. GND 17 Low current sensitive analog and digital ground. On PCB layout, connect with thermal pad underneath the IC. HIDRV 21 PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace. ISET1 11 Fast charge current set input. The voltage on the ISET1 pin programs the fast charge current regulation set point. ISET2 15 Precharge and termination current set input. The voltage on the ISET2 pin programs the precharge current regulation set point and termination current trigger point. 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 Pin Functions (continued) PIN NAME DESCRIPTION NO. LODRV 19 PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace. PG 8 Open-drain power good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH when IC has an invalid VCC. PG can be used to drive an LED or communicate with a host processor. PH 20 PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor). REGN 18 PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the GND pin, close to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST. SRN 13 Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for commonmode filtering. SRP 14 Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to GND for common-mode filtering. STAT1 5 Open-drain charge status pin to indicate various charger operations (see Table 2). Thermal Pad — Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal-pad plane star-connecting to GND and to the ground plane for a high-current power converter. It also serves as a thermal pad to dissipate the heat. TS 6 Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND (see Figure 15). TTC 7 Safety Timer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed. STAT2 9 Open-drain charge status pin to indicate various charger operations (see Table 2). VFB 12 Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage. VREF 10 3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming of voltage and current regulation and for programming the TS threshold. VCC 24 IC power positive supply. Connect through a 10-Ω to the common-source (diode-OR) point: source of high-side Pchannel MOSFET and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from VCC to the GND pin close to the IC. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 5 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX –0.3 33 PH –2 36 VFB –0.3 16 REGN, LODRV, ACSET, TS, TTC –0.3 7 BTST, HIDRV with respect to GND –0.3 39 VREF, ISET1, ISET2 –0.3 3.6 –0.5 0.5 V Junction temperature –40 155 °C Tstg Storage temperature –55 155 °C VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG Voltage Maximum difference voltage TJ (1) (2) (3) ACP–ACN, SRP–SRN UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages. If the battery voltage in the application exceeds 16 V, a series resistor between the battery pack and VFB is required. The top resistor of the resistor-divider on VFB satisfies this requirement. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 7.3 Recommended Operating Conditions MIN VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG 28 30 VFB –0.3 14 REGN, LODRV, ACSET, TS, TTC –0.3 6.5 BTST, HIDRV with respect to GND –0.3 34 ISET1, ISET2 –0.3 3.3 VREF Maximum difference voltage MAX UNIT –2 PH Voltage NOM –0.3 V 3.3 ACP–ACN, SRP–SRN TJ Junction temperature –0.2 0.2 V 0 125 °C 7.4 Thermal Information bq24616 THERMAL METRIC (1) RGE [VQFN] UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 43 °C/W RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 54.3 °C/W 20 ψJT °C/W Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 19 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 7 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 7.5 Electrical Characteristics 4.7 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CONDITIONS VVCC_OP VCC input voltage operating range 4.7 28 V QUIESCENT CURRENTS Total battery discharge current (sum of currents into VCC, BTST, PH, ACP, ACN, SRP, SRN, VFB), VFB ≤ 2.1 V IBAT Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1 V Adapter supply current (current into VCC, ACP, ACN pin) IAC VVCC < VSRN, VVCC > VUVLO (SLEEP) 15 VVCC > VSRN, VVCC > VUVLO CE = LOW 5 VVCC > VSRN, VVCC > VVCCLOW CE = HIGH, charge done 5 VVCC > VSRN, VVCC > VUVLO CE = LOW (IC quiescent current) 1 1.5 VVCC > VSRN, VVCC > VVCCLOW , CE = HIGH, charge done 2 5 VVCC > VSRN, VVCC > VVCCLOW , CE = HIGH, charging, Qg_total = 20 nC µA mA 25 CHARGE VOLTAGE REGULATION VFB Feedback regulation voltage Charge voltage regulation accuracy IVFB Leakage current into VFB pin 2.1 V TJ = 0°C to 85°C –0.5% 0.5% TJ = –40°C to 125°C –0.7% 0.7% VFB = 2.1 V 100 100 nA CURRENT REGULATION – FAST CHARGE VISET1 ISET1 voltage range VIREG_CHG SRP-SRN current sense voltage range VIREG_CHG = VSRP – VSRN KISET1 Charge current set factor (amps of charge current per volt on ISET1 pin) RSENSE = 10 mΩ Charge-current regulation accuracy IISET1 Leakage current into ISET1 pin 2 5 V mV A/V VIREG_CHG = 40 mV –3% VIREG_CHG = 20 mV –4% 3% 4% VIREG_CHG = 5 mV –25% 25% VIREG_CHG = 1.5 mV (VSRN > 3.1 V) –40% 40% VISET1 = 2 V 100 nA 2 V CURRENT REGULATION – PRECHARGE VISET2 ISET2 voltage range KISET2 Precharge current set factor (amps of Precharge current per volt on ISET2 pin) Precharge-current regulation accuracy IISET2 Leakage current into ISET2 pin RSENSE = 10 mΩ 1 A/V VIREG_PRECH = 20 mV –4% 4% VIREG_PRECH = 5 mV –25% 25% VIREG_PRECH = 1.5 mV (VSRN < 3.1 V) –55% 55% VISET2 = 2 V 100 nA CHARGE TERMINATION Termination current set factor (amps of termination current per volt on ISET2 pin) KTERM Termination current accuracy RSENSE = 10 mΩ 1 A/V VITERM = 20 mV –4% 4% VITERM = 5 mV –25% 25% VITERM = 1.5 mV –45% 45% Deglitch time for termination (both edges) 100 tQUAL Termination qualification time VBAT > VRECH and ICHG < ITERM IQUAL Termination qualification current Discharge current once termination is detected ms 250 ms 2 mA INPUT CURRENT REGULATION VACSET ACSET voltage range VIREG_DPM ACP-ACN current sense voltage range VIREG_DPM = VACP – VACN KACSET Input current set factor (amps of input current per volt on ACSET pin) RSENSE = 10 mΩ 8 2 Submit Documentation Feedback 100 5 V mV A/V Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 Electrical Characteristics (continued) 4.7 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIREG_DPM = 40 mV Input current regulation accuracy leakage current into ACSET pin IACSET IISET1 Leakage current into ACSET pin TYP –3% MAX UNIT 3% VIREG_DPM = 20 mV –4% 4% VIREG_DPM = 5 mV –25% 25% VACSET = 2 V 100 nA INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO) VUVLO AC undervoltage rising threshold VUVLO_HYS AC undervoltage hysteresis, falling Measure on VCC 3.65 3.85 4 350 V mV VCC LOWV COMPARATOR Falling threshold, disable charge Measure on VCC 4.1 Rising threshold, resume charge V 4.35 4.5 V 100 150 mV 600 mV SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) VSLEEP _FALL VSLEEP_HYS SLEEP falling threshold VVCC – VSRN to enter SLEEP 40 SLEEP rising threshold μs SLEEP rising delay VCC falling below SRN, delay to turn off ACFET 1 SLEEP falling delay VCC rising above SRN, delay to turn on ACFET 30 μs SLEEP rising shutdown deglitch VCC falling below SRN, delay to enter SLEEP mode 100 ms SLEEP falling power up deglitch VCC rising above SRN, delay to exit SLEEP mode 30 ms ACN / SRN COMPARATOR VACN-SRN_FALL ACN to SRN falling threshold VACN-SRN_HYS ACN to SRN rising hysteresis VACN – VSRN to turn on BATFET 100 200 310 mV 100 mV ACN to SRN rising deglitch VACN – VSRN > VACN-SRN_RISE 2 ms ACN to SRN falling deglitch VACN – VSRN < VACN-SRN_FALL 50 μs BAT LOWV COMPARATOR VLOWV Precharge to fast charge transition (LOWV threshold) VLOWV_HYS LOWV hysteresis Measured on VFB pin, Rising 1.534 1.55 1.566 V 100 mV LOWV rising deglitch VFB falling below VLOWV 25 ms LOWV falling deglitch VFB rising above VLOWV + VLOWV_HYS 25 ms RECHARGE COMPARATOR VRECHG Recharge threshold (with respect to VREG) Measured on VFB pin, falling Recharge rising deglitch VFB decreasing below VRECHG 10 ms Recharge falling deglitch VFB decreasing above VRECHG 10 ms 35 50 65 mV BAT OVERVOLTAGE COMPARATOR VOV_RISE Overvoltage rising threshold As percentage of VFB 104% VOV_FALL Overvoltage falling threshold As percentage of VFB 102% INPUT OVERVOLTAGE COMPARATOR (ACOV) VACOV AC overvoltage rising threshold on VCC VACOV_HYS AC overvoltage falling hysteresis 31.04 32 32.96 V 1 V 1 ms AC overvoltage deglitch (both edge) Delay to changing the STAT pins AC overvoltage rising deglitch Delay to disable charge 1 ms AC overvoltage falling deglitch Delay to resume charge 20 ms Temperature increasing 145 °C 15 °C THERMAL SHUTDOWN COMPARATOR TSHUT Thermal shutdown rising temperature TSHUT_HYS Thermal shutdown hysteresis Thermal shutdown rising deglitch Temperature increasing 100 μs Thermal shutdown falling deglitch Temperature decreasing 10 ms THERMISTOR COMPARATOR VLTF Cold temperature rising threshold As percentage of VVREF 72.5% 73.5% 74.5% VLTF_HYS Rising hysteresis As percentage of VVREF 0.2% 0.4% 0.6% VHTF Hot temperature rising threshold As percentage of VVREF 36.2% 37% 37.8% Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 9 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com Electrical Characteristics (continued) 4.7 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER VTCO TEST CONDITIONS Cut-off temperature rising threshold As percentage of VVREF Deglitch time for temperature out-ofrange detection VTS > VLTF, or VTS < VTCO, or VTS < VHTF Deglitch time for temperature in-validrange detection VTS < VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF MIN TYP MAX 33.7% 34.4% 35.1% UNIT 400 ms 20 ms 45.5 mV CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE) Charge overcurrent falling threshold VOC Current rising, in nonsynchronous mode, measure on V(SRP-SRN), VSRP < 2 V Current rising, as percentage of V(IREG_CHG), in synchronous mode, VSRP > 2.2 V 160% Charge overcurrent threshold floor Minimum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2 V 50 Charge overcurrent threshold ceiling Maximum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2 V 180 mV CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE) VISYNSET Charge undercurrent falling threshold Switch from SYNCH to NON-SYNCH, VSRP > 2.2 V 1 5 9 mV BATTERY SHORTED COMPARATOR (BATSHORT) VBATSHT BAT short falling threshold, forced nonsynchronous mode VBATSHT_HYS BAT short rising hysteresis VBATSHT_DEG Deglitch on both edge VSRP falling 2 V 200 mV 1 μs 1.25 mV 1.25 mV 1 μs LOW CHARGE CURRENT COMPARATOR VLC Low charge current (average) falling threshold to force into nonsynchronous mode VLC_HYS Low charge current rising hysteresis VLC_DEG Deglitch on both edge Measure on V(SRP-SRN) VREF REGULATOR VVREF_REG VREF regulator voltage VVCC > VUVLO, (0- to 35-mA load) IVREF_LIM VREF current limit VVREF = 0 V, VVCC > VUVLO 3.267 35 3.3 3.333 V mA REGN REGULATOR VREGN_REG REGN regulator voltage VVCC > 10 V, CE = HIGH, (0- to 40-mA load) 5.7 IREGN_LIM REGN current limit VREGN = 0 V, VVCC > VUVLO, CE = HIGH 40 6.0 6.3 V mA TTC INPUT AND SAFETY TIMER TPRECHG Precharge safety timer range (1) Precharge time before fault occurs TCHARGE Fast-charge safety timer range, with ±10% accuracy (1) Tchg = CTTC × KTTC Fast-charge timer accuracy (1) 0.01 μF ≤ CTTC ≤ 0.11 μF KTTC 1440 2160 sec 1 10 Hr –10% 10% Timer multiplier TTC low threshold 1800 5.6 VTTC below this threshold disables the safety timer and termination min/nF 0.4 TTC oscillator high threshold 1.5 TTC oscillator low threshold V 1 TTC source/sink current 45 50 V V 55 μA BATTERY SWITCH (BATFET) DRIVER RDS_BAT_OFF BATFET turnoff resistance VACN > 5 V 150 Ω RDS_BAT_ON BATFET turnon resistance VACN > 5 V 20 kΩ VBATDRV_REG BATFET drive voltage VBATDRV_REG = VACN – VBATDRV when VACN > 5 V and BATFET is on 4.2 7 V VBATFET_ACN ACN voltage to keep BATFET on BATFET on 2.6 V AC SWITCH (ACFET) DRIVER RDS_AC_OFF ACFET turnoff resistance VVCC > 5 V 30 Ω RDS_AC_ON ACFET turnon resistance VVCC > 5 V 20 kΩ (1) 10 Verified by design. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 Electrical Characteristics (continued) 4.7 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER VACDRV_REG TEST CONDITIONS MIN VACDRV_REG = VVCC – VACDRV when VVCC > 5 V and ACFET is on ACFET drive voltage TYP 4.2 MAX 7 UNIT V AC / BAT MOSFET DRIVERS TIMING Driver dead time Dead time when switching between AC and BAT μs 10 BATTERY DETECTION tWAKE Wake time Maximum time charge is enabled IWAKE Wake current RSENSE = 10 mΩ tDISCHARGE Discharge time Maximum time discharge current is applied IDISCHARGE Discharge current IFAULT Fault current after a time-out fault VWAKE Wake threshold (with respect to VREG) Voltage on VFB to detect battery absent during wake Discharge threshold Voltage on VFB to detect battery absent during discharge VDISCH 500 50 125 ms 200 mA 1 s 8 mA 2 mA 50 mV 1.55 V PWM HIGH-SIDE DRIVER (HIDRV) RDS_HI_ON High-side driver (HSD) turnon resistance VBTST – VPH = 5.5 V 3.3 6 Ω RDS_HI_OFF High-side driver turnoff resistance VBTST – VPH = 5.5 V 1 1.3 Ω VBTST_REFRESH Bootstrap refresh comparator threshold voltage VBTST – VPH when low side refresh pulse is requested 4.0 4.2 V PWM LOW-SIDE DRIVER (LODRV) RDS_LO_ON Low-side driver (LSD) turnon resistance RDS_LO_OFF Low-side driver turnoff resistance 4.1 7 Ω 1 1.4 Ω PWM DRIVERS TIMING Driver dead time Dead time when switching between LSD and HSD, no load at LSD and HSD PWM ramp height As percentage of VCC 30 ns PWM OSCILLATOR VRAMP_HEIGHT 7% PWM switching frequency (1) 510 600 690 kHz INTERNAL SOFT START (8 steps to regulation current ICHG) Soft-start steps Soft-start step time 8 step 1.6 ms 1.5 s CHARGER SECTION POWER-UP SEQUENCING Charge enable delay after power up Delay from CE = 1 until charger is allowed to turn on LOGIC IO PIN CHARACTERISTICS (CE, STAT1, STAT2, PG) VIN_LO CE input-low threshold voltage VIN_HI CE input-high threshold voltage 0.8 V VBIAS_CE CE input bias current V = 3.3 V (CE has internal 1-MΩ pulldown resistor) VOUT_LO STAT1, STAT2, PG output low saturation voltage 6 μA Sink current = 5 mA 0.5 V IOUT_HI Leakage current V = 32 V 1.2 µA 2.1 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 11 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 7.6 Typical Characteristics Table 1. Table of Graphs FIGURE Figure 1 Charge Enable Figure 2 Current Soft Start (CE = 1) Figure 3 Charge Disable Figure 4 Continuous Conduction Mode Switching Waveforms Figure 5 Cycle-by-Cycle Synchronous to Nonsynchronous Figure 6 100% Duty and Refresh Pulse Figure 7 Transient System Load (DPM) Figure 8 Battery Insertion Figure 9 Battery-to-Ground Short Protection Figure 10 Battery-to-Ground Short Transition Figure 11 Efficiency vs Output Current Figure 12 10 V/div 10 V/div REF, REGN, and PG Power Up (CE = 1) PH 2 A/div IBAT REGN 5 V/div CE 5 V/div 2 V/div VREF 5 V/div /PG 2 V/div VCC LODRV t − Time = 200 ms/div t − Time = 4 ms/div Figure 2. Charge Enable 10 V/div 10 V/div Figure 1. REF, REGN, and PG Power Up (CE = 1) CE 5 V/div 2 A/div IBAT PH 5 V/div 2 A/div 5 V/div LODRV 5 V/div PH LODRV IL CE t − Time = 2 μs/div t − Time = 4 ms/div Figure 3. Current Soft Start (CE = 1) 12 Submit Documentation Feedback Figure 4. Charge Disable Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 5 V/div PH HIDRV LODRV 1 A/div 5 V/div PH 2 A/div 5 V/div 20 V/div 20 V/div www.ti.com IL LODRV IL t − Time = 100 ns/div t − Time = 100 ns/div 10 V/div 2 A/div IIN PH ISYS LODRV 2 A/div 0.5 A/div 5 V/div Figure 6. Cycle-by-Cycle Synchronous to Nonsynchronous 2 A/div Figure 5. Continuous Conduction Mode Switching Waveform IL IBAT t − Time = 200 μs/div t − Time = 400 ns/div Figure 7. 100% Duty and Refresh Pulse 10 V/div 10 V/div Figure 8. Transient System Load (DPM) PH 2 A/div LODRV IL IL 20 V/div 2 A/div 5 V/div 5 V/div PH VBAT VBAT t − Time = 200 ms/div Figure 9. Battery Insertion t − Time = 4 ms/div Figure 10. Battery-to-GND Short Protection Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 13 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 10 V/div 98 96 94 20 V/div 20 Vin, 4 cell Efficiency - % 92 LODRV 2 A/div 5 V/div PH 12 Vin, 2 cell 20 Vin, 3 cell 90 88 86 IL 12 Vin, 1 cell VBAT 84 82 t − Time = 10 μs/div 80 0 Figure 11. Battery-to-GND Short Transition 14 Submit Documentation Feedback 1 2 5 4 3 IBAT - Output Current - A 6 7 8 Figure 12. Efficiency vs Output Current Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 8 Detailed Description 8.1 Overview The bq2461x is a stand-alone, integrated Li-ion or Li-polymer battery charger that accommodates USB applications with a minimum input voltage of 4.7 V. It employs a switched-mode synchronous buck PWM controller with constant switching frequency. The device controls external switches to prevent battery discharge back to the input, to connect the adapter to the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. The bq2461x features Dynamic Power Management (DPM) which reduces battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying current to the system and the battery charger simultaneously. A highly accurate current sense amplifier enables precise measurement of input current from the AC adapter to monitor the overall system power. The input current limit can be configured through the ACSET pin of the device. The bq2461x has a battery detect scheme that allows it to automatically detect the presence and absence of a battery. When the battery is detected, charging begins in one of three phases (depending upon battery voltage): precharge, constant current (fast charge current regulation), and constant voltage (fast charge voltage regulation). The device will terminate charging when the termination current threshold has been reached and will begin a recharge cycle when the battery voltage has dropped below the recharge threshold (VRECHG). Precharge, constant current, and termination current can be configured through the ISET1 and ISET2 pins, allowing for flexibility in battery charging profile. During charging, the integrated fault monitors of the device, such as battery overvoltage protection, battery short detection (VBATSHT), thermal shutdown (internal TSHUT and TS pin), safety timer expiration (TTC pin), and input voltage protection (VACOV), ensure battery safety. The bq2461x has three status pins (STAT1, STAT2, and PG) to indicate the charging status and input voltage (AC adapter) status. These pins can be used to drive LEDs or communicate with a host processor. Regulation Voltage VRECH Regulation Current Precharge Current Regulation Phase Fastcharge Current Regulation Phase Fastcharge Voltage Regulation Phase Termination Charge Current Charge Voltage VLOWV IPRECH and ITERM Precharge Fastcharge Safety Time Time Figure 13. Typical Charging Profile Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 15 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 8.2 Functional Block Diagram bq24618 VREF VCC-6 V ACN ACN-6 V ACN-6 V LDO INTERNAL REFERENCE VREF 3.3 V LDO VCC - SRN+100 mV + VCC - VUVLO + ACN + VCC VCC SLEEP UVLO VCC VCC-6 V LDO SLEEP SRN+200 mV UVLO ACN-SRN - ACDRV SYSTEM POWER SELECTOR LOGIC VCC-6V ACN ACOV CE BATDRV 1M ACN-6V + 20X - V(ACP-ACN) + COMP ERROR AMPLIFIER ACN ACSET CE + 1V + - 2.1 V + + 5 mV - REGN 2 mA LODRV V(SRP-SRN) 160% X IBAT_REG - CHG_OCP GND TTC Safety Timer IC Tj + 145 degC - CHARGE FAULT STAT 1 STAT1 ISET1 IBAT_ REG ISET2 + LOWV 104% X VBAT_REG - - BAT + ISET2 6 V LDO REFRESH 4.2V FAULT + ISET1 CE + + - PH - PH VCC PWM CONTROL LOGIC BTST 20µA 8 mA SYNCH - IBAT_ REG SRN CHARGE OR DISCHARGE + SRP-SRN - V(SRP-SRN) HIDRV BAT_OVP 20 µA + 20X - LEVEL SHIFTER PWM - VFB SRP BTST + ACP TSHUT STATE MACHINE LOGIC BAT_OVP STAT 2 STAT2 PG PG VFB + - 1.55V TTC - 0.4 V + VCC + DISABLE TMR/TERM BATTERY DETECTION LOGIC ACOV TTC TTC VREF DISCHARGE VACOV +- LTF + VFB - TS SUSPEND RCHRG HTF + + - 2.05 V +- RCHRG V(SRP - SRN) + ISET2 - TERM TERM TCO + - TERMINATE CHARGE 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 8.3 Feature Description 8.3.1 Battery Voltage Regulation The bq24618 uses a high-accuracy voltage band gap and regulator for the high charging voltage accuracy. The charge voltage is programmed through a resistor divider from the battery to ground, with the midpoint tied to the VFB pin. The voltage at the VFB pin is regulated to 2.1 V, giving the following equation for the regulation voltage: é R2 ù V = 2.1 V ´ ê1+ ú, BAT ë R1 û where • • R2 is connected from VFB to the battery. R1 is connected from VFB to GND. (1) 8.3.2 Battery Current Regulation The ISET1 input sets the maximum fast-charging current. Battery charge current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 10-mΩ sense resistor, the maximum charging current is 10 A. The equation for charge current is: VISET1 ICHARGE = 20 ´ RSR (2) VISET1, the input voltage range of ISET1, is from 0 V to 2 V. The SRP and SRN pins are used to sense voltage across RSR using the default value of 10 mΩ. However, resistors of other values can also be used. A larger sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction loss. 8.3.3 Input Adapter Current Regulation The total input from an AC adapter or other DC source is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the systems are powered up or down. Without DPM, the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the battery charger reduces the charging current when the input current exceeds the input current limit set by ACSET. The current capability of the AC adaptor can be lowered, reducing system cost. Similar to sensing battery regulation current, adaptor current is sensed by resistor RAC connected between ACP and ACN. Its maximum value is set by ACSET using Equation 3: VACSET IDPM = 20 ´ RAC (3) VACSET, the input voltage range of ACSET, is from 0 V to 2 V. The ACP and ACN pins are used to sense voltage across RAC using the default value of 10 mΩ. However, resistors of other values can also be used. A larger sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction loss. 8.3.4 Precharge On power up, if the battery voltage is below the VLOWV threshold, the bq24618 applies the precharge current to the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins. The precharge current is determined by the voltage on the ISET2 pin, VISET2, according to Equation 4. VISET2 IPRECHARGE = 100 ´ R SR Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 (4) 17 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com Feature Description (continued) 8.3.5 Charge Termination, Recharge, and Safety Timer The bq24618 monitors the charging current during the voltage regulation phase. When VTTC is valid, termination is detected while the voltage on the VFB pin is higher than the VRECH threshold AND the charge current is less than the ITERM threshold, as calculated in Equation 5: VISET2 ITERM = 100 ´ RSR (5) The input voltage of ISET2 is from 0 V to 2 V. The minimum precharge and termination current is clamped to be around 125 mA with default 10-mΩ sensing resistor. As a safety backup, the bq24618 also provides a programmable charge timer. The charge time is programmed by the capacitor connected between the TTC pin and GND, and is given by Equation 6 tCHARGE = CTTC ´ K TTC where • • A • • • CTTC (range from 0.01 µF to 0.11 µF to give 1-h to 10-h safety time) is the capacitor connected from the TTC pin to GND. KTTC is the constant multiplier (5.6 min/nF). (6) new charge cycle is initiated and the safety timer is reset when any of the following conditions occurs: The battery voltage falls below the recharge threshold. A power-on-reset (POR) event occurs. CE is toggled. The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF, the bq24618 continues to allow termination but disable the safety timer. TTC taken low resets the safety timer. When ACOV, VCCLOWV, and SLEEP mode resume normal, the safety timer is reset. 8.3.6 Power Up The bq24618 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, the bq24618 enables the ACFET and disables BATFET. If all other conditions are met for charging, the bq24618 then attempts to charge the battery (see Enable and Disable Charging). If the SRN voltage is greater than VCC, indicating that the battery is the power source, the bq24618 enables the BATFET and enters a low quiescent current ( VRECH Yes Disable 125-mA Charge No 0.5-s timer expired No Yes Battery Present, Begin Charge Battery Absent Figure 16. Battery-Detection Flow Chart Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on at low charge current (125 mA). If the battery voltage rises above the recharge threshold within 500 ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before its respective threshold is hit, a battery is detected and a charge cycle is initiated. 24 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 Battery not detected VREG VRECH (VWAKE) Battery inserted VLOWV Battery detected (VDISH) tRECH_DEG tLOWV_DEG tWAKE Figure 17. Battery-Detect Timing Diagram Ensure that the total output capacitance at the battery node is not so large that the discharge current source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum output capacitance can be calculated as follows: CMAX = IDISCH ´ tDISCH é R ù 0.5 ´ ê1+ 2 ú ë R1 û where • • • • CMAX is the maximum output capacitance. IDISCH is the discharge current. tDISCH is the discharge time. R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. (10) The 0.5 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin. Example For a three-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 12.6 V for voltage regulation), IDISCH = 8 mA, tDISCH = 1 second, 8mA ´ 1sec CMAX = = 2.7 mF é 500k ù 0.5 ´ ê1+ ú ë 100k û (11) Based on these calculations, no more than 2.7 mF should be allowed on the battery node for proper operation of the battery detection circuit. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 25 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 8.4 Device Functional Modes Figure 18. Operational Flow Chart 26 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The bq24618 battery charger is ideal for high current charging (up to 10 A) and can charge battery packs consisting of single cells or multiple cells in series. The bq24610EVM evaluation module is a complete charge module for evaluating the bq2461x. The application curves were taken using the bq24610EVM. Refer to the EVM user's guide (SLUU396) for EVM information. 9.2 Typical Application Q1 (ACFET) SI7617DN R17 10Ω SYSTEM P ADAPTER- P R14 100 kW C16 2.2μF RAC 0.010 W Q2 (ACFET) SI7616DN C14 0.1 mF C15 0.1 µF C3 0.1 µF C2 0.1 µF ACN VCC BATDRV ACDRV R5 100 kW R7 100 kW R18 1 kΩ R6 10 kW R15 100 kW PH ISET2 BTST R8 22.1 kW REGN C6 0.1 µF C5 1 µF bq24618 VREF LODRV C4 1 µF Q4 SIS412DN L1 D1 BAT54 D2 R12 10 kW D3 C10 0.1 µF D4 VREF Pack Thermistor Sense 103AT R10 430 kW PACK+ PACK- C12 C13 10 µF* 10 µF* C11 0.1 µF R2 500 kΩ Cff 22 pF STAT1 SRP ADAPTER + VBAT 6.8 µH* Q5 SIS412DN GND R9 9.31 kW RSR 0.010 W CE R11 10 kW R13 10 kW P Q3 (BATFET) SI7617DN R19 1 kΩ HIDRV ISET1 ACSET R4 32.4 kW C7 1µF ACP VREF R3 100 kW C9 10 μF C8 10 µF N R20 2Ω N ADAPTER+ R1 100 kW SRN STAT2 PG VFB R16 100 W C1 0.1 μF TS TTC PwrPad CTTC 0.056 μF VIN = 19 V, 3-cell, Iadapter_limit = 4 A, Icharge = 3 A, Ipre-charge = Iterm = 0.3 A, 5-hour safety timer Figure 19. Typical System Schematic Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 27 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com Typical Application (continued) 9.2.1 Design Requirements For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters DESIGN PARAMETER AC adapter voltage (VIN) VALUE 19 V AC adapter current limit 4A Battery charge voltage (number of cells in series) Battery charge current (during constant current phase) Precharge and termination current 12.6 V (3 cells) 3A 0.3 A Safety timer 5 hours 9.2.2 Detailed Design Procedure 9.2.2.1 Inductor Selection The bq2461x has 600-kHz switching frequency to allow the use of small inductor and capacitor values. Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ³ ICHG + (1/2) IRIPPLE (12) The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and inductance (L): V ´ D ´ (1 - D) IRIPPLE = IN fS ´ L (13) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9 V to 12.6 V for a three-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives the maximum inductor ripple current. Another example is a four-cell battery, where the battery voltage range is from 12 V to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current. Usually inductor ripple is designed in the range of 20% to 40% of maximum charging current as a trade-off between inductor size and efficiency for a practical design. The bq24618 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charge current-sensing resistor to prevent negative inductor current. The typical UCP threshold is 5 mV falling edge, corresponding to 0.5 A falling edge for a 10-mΩ charge current-sensing resistor. 9.2.2.2 Input Capacitor The input capacitor should have enough ripple current rating to absorb the input switching ripple current. The worst-case RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst-case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation: ICIN = ICHG ´ D ´ (1 - D) (14) A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V rating or higher capacitor is preferred for 20-V input voltage. A 10-µF to 20-µF capacitor is suggested for typical 3-A to 4-A charging current. 9.2.2.3 Output Capacitor The output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given: 28 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 ICOUT = IRIPPLE 2 ´ 3 » 0.29 ´ IRIPPLE (15) The output capacitor voltage ripple can be calculated as follows: DVo = 1 8LCfs 2 æ V 2 ç VBAT - BAT ç VIN è ö ÷ ÷ ø (16) At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The bq24618 has an internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed from 12 kHz to 17 kHz. The preferred ceramic capacitor is 25V or higher rating, X7R or X5R for 4-cell applications. 9.2.2.4 Power MOSFET Selection Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6 V of gate drive voltage. MOSFETs of 30-V or higher voltage rating are preferred for 20-V input voltage and 40-V or higher rating MOSFETs are preferred for 20-V to 28-V input voltage. Figure-of-merit (FOM) is usually used for selecting proper the MOSFET, based on a trade-off between the conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of a MOSFET ONresistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product of the MOSFET ON-resistance, rDS(on), and the total gate charge, QG. FOM top = RDS(on) ´ QG D FOMbottom = RDS(on) ´ QG (17) The lower the FOM value, the lower the total power loss. Usually, lower rDS(on) has higher cost with the same package size. The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D = VOUT/VIN), charging current (ICHG), MOSFET ON-resistance rDS(on)), input voltage (VIN), switching frequency (fS), turnon time (ton) and turnoff time (toff): 1 Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ fS 2 (18) The first item represents the conduction loss. Usually MOSFET rDS(on) increases by 50% with a 100ºC junction temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are given by: Q Q ton = SW , t off = SW Ion Ioff where • • • Qsw is the switching charge. Ion is the turnon gate-drive current. Ioff is the turnoff gate-drive current. (19) If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS): 1 QSW = QGD + ´ QGS 2 (20) Total gate drive current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turnon gate resistance (Ron), and turnoff gate resistance (Roff) of the gate driver: VREG N - Vplt Vplt Ion = , Ioff = Ron Roff (21) The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode: Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 29 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on) (22) If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the switching cycle to prevent negative inductor current. As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum charging current in nonsynchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging current sensing resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum nonsynchronous mode charging current. MOSFET gate driver power loss contributes to the dominant losses on the controller IC when the buck converter is switching. Choosing a MOSFET with a small Qg_total reduces the IC power loss to avoid thermal shutdown. PICLoss_driver = VIN × Qg_total × fs where • Qg_total is the total gate charge for both upper and lower MOSFET at 6 V VREGN. (23) 9.2.2.5 Input Filter Design During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a secondorder system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin. The ACP/ACN pin must be placed after the input ACFET in order to avoid overvoltage stress on these pins during hot plug-in. There are several methods to damping or limiting the overvoltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the overvoltage level to an IC-safe level. However, these two solutions may not have low cost or small size. A cost-effective and small-size solution is shown in Figure 20. R1 and C1 comprise a damping RC network to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for reverse voltage protection for the VCC pin (it can be the body diode of the input ACFET). C2 is a VCC pin decoupling capacitor, and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping RC network to further protect the IC from high dv/dt and high-voltage spikes. The value of C2 should be less than the value of C1 so R1 can be dominant over the ESR orf C1 to get enough damping effect for hot plug-in. The R1 and R2 packages must be sized to handle the inrush current power loss according to the resistor manufacturer’s data sheet. The filter component values always must be verified with the real application, and minor adjustments may be needed to fit in the real application circuit. D1 Adapter connector R1 2W C1 2.2 mF (2010) R2 (1206) 4.7 -30W VCC pin C2 0.1-1 mF Figure 20. Input Filter 9.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines The bq24618 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant frequency, fo, is approximately 12 kHz to 17 kHz for the bq24618. The following table provides a summary of typical LC components for various charge currents: 30 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 Table 4. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current for bq24618 (600-kHz Switching Frequency) CHARGE CURRENT 2A 4A 6A 8A 10 A Output inductor LO 6.8 μH 6.8 μH 4.7 μH 3.3 μH 3.3 μH Output capacitor CO 20 μF 20 μF 30 μF 40 μF 40 μF Sense resistor 10 mΩ 10 mΩ 10 mΩ 10 mΩ 10 mΩ 9.2.2.7 Component List for Typical System Circuit of Figure 19 PART DESIGNATOR QTY DESCRIPTION Q1, Q2, Q3 2 P-channel MOSFET, –30 V, –35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN Q4, Q5 2 N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN D1 1 Diode, dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C D2, D3, D4 3 LED diode, green, 2.1 V, 20 mA, LTST-C190GKT RAC, RSR 2 Sense resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F L1 1 Inductor, 6.8 µH, 5.5 A, Vishay-Dale IHLP2525CZ C8, C9, C12, C13 4 Capacitor, ceramic, 10 µF, 35 V, 20%, X7R C4, C5 2 Capacitor, ceramic, 1 µF, 16 V, 10%, X7R C1, C3, C6, C11 4 Capacitor, ceramic, 0.1 µF, 16 V, 10%, X7R C2, C10 2 Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R C7 1 Capacitor, ceramic, 1 µF, 50 V, 10%, X7R C14, C15 (Optional) 2 Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R C16 1 Capacitor, ceramic, 2.2 µF, 35 V, 10%, X7R Cff 1 Capacitor, ceramic, 22 pF, 25 V, 10%, X7R CTTC 1 Capacitor, ceramic, 0.056 µF, 16 V, 5%, X7R R1, R3, R5, R7 4 Resistor, chip, 100 kΩ, 1/16 W, 0.5% R2 1 Resistor, chip, 500 kΩ, 1/16 W, 0.5% R4 1 Resistor, chip, 32.4 kΩ, 1/16 W, 0.5% R6 1 Resistor, chip, 10 kΩ, 1/16 W, 0.5% R8 1 Resistor, chip, 22.1 kΩ, 1/16 W, 0.5% R9 1 Resistor, chip, 9.31 kΩ, 1/16 W, 1% R10 1 Resistor, chip, 430 kΩ, 1/16 W, 1% R11, R12, R13, R18, R19 5 Resistor, chip, 10 kΩ, 1/16 W, 5% R14, R15 (optional) 2 Resistor, chip, 100 kΩ, 1/16 W, 5% R16 1 Resistor, chip, 100 Ω, 1/16 W, 5% R17 1 Resistor, chip, 10 Ω, 1/4 W, 5% R20 1 Resistor, chip, 2 Ω, 1 W, 5% Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 31 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 9.2.3 Application Curves VIN: 19 V VBAT: 12 V ICHG = 4 A VIN: 19 V Figure 21. Continuous Conduction Mode Switching Waveform 32 Submit Documentation Feedback VBAT: 12 V Figure 22. Battery Charging Soft Start Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 10 Power Supply Recommendations For proper operation of bq2461x, VCC must be from 5 V to 28 V (bq24610) or 24 V (bq24617). To begin charging, VCC must be higher than SRN by at least 500 mV (otherwise, the device will be in sleep mode). TI recommends an input voltage of at least 1.5 V to 2 V higher than the battery voltage, taking into consideration the DC losses in the high-side FET (Rdson), inductor (DCR), and input sense resistor (between ACP and ACN), the body diode drop of RBFET between VCC and input power supply, and battery sense resistor (between SRP and SRN). Power limit for the input supply must be greater than the max power required by either the system load or for battery charging (the greater of the two). 11 Layout 11.1 Layout Guidelines The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize the high-frequency current-path loop (see Figure 23) is important to prevent electrical and magnetic field radiation and high-frequency resonance problems. The following is a PCB layout priority list for proper layout. Layout of the PCB according to this specific order is essential. 1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections, and use the shortest-possible copper trace connection. These parts should be placed on the same layer of PCB, instead of on different layers using vias to make the connection. 2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching MOSFETs. 3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize loop area), and do not route the sense leads through a high-current path (see Figure 24 for the Kelvin connection for best current accuracy). Place decoupling capacitors on these traces next to the IC. 5. Place the output capacitor next to the sensing resistor output and ground. 6. The output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. Route the analog ground separately from the power ground and use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath the IC, use the copper pour for analog ground, but avoid the power pins to reduce inductive and capacitive noise coupling. Connect the analog ground to GND. Connect the analog ground and power ground together using the thermal pad as the single ground connection point. Alternatively, use a 0-Ω resistor to tie the analog ground to power ground (the thermal pad should tie to analog ground in this case). A star-connection under the thermal pad is highly recommended. 8. It is critical to solder the exposed thermal pad on the back side of the IC package to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other layers. 9. Place decoupling capacitors next to the IC pins, and make the trace connection as short as possible. 10. All via sizes and numbers must be adequate for a given current path. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 33 bq24618 SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 www.ti.com 11.2 Layout Example SW L1 V BAT R1 High Frequency VIN BAT Current C1 Path PGND C2 C3 Figure 23. High-Frequency Current Path Current Direction R SNS Current Sensing Direction To SRP - SRN pin or ACP - ACN pin Figure 24. Sensing Resistor PCB Layout See the EVM design (SLUU396) for recommended component placement with trace and via locations. For QFN information, see SCBA017 and SLUA271. 34 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 bq24618 www.ti.com SLUSA55B – OCTOBER 2010 – REVISED APRIL 2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following: • EVM user's guide, SLUU396 • EVM design, SLUU396 • QFN information, SCBA017 and SLUA271 12.3 Trademarks All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: bq24618 35 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ24618RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 QWG BQ24618RGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 QWG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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BQ24618RGER
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