bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
Low Cost, Host-Controlled Li-Ion and Li-Polymer Battery Charger With Low Iq
FEATURES
APPLICATIONS
• NMOS-NMOS Synchronous Buck Converter
with 300 kHz Frequency and >95% Efficiency
• 30-ns Minimum Driver Dead-time and 99.5%
Maximum Effective Duty Cycle
• High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy
• Integration
– Internal Loop Compensation
– Internal Soft-Start
• Safety
– Dynamic Power Management (DPM) with
Status Indicator
– Charger Overcurrent Protection
– Battery Overvoltage Protection
– Thermal Shutdown
• Supports Two, Three, or Four Li+ Cells
• 8 – 24 V AC/DC-Adapter Operating Range
• Analog Inputs with Ratiometric Programming
via Resistors or DAC/GPIO Host Control
– Charge Voltage (4-4.512 V/cell)
– Charge Current (up to 8 A, with 10-mΩ
Sense Resistor)
– Adapter Current Limit (DPM)
• Status and Monitoring Outputs
– AC/DC Adapter Present with Programmable
Voltage Threshold
– DPM Loop Active (DPMDET)
– Current Drawn from Input Source
• Charge Enable
• 24-pin, 4x4-mm QFN Package
• Energy Star Low Iq
– < 10 µA Off-state Discharge Current
– < 1.5 mA Off-state Input Quiescent Current
•
•
•
•
•
•
Notebook and Netbook Computers
Portable Data-Capture Terminals
Portable Printers
Medical Diagnostics Equipment
Battery Bay Chargers
Battery Back-Up Systems
DESCRIPTION
The bq24704 is a high-efficiency, synchronous
battery charger with integrated compensation offering
low component count for space-limited Li-Ion and
Li-Polymer battery charging applications. Charge
current and voltage programming allows high
regulation accuracies, and can be either hardwired
with resistors, or programmed by the system
power-management microcontroller using a DAC or
GPIOs.
The bq24704 charges two, three, or four series Li+
cells, supporting up to 8 A of charge current, and is
available in a 24-pin, 4x4-mm thin QFN package.
PVCC
1
CHGEN
2
PH
REGN
LODRV
PGND
24
HIDRV
PACKAGE AND PIN-OUT
BTST
23
22
21
20
19
bq24704
QFN - 24
TOP VIEW
18
DPMDET
17
CELLS
16
SRP
SRN
ACDET
14
BAT
ACSET
6
13
SRSET
7
8
9
10
11
12
IADAPT
15
5
ISYNSET
ACP
4
ACGOOD
3
VADJ
ACN
VREF
2
AGND
1
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24704 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying
the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables precise
measurement of input current from the AC adapter to monitor the overall system power.
ADAPTER +
ADAPTER–
SYSTEM
R10
2Ω
C1
2.2 µF
RAC
0.01 Ω
P
P
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
HOST
C2
0.1 µF
R1
D2
BAT54
C6
10 µF
C7
10 µF
C3
0.1 µF
ACN
432 kΩ
1%
PVCC
Q3(BATFET)
SI4435
Controlled by
HOST
C8
0.1 µF
ACP
ACDET
VREF
P
Q4
FDS6680A
HIDRV
AGND
N
R2
66.5 kΩ
1%
PH
R3
10 kΩ
C9
ACGOOD
D1
BAT54 0.1 µF
REGN
SRSET
C10
1 µF
bq24704
VREF
C4
1 µF
R4
10 kΩ
PACK+
LODRV
PGND
C11
10 µF
C12
10 µF
PACK–
C13
0.1 µF
N
ACSET
RSR
0.01 Ω
BTST
ACGOOD
GPIO
L1
8.2 µH
Q5
FDS6680A
C14
0.1 µF
SRP
DPMDET
SRN
HOST
CELLS
BAT
10 kΩ
C15
0.1 µF
CHGEN
R15
VADJ
DAC
ISYNSET
R6
20 kΩ
ADC
IADAPT
PowerPad
C5
100 pF
(1)
Pull-up rail could be either VREF or other system rail.
(2)
SRSET/ACSET could come from either DAC or resistor dividers.
(3)
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC
2
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
ADAPTER +
ADAPTER–
SYSTEM
R10
2Ω
C1
2.2 µF
RAC
0.01 Ω
P
P
Q1 (ACFET) Q2 (ACFET)
SI4435
SI4435
Controlled by
HOST
C2
0.1 µF
R1
C6
10 µF
D2
BAT54
C7
10 µF
C3
0.1 µF
ACN
432 kΩ
1%
PVCC
Q3(BATFET)
SI4435
Controlled by
HOST
C8
0.1 µF
ACP
ACDET
VREF
P
PH
R3
10 kΩ
C9
ACGOOD
R14
R11
100 kΩ
R13
100 kΩ
REGN
SRSET
C10
1 µF
42 kΩ
bq24704
RSR
0.01 Ω
PACK+
VREF
C4
1 µF
PGND
C11
10 µF
C12
10 µF
PACK–
C13
0.1 µF
LODRV
N
R12
47 kΩ
R4
10 kΩ
BAT54 0.1 µF
D1
ACSET
L1
8.2 µH
BTST
ACGOOD
VREF
Q4
FDS6680A
HIDRV
AGND
N
R2
66.5 kΩ
1%
Q5
FDS6680A
C14
0.1 µF
SRP
DPMDET
GPIO
SRN
CELLS
BAT
10 kΩ
C15
0.1 µF
CHGEN
R15
HOST
REGN
ISYNSET
VADJ
ADC
IADAPT
R6
20 kΩ
PowerPad
C5
100 pF
(1)
Pull-up rail could be either VREF or other system rail.
(2)
SRSET/ACSET could come from either DAC or resistor dividers.
(3)
VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A
Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor
ORDERING INFORMATION
Part Number
Package
bq24704
24-PIN 4 x 4 mm QFN
Ordering Number
(Tape and Reel)
Quantity
bq24704RGER
3000
bq24704RGET
250
PACKAGE THERMAL DATA
(1)
(2)
PACKAGE
θJA
TA=25°C POWER RATING
DERATING FACTOR ABOVE
TA= 25°C
QFN – RGE (1) (2)
45°C/W
2.33 W
0.023 W/°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
3
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
Table 1. TERMINAL FUNCTIONS – 24-PIN QFN
TERMINAL
DESCRIPTION
NAME
NO.
PVCC
1
IC power positive supply. Place a 0.1-µF ceramic capacitor from PVCC to PGND pin close to the IC.
CHGEN
2
Charge enable active-low logic input. LO enables charge. HI disables charge. Connect a 10-kΩ pull-up resistor from
CHGEN to a pull-up supply rail.
ACN
3
Adapter current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
ACN 2 differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND for
common-mode filtering.
ACP
4
Adapter current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.
ACDET
5
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from
adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V.
The IADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V.
ACSET
6
Adapter current set input. The voltage ratio of ACSET voltage versus VREF voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VREF
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin.
AGND
7
Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the
analog ground plane, and only connect to PGND through the PowerPad underneath the IC.
VREF
8
3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratiometric programming of voltage and current regulation.
VADJ
9
Charge voltage set input. The voltage ratio of VADJ voltage versus VREF voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VREF to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ. VADJ connected to REGN programs the default of 4.2 V per cell.
ACGOOD
10
Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed
threshold. Connect a 10-kΩ pullup resistor from ACGOOD pin to pullup supply rail.
ISYNSET
11
Synchronous mode current set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent
threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor
current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).
IADAPT
12
Adapter current sense amplifier output. IADAPT voltage is 16 times the differential voltage across ACP-ACN. Place a
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
SRSET
13
Charge current set input. The voltage ratio of SRSET voltage versus VREF voltage programs the charge current
regulation set-point. Program by connecting a resistor divider from VREF to SRSET to AGND; or by connecting the
output of an external DAC to SRSET pin.
BAT
14
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the
BAT pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to
filter high-frequency noise.
SRN
15
Charge current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND for common-mode
filtering.
SRP
16
Charge current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. A 0.1-µF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.
CELLS
17
2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
DPMDET
18
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input
current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a
different pullup-supply rail.
PGND
19
Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source
of low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to
AGND through the PowerPad underneath the IC.
LODRV
20
PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
REGN
21
PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
PH
22
PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power
MOSFET drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from
from PH to BTST.
HIDRV
23
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
24
PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a
small bootstrap Schottky diode from REGN to BTST.
BTST
4
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
Table 1. TERMINAL FUNCTIONS – 24-PIN QFN (continued)
TERMINAL
NAME
NO.
DESCRIPTION
Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder
PowerPad to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes . It also
serves as a thermal pad to dissipate the heat.
PowerPad™
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VALUE
PVCC, ACP, ACN, SRP, SRN, BAT
Voltage range
Maximum difference voltage
UNIT
–0.3 to 30
PH
–1 to 30
REGN, LODRV, VADJ, ACSET, SRSET, ACDET, ISYNSET, CHGEN,
CELLS, ACGOOD, DPMDET, IADAPT
–0.3 to 7
V
VREF
–0.3 to 3.6
BTST, HIDRV with respect to AGND and PGND
–0.3 to 36
ACP–ACN, SRP–SRN, AGND–PGND
–0.5 to 0.5
Junction temperature range
–40 to 155
Storage temperature range
–55 to 155
(1)
(2)
V
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
PH
Voltage range
–1
NOM
MAX
24
PVCC, ACP, ACN, SRP, SRN, BAT
0
24
REGN, LODRV, VADJ
0
6.5
VREF
0
3.3
ACSET, SRSET, ACDET, ISYNSET, CHGEN, CELLS, ACGOOD, DPMDET,
IADAPT
0
5.5
BTST, HIDRV with respect to AGND and PGND
0
30
0.3
AGND, PGND
–0.3
Maximum difference voltage: ACP–ACN, SRP–SRN
–0.3
0.3
Junction temperature range
–40
125
Storage temperature range
–55
150
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
UNIT
V
V
°C
5
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS
7 V ≤ VPVCC ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VPVCC_OP
PVCC Input voltage operating range
5
24
V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG
BAT voltage regulation range
VADJ_OP
VADJ voltage range
4V-4.512V per cell, times 2,3,4 cell
Charge voltage regulation accuracy
Charge voltage regulation set to default to
4.2 V per cell
8
18
V
0
REGN
V
8 V, 8.4 V, 9.024 V
–0.5%
0.5%
12 V, 12.6 V, 13.536 V
–0.5%
0.5%
16 V, 16.8 V, 18.048 V
–0.5%
0.5%
VADJ connected to REGN, 8.4 V, 12.6
V, 16.8 V
–0.5%
0.5%
0
100
CHARGE CURRENT REGULATION
VIREG_CHG
Charge current regulation differential
voltage range
VSRSET_OP
SRSET voltage range
Charge current regulation accuracy
VIREG_CHG = VSRP – VSRN
0
VREF
VIREG_CHG = 40–100 mV
–3%
3%
VIREG_CHG = 20 mV
–5%
5%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV ( VBAT ≥ 4V)
–33%
33%
0
125
0
VREF
VIREG_DPM = 40–125 mV
–3%
3%
VIREG_DPM = 20 mV
–5%
5%
VIREG_DPM = 5 mV
–25%
25%
VIREG_DPM = 1.5 mV
–33%
33%
3.267
mV
V
INPUT CURRENT REGULATION
VIREG_DPM
Adapter current regulation differential
voltage range
VACSET_OP
ACSET voltage range
Input current regulation accuracy
VIREG_DPM = VACP – VACN
mV
V
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VACDET > 0.6 V, 0-30 mA
IVREF_LIM
VREF current limit
VVREF = 0 V, VACDET > 0.6 V
35
3.3
3.333
V
75
mA
6.2
V
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VACDET > 0.6 V, 0-75 mA,
PVCC > 10 V
5.6
IREGN_LIM
REGN current limit
VREGN = 0 V, VACDET > 0.6 V
90
135
mA
0
24
V
0
2
V
5.9
ADAPTER CURRENT SENSE AMPLIFIER
VACP/N_OP
Input common mode range
VIADAPT
IADAPT output voltage range
Voltage on ACP/ACN
IIADAPT
IADAPT output current
AIADAPT
Current sense amplifier voltage gain
0
AIADAPT = VIADAPT / VACP-ACN
VACP-ACN = 40–125 mV
Adapter current sense accuracy at the
condition
VACP-ACN VPVCC-BAT_RISE
7
PVCC to BAT Falling Deglitch
VPVCC – VBAT < VPVCC-BAT_FALL
185
240
50
9
mV
mV
11
ms
µs
6
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
UVLO
AC Undervoltage rising threshold
Measure on PVCC
3.5
AC Undervoltage hysteresis, falling
4
4.5
260
V
mV
BAT OVERVOLTAGE COMPARATOR
Overvoltage rising threshold
VO
Overvoltage falling threshold
(2)
104%
As percentage of VBAT_REG
(2)
102%
CHARGE OVERCURRENT COMPARATOR
VOC
Charge overcurrent rising threshold
As percentage of IREG_CHG
145%
Minimum Current Limit (SRP-SRN)
50
mV
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis, falling
Temperature Increasing
155
°C
20
PWM HIGH SIDE DRIVER (HIDRV)
RDS(on)
VBTST_REFRESH
(2)
High side driver turn-on resistance
VBTST – VPH = 5.5 V, tested at 100 mA
3
6
High side driver turn-off resistance
VBTST – VPH = 5.5 V, tested at 100 mA
0.7
1.4
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low side refresh
pulse is requested
4
Ω
V
Specified by design.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
7
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
7 V ≤ VPVCC ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM LOW SIDE DRIVER (LODRV)
RDS(on)
Low side driver turn-on resistance
REGN = 6 V, tested at 100 mA
3
6
Low side driver turn-off resistance
REGN = 6 V, tested at 100 mA
0.6
1.2
Ω
PWM DRIVERS TIMING
Driver Dead Time — Dead time when
switching between LODRV and HIDRV. No
load at LODRV and HIDRV
30
ns
PWM OSCILLATOR
FSW
PWM switching frequency
VRAMP_HEIGHT
PWM ramp height
240
As percentage of PVCC
300
360
6.6
kHz
%PVCC
QUIESCENT CURRENT
IOFF_STATE
IAC
Total off-state battery current from SRP,
SRN, BAT, VCC, BTST, PH, etc.
Adapter quiescent current
VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 85°C
7
10
VBAT = 16.8 V, VACDET < 0.6 V,
VPVCC > 5 V, TJ = 125°C
7
11
VPVCC = 20 V, charge disabled
1
1.5
µA
mA
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps
Soft start step time
8
step
1.7
ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from when adapter is detected
to when the charger is allowed to turn
on
0.9
1.2
1.5
s
ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION)
ISYN Accuracy
V(SRP-SRN) = 5 mV
–20%
ISYNSET pin voltage
VISYNSET
20%
1
V
ISYNSET rising deglitch
20
µs
ISYNSET falling deglitch
640
µs
LOGIC IO PIN CHARACTERISTICS (CHGEN)
VIN(LO)
Input low threshold voltage
VIN(HI)
Input high threshold voltage
IBIAS
Input bias current
0.8
V
1
µA
2.1
VCHGEN = 0 to VREGN
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
VIN(LO)
Input low threshold voltage, 3 cells
CELLS voltage falling edge
VIN(MID)
Input mid threshold voltage, 2 cells
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
0.5
0.8
VIN(HI)
Input high threshold voltage, 4 cells
CELLS voltage rising
2.5
IBIAS_FLOAT
Input bias float current for 2-cell selection
V = 0 to VREGN
–1
1.8
V
1
µA
0.5
V
11
ms
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET)
VO(LO)
Output low saturation voltage
Sink Current = 5 mA
Delay, rising/falling
8
7
Submit Documentation Feedback
9
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
TYPICAL CHARACTERISTICS
Table of Graphs (1)
Y
X
Figure
VREF Load and Line Regulation
vs Load Current
Figure 3
REGN Load and Line Regulation
vs Load Current
Figure 4
BAT Voltage
vs VADJ/VREF Ratio
Figure 5
Charge Current
vs SRSET/VREF Ratio
Figure 6
Input Current
vs ACSET/VREF Ratio
Figure 7
BAT Voltage Regulation Accuracy
vs Charge Current
Figure 8
BAT Voltage Regulation Accuracy
Figure 9
Charge Current Regulation Accuracy
Figure 10
Input Current Regulation (DPM) Accuracy
Figure 11
VIADAPT Input Current Sense Amplifier Accuracy
Figure 12
Input Regulation Current (DPM), and Charge Current
vs System Current
Figure 13
Transient System Load (DPM) Response
Figure 14
Charge Current Regulation
vs BAT Voltage
Figure 15
Efficiency
vs Battery Charge Current
Figure 16
Battery Removal (from Constant Current Mode)
Figure 17
REF and REGN Startup
Figure 18
Charger on Adapter Removal
Figure 19
Charge Enable / Disable and Current Soft-Start
Figure 20
Nonsynchronous to Synchronous Transition
Figure 21
Synchronous to Nonsynchronous Transition
Figure 22
Near 100% Duty Cycle Bootstrap Recharge Pulse
Figure 23
Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation
Figure 24
Continuous Conduction Mode (CCM) Switching Waveforms
Figure 25
Discontinuous Conduction Mode (DCM) Switching Waveforms
Figure 26
DPMDET Response with Transient System Load
Figure 27
(1)
Test results based on Figure 2 application schematic. VIN = 20 V, VBAT = 3-cell Li-Ion, ICHG = 3 A, IADAPTER_LIMIT = 4 A, TA = 25°C,
unless otherwise specified.
VREF LOAD AND LINE REGULATION
vs
Load Current
REGN LOAD AND LINE REGULATION
vs
LOAD CURRENT
0
0.50
-0.50
Regulation Error - %
Regulation Error - %
0.40
0.30
PVCC = 10 V
0.20
0.10
0
-1
-1.50
PVCC = 10 V
-2
PVCC = 20 V
-0.10
-2.50
-0.20
-3
PVCC = 20 V
0
10
20
30
VREF - Load Current - mA
40
50
0
Figure 3.
10
20
30
40
50
60
REGN - Load Current - mA
70
80
Figure 4.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
9
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
BAT VOLTAGE
vs
VADJ/VREF RATIO
CHARGE CURRENT
vs
SRSET/VREF RATIO
10
18.2
VADJ = 0 -VREF,
4-Cell,
No Load
Voltage Regulation - V
17.8
SRSET Varied,
4-Cell,
Vbat = 16 V
9
Charge Current Regulation - A
18
17.6
17.4
17.2
17
16.8
16.6
16.4
8
7
6
5
4
3
2
1
16.2
0
16
0
0.1
0.2
VADJ/VREF Ratio
0.4
0.5
0.6
SRSET/VREF Ratio
Figure 5.
Figure 6.
INPUT CURRENT
vs
ACSET/VREF RATIO
BAT VOLTAGE REGULATION ACCURACY
vs
CHARGE CURRENT
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
1
0.1
0.2
0.3
0.7
0.8
0.9
1
0.2
13
12
Vreg = 16.8 V
11
ACSET Varied,
4-Cell,
Vbat = 16 V
Input Current Regulation - A
9
8
0.1
Regulation Error - %
10
7
6
5
0
-0.1
4
3
2
-0.2
0
1
2000
0
0
0.1
0.2
0.3
0.4
0.5
ACSET/VREF Ratio
0.6
0.7
0.8
0.9
BAT VOLTAGE REGULATION ACCURACY
CHARGE CURRENT REGULATION ACCURACY
2
4-Cell, VBAT = 16 V
1
VADJ = 0 -VREF
SRSET Varied
0
0.06
-1
0.04
Regulation Error - %
Regulation Error - %
8000
Figure 8.
0.10
4-Cell, no load
0.02
0
-0.02
-0.04
-0.06
-0.10
16.5
-2
-3
-4
-5
-6
-7
-8
-0.08
-9
-10
17
17.5
18
18.5
19
0
V(BAT) - Setpoint - V
Figure 9.
10
6000
1.0
Figure 7.
0.08
4000
Charge Current - mA
2
4
I(CHRG) - Setpoint - A
6
8
Figure 10.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
INPUT CURRENT REGULATION (DPM) ACCURACY
VIADAPT INPUT CURRENT SENSE AMPLIFIER ACCURACY
5
10
ACSET Varied
9
0
7
4-Cell, VBAT = 16 V
6
Percent Error
Regulation Error - %
8
5
4
3
2
VI = 20 V, CHG = EN
-5
VI = 20 V, CHG = DIS
-10
-15
VACP-ACN < 1.5 x IADAPTER x RAC
1
0
-20
-1
-2
-25
IADAPTER Amplifier Gain
0
1
2
3
4
Input Current Regulation Setpoint - A
5
0
6
1
2
3
4
5
6
I(ACPWR) - A
7
8
9
10
Figure 11.
Figure 12.
INPUT REGULATION CURRENT (DPM), AND CHARGE
CURRENT
vs
SYSTEM CURRENT
TRANSIENT SYSTEM LOAD (DPM) RESPONSE
5
4
2 A/div
VI = 20 V,
4-Cell,
Vbat = 16 V
Isys
2 A/div
3
System Current
2
IIN
Charge Current
2 A/div
Ichrg and Iin - A
Input Current
1
Ibat
0
0
1
2
System Current - A
3
4
Time = 200 μs/div
Figure 13.
Figure 14.
CHARGE CURRENT REGULATION
vs
BAT VOLTAGE
EFFICIENCY
vs
BATTERY CHARGE CURRENT
5
100
Efficiency - %
Charge Current - A
4
3
2
90
VI = 21 V
V(BAT) = 16.8 V
VI = 20 V
V(BAT) = 12.6 V
VI = 20 V
V(BAT) = 8.4 V
80
1
o
TA =20 C
Ichrg_set = 4 A
0
70
0
2
4
6
8
10
12
Battery Voltage - V
14
16
18
0
Figure 15.
2000
6000
4000
Battery Charge Current - mA
8000
Figure 16.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
11
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
VBAT
Ch2
2 V/div
VACDET
VREF
Ch3
5 V/div
Ch2
Ch3
5 A/div 20 V/div
VPH
Ch1
2 V/div
REF AND REGN STARTUP
Ch4
12.3 V
Ch4
1 V/div
BATTERY REMOVAL
IBAT
VREGN
t − Time = 2 ms/div
CHARGER ON ADAPTER REMOVAL
CHARGE ENABLE / DISABLE AND CURRENT
SOFT-START
VCHGEN
Ch4
1 V/div
VIN
Ch1
12.6 V
VPH
Ch3
2 A/div
IL
VBAT
Ch2
20 V/div
VBAT
Ch1
1.8 V
Figure 18.
Ch1
10 V/div
Figure 17.
Ch3
2 A/div
Ch1
Ch4
5 V/div 5 V/div
t − Time = 5 ms/div
IBAT
t − Time = 200 ms/div
t − Time = 4 ms/div
Figure 19.
Figure 20.
NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION
SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION
PH
Ch2
10 V/div
LDRV
Ch4
5 V/div
LDRV
IL
IL
Ch3
2 A/div
Ch3
2 A/div
Ch4
5 V/div
Ch2
10 V/div
PH
t − Time = 1 ms/div
12
t − Time = 1 ms/div
Figure 21.
Figure 22.
NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE
PULSE
BATTERY SHORTED CHARGER RESPONSE,
OVERCURRENT PROTECTION (OCP) AND CHARGE
CURRENT REGULATION
Figure 23.
Figure 24.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
Ch1
20 V/div
HIDRV
PH
Ch3
5 V/div
PH
Ch2
20 V/div
DISCONTINUOUS CONDUCTION MODE (DCM)
SWITCHING WAVEFORMS
LODRV
Ch4
2 A/div
Ch4
5 A/div
Ch3
5 V/div
Ch2
20 V/div
Ch1
20 V/div
CONTINUOUS CONDUCTION MODE (CCM) SWITCHING
WAVEFORMS
IL
t − Time = 400 ns/div
HIDRV
LODRV
IL
t − Time = 400 ns/div
Figure 25.
Figure 26.
Ch4
5 A/div
Ch3
5 A/div
Ch2
5 A/div
Ch1
2 V/div
DPMDET RESPONSE WITH TRANSIENT SYSTEM LOAD
DPMDET
IBAT
Isys
IIN
t - Time = 20 ms/div
Figure 27.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
13
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
FUNCTIONAL BLOCK DIAGRAM
–
0.6 V
+
ACGOOD
AC_VGOOD
–
2.4 V
Delay
+
ACDET
1.2 s Rising
10 μs Falling
3.3V
LDO
VREF
ENA_BIAS
PVCC
EAI
ACP
CHGEN
EAO
FBO
+
V(ACP-ACN)
16x
–
–
IIN_REG
PVCC
IIN_ER
COMP
ERROR
AMPLIFIER
+
ACN
BTST
CHGEN
–
BAT
–
1V
LEVEL
SHIFTER
3.5 mA
HIDRV
20 mA
V(SRP-SRN)
+
–
SRN
+
+
VBAT_REG
SRP
BAT_ER
–
20x
IBAT_REG
PH
ICH_ER
DC-DC
CONVERTER
PWM LOGIC
+
3.5 mA
SYNCH
20 mA
CHRG_ON
V(SRP-SRN)
PVCC
REGN
6V LDO
ENA_BIAS
+
SYNCH
BTST
–
–
REFRESH
CBTST
LODRV
+
ISYNSET
+
4V _
PH
ACSET
PGND
IC Tj
+
155°C
–
TSHUT
ACP
SRSET
VBATSET
IBATSET
IINSET
RATIO
PROGRAM
VADJ
ACN
VBAT_REG
104% X VBAT_REG
–
IBAT_REG
BAT
+
+
16x
–
V(IADAPT)
IADAPT
BAT_OVP
IIN_REG
VREF
CELLS
145% X IBAT_REG
–
V(SRP-SRN)
+
PVCC
–
BAT
–+
CHG_OCP
DPMDET
DPM_LOOP_ON
PVCC_BAT
+
185 mV
AGND
PGND
bq24704
14
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
DETAILED DESCRIPTION
BATTERY VOLTAGE REGULATION
The bq24704 uses a high-accuracy voltage regulator for charging voltage. The internal default battery voltage
setting VBATT= 4.2 V × cell count. The regulation voltage is ratio-metric with respect to VREF. The ratio of VADJ
and VREF provides extra 12.5% adjust range on VBATT regulation voltage. By limiting the adjust range to 12.5%
of the regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an
overall voltage accuracy as good as 0.5% is maintained, while using 1% mis-match resistors. Ratio-metric
conversion also allows compatibility with D/As or microcontrollers (µC). The battery voltage is programmed
through VADJ and VREF using Equation 1.
é
æ
öù
V
VBAT = cell count x êê 4V + ççç0.512 x VADJ ÷÷÷úú
çè
VREF ÷øúû
êë
(1)
VADJ is set between 0 and VREF. VBATT defaults to 4.2 V × cell count when VADJ is connected to REGN.
CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2,3, or 4 Li+ cells. When charging
other cell chemistries, use CELLS to select an output voltage range for the charger.
CELLS
CELL COUNT
Float
2
AGND
3
VREF
4
The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to
determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is
recommended to be as close to the BAT pin as possible to decouple high frequency noise.
BATTERY CURRENT REGULATION
The SRSET input sets the maximum charging current. Battery current is sensed by resistor RSR connected
between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010 Ω
sense resistor, the maximum charging current is 10 A. SRSET is ratio-metric with respect to VREF using
Equation 2:
V
0.10
ICHARGE = SRSET x
VREF
RSR
(2)
The input voltage range of SRSET is between 0 and VREF, up to 3.3 V.
The SRP and SRN pins are used to sense across RSR with default value of 10 mΩ. However, resistors of other
values can also be used. A larger the sense resistor, gives a larger sense voltage, and a higher regulation
accuracy, but at the expense of higher conduction loss.
INPUT ADAPTER CURRENT REGULATION
The total input from an AC adapter or other DC sources is a function of the system supply current and the battery
charging current. System current normally fluctuates as portions of the systems are powered up or down. Without
Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the
maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging
current when the input current exceeds the input current limit set by ACSET. The current capability of the AC
adapter can be lowered, which may reduce the system cost.
Similar to setting battery regulation current, adapter current is sensed by resistor RAC connected between ACP
and ACN. The maximum value is set by ACSET, which is a ratio-metric with respect to VREF, using Equation 3.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
15
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
IADAPTER =
VACSET 0.125
´
VREF
R AC
(3)
The input voltage range of ACSET is between 0 and VREF, up to 3.3 V.
The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values
can also be used. A larger the sense resistor, gives a larger sense voltage, and a higher regulation accuracy;
but, at the expense of higher conduction loss.
ADAPTER DETECT AND POWER UP
An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect
threshold should typically be programmed to a value greater than the maximum battery voltage, and lower than
the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense
the true adapter input voltage whether the ACFET is on or off.
If PVCC is below 4 V, the device is disabled.
If ACDET is below 0.6 V but PVCC is above 4 V, part of the bias is enabled, including a crude bandgap
reference. IADAPT is disabled and pulled down to GND. The total quiescent current is less than 10 µA.
Once ACDET rises above 0.6 V and PVCC is above 4 V, all the bias circuits are enabled. VREF goes to 3.3 V
and REGN output goes to 6 V. IADAPT becomes valid to proportionally reflect the adapter current.
When ACDET rises and passes 2.4 V, a valid AC adapter is present. Then the following occurs:
• ACGOOD becomes high through external pull-up resistor to the host digital voltage rail;
• Charger turns on if all the conditions are satisfied (see Enable and Disable Charging).
ENABLE AND DISABLE CHARGING
The following conditions must be valid before a charge is enabled:
• CHGEN is LOW;
• PVCC > UVLO;
• Adapter is detected;
• Adapter is higher than PVCC-BAT threshold;
• Adapter is not over voltage;
• 1.2 s delay is complete after adapter detected;
• REGNGOOD and VREFGOOD are valid;
• Thermal Shut (TSHUT) is not valid;
One of the following conditions will stop on-going charging:
• CHGEN is HIGH;
• PVCC < UVLO;
• Adapter is removed;
• Adapter is less than PVCC-BAT threshold;
• Adapter is over voltage;
• Adapter is over current;
• TSHUT IC temperature threshold is reached (155°C on rising-edge with 20°C hysteresis).
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure
there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of
stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each
step lasts around 1.7ms, for a typical rise time of 13.6ms. No external components are needed for this function.
16
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward control
scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal.
fo +
Where resonant frequency, fo, is given by:
• CO = C11 + C12
• LO = L1
1
2p ǸLoC o where (from Figure 1 schematic)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to
the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 200 mV in order to allow zero percent duty-cycle, when
the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order
to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while
ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin
voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the
low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor.
Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low
again due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the
audible noise region. The charge current sense resistor RSR should be placed with at least half or more of the
total output capacitance placed before the sense resistor contacting both sense resistor and the output inductor;
and the other half or remaining capacitance placed after the sense resistor. The output capacitance should be
divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best
performance; but the node in which the output inductor and sense resistor connect should have a minimum of
50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching noise and give
better current sense accuracy. The type III compensation provides phase boost near the cross-over frequency,
giving sufficient phase margin.
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value.
Otherwise, the charger operates in synchronous mode.
During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power
MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent
shoot-through currents. During the 30ns dead time where both FETs are off, the back-diode of the low-side
power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low,
and allows safely charging at high currents. During synchronous mode the inductor current is always flowing and
operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.
During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the
break-before-make dead-time, the low-side n-channel power MOSFET will turn-on for around 80ns, then the
low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power
MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap capacitor is
always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for
battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can
both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high and low-side
MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80 ns, the
low-side MOSFET is kept off to prevent negative inductor current from occurring. The inductor current is blocked
by the off low-side MOSFET, and the inductor current will become discontinuous. This mode is called
Discontinuous Conduction Mode (DCM).
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
17
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
During the DCM mode the loop response automatically changes and has a single pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at low currents the loop response is slower, as there is less sinking current available to
discharge the output voltage. At low currents during non-synchronous operation, there may be a small amount of
negative inductor current during the 80 ns recharge pulse. The charge should be low enough to be absorbed by
the input capacitance.
When BTST – PH < 4 V, the 80-ns recharge pulse occurs on LODRV, the high-side MOSFET does not turn on.
The low-side MOSFET does not turn on (only 80-ns recharge pulse).
ISYNSET CONTROL (SYN AND NON-SYN MODE SETTING)
The ISYNSET pin is used to program the charge current threshold at which the charger changes from
synchronous operation into non-synchronous operation. The low side driver turns on for only 80 ns to charge the
boost capacitor. This is important to prevent negative inductor current, which may cause a boost effect in which
the input voltage increases as power is transferred from the battery to the input capacitors. This boost effect can
lead to an overvoltage on the PVCC node, and potentially cause some damage to the system. This
programmable value allows setting the current threshold for any inductor current ripple, and avoiding negative
inductor current. The minimum synchronous threshold should be set from 1/2 of the inductor current ripple to the
full ripple current, where the inductor current ripple is given by:
IRIPPLE_MAX
£ ISYN £ IRIPPLE_MAX
2
and
V
1
1
(VIN - VBAT )´ BAT ´
VIN ´(1- D)´D´
fS
VIN fS
IRIPPLE =
=
L
L
(4)
where:
VIN = adapter voltage
VBAT = BAT voltage
fS
=
switching frequency
L = output inductor
D = duty-cycle
18
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
IRIPPLE_MAX happens when the duty-cycle, D is mostly near to 0.5 at given Vin, fs,and L.
The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between SRP-SRN, and
the threshold set by an external resistor RISYNSET, which can be calculated by:
250 V
W
RISYNSET =
ISYN x RSENSE
(5)
RSENSE
SRN
SRP
+
–
3.3 V
ISYN
20x
I = 1 V/RISYNSET
–
SYNCH
+
+
1V
UCP
–
5 kW
ISYNSET
RISYNSET
Figure 28. ISYNSET Comparator Block
HIGH ACCURACY IADAPT USING CURRENT SENSE AMPLIFIER (CSA)
An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the
host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input
sensed voltage of ACP – ACN by 16x through the IADAPT pin. The IADAPT output is a voltage source 16 times
the input differential voltage. Once PVCC is above 5 V and ACDET is above 0.6V, IADAPT no longer stays at
ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT to
AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.
A 100-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, after the 100-pF capacitor, if additional filtering is desired. Note that adding filtering also
adds additional response delay.
INPUT UNDERVOLTAGE LOCK OUT (UVLO)
The system must have a minimum 4 V PVCC voltage to allow proper operation. This PVCC voltage could come
from either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 4 V the bias
circuits REGN and VREF stay inactive, even with ACDET above 0.6 V.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
19
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
BATTERY OVERVOLTAGE PROTECTION
The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will
not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This
allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is
disconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging the
stored output-inductor energy into the output capacitors.
CHARGE OVERCURRENT PROTECTION
The charger has a secondary overcurrent protection. It monitors the charge current, and prevents the current
from exceeding 145% of regulated charge current. The high-side gate drive turns off when the overcurrent is
detected, and automatically resumes when the current falls below the overcurrent threshold.
THERMAL SHUTDOWN PROTECTION
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 155°C. The charger stays off
until the junction temperature falls below 135°C.
Status Outputs (ACGOOD, DPMDET)
Two status outputs are available, and they require external pull up resistors to pull the pins to system digital rail
for a high level.
ACGOOD open-drain output goes low if ACDET is above 2.4 V.
DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current (after a
10-ms delay).
20
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
Table 2. Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30V,-6A, SO-8, Vishay-Siliconix, Si4435
Q4, Q5
2
N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A
D1, D2
2
Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C
RAC, RSR
2
Sense Resistor, 10 mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 8.2µH, Vishay-Dale, IHLP5050CE-01
C6, C7, C11, C12
4
Capacitor, Ceramic, 10µF, 25V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M
C4, C10
2
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K
C2, C3, C8, C9, C13, C14, C15
7
Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU
C5
1
Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0805, Kemet, C0805C101K5RACTU
C1
1
Capacitor, Ceramic, 2.2µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E225K
R3, R4, R15
3
Resistor, Chip, 10 kΩ, 1/16W, 5%, 0402
R1
1
Resistor, Chip, 432 kΩ, 1/16W, 1%, 0402
R2
1
Resistor, Chip, 66.5 kΩ, 1/16W, 1%, 0402
R10
1
Resistor, Chip, 2 Ω, 1W, 1%, 1210
R6
1
Resistor, Chip, 20 kΩ, 1/16W, 1%, 0402
APPLICATION INFORMATION
Input Capacitance Calculation
During the adapter hot plug-in, the ACFET has not been turned on. The AC switch is off and the simplified
equivalent circuit of the input is shown in Figure 29.
IIN
VIN
Ri
Li
Charger
Vi
Rc
Ci
A.
Ri: Equivalent resistance of cable
B.
Li: Equivalent inductance of cable
C.
RC ESR of Ci
D.
Ci: Decoupling capacitor
Figure 29. Simplified Equivalent Circuit During Adapter Insertion
The voltage on the input capacitor(s) is given by:
R
t
t é R -R
ù
C
VIN (t) = IIN (t) x RC + VCi (t) = Vi - VIe 2Li ê i
sinwt + coswt ú
ê wL
ú
i
ë
û
R
t
t é R
ù
VCi (t) = Vi - VIe 2Li ê t sinwt + coswt ú
ê 2 wL
ú
i
ë
û
R t = Ri + RC
æ R t ÷ö2
I
- çç
w=
÷÷
LiCi ççè 2Li ÷ø
Rt
t
V
IIn (t) = i e 2Li sinwt
wL i
(6)
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
21
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
Damping Conditions:
R t = Ri + RC > 2
Li
Ci
(7)
Figure 30(a) demonstrates a highr Ci which helps dampen the voltage spike. Figure 30(b) demonstrates the
effect of the input stray inductance (Li) on the input voltage spike. The dashed curve in Figure 30(b) represents
the worst case for Ci = 40 µF. Figure 30(c) shows how the resistance helps to suppress the input voltage spike.
35
35
Ci = 20 mF
Ci = 40 mF
Ri = 0.15 W,
Ci = 40 mF
30
Input Capacitor Voltage - V
Input Capacitor Voltage - V
Li = 5 mH
Ri = 0.21 W,
Li = 9.3 mH
30
25
20
15
10
5
Li = 12 mH
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
Time - 100 ms/div
(a) Vc with various Ci values
4
4.5
0
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time - 100 ms/div
(b) Vc with various Li values
35
Li = 9.3 mH,
Ci = 40 mF
Ri = 0.15 W
Input Capacitor Voltage - V
30
Ri = 0.50 W
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
Time - 100 ms/div
3.5
4
4.5
5
(c) Vc with various Ri values
Figure 30. Parametric Study Of The Input Voltage
As shown in Figure 30, minimizing the input stray inductance, increasing the input capacitance, and adding
resistance (including using higher ESR capacitors) helps supress the input voltage spike. However, a user often
cannot control input srtay inductance, and increasing capacitance can increase costs. therefore, the most
efficient and cost-effective approach is to add an external resistor.
Figure 31 depicts the recommended input filter design. The measured input voltage and current waveforms are
shown in Figure 32. The input voltage spike has been well damped by adding a 2 Ω resistor, while keeping the
capacitance low.
22
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
bq24704
www.ti.com........................................................................................................................................................................................................ SLUS838 – MAY 2009
VIN
2W
(0.5 W, 1210 anti-surge)
2.2 mF
(25 V, 1210)
VPVCC
Rext
C1
C2
0.1 mF
(50 V, 0805, close to PVCC)
Figure 31. Recommended Input Filter Design
Figure 32. Adapter DC Side Hot Plug-In Test Waveforms
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
23
bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
PCB Layout Design Guideline
1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the
power ground are connected only at the power pad.
3. The AC current-sense resistor must be connected to ACP (pin 4) and ACN (pin 3) with a Kelvin contact. The
area of this loop must be minimized. An additional 0.1 µF decoupling capacitor for ACN is required to further
reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as possible.
4. The charge-current sense resistor must be connected to SRP (pin 16), SRN (pin 15) with a Kelvin contact.
The area of this loop must be minimized. An additional 0.1µF decoupling capacitor for SRN is required to
further reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as
possible.
5. Decoupling capacitors for PVCC (pin 1), VREF (pin 8), REGN (pin 21) should be placed underneath the IC
(on the bottom layer) with the interconnections to the IC as short as possible.
6. Decoupling capacitors for BAT (pin 14), IADAPT (pin 12) must be placed close to the corresponding IC pins
with the interconnections to the IC as short as possible.
7. Decoupling capacitor CX for the charger input must be placed close to the Q4 drain and Q5 source.
Figure 33 shows the recommended component placement with trace and via locations. For the QFN information,
see the SCBA017 and SLUA271 documents.
(a) Top Layer
(b) Bottom Layer
Figure 33. Layout Example
24
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24704
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24704RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQ
24704
BQ24704RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQ
24704
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
