BQ24740RHDT

bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 Host-Controlled Multi-Chemistry Battery Charger With Low Input Power Detect FEATURES APPLICATIONS • NMOS-NMOS Synchronous Buck Converter with 300 kHz Frequency and >95% Efficiency • 30-ns Minimum Driver Dead-time and 99.5% Maximum Effective Duty Cycle • High-Accuracy Voltage and Current Regulation – ±0.5% Charge Voltage Accuracy – ±3% Charge Current Accuracy – ±3% Adapter Current Accuracy – ±2% Input Current Sense Amp Accuracy • Integration – Internal Loop Compensation – Internal Soft Start • Safety – Input Overvoltage Protection (OVP) – Dynamic Power Management (DPM) with Status Indicator • Supports Two, Three, or Four Li+ Cells • 5 – 24 V AC/DC-Adapter Operating Range • Analog Inputs with Ratiometric Programming via Resistors or DAC/GPIO Host Control – Charge Voltage (4-4.512 V/Cell) – Charge Current (up to 10 A, with 10-mΩ Sense Resistor) – Adapter Current Limit (DPM) • Status and Monitoring Outputs – AC/DC Adapter Present with Programmable Voltage Threshold – Low Input-Power Detect with Adjustable Threshold and Hysteresis – DPM Loop Active – Current Drawn from Input Source • Battery Discharge Current Sense with No Adapter, or Selectable Low-Iq mode • Supports Any Battery Chemistry: Li+, NiCd, NiMH, Lead Acid, etc. • Charge Enable • 10-µA Off-State Current • 28-pin, 5x5-mm QFN package • • • • • • Notebook and Ultra-Mobile Computers Portable Data-Capture Terminals Portable Printers Medical Diagnostics Equipment Battery Bay Chargers Battery Back-up Systems DESCRIPTION The bq24740 is a high-efficiency, synchronous battery charger with integrated compensation, offering low component count for space-constrained multi-chemistry battery charging applications. Ratiometric charge current and voltage programming allows high regulation accuracies, and can be either hardwired with resistors or programmed by the system power-management microcontroller using a DAC or GPIOs. PGND REGN LODRV PH HIDRV PVCC BTST The bq24740 charges two, three, or four series Li+ cells, supporting up to 10 A of charge current, and is available in a 28-pin, 5x5-mm thin QFN package. 28 27 26 25 24 23 22 CHGEN 1 ACN 2 ACP 3 bq24740 DPMDET 20 CELLS 19 SRP 4 28 LD QFN 18 SRN ACDET 5 TOP VIEW 17 BAT ACSET 6 16 SRSET LPREF 7 15 IADAPT ISYNSET 10 11 12 13 14 EXTPWR 9 VADJ 8 VDAC LPMD VREF 21 AGND 2 IADSLP 1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2009, Texas Instruments Incorporated bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The bq24740 features Dynamic Power Management (DPM) and input power limiting. These features reduce battery charge current when the input power limit is reached to avoid overloading the ac adapter when supplying the load and the battery charger simultaneously. A current-sense amplifier enables precise measurement of input current from the ac adapter to monitor the overall system power. If the adapter current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its power performance according to what is available from the adapter. TYPICAL APPLICATION SYSTEM ADAPTER+ ADAPTER- R10 2Ω C1 2.2 µF P Q1 (ACFET) SI4435 RAC 0.010 Ω P Q2 (ACFET ) SI4435 Controlled by HOST R1 432 kΩ 1% C6 10 µF C7 10 µF D2 BAT54 C3 C2 0.1 µF 0.1 µF ACN PVCC Q3(BATFET ) SI4435 Controlled by HOST C8 0.1 µF ACP ACDET VREF R3 10k Ω bq24740 EXTPWR PH L1 C9 BTST EXTPWR D1 PACK+ ACSET R5 10k Ω C13 0.1 µF LODRV VREF R4 10k Ω C4 1 µF PGND C12 10 µF C11 10 µF C10 1 µF N DAC RSR 0.010 Ω 8.2 µH BAT 54 0.1 µF REGN SRSET P Q4 FDS6680A HIDRV AGND N R2 66.5 kΩ 1% Q5 FDS6680 A PACK- C14 0.1 µF IADSLP SRP HOST DPMDET SRN LPMD BAT VREF CELLS R7 200 kΩ CHGEN LPREF VDAC ISYNSET DAC R6 24 kΩ VADJ ADC R8 24.9 kΩ PowerPad IADAPT C5 100 pF C15 0.1 µF R9 1.8 MΩ ( 1 ) Pull - up rail could be either VREF or other system rail . ( 2 ) SRSET /ACSET could come from either DAC or resistor dividers . VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC 2 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ADAPTER+ ADAPTER- SYSTEM R 10 2Ω C1 2.2 µ F P Q 1 ( ACFET ) SI 4435 R AC 0 .010 Ω P Q 2 (ACFET) SI4435 Controlled by HOST C7 10 µ F C3 C2 0.1 µ F R1 432 k Ω 1% C6 10 µ F D2 BAT54 0.1 µ F ACN PVCC C8 0.1 µ F ACP Q 3 (BATFET ) SI 4435 Controlled by HOST ACDET FDS 6680 A PH R3 10 k Ω bq24740 EXTPWR D1 R 13 100 kΩ SRSET R 11 100 kΩ BAT 54 PACK+ 8.2 µH C 11 10 µF 0.1 µ F REGN R 14 C 10 1 µF 43 k Ω C4 1 µF N R5 10 kΩ PACK- C 14 0 .1 µF LODRV VREF R4 10 k Ω C 12 10 µF C 13 0 .1 µF ACSET R 12 66.5 k Ω R SR 0 .010 Ω L1 C9 BTST EXTPWR VREF P Q4 HIDRV AGND N VREF R2 66 .5 k Ω 1% PGND Q5 FDS 6680 A IADSLP SRP DPMDET SRN GPIO LPMD BAT VREF CELLS C 15 R7 200 k Ω CHGEN 0.1 µF LPREF HOST ADC VREF VDAC REGN VADJ R8 24.9 k Ω ISYNSET R6 24 k Ω PowerPad IADAPT C5 100 pF R9 1 .8 M Ω ( 1 ) Pull- up rail could be either VREF or other system rail. ( 2 ) SRSET / ACSET could come from either DAC or resistor dividers. A. VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 3 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com ADAPTER+ SYSTEM R10 2Ω ADAPTER- C1 2.2 µF P Q1 (ACFET) SI4435 R AC 0 .010 Ω P Q 2 (ACFET ) SI 4435 Controlled by HOST R1 432 kΩ 1% C6 10 µF D2 BAT54C C7 10 µF C3 C2 0.1 µF ACN 0.1 µF PVCC C8 0.1 µF ACP Q3 (BATFET) SI4435 Controlled by HOST ACDET VREF R3 10 kΩ PH bq 24740 /EXTPWR C9 L1 PACK+ D1 BAT 54 8.2 µH C 11 10 µF 0.1 µF REGN SRSET C10 1 µF ACSET C4 1 µF PGND IADSLP HOST C 12 10 µF PACK- C 14 0 .1 µF N R5 10 k Ω C 13 0 .1 µF LODRV VREF R4 10 k Ω R SR 0 .010 Ω BTST EXTPWR DAC P Q4 FDS 6680 A HIDRV AGND N R2 66.5 kΩ 1% Q5 FDS6680A SRP DPMDET SRN LPMD BAT VREF CELLS R7 200 kΩ CHGEN C 15 0 .1 µF LPREF VDAC R8 24.9 kΩ ISYNSET DAC R6 24 kΩ VADJ ADC PowerPad IADAPT C5 100 pF R9 1.8 MΩ ( 1 ) Pull- up rail could be either VREF or other system rail . ( 2 ) SRSET / ACSET could come from either DAC or resistor dividers. VIN = 20 V, VBAT = 3-cell Li-Ion, ICHARGE = 3 A, IADAPTER_LIMIT = 4 A Figure 3. Typical System Schematic: Sensing Battery Discharge Current, When Adapter Removed. (Set IADSLP at logic high) ORDERING INFORMATION Part number Package bq24740 28-PIN 5 x 5 mm QFN Ordering Number (Tape and Reel) Quantity bq24740RHDR 3000 bq24740RHDT 250 PACKAGE THERMAL DATA PACKAGE QFN – RHD (1) (2) 4 (1) (2) θJA TA = 70°C POWER RATING DERATING FACTOR ABOVE TA = 25°C 39°C/W 2.36 W 0.028 W/°C For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is connected to the ground plane by a 2x3 via matrix. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 Table 1. TERMINAL FUNCTIONS – 28-PIN QFN TERMINAL NAME NO. DESCRIPTION CHGEN 1 Charge enable active-low logic input. LO enables charge. HI disables charge. ACN 2 Adapter current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from ACN pin to AGND for common-mode filtering. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. ACP 3 Adapter current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering. 4 Low power mode detect active-high open-drain logic output. Place a 10-kΩ pullup resistor from LPMD pin to the pullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (see the design example for calculation). The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LO when IADAPT pin voltage is higher than LPREF pin voltage. ACDET 5 Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The IADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. ACOV is input overvoltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation resumes when ACDET < 3.1 V. ACSET 6 Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the VDAC pin. LPREF 7 Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference for the LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is given on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs the hysteresis. IADSLP 8 Enable IADAPT to enter sleep mode; active-low logic input. Allows low Iq sleep mode when adapter not detected. Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is < 0.6 V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is not detected and ACDET pin is 0.6 V, 0-30 mA IVREF_LIM VREF current limit VVREF = 0 V, VACDET > 0.6 V 35 3.3 3.333 V 75 mA 6.2 V REGN REGULATOR VREGN_REG REGN regulator voltage VACDET > 0.6 V, 0-75 mA, PVCC > 10 V 5.6 IREGN_LIM REGN current limit VREGN = 0 V, VACDET > 0.6 V 90 135 mA V 5.9 ADAPTER CURRENT SENSE AMPLIFIER VACP/N_OP Input common mode range 0 24 VIADAPT IADAPT output voltage range Voltage on ACP/SRN 0 2 V IIADAPT IADAPT output current 0 1 mA AIADAPT Current sense amplifier voltage gain Adapter current sense accuracy AIADAPT = VIADAPT / VIREG_DPM 20 V/V VIREG_DPM = 40–100 mV –2% 2% VIREG_DPM = 20 mV –3% 3% VIREG_DPM = 5 mV –25% 25% VIREG_DPM = 1.5 mV –30% 30% IIADAPT_LIM Output current limit VIADAPT = 0 V 1 CIADAPT_MAX Maximum output load capacitance For stability with 0 mA to 1 mA load mA 100 pF 24 V 2.424 V ACDET COMPARATOR VPVCC-BAT_OP VACDET_CHG Differential Voltage from PVCC to BAT ACDET adapter-detect rising threshold VACDET_CHG_HYS ACDET falling hysteresis VACDET_BIAS –20 Min voltage to enable charging, VACDET rising 2.376 2.40 VACDET falling 40 mV ACDET rising deglitch (1) VACDET rising 518 700 908 ms ACDET falling deglitch VACDET falling 7 9 11 ms ACDET enable-bias rising threshold Min voltage to enable all bias, VACDET rising 0.56 0.62 0.68 VACDET_BIAS_HYS Adapter present falling hysteresis ACDET rising deglitch (1) ACDET falling deglitch VACDET falling 20 VACDET rising 10 VACDET falling 10 V mV µs INPUT OVERVOLTAGE COMPARATOR (ACOV) AC Over-voltage rising threshold on ACDET (See ACDET in Terminal Functions) VACOV VACOV_HYS (1) 8 3.007 3.1 AC Overvoltage rising deglitch 1.3 AC Overvoltage falling deglitch 1.3 3.193 V ms Specified by design. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS (continued) 7 V ≤ VPVCC ≤ 24 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 250 300 mV AC CURRENT DETECT COMPARATOR (INPUT UNDERCURRENT) VACIDET Adapter current detect rising threshold VACI = IAC × RAC × 20, falling edge VACIDET_HYS Adapter current detect hysteresis Rising edge 50 mV PVCC / BAT COMPARATOR VPVCC-BAT_FALL PVCC to BAT falling threshold VPVCC-BAT__HYS PVCC to BAT hysteresis VPVCC – VBAT to disable charger 140 185 240 50 PVCC to BAT Rising Deglitch VPVCC – VBAT > VPVCC-BAT_RISE PVCC to BAT Falling Deglitch VPVCC – VBAT < VPVCC-BAT_FALL 7 9 mV mV 11 ms µs 10 INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO) UVLO AC Undervoltage rising threshold UVLO_HYS AC Undervoltage hysteresis, falling Measure on PVCC 3.5 4 4.5 260 V mV BAT OVERVOLTAGE COMPARATOR VOV_RISE Overvoltage rising threshold (2) VOV_FALL Overvoltage falling threshold (2) 104% As percentage of VBAT_REG 102% CHARGE OVERCURRENT COMPARATOR VOC Charge overcurrent falling threshold As percentage of IREG_CHG 145% Minimum Current Limit (SRP-SRN) 50 mV INPUT CURRENT LOW-POWER MODE COMPARATOR VACLP_HYS AC low power hysteresis VACLP_OFFSET AC low power rising threshold 2.8 mV 1 THERMAL SHUTDOWN COMPARATOR TSHUT Thermal shutdown rising temperature TSHUT_HYS Thermal shutdown hysteresis, falling Temperature Increasing 155 °C 20 PWM HIGH SIDE DRIVER (HIDRV) RDS(on)_HI High side driver turn-on resistance VBTST – VPH = 5.5 V, tested at 100 mA 3 6 RDS(off)_HI High side driver turn-off resistance VBTST – VPH = 5.5 V, tested at 100 mA 0.7 1.4 VBTST_REFRESH Bootstrap refresh comparator threshold voltage VBTST – VPH when low side refresh pulse is requested 4 Ω V PWM LOW SIDE DRIVER (LODRV) RDS(on)_HI Low side driver turn-on resistance REGN = 6 V, tested at 100 mA 3 6 RDS(off)_LO Low side driver turn-off resistance REGN = 6 V, tested at 100 mA 0.6 1.2 Ω PWM DRIVERS TIMING Driver Dead Time — Dead time when switching between LODRV and HIDRV. No load at LODRV and HIDRV 30 ns PWM OSCILLATOR FSW PWM switching frequency VRAMP_HEIGHT PWM ramp height (2) 240 As percentage of PVCC 360 6.6 kHz %PVCC Specified by design. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 9 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) 7 V ≤ VPVCC ≤ 24 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VBAT = 16.8 V, VACDET < 0.6 V, VPVCC > 5 V, TJ = 85°C 7 10 VBAT = 16.8 V, VACDET < 0.6 V, VPVCC > 5 V, TJ = 125°C 7 11 UNIT QUIESCENT CURRENT IOFF_STATE Total off-state quiescent current into pins SRP, SRN, BAT, BTST, PH, PVCC, ACP, ACN IBATQ_CD Total quiescent current into pins SRP, SRN, BAT, BTST, PH Adapter present, VACDET >2.4V, charge disabled 100 200 IAC Adapter quiescent current VPVCC = 20 V, charge disabled 2.8 4 µA mA INTERNAL SOFT START (8 steps to regulation current) Soft start steps Soft start step time 8 step 1.7 ms CHARGER SECTION POWER-UP SEQUENCING Charge-enable delay after power-up Delay from when adapter is detected to when the charger is allowed to turn on 518 700 908 ms ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION) ISYN Accuracy V(SRP-SRN) = 5 mV –20% ISYNSET pin voltage VISYNSET 20% 1 V ISYNSET rising deglitch 20 µs ISYNSET falling deglitch 640 µs LOGIC IO PIN CHARACTERISTICS (CHGEN, IADSLP ) VIN_LO Input low threshold voltage VIN_HI Input high threshold voltage IBIAS Input bias current 0.8 V 1 µA 2.1 VCHGEN = 0 to VREGN LOGIC INPUT PIN CHARACTERISTICS (CELLS) VIN_LO Input low threshold voltage, 3 cells CELLS voltage falling edge 0.5 VIN_MID Input mid threshold voltage, 2 cells CELLS voltage rising for MIN, CELLS voltage falling for MAX 0.8 VIN_HI Input high threshold voltage, 4 cells CELLS voltage rising 2.5 IBIAS_FLOAT Input bias float current for 2-cell selection V = 0 to V –1 1.8 V 1 µA OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (EXTPWR) VOUT_LO Output low saturation voltage 0.5 V Delay, EXTPWR falling Sink Current = 4 mA 518 700 908 ms Delay, EXTPWR rising 7 9 11 ms 0.5 V OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET, LPMD) VOUT_LO Output low saturation voltage Sink Current = 5 mA Delay, rising/falling 10 10 Submit Documentation Feedback ms Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS Table of Graphs Y X Figure VREF Load and Line Regulation vs Load Current Figure 4 REGN Load and Line Regulation vs Load Current Figure 5 BAT Voltage vs VADJ/VDAC Ratio Figure 6 Charge Current vs SRSET/VDAC Ratio Figure 7 Input Current vs ACSET/VDAC Ratio Figure 8 BAT Voltage Regulation Accuracy vs Charge Current Figure 9 BAT Voltage Regulation Accuracy Figure 10 Charge Current Regulation Accuracy Figure 11 Input Current Regulation (DPM) Accuracy Figure 12 VIADAPT Input Current Sense Amplifier Accuracy Figure 13 Input Regulation Current (DPM), and Charge Current vs System Current Figure 14 Transient System Load (DPM) Response Figure 15 Charge Current Regulation vs BAT Voltage Figure 16 Efficiency vs Battery Charge Current Figure 17 Battery Removal (from Constant Current Mode) Figure 18 REF and REGN Startup Figure 19 Charger on Adapter Removal Figure 20 Charge Enable / Disable and Current Soft-Start Figure 21 Nonsynchronous to Synchronous Transition Figure 22 Synchronous to Nonsynchronous Transition Figure 23 Near 100% Duty Cycle Bootstrap Recharge Pulse Figure 24 Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation Figure 25 Continuous Conduction Mode (CCM) Switching Waveforms Figure 26 Discontinuous Conduction Mode (DCM) Switching Waveforms Figure 27 DPMDET Response With Transient System Load Figure 28 VREF LOAD AND LINE REGULATION vs LOAD CURRENT REGN LOAD AND LINE REGULATION vs LOAD CURRENT 0 0.50 -0.50 Regulation Error - % Regulation Error - % 0.40 0.30 PVCC = 10 V 0.20 0.10 0 -1 -1.50 PVCC = 10 V -2 PVCC = 20 V -2.50 -0.10 PVCC = 20 V -0.20 -3 0 10 20 30 VREF - Load Current - mA 40 50 0 Figure 4. 10 20 30 40 50 60 REGN - Load Current - mA 70 80 Figure 5. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 11 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com BAT VOLTAGE vs VADJ/VDAC RATIO CHARGE CURRENT vs SRSET/VDAC RATIO 10 18.2 VADJ = 0 -VDAC, 4-Cell, No Load Voltage Regulation - V 17.8 SRSET Varied, 4-Cell, Vbat = 16 V 9 Charge Current Regulation - A 18 17.6 17.4 17.2 17 16.8 16.6 16.4 8 7 6 5 4 3 2 1 16.2 0 16 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 0.1 0.2 0.3 VADJ/VDAC Ratio 0.8 0.9 Figure 6. Figure 7. INPUT CURRENT vs ACSET/VDAC RATIO BAT VOLTAGE REGULATION ACCURACY vs CHARGE CURRENT 1 0.2 10 ACSET Varied, 4-Cell, Vbat = 16 V 9 8 Vreg = 16.8 V 0.1 Regulation Error - % Input Current Regulation - A 0.4 0.5 0.6 0.7 SRSET/VDAC Ratio 7 6 5 4 3 0 -0.1 2 1 -0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 ACSET/VDAC Ratio 0.8 0.9 0 1 2000 Figure 8. BAT VOLTAGE REGULATION ACCURACY CHARGE CURRENT REGULATION ACCURACY 4-Cell, VBAT = 16 V 1 VADJ = 0 -VDAC SRSET Varied 0 -1 0.04 Regulation Error - % Regulation Error - % 8000 2 0.06 4-Cell, no load 0.02 0 -0.02 -0.04 -0.06 -0.10 16.5 -2 -3 -4 -5 -6 -7 -8 -0.08 -9 -10 17 17.5 18 18.5 19 0 V(BAT) - Setpoint - V Figure 10. 12 6000 Figure 9. 0.10 0.08 4000 Charge Current - mA 2 4 I(CHRG) - Setpoint - A 6 8 Figure 11. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 INPUT CURRENT REGULATION (DPM) ACCURACY VIADAPT INPUT CURRENT SENSE AMPLIFIER ACCURACY 5 10 ACSET Varied 9 0 7 4-Cell, VBAT = 16 V 6 Percent Error Regulation Error - % 8 5 4 3 2 VI = 20 V, CHG = EN -5 VI = 20 V, CHG = DIS -10 -15 1 0 -20 -1 -2 -25 Iadapt Amplifier Gain 0 1 2 3 4 Input Current Regulation Setpoint - A 5 0 6 1 2 3 4 5 6 I(ACPWR) - A 7 8 9 10 Figure 12. Figure 13. INPUT REGULATION CURRENT (DPM), AND CHARGE CURRENT vs SYSTEM CURRENT TRANSIENT SYSTEM LOAD (DPM) RESPONSE 5 VI = 20 V, 4-Cell, Vbat = 16 V 4 Ichrg and Iin - A Input Current 3 2 System Current Charge Current 1 0 0 1 2 System Current - A 3 4 Figure 14. Figure 15. CHARGE CURRENT REGULATION vs BAT VOLTAGE EFFICIENCY vs BATTERY CHARGE CURRENT 5 100 V(BAT) = 16.8 V Efficiency - % Charge Current - A 4 3 2 90 Vreg = 12.6 V Vreg = 8.4 V 80 1 Ichrg_set = 4 A 70 0 0 2 4 6 8 10 12 Battery Voltage - V 14 16 18 0 Figure 16. 2000 6000 4000 Battery Charge Current - mA 8000 Figure 17. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 13 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com VBAT Ch2 2 V/div VACDET VREF Ch3 5 V/div IBAT VREGN t − Time = 2 ms/div Figure 19. CHARGER ON ADAPTER REMOVAL CHARGE ENABLE / DISABLE AND CURRENT SOFT-START Ch1 10 V/div Figure 18. VCHGEN Ch4 1 V/div VIN VBAT Ch2 20 V/div VBAT Ch3 2 A/div Ch4 Ch1 5 V/div 5 V/div t − Time = 5 ms/div VPH Ch3 2 A/div IL IBAT t − Time = 200 ms/div t − Time = 4 ms/div Figure 21. NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION VHIDRV Ch2 10 V/div VPH VLODRV Ch4 5 V/div VPH VLDDRV Ch3 2 A/div Ch2 Ch3 Ch4 2 A/div 5 V/div 10 V/div Ch1 10 V/div Figure 20. IL IL t − Time = 2 ms/div t − Time = 4 ms/div Figure 22. 14 Ch1 1.8 V Ch2 Ch3 5 A/div 20 V/div VPH Ch1 2 V/div REF AND REGN STARTUP Ch4 12.3 V Ch4 1 V/div BATTERY REMOVAL Figure 23. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 BATTERY SHORTED CHARGER RESPONSE, OVERCURRENT PROTECTION (OCP) AND CHARGE CURRENT REGULATION Ch4 10 V/div VPH VBAT VHIDRV Ch3 2 A/div Ch4 Ch3 2 A/div 5 V/div Ch2 Ch1 20 V/div 20 V/div NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE PULSE VLODRV IL IL t − Time = 400 ms/div t − Time = 4 ms/div CONTINUOUS CONDUCTION MODE (CCM) SWITCHING WAVEFORMS DISCONTINUOUS CONDUCTION MODE (DCM) SWITCHING WAVEFORMS Ch2 20 V/div VPH Ch3 5 V/div VHIDRV VLODRV Ch4 2 A/div Ch2 20 V/div Ch3 5 V/div Ch4 5 A/div Ch1 20 V/div Figure 25. Ch1 20 V/div Figure 24. IL VPH VHIDRV VLODRV IL t − Time = 1 ms/div t − Time = 1 ms/div Figure 26. Figure 27. DPMDET IBAT Isys Ch4 5 A/div Ch3 5 A/div Ch2 5 A/div Ch1 2 V/div DPMDET RESPONSE WITH TRANSIENT SYSTEM LOAD IIN t - Time = 20 ms/div Figure 28. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 15 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAM 700 ms ENA_BIAS_CMP - 0.6 V AC_VGOOD - 2.4 V + + ACDET VREFGOOD 3.3 V LDO VREF V(IADAPT) ENA_BIAS + - 250 mV +- IADSLP IADSLP UVLO EAI ACP EXTPWR AC_VGOOD_DG Rising Delay AC_IGOOD CHGEN EAO FBO + V(ACP-ACN) 20x - - IIN_REG PVCC IIN_ER AC_VGOOD_DG COMP ERROR AMPLIFIER + ACN BTST CHGEN BAT VBAT_REG BAT_ER + 1V LEVEL SHIFTER + HIDRV SRP 3.5 mA V(SRP-SRN) + – - 20x IBAT_REG SRN DC-DC CONVERTER PWM LOGIC ICH_ER 20 µA + PH 3.5 mA SYNCH 20 µA CHRG_ON PVCC PVCC_BAT V(SRP-SRN) + SYNCH BTST - ISYNSET REGN 6 V LDO VREFGOOD REFRESH CBTST LODRV + + 4V _ PH ACSET IC Tj + 155°C - PGND TSHUT ACP SRSET VBATSET VBAT_REG IBATSET IINSET IBAT_REG VADJ ACN 104% X VBAT_REG - BAT + + V(IADAPT) 20x - IADAPT BAT_OVP RATIO IIN_REG PROGRAM 145% X IBAT_REG - V(SRP-SRN) + ACDET + CHG_OCP DPMDET DPM_LOOP_ON VDAC 3.1 V +V(IADAPT) LPREF ACOV - CELLS + AGND PVCC LPMD - UVLO PGND + 4 V +- PVCC BAT –+ 185 mV 16 Submit Documentation Feedback + PVCC_BAT – bq24740 Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 DETAILED DESCRIPTION BATTERY VOLTAGE REGULATION The bq24740 uses a high-accuracy voltage regulator for charging voltage. Internal default battery voltage setting VBATT = 4.2 V × cell count. The regulation voltage is ratio-metric with respect to VADC. The ratio of VADJ and VDAC provides extra 12.5% adjust range on VBATT regulation voltage. By limiting the adjust range to 12.5% of the regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, while using 1% mis-match resistors. Ratio-metric conversion also allows compatibility with D/As or microcontrollers (µC). The battery voltage is programmed through VADJ and VDAC using Equation 1. é æ öù V VBAT = cell count x êê 4V + ççç0.512 x VADJ ÷÷÷úú çè VVDAC ÷øúû êë (1) The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. VBATT defaults to 4.2 V × cell count when VADJ is connected to REGN. CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2, 3, or 4 Li+ cells. When charging other cell chemistries, use CELLS to select an output voltage range for the charger. CELLS CELL COUNT Float 2 AGND 3 VREF 4 The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to determine this voltage. The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is recommended to be as close to the BAT pin as possible to decouple high frequency noise. BATTERY CURRENT REGULATION The SRSET input sets the maximum charging current. Battery current is sensed by resistor RSR connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010 Ω sense resistor, the maximum charging current is 10 A. SRSET is ratio-metric with respect to VDAC using Equation 2: V I CHARGE + SRSET 0.10 VVDAC R SR (2) The input voltage range of SRSET is between 0 and VDAC, up to 3.6 V. The SRP and SRN pins are used to sense across RSR with default value of 10 mΩ. However, resistors of other values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss. INPUT ADAPTER CURRENT REGULATION The total input from an AC adapter or other DC sources is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the systems are powered up or down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging current when the input current exceeds the input current limit set by ACSET. The current capability of the AC adapter can be lowered, reducing system cost. Similar to setting battery regulation current, adapter current is sensed by resistor RAC connected between ACP and ACN. Its maximum value is set ACSET, which is ratio-metric with respect to VDAC, using Equation 3. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 17 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com V I ADAPTER + ACSET VVDAC 0.10 R AC (3) The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V. The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss. ADAPTER DETECT AND POWER UP An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage and lower than the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense the true adapter input voltage whether the ACFET is on or off. If PVCC is below 4 V, the device is disabled. If ACDET is below 0.6 V but PVCC is above 4 V, part of the bias is enabled, including a crude bandgap reference. IADAPT is disabled and pulled down to GND. The total quiescent current is less than 10 µA. Once ACDET rises above 0.6 V and PVCC is above 4 V, all the bias circuits are enabled and REGN output goes to 6 V and VREF goes to 3.3 V. IADAPT becomes valid to proportionally reflect the adapter current. The total quiescent current is about 1 mA. When ACDET keeps rising and passes 2.4 V, a valid ac adapter is present. 700ms later, the following occurs: • EXTPWR becomes low through external pull-up resistor to the host digital voltage rail. • Charging begins if all the conditions are satisfied, see the ENABLE AND DISABLE CHARGING section. ENABLE AND DISABLE CHARGING The following conditions have to be valid before charge is enabled: • CHGEN is LOW; • PVCC > UVLO; • Adapter is detected; • Adapter is higher than PVCC-BAT threshold; • Adapter is not overvoltage; • 700 ms delay is complete after adapter detected; • REGNGOOD and VREFGOOD are valid; • Thermal Shut (TSHUT) is not valid; One of the following conditions will stop on-going charging: • CHGEN is HIGH; • PVCC < UVLO; • Adapter is removed; • Adapter is less than 185 mV above battery; • Adapter is overvoltage; • Adapter is overcurrent; • TSHUT IC temperature threshold is reached (155°C on rising-edge with 20°C hysteresis). AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each step lasts around 1.7 ms, for a typical rise time of 13.6 ms. No external components are needed for this function. 18 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 CONVERTER OPERATION The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal. Where resonant frequency, fo, is given by: 1 fo + Ǹ 2p LoC o (4) where (from Figure 1 schematic) • CO = C11 + C12 • LO = L1 An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset by 200 mV in order to allow zero percent duty-cycle, when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued. The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region. The charge current sense resistor RSR should be placed with at least half or more of the total output capacitance placed before the sense resistor contacting both sense resistor and the output inductor; and the other half or remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best performance; but the node in which the output inductor and sense resistor connect should have a minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better current sense accuracy. The type III compensation provides phase boost near the cross-over frequency, giving sufficient phase margin. SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value. Otherwise, the charger operates in synchronous mode. During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent shoot-through currents. During the 30ns dead time where both FETs are off, the back-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safe charging at high currents. During synchronous mode the inductor current is always flowing and operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system. During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the break-before-make dead-time, the low-side n-channel power MOSFET turns on for around 80ns, then the low-side power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The 80ns low-side MOSFET on time is required to ensure the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery chargers; where, unlike regular dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The inductor current is blocked by the off low-side MOSFET, and the inductor current will become discontinuous. This mode is called Discontinuous Conduction Mode (DCM). Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 19 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com During the DCM mode the loop response automatically changes and has a single pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means at very low currents the loop response is slower, as there is less sinking current available to discharge the output voltage. At low currents during non-synchronous operation, there may be a small amount of negative inductor current during the 80 ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance. When BTST – PH < 4 V, the 80-ns recharge pulse occurs on LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (only 80-ns recharge pulse). ISYNSET CONTROL (SYN and NON-SYN MODE SETTING) The ISYNSET pin is used to program the charge current threshold at which the charger changes from synchronous operation into non-synchronous operation. The low side driver turns on for only 80 ns to charge the boost cap. This is important to prevent negative inductor current, which may cause a boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors. This boost effect can lead to an overvoltage on the PVCC node and potentially cause some damage to the system. This programmable value allows setting the current threshold for any inductor current ripple, and avoiding negative inductor current. The minimum synchronous threshold should be set from ＝ of the inductor current ripple to the full ripple current, where the inductor current ripple is given by: I ripple _ max 2 £ I SYN £ I ripple _ max and (Vin - Vbat ) ´ I ripple = Vbat 1 ´ Vin f s L Vin ´ (1 - D) ´ D ´ = 1 fs L (5) where VIN: adapter voltage VBAT: BAT voltage fS: switching frequency L: output inductor D: duty cycle IRIPPLE_MAX occurs when the duty cycle, D is mostly near to 0.5 at given Vin, fs and L. The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between SRP-SNR and the threshold set by an external resistor RISYNSET, which can be calculated by: 20 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 RISYNSET = 250 V W ISYN x RSENSE (6) RSENSE SRN SRP - + 3.3 V ISYN 20X I =1V/R_ISYNSET 1V SYNCH UCP + - + 5 kΩ ISYNSET R_ISYNSET Figure 29. Charge Undercurrent Comparator, ISYNSET Comparator Block HIGH ACCURACY IADAPT USING CURRENT SENSE AMPLIFIER (CSA) An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input sensed voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times the input differential voltage. Once PVCC is above 5 V and ACDET is above 0.6V, IADAPT no longer stays at ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT to AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients. A 100-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional RC filter is optional, after the 100-pF capacitor, if additional filtering is desired. Note that adding filtering also adds additional response delay. INPUT OVERVOLTAGE PROTECTION (ACOV) ACOV provides protection to prevent system damage due to high input voltage. The controller enters ACOV when ACDET > 3.1 V and charge is disabled. ACOV is not latched—normal operation resumes when the ACDET voltage returns below 3.1 V. ACOV threshold is 130% of the adapter-detect threshold. INPUT UNDERVOLTAGE LOCK OUT (UVLO) The system must have a minimum 4 V PVCC voltage to allow proper operation. This PVCC voltage could come from either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 4 V the bias circuits REGN and VREF stay inactive, even with ACDET above 0.6 V. INPUT CURRENT LOW-POWER MODE DETECTION To optimize the system performance, the HOST monitors the adapter current. Once the adapter current is above threshold set via LPREF, LPMD pin sends signal to HOST. The signal alarms the host that input power has exceeded the programmed limit, allowing the host to throttle back system power by reducing clock frequency, lowering rail voltages, or disabling certain parts of the system. The LPMD pin is an open-drain output. Connect a pull-up resistor to LPMD. The output is logic HI when the IADAPT output voltage (IADAPT = 20 × VACP-ACN) is lower than the LPREF input voltage. The LPREF threshold is set by an external resistor divider using VREF. A hysteresis can be programmed by a positive feedback resistor from LPMD pin to the LPREF pin. Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 21 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com ACVDET Comparator ACDET 2.4 V + - t_dg rising 700 ms AC_VGOOD AC_VGOOD_DG To Control Logic EXT_PWR_DG ACP 1 kΩ Adaptor Current Sense Amplifier + ACIDET Comparator 250 mV AC_IGOOD (1.25 A) + - ACN EXTPWR IADAPT Error Amplifier Disable 20 kΩ + 20 xV(ACP-ACN) IADAPT IADAPT Disable IADAPT OUTPUT BUFFER LPMD Comparator + LPREF LOPWR_DET LPMD Program Hysteresis of comparator externally by putting a resistor in feedback from LPMD pin to LPREF pin. Figure 30. EXTPWR, LPREF and LPMD Logic BATTERY OVERVOLTAGE PROTECTION The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is disconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging the stored output-inductor energy into the output capacitors. CHARGE OVERCURRENT PROTECTION The charger has a secondary overcurrent protection. It monitors the charge current, and prevents the current from exceeding 145% of regulated charge current. The high-side gate drive turns off when the overcurrent is detected, and automatically resumes when the current falls below the over-current threshold. THERMAL SHUTDOWN PROTECTION The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 155°C. The charger stays off until the junction temperature falls below 135°C. 22 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 Status Outputs (EXTPWR, LPMD, DPMDET pin) Four status outputs are available, and they all, except for LPMD, require external pull up resistors to pull the pins to system digital rail for a high level. EXTPWR open-drain output goes low under either of the two conditions: 1. ACDET is above 2.4 V 2. Adapter current is above 1.25 A using a 10-mΩ sense resistor (IADAPT voltage above 250 mV). Internally, the AC current detect comparator looks between IADAPT and an internal 250-mV threshold. It indicates a good adapter is connected because of valid voltage or current. LPMD open-drain output goes low when the input current is higher than the programmed threshold via LPREF pin. Hysteresis can be programmed by putting a resistor from LPREF pin to LPMD pin. DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current (after a 10-ms delay). Table 2. Component List for Typical System Circuit of Figure 1 PART DESIGNATOR QTY DESCRIPTION Q1, Q2, Q3 3 P-channel MOSFET, –30V,-6A, SO-8, Vishay-Siliconix, Si4435 Q4, Q5 2 N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A D1, D2 2 Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C RAC, RSR 2 Sense Resistor, 10 mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F L1 1 Inductor, 8.2µH, 24.8mΩ, Vishay-Dale, IHLP5050CE-01 C6, C7, C11, C12 4 Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M C4, C10 2 Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K C2, C3, C8, C9, C13, C14, C15 7 Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU C1 1 Capacitor, Ceramic, 2.2µF, 25V, 2%, X5R, 1206, Panasonic, ECJ3YB1E225M C5 1 Capacitor, Ceramic, 100pF, 50V, 10%, X7R, 0805, Kemet, C0805C101K5RACTU R3, R4, R5 3 Resistor, Chip, 10 kΩ, 1/16W, 5%, 0402 R1 1 Resistor, Chip, 432 kΩ, 1/16W, 1%, 0402 R2 1 Resistor, Chip, 66.5 kΩ, 1/16W, 1%, 0402 R6 1 Resistor, Chip, 24kΩ, 1/16W, 1%, 0402 R7 1 Resistor, Chip, 200 kΩ, 1/16W, 1%, 0402 R8 1 Resistor, Chip, 24.9 kΩ, 1/16W, 1%, 0402 R9 1 Resistor, Chip, 1.8 MΩ, 1/16W, 1%, 0402 R10 1 Resistor, Chip, 2 Ω, 1W, 5%, 2012 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 23 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com APPLICATION INFORMATION During the adapter hot plug-in, the ACFET has not been turned on. The AC switch is off and the simplified equivalent circuit of the input is shown in Figure 31 IIN Ri Vi VIN Li Rc Ci Vc Figure 31. Simplified Equivalent Circuit During Adapter Insertion The voltage on the charger input side VIN is given by: V IN(t) + I IN(t) RC ) VCi(t) + Vie Ri t 2L i ƪ Ri * RC sin wt ) cos wt wL i ƫ (7) in which, 1 R t = Ri + R C w = VCi (t) = Vi - Vie L i Ci Rt t 2Li - æ Rt ö ç ÷ è 2Li ø 2 IIN (t) = Vi Ri t 2Li e sin w t wL i æ Rt ö s in w t + cosw t ÷ ç è 2w L i ø (8) (9) The damping condition is: Ri ) Rc u 2 24 Ǹ Li Ci (10) Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 Figure 32(a) demonstrates a higher Ci helps dampen the voltage spike. Figure 32(b) demonstrates the effect of the input stray inductance Li upon the input voltage spike. Figure 32(c) shows how increased resistance helps to suppress the input voltage spike. 35 35 Ci = 20 mF Ci = 40 mF 30 Input Capacitor Voltage - V Input Capacitor Voltage - V Li = 5 mH Ri = 0.21 W Li = 9.3 mH 30 25 20 15 10 5 0 Li = 12 mH Ri = 0.15 W Ci = 40 mF 25 20 15 10 5 0 0.5 1 1.5 4 2 2.5 3 3.5 Time - ms (a) Vc with various Ci values 4.5 0 5 0 0.5 1 1.5 2 2.5 3 3.5 Time - ms (b) Vc with various Li values 4 4.5 5 35 Ri = 0.15 W Li = 9.3 mH Ci = 40 mF Input Capacitor Voltage - V 30 Ri = 0.5 W 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 Time - ms 3.5 4 4.5 5 (c) Vc with various Ri values Figure 32. Parametric Study Of The Input Voltage As shown in Figure 32, minimizing the input stray inductance, increasing the input capacitance, and adding resistance (including using higher ESR capacitors) helps suppress the input voltage spike. However, a user often cannot control input stray inductance and increasing capacitance can increase costs. Therefore, the most efficient and cost-effective approach is to add an external resistor. Figure 33 depicts the recommended input filter design. The measured input voltage and current waveforms are shown in Figure 34. The input voltage spike has been well damped by adding a 2-Ω resistor, while keeping the capacitance low. VIN 2W (0.5 W, 1210 anti-surge) 2.2 mF (25 V, 1210) VPVCC Rext C1 C2 0.1 mF (50 V, 0805, very close to PVCC) Figure 33. Recommended Input Filter Design Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 25 bq24740 SLUS736C – DECEMBER 2006 – REVISED MARCH 2009............................................................................................................................................... www.ti.com Figure 34. Adapter DC Side Hot Plug-In Test Waveforms 26 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 bq24740 www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 PCB Layout Design Guideline 1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the power ground are connected only at the power pad. 3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The area of this loop must be minimized. An additional 0.1 µF decoupling capacitor for ACN is required to further reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as possible. 4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact. The area of this loop must be minimized. An additional 0.1 µF decoupling capacitor for SRN is required to further reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as possible. 5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC (on the bottom layer) with the interconnections to the IC as short as possible. 6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins with the interconnections to the IC as short as possible. 7. Decoupling capacitor CX for the charger input must be placed close to the Q4 drain and Q5 source. Figure 35 shows the recommended component placement with trace and via locations. For the QFN information, see the SCBA017 and SLUA271 documents. (a) Top Layer (b) Bottom Layer Figure 35. Layout Example Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s) :bq24740 27 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) BQ24740RHDR ACTIVE VQFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24740RHDRG4 ACTIVE VQFN RHD 28 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24740RHDT ACTIVE VQFN RHD 28 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24740RHDTG4 ACTIVE VQFN RHD 28 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ24740RHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 BQ24740RHDT VQFN RHD 28 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24740RHDR VQFN RHD 28 3000 346.0 346.0 29.0 BQ24740RHDT VQFN RHD 28 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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