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bq25570
SLUSBH2G – MARCH 2013 – REVISED MARCH 2019
bq25570 nano power boost charger and buck converter
for energy harvester powered applications
1 Features
2 Applications
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1
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Ultra Low Power DC-DC Boost Charger
– Cold-Start Voltage: VIN ≥ 600 mV
– Continuous Energy Harvesting From VIN as
low as 100 mV
– Input Voltage Regulation Prevents Collapsing
High Impedance Input Sources
– Full Operating Quiescent Current of 488 nA
(typical)
– Ship Mode with < 5 nA From Battery
Energy Storage
– Energy can be Stored to Re-chargeable Li-ion
Batteries, Thin-film Batteries, Supercapacitors, or Conventional Capacitors
Battery Charging and Protection
– Internally Set Undervoltage Level
– User Programmable Overvoltage Levels
Battery Good Output Flag
– Programmable Threshold and Hysteresis
– Warn Attached Microcontrollers of Pending
Loss of Power
– Can be Used to Enable or Disable System
Loads
Programmable Step Down Regulated Output
(Buck)
– High Efficiency up to 93%
– Supports Peak Output Current up to 110 mA
(typical)
Programmable Maximum Power Point Tracking
(MPPT)
– Provides Optimal Energy Extraction From a
Variety of Energy Harvesters including Solar
Panels, Thermal and Piezo Electric Generators
Energy Harvesting
Solar Chargers
Thermal Electric Generator (TEG) Harvesting
Wireless Sensor Networks (WSN)
Low Power Wireless Monitoring
Environmental Monitoring
Bridge and Structural Health Monitoring (SHM)
Smart Building Controls
Portable and Wearable Health Devices
Entertainment System Remote Controls
3 Description
The bq25570 device is specifically designed to
efficiently extract microwatts (µW) to milliwatts (mW)
of power generated from a variety of high output
impedance DC sources like photovoltaic (solar) or
thermal electric generators (TEG) without collapsing
those sources. The battery management features
ensure that a rechargeable battery is not overcharged
by this extracted power, with voltage boosted, or
depleted beyond safe limits by a system load. In
addition to the highly efficient boosting charger, the
bq25570 integrates a highly efficient, nano- power
buck converter for providing a second power rail to
systems such as wireless sensor networks (WSN)
which have stringent power and operational
demands. All the capabilities of bq25570 are packed
into a small foot-print 20-lead 3.5-mm x 3.5-mm QFN
package (RGR).
Device Information(1)
PART NUMBER
bq25570
PACKAGE
VQFN (20)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
spacing
Typical Application Schematic
CSTOR
VOC_SAMP
CIN
VSTOR
90
80
LBUCK
Boost
Controller
VSS
COUT
Buck
Controller
MPPT
VIN_DC
VSS
Cold Start
VBAT
VOUT_EN
GPIO3
VBAT_OK
ROV2
ROK3
OK_HYST
GPIO2
VBAT_OV
EN
VRDIV
GPIO1
OK_PROG
Nano-Power
Management
Host
L2
VOUT
CREF
VSTOR
100
VBAT
VREF_SAMP
+
-
Charger Efficiency vs Input Voltage
BAT
LBOOST
bq25570
ROUT2
ROUT1
ROK1
70
IIN = 100 PA
60
50
40
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
20
10
0
ROK2
ROV1
System
Load
30
VOUT_SET
Solar
Cell
+
Efficiency (%)
L1
CBYP
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Input Voltage (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq25570
SLUSBH2G – MARCH 2013 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
14
14
17
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 25
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
10.3 Thermal Considerations ........................................ 36
11 Device and Documentation Support ................. 37
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
37
12 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (December 2018) to Revision G
Page
•
Changed From: "330 mV typical,.." To: "600 mV typical,.." in the second paragraph of the Overview section ................... 13
•
Changed Figure 21 .............................................................................................................................................................. 16
•
Changed From: "VIN(CS) = 330 mV typical." To: "VIN(CS) = 600 mV typical." in the last paragraph of the Cold-Start
Operation section.................................................................................................................................................................. 19
Changes from Revision E (March 2015) to Revision F
Page
•
Changed Feature From: Cold-Start Voltage: VIN ≥ 330 mV (Typical) To: Cold-Start Voltage: VIN ≥ 600 mV ........................ 1
•
Changed the RGR Package appearance ............................................................................................................................... 4
•
Increased VIN(CS) From: TYP = 330 mV and MAX = 450 mV To: TYP = 600 mV and MAX = 700 mV in Electrical
Characteristics table ............................................................................................................................................................... 6
Changes from Revision D (December 2014) to Revision E
Page
•
Changed the Test Condition for PIN(CS) in the Electrical Characteristics ............................................................................... 6
•
Changed the values for PIN(CS) in the Electrical Characteristics From: TYP = 5 To: TYP = 15.............................................. 6
•
Changed CBYP = 0.1 µF To: CBYP = 0.01 µF in Detailed Design Procedure .................................................................... 25
•
Changed CBYP = 0.1 µF To: CBYP = 0.01 µF in Detailed Design Procedure .................................................................... 28
•
Changed CBYP = 0.1 µF To: CBYP = 0.01 µF in Detailed Design Procedure .................................................................... 31
Changes from Revision C (December 2013) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SLUSBH2G – MARCH 2013 – REVISED MARCH 2019
Changes from Revision B (September 2013) to Revision C
Page
•
Changed Feature: Continuous Energy Harvesting From Input Sources as low as 120 mV To: Continuous Energy
Harvesting From Input Sources as low as 100 mV ................................................................................................................ 1
•
Changed Feature From: High Efficiency up to 98% To: High Efficiency up to 93% ............................................................. 1
•
Changed text in the Description From: can continue to harvest energy down to VIN = 120 mV. To: can continue to
harvest energy down to VIN = 100 mV. .................................................................................................................................. 1
•
Changed Peak Input Power n the Absolute Maximum Ratings table From: MAX = 400 mW To: MAX = 510 mW............... 5
•
Changed VIN(DC) in the Recommended Operating Conditions table From: MIN = 0.12 V MAX = 4 V To: MIN = 0.1
V MAX = 5.1 V........................................................................................................................................................................ 5
•
Changed VIN(DC) in the Electrical Characteristics table From: MIN = 120 mV MAX = 4000 mV To: MIN = 100 mV
MAX = 5100 mV ..................................................................................................................................................................... 6
•
Changed PIN in the Electrical Characteristics table From: MAX = 400 mW To: MAX = 510 mW......................................... 6
•
Added VDELTA, VBAT_OV - VIN(DC to the ELECTRICAL CHARACTERISTICS table....................................................... 7
•
Changed VOUT_EN(H) From: VSTOR - 0.2 To: VSTOR - 0.4 in the ELECTRICAL CHARACTERISTICS table................. 7
Changes from Revision A (September 2013) to Revision B
•
Page
Changed values in the Thermal Information table.................................................................................................................. 6
Changes from Original (March 2013) to Revision A
•
Page
Changed the data sheet from a Product Brief to Production data ......................................................................................... 4
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5 Pin Configuration and Functions
LBOOST
VSTOR
VBAT
NC
LBUCK
20
19
18
17
16
RGR Package
20 Pins
Top View
VSS
1
15
VSS
VIN_DC
2
14
VOUT
13
VBAT_OK
VOC_SAMP
Thermal
3
Pad
10
9
NC
OK_HYST
8
VRDIV
OK_PROG
7
VOUT_SET
11
6
12
5
VBAT_OV
4
EN
VOUT_EN
VREF_SAMP
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
5
I
LBOOST
20
I/O
Inductor connection for the boost charger switching node. Connect a 22 µH inductor between this pin and pin
2 (VIN_DC).
LBUCK
16
I/O
Inductor connection for the buck converter switching node. Connect at least a 4.7 µH inductor between this
pin and pin 14 (VOUT).
NC
9
I
Connect to ground using the IC's PowerPAD™.
NC
17
I
Connect to ground using the IC's PowerPAD.
OK_HYST
10
I
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT_OK
hystersis threshold. If not used, connect this pin to GND.
OK_PROG
11
I
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT_OK
threshold. If not used, connect this pin to GND.
VBAT
18
I/O
Connect a rechargeable storage element with at least 100uF of equivalent capacitance between this pin and
either VSS pin.
VBAT_OK
13
O
Digital output for battery good indicator. Internally referenced to the VSTOR voltage. Leave floating if not
used.
VBAT_OV
7
I
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VBAT
overvoltage threshold.
VIN_DC
2
I
DC voltage input from energy harvesting source. Connect at least a 4.7 µF capacitor as close as possible
between this pin and pin 1.
VOC_SAMP
3
I
Sampling pin for MPPT network. Connect to VSTOR to sample at 80% of input source open circuit voltage.
Connect to GND for 50% or connect to the mid-point of external resistor divider between VIN_DC and GND.
VOUT
14
O
Buck converter output. Connect at least 22 µF output capacitor between this pin and pin 15 (VSS).
VOUT_EN
6
I
Active high digital programming input for enabling/disabling the buck converter. Connect to VSTOR to enable
the buck converter.
VOUT_SET
12
I
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the VOUT
regulation set point.
VREF_SAMP
4
I
Connect a 0.01-µF low-leakage capacitor from this pin to GND to store the voltage to which VIN_DC will be
regulated. This voltage is provided by the MPPT sample circuit.
VRDIV
8
O
Connect high side of resistor divider networks to this biasing voltage.
VSS
1
I
Power ground for the boost charger.
VSS
15
—
Power ground for the buck converter and analog/signal ground for the resistor dividers and VREF_SAMP
capacitor.
VSTOR
19
O
Connection for the output of the boost charger. Connect at least a 4.7 µF capacitor in parallel with a 0.1 µF
capacitor as close as possible to between this pin and pin 1 (VSS).
4
Active low digital programming input for enabling/disabling the IC. Connect to GND to enable the IC.
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6
SLUSBH2G – MARCH 2013 – REVISED MARCH 2019
Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
VIN_DC, VOC_SAMP, VREF_SAMP, VBAT_OV, VRDIV, OK_HYST,
OK_PROG, VBAT_OK, VBAT, VSTOR, LBOOST, EN, VOUT_EN,
VOUT_SET, LBUCK, VOUT (2)
MIN
MAX
UNIT
–0.3
5.5
V
510
mW
Peak Input Power, PIN_PK
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS/ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VIN(DC)
DC input voltage into VIN_DC (1)
(2)
NOM
MAX
0.1
5.1
2
5.5
UNIT
V
VBAT, VOUT
Voltage range
CIN
Capacitance on VIN_DC pin
4.7
µF
CSTOR
Capacitance on VSTOR pin
4.7
µF
COUT
Capacitance on VOUT pin
10
CBAT
Capacitance or battery with at least the same equivalent capacitance on
VBAT pin
CREF
Capacitance on VREF_SAMP that stores the samped VIN reference
ROC1 + ROC2
ROK 1 + ROK 2 + ROK3
22
V
µF
100
µF
9
10
11
nF
Total resistance for setting for MPPT reference if needed
18
20
22
MΩ
Total resistance for setting VBAT_OK threshold voltage.
11
13
15
MΩ
ROUT1 + ROUT2
Total resistance for setting VOUT threshold voltage.
11
13
15
MΩ
ROV1 + ROV2
Total resistance for setting VBAT_OV voltage.
11
13
15
MΩ
L1
Inductance on LBOOST pin
22
L2
Inductance on LBUCK pin
4.7
TA
Operating free air ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
105
°C
(1)
(2)
µH
10
µH
Maximum input power ≤ 400 mW. Cold start has been completed
VBAT_OV setting must be higher than VIN_DC
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6.4 Thermal Information
bq25570
THERMAL METRIC (1)
RGR
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
34.6
RθJC(top)
Junction-to-case (top) thermal resistance
49.0
RθJB
Junction-to-board thermal resistance
12.5
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
12.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for
conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10 µH, COUT
= 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5100
mV
285
mA
510
mW
600
700
mV
1.73
1.9
V
BOOST CHARGER
VIN(DC)
DC input voltage into VIN_DC
Cold-start completed
ICHG(CBC_LIM)
Cycle-by-cycle current limit of charger
0.5V < VIN < 4.0 V; VSTOR
= 4.2 V
PIN
Input power range for normal charging
VBAT_OV > VSTOR >
VSTOR_CHGEN
VIN(CS)
Minimum input voltage for cold start
circuit to start charging VSTOR
VBAT < VBAT_UV; VSTOR
= 0 V; 0°C < TA < 85°C
VSTOR(CHGEN)
Voltage on VSTOR when cold start
operation ends and normal charger
operation commences
Minimum cold-start input power for
VSTOR to reach VSTOR(CHGEN) and
allow normal charging to commence
PIN(CS)
tBAT_HOT_PLUG
Time for which switch between VSTOR
and VBAT closes when battery is hot
plugged into VBAT
100
230
0.005
1.6
VSTOR < VSTOR(CHGEN)
VIN_DC clamped to VIN(CS)
by cold start circuit
VBAT = 100 µF
15
µW
Battery resistance = 300
Ω, Battery voltage = 3.3V
50
ms
VIN_DC = 0V; VSTOR =
2.1V; TJ = 25°C
488
QUIESCENT CURRENTS
EN = 0, VOUT_EN = 1 - Full operating
mode
EN = 0, VOUT_EN = 0 - Partial standby
mode
IQ
VIN_DC = 0V; VSTOR =
2.1V; –40°C < TJ < 85°C
VIN_DC = 0V; VSTOR =
2.1V; TJ = 25°C
EN = 1, VOUT_EN = x - Ship mode
900
445
VIN_DC = 0V; VSTOR =
2.1V; –40°C < TJ < 85°C
VBAT = 2.1 V; TJ = 25°C;
VSTOR = VIN_DC = 0 V
700
615
815
1
VBAT = 2.1 V; –40°C < TJ
< 85°C; VSTOR = VIN_DC
=0V
nA
5
30
MOSFET RESISTANCES
RDS(ON)-BAT
6
ON resistance of switch between VBAT
and VSTOR
VBAT = 4.2 V
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0.95
1.50
Ω
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SLUSBH2G – MARCH 2013 – REVISED MARCH 2019
Electrical Characteristics (continued)
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for
conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10 µH, COUT
= 22 µF
PARAMETER
TEST CONDITIONS
Charger low side switch ON resistance
RDS(ON)_CHG
Charger high side switch ON resistance
Charger low side switch ON resistance
Charger high side switch ON resistance
Buck low side switch ON resistance
RDS(ON)_BUCK
Buck high side switch ON resistance
Buck low side switch ON resistance
Buck high side switch ON resistance
fSW_CHG
Maximum charger switching frequency
fSW_BUCK
Maximum buck switching frequency
TTEMP_SD
Junction temperature when charging is
discontinued
MIN
VBAT = 4.2 V
VBAT = 2.1 V
VBAT = 4.2 V
VBAT = 2.1 V
VBAT_OV > VSTOR >
1.8V
TYP
MAX
0.70
0.90
2.30
3.00
0.80
1.00
3.70
4.80
0.80
1.00
1.60
2.00
1.00
1.20
2.40
2.90
UNIT
Ω
Ω
1
MHz
500
kHz
125
C
BATTERY MANAGEMENT
VBAT_OV
Programmable voltage range for
overvoltage threshold
VBAT increasing
2.2
Battery over-voltage hysteresis (internal)
VBAT decreasing;
VBAT_OV = 5.25V
VBAT_OV - VIN(DC)
Main boost charger on;
MPPT not sampling VOC
400
VBAT_UV
Under-voltage threshold
VBAT decreasing
1.91
VBAT_UV_HYST
Battery under-voltage hysteresis (internal) VBAT increasing
VBAT_OK_HYST
Programmable voltage range of digital
signal indicating VSTOR (=VBAT) is OK
VBAT_OV_HYST
VDELTA
VBAT_OK_PROG
VBAT_ACCURACY
VBAT_OK(H)
VBAT_OK(L)
VBAT increasing
Programmable voltage range of digital
signal indicating VSTOR (=VBAT) is OK
VBAT decreasing
Overall Accuracy for threshold values
VBAT_OV, VBAT_OK
Selected resistors are 0.1%
tolerance
VBAT_OK (High) threshold voltage
VBAT_OK (Low) threshold voltage
24
5.5
V
55
mV
mV
1.95
2.0
V
15
32
mV
VBAT_UV
VBAT_OV
V
VBAT_UV
VBAT_OK
_HYST –
50
mV
-2%
2%
Load = 10 µA
VSTOR –
200
mV
Load = 10 µA
100
mV
ENABLE THRESHOLDS
EN(H)
Voltage for EN high setting. Relative to
VBAT.
VBAT = 4.2V
EN(L)
Voltage for EN low setting
VBAT = 4.2V
VOUT_EN(H)
VOUT_EN(L)
Voltage for VOUT_EN High setting.
Voltage for VOUT_EN Low setting.
VSTOR = 4.2V
VBAT –
0.2
V
0.3
VSTOR –
0.4
V
V
VSTOR = 4.2V
0.3
V
BIAS and MPPT CONTROL STAGE
VOC_SAMPLE
Time period between two MPPT samples
VOC_STLG
Settling time for MPPT sample
measurement of VIN_DC open circuit
voltage
Device not switching
VIN_REG
Regulation of VIN_DC during charging
0.5 V < VIN < 4 V; IIN(DC)
= 10 mA
MPPT_80
Voltage on VOC_SAMP to set MPPT
threshold to 0.80 of open circuit voltage of
VIN_DC
16
s
256
ms
10%
VSTOR –
0.015
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Electrical Characteristics (continued)
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for
conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10 µH, COUT
= 22 µF
PARAMETER
TEST CONDITIONS
MPPT_50
Voltage on VOC_SAMP to set MPPT
threshold to 0.50 of open circuit voltage of
VIN_DC
VBIAS
Internal reference for the programmable
voltage thresholds
MIN
TYP
MAX
15
VSTOR ≥ VSTOR_CHGEN
1.205
1.21
1.217
UNIT
mV
V
6.6 Electrical Characteristics
Over recommended ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10
µH, COUT = 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK CONVERTER
VOUT
Output regulation (excluding resistor tolerance
error)
IOUT = 10 mA;
1.3 V < VOUT < 3.3 V
Output line regulation
IOUT = 10 mA;
VSTOR = 2.1 V to 5.5 V,
COUT = 22 µF
Output load regulation
IOUT = 100 µA to 95 mA,
VSTOR = 3.6 V, COUT = 22
µF
Output ripple
VSTOR = 4.2V, IOUT = 1 mA,
COUT = 22 μF
–2%
Programmable voltage range for output voltage
threshold
Output Current
VSTOR = 3.3V; VOUT = 1.8 V
tSTART-STBY
Startup time with EN low and VOUT_EN transition
to high (Standby Mode)
tSTART-SHIP
I-BUCK(CBC-LIM)
8
0.09
%/V
-0.01
%/mA
30
mVpp
VSTOR –
0.2 (1)
1.3
IOUT
(1)
2%
93
V
110
mA
COUT = 22 µF
250
μs
Startup time with VOUT_EN high and EN
transition from high to low (Ship Mode)
COUT = 22 µF
100
ms
Cycle-by-cycle current limit of buck converter
2.4 V < VSTOR < 5.5 V;
1.3 V < VOUT < 3.3 V
160
185
205
mA
The dropout voltage can be computed as the maximum output current times the buck high side resistance.
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6.7 Typical Characteristics
Unless otherwise noted, graphs were taken using Figure 24 with CIN = 4.7µF, L1 = Coilcraft 22µH LPS4018, CSTOR =
4.7µF, L2 = Toko 10 µH DFE252012C, COUT = 22µF, VBAT_OV=4.2V, VOUT=1.8V
Table 1. Table of Graphs
FIGURE
vs. Input Voltage
Charger Efficiency (η) (1)
vs. Input Current
VSTOR Quiescent Current
vs. VSTOR Voltage
VBAT Quiescent Current
vs. VBAT Voltage
Buck Efficiency (η)
Normalized Buck Output Voltage
Buck Maximum Output Current
vs. Input Voltage
Figure 1
IN= 100 µA
Figure 2
IIN = 10 mA
Figure 3
VIN = 2.0 V
Figure 4
VIN = 1.0 V
Figure 5
VIN = 0.5 V
Figure 6
VIN = 0.2 V
Figure 7
EN = 1, VOUT_EN = X (Ship Mode)
Figure 8
EN = 0, VOUT_EN = 0 (Standby Mode)
Figure 9
EN = 0, VOUT_EN = 1 (Active Mode)
Figure 10
vs. Output Current
Figure 11
vs. Input Voltage
Figure 12
vs. Output Current
Figure 13
vs. Input Voltage
Figure 14
vs. Temperature
Figure 15
VOUT = 1.8V - 100mV
Figure 16
Buck Major Switching Frequency
Buck Output Ripple
(1)
IN= 10 µA
vs. Output Current
Figure 17
vs. Input Voltage
Figure 18
vs.Output Current
Figure 19
vs. Input Voltage
Figure 20
See SLUA691 for an explanation on how to take these measurements. Because the MPPT feature cannot be disabled on the bq25570,
these measurements need to be taken in the middle of the 16 s sampling period.
100
90
80
100
90
IIN = 10PA
80
70
Efficiency (%)
Efficiency (%)
70
60
50
40
30
IIN = 100 PA
60
50
40
30
20
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
20
VSTOR = 2.0 V
10
VSTOR = 3.0 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Input Voltage (V)
Input Voltage (V)
VIN_DC = sourcemeter configured with ICOMP = 10 µA and
outputing 0 to 3.0 V
VSTOR = sourcemeter configured to measure current and voltage
source set to hold the VSTOR voltage = 2.0 V or 3.0 V
Figure 1. Charger Efficiency vs Input Voltage
VIN_DC = Keithley Source Meter configured with ICOMP = 100 µA
and voltage source varied from 0.1 V to 3.0 V s
VSTOR = Keithley Sourcemeter configured to measure current
and voltage source set to hold the VSTOR voltage = 2.0 V, 3.0 V
or 5.5 V
Figure 2. Charger Efficiency vs Input Voltage
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100.00
100
90
90.00
IIN = 10 mA
70
60
50
40
80.00
Efficiency (%)
Efficiency (%)
80
70.00
60.00
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
30
20
VIN = 2 V
VSTOR = 2.2 V
VSTOR = 3.0 V
VSTOR = 5.5 V
50.00
40.00
0.01
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
0.1
Input Voltage (V)
VIN_DC = sourcemeter configured with ICOMP = 10 mA and
voltage source varied from 0.1 V to 3.0 V
VSTOR = sourcemeter configured to measure current and voltage
source set to hold the VSTOR voltage = 2.0 V, 3.0 V or 5.5 V
Figure 3. Charger Efficiency vs Input Voltage
80.00
80
Efficiency (%)
90
Efficiency (%)
90.00
VIN = 1 V
60.00
50.00
20.00
0.01
0.1
1
10
VIN = 0.5 V
70
60
50
40
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
30.00
VSTOR = 1.8 V
VSTOR = 3.0 V
VSTOR = 5.5 V
30
20
0.01
100
0.1
Input Current (mA)
90
1400
VIN = 0.2 V
Efficiency (%)
80
70
60
50
VSTOR = 3.0 V
VSTOR = 2.0 V
VSTOR = 5.5 V
20
1.0
10.0
100.0
TA
TA =
= 85C
85oC
TA
TA = 25C
25oC
1200
TA
TA = -40C
-40oC
1000
800
600
400
200
0
2
3
4
5
Input Voltage (V)
Input Current (mA)
VIN_DC = souremeter configured with voltage source = 0.2 V and
ICOMP varied from 0.01 mA to 100 mA
VSTOR = sourcemeter configured to measure current and voltage
source set to hold the VSTOR voltage = 2.0 V, 3.0 V or 5.5 V
Figure 7. Charger Efficiency vs Input Current
10
Input Quiescent Current (nA)
1600
0.1
100
Figure 6. Charger Efficiency vs Input Current
100
0.0
10
VIN_DC = sourcemeter configured with voltage source = 0.5 V
and ICOMP varied from 0.01 mA to 100 mA
VSTOR = sourcemeter configured to measure current and voltage
source set to hold the VSTOR voltage = 1.8 V, 3.0 V or 5.5 V
Figure 5. Charger Efficiency vs Input Current
30
1
Input Current (mA)
VIN_DC = sourcemeter configured with voltage source = 1.0 V
and ICOMP varied from 0.01 mA to 100 mA
VSTOR = sourcemeter configured to measure current and voltage
source set to hold the VSTOR voltage = 2.0 V, 3.0 V or 5.5 V
40
100
Figure 4. Charger Efficiency vs Input Current
100
40.00
10
VIN_DC = sourcemeter configured with voltage source = 2.0 V
and ICOMP varied from 0.01 mA to 100 mA
VSTOR = sourcemeter configured to measure current and voltage
source set to hold the VSTOR voltage = 2.2 V , 3.0 V or 5.5 V
100.00
70.00
1
Input Current (mA)
VIN_DC = floating and EN = VOUT_EN = GND
VSTOR = sourcemeter configured to measure current and voltage
source varied from 2.0 V or 5.5 V
Figure 8. VSTOR Quiescent Current vs VSTOR Voltage:
Standby Mode
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700
2000
o
TA =
85C
T
A = 85 C
TA =
T
A
1500
Input Quiescent Current (nA)
Input Quiescent Current (nA)
TA =
= 25C
o
T
A 25 C
oC
85C
85
oC
TA
-40C
T
A = -40
1000
500
600
T
25oC
TA
A = 25C
500
T
= -40C
-40oC
TA
A=
400
300
200
100
0
0
2
3
4
2
5
3
4
5
Input Voltage (V)
Input Voltage (V)
VIN_DC = floating and EN = GND and VOUT_EN=VSTOR
VSTOR= sourcemeter configured to measure current and voltage
source varied from 2.0 V or 5.5 V
Figure 9. VSTOR Quiescent Current vs VSTOR Voltage:
Active Mode
VIN_DC = floating and EN = VSTOR
VSTOR = sourcemeter configured to measure current and voltage
source varied from 2.0 V or 5.5 V
Figure 10. VBAT Quiescent Current vs VBAT Voltage: Ship
Mode
100
100
90
95
80
90
70
Efficiency (%)
Efficiency (%)
VOUT = 1.8V
VOUT = 1.8V, TA = 25oC
60
VSTOR = 2.1V
VSTOR = 3.6V
VSTOR = 5.5V
50
40
0.001
0.01
0.1
1
10
85
80
IOUT = 0.01mA
IOUT = 0.1mA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
75
70
2.0
100
3.0
4.0
5.0
Input Voltage (V)
Output Current (mA)
VSTOR = sourcemeter configured as a voltage source, measuring
current
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT)
VSTOR = sourcemeter configured as a voltage source, measuring
current
OUT = sourcemeter configured sink current with VCOMP>V(OUT)
Figure 12. Buck Efficiency vs Input Voltage
Figure 11. Buck Efficiency vs Output Current
1.02
1.004
VOUT = 1.8V
VOUT = 1.8V
1
IOUT = 0.001mA
IOUT = 0.1mA
IOUT = 10mA
0.998
IOUT = 0.01mA
IOUT = 1mA
IOUT = 90mA
0.996
Normalized VOUT
Normalized VOUT
1.002
1.01
1
0.99
0.994
VSTOR = 5.5V
VSTOR = 3.6V
0.992
2.0
3.0
4.0
5.0
0.98
0.001
VSTOR Voltage (V)
VSTOR = 2.1V
0.01
0.1
1
10
100
Output Current (mA)
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Figure 13. Normalized Buck Output Voltage vs Input Voltage
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Figure 14. Normalized Buck Output Voltage vs Output
Current
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1.02
VOUT = 1.8V
1.01
1
0.99
o
TA =
= 85C
T
A 85 C
VOUT = 1.8V - 100 mV
160
Output Current (mA)
Normalized VOUT
170
IOUT = 0.01mA
IOUT = 1mA
IOUT = 70mA
oC
TA
25C
T
A = 25
150
oC
T
TA
0C
A=0
140
o
T
TA
-40CC
A = -40
130
120
110
100
90
0.98
80
-40 -30 -20 -10
0
10
20
30
40
50
60
70
2
80
3
Temperature (oC)
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Thermal stream for temperature variation
Figure 16. Buck Maximum Output Current vs Input Voltage
120
VOUT = 1.8V
Major Switching Frequency (kHz)
Major Switching Frequency (kHz)
120
100
80
60
40
VSTOR= 2.1V
VSTOR = 3V
VSTOR = 4.2V
VSTOR = 5.5V
20
0
0
10
20
30
40
50
60
VOUT = 1.8V
100
80
IOUT
IOUT
IOUT
IOUT
60
= 0.5mA
= 5mA
= 100mA
= 50mA
40
20
0
70
80
90
100
2.1
2.6
3.1
Output Current (mA)
40
40
35
30
25
20
VOUT = 1.8V
15
10
VSTOR = 2.1V
VSTOR = 3V
VSTOR = 4.2V
VSTOR = 5.5V
5
0
30
40
50
60
70
80
90
100
Output Voltage Ripple (mV)
45
20
4.6
5.1
Figure 18. Buck Major Switching Frequency vs Input
Voltage
45
10
4.1
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Oscilloscope used to measure switching frequency at LBOOST
Figure 17. Buck Major Switching Frequency vs Output
Current
0
3.6
VSTOR Voltage (V)
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Oscilloscope used to measure switching frequency at LBOOST
Output Voltage Ripple (mV)
5
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to increasingly sink current with
VCOMP>V(OUT) until V(OUT) < VOUT - 100 mV
Thermal stream for temperature variation
Figure 15. Normalized Buck Output Voltage vs Temperature
VOUT = 1.8V
35
30
25
20
15
10
IOUT
IOUT
IOUT
IOUT
5
0
2.1
Output Current (mA)
2.6
3.1
3.6
4.1
= 0.5mA
= 5mA
= 50mA
= 100mA
4.6
5.1
VSTOR Voltage (V)
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Oscilloscope used to measure voltage ripple at OUT
Figure 19. Buck Output Voltage Ripple vs Output Current
12
4
VSTOR Voltage (V)
VSTOR = sourcemeter configured as a voltage source
OUT = sourcemeter configured to sink current with
VCOMP>V(OUT) and measuring voltage
Oscilloscope used to measure voltage ripple at OUT
Figure 20. Buck Output Voltage Ripple vs Input Voltage
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7 Detailed Description
7.1 Overview
The bq25570 device is a highly integrated energy harvesting Nano-Power management solution that is well
suited for meeting the special needs of ultra low-power applications. The product is specifically designed to
efficiently acquire and manage the microwatts (µW) to milliwatts (mW) of power generated from a variety of DC
sources like photovoltaic (solar) or thermal electric generators. targeted toward products and systems, such as
wireless sensor networks (WSN) which have stringent power and operational demands.
The main boost charger is powered from the boost output, VSTOR. Once the VSTOR voltage is above
VSTOR_CHGEN (1.8 V typical), for example, after a partially discharged battery is attached to VBAT, the boost
charger can effectively extract power from low voltage output harvesters such as TEGs or single or dual cell
solar panels outputting voltages down to VIN(DC) (100 mV minimum). When starting from VSTOR = VBAT < 100
mV, the cold start circuit needs at least VIN(CS), 600 mV typical, to charge VSTOR up to 1.8 V.
The bq25570 also implements a programmable maximum power point tracking sampling network to optimize the
transfer of power into the device. The fraction of open circuit voltage that is sampled and held can be controlled
by pulling VOC_SAMP high or low (80% or 50% respectively) or by using external resistors. This sampled
voltage is maintained via internal sampling circuitry and held with an external capacitor (CREF) on the
VREF_SAMP pin. For example, solar cells typically operate with a maximum power point (MPP) of 80% of their
open circuit voltage. Connecting VOC_SAMP to VSTOR sets the MPPT threshold to 80% and results in the IC
regulating the voltage on the solar cell to ensure that the VIN_DC voltage does not fail below the voltage on
CREF which equals 80% of the solar panel's open circuit voltage. Alternatively, an external reference voltage can
be provided by a MCU to produce a more complex MPPT algorithm.
The bq25570 is designed with the flexibility to support a variety of energy storage elements. The availability of
the sources from which harvesters extract their energy can often be sporadic or time-varying. Systems will
typically need some type of energy storage element, such as a re-chargeable battery, super capacitor, or
conventional capacitor. The storage element provides constant power to the system. The storage element also
allows the system to handle any peak currents that can not directly come from the input source. To prevent
damage to a customer’s storage element, both maximum and minimum voltages are monitored against the
internally set under-voltage (UV) and user programmable over-voltage (OV) levels.
To further assist users in the strict management of their energy budgets, the bq25570 toggles the battery good
(VBAT_OK) flag to signal an attached microprocessor when the voltage on an energy storage battery or
capacitor has dropped below a pre-set critical level. This should trigger the reduction of load currents to prevent
the system from entering an under voltage condition. There is also independent enable signals to allow the
system to control when to run the regulated output or even put the whole IC into an ultra-low quiescent current
sleep state.
In addition to the boost charging front end, the bq25570 provides the system with an externally programmable
regulated supply via the buck converter. The regulated output has been optimized to provide high efficiency
across low output currents (< 10 µA) to high currents (~110 mA).
All the capabilities of bq25570 are packed into a small foot-print 20-lead 3.5-mm x 3.5-mm QFN package (RGR).
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7.2 Functional Block Diagram
VSTOR
LBST
VBAT
LBUCK
PFM Buck
Controller
VOUT
VOUT_SET
PFM Boost Charger
Controller
VOUT_EN
VSS
VSS
Cold-start
Unit
VIN_DC
Enable
Enable
Interrupt
VBAT_OK
VOC_SAMP
OK_PROG
BAT_SAVE
+
VREF_SAMP
Battery Threshold
Control
OT
VREF
+
MPPT
Controller
OK
OK_HYST
UV
OV
Temp
Sensing
Element
+
+
Vref
Bias Reference &
Oscillator
VREF
VBAT_UV
EN
VBAT_OV
VRDIV
7.3 Feature Description
7.3.1 Maximum Power Point Tracking
Maximum power point tracking (MPPT) is implemented in order to maximize the power extracted from an energy
harvester source. The boost charger indirectly modulates the input impedance of the main boost charger by
regulating the charger's input voltage, as sensed by the VIN_DC pin, to the sampled reference voltage, as stored
on the VREF_SAMP pin. The MPPT circuit obtains a new reference voltage every 16 s (typical) by periodically
disabling the charger for 256 ms (typical) and sampling a fraction of the open-circuit voltage (VOC). For solar
harvesters, the maximum power point is typically 70%-80% and for thermoelectric harvesters, the MPPT is
typically 50%. Tying VOC_SAMP to VSTOR internally sets the MPPT regulation point to 80% of VOC. Tying
VOC_SAMP to GND internally sets the MPPT regulation point to 50% of VOC. If input source does not have
either 80% or 50% of VOC as its MPP point, the exact ratio for MPPT can be optimized to meet the needs of the
input source being used by connecting external resistors ROC1 and ROC2 between VRDIV and GND with midpoint at VOC_SAMP.
The reference voltage is set by the following expression:
æ
ö
R OC1
VREF_SAMP = VIN_DC(OpenCircuit) ç
÷
è R OC1 + R OC2 ø
14
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Feature Description (continued)
7.3.2 Battery Undervoltage Protection
To prevent rechargeable batteries from being deeply discharged and damaged, and to prevent completely
depleting charge from a capacitive storage element, the boost charger has an internally set undervoltage
(VBAT_UV) threshold plus an internal hysteresis voltage (VBAT_UV_HYST). The VBAT_UV threshold voltage
when the battery voltage is decreasing is internally set to 1.95V (typical). The undervoltage threshold when
battery voltage is increasing is given by VBAT_UV plus VBAT_UV_HYST. For the VBAT_UV feature to function
properly, the system load should be connected to the VSTOR pin while the storage element should be connected
to the VBAT pin. Once the VSTOR pin voltage goes above VBAT_UV plus VBAT_UV_HYST threshold, the
VSTOR pin and the VBAT pins are effectively shorted through an internal PMOS FET. The switch remains
closed until the VSTOR pin voltage falls below the VBAT_UV threshold. The VBAT_UV threshold should be
considered a fail safe to the system and the system load should be removed or reduced based on the VBAT_OK
threshold which should be set above the VBAT_UV threshold.
7.3.3 Battery Overvoltage Protection
To prevent rechargeable batteries from being exposed to excessive charging voltages and to prevent over
charging a capacitive storage element, the over-voltage (VBAT_OV) threshold level must be set using external
resistors. This is also the voltage value to which the charger will regulate the VSTOR/VBAT pin when the input
has sufficient power. The VBAT_OV threshold when the battery voltage is rising is given by Equation 2:
æ
ö
R
3
VBAT_OV = VBIAS ç 1 + OV2 ÷
2
R OV 1 ø
è
(2)
The sum of the resistors is recommended to be no higher than 13 MΩ that is, ROV1 + ROV2 = 13 MΩ.
Spreadsheet SLUC484 provides help on sizing and selecting the resistors. The overvoltage threshold when
battery voltage is decreasing is given by VBAT_OV minus VBAT_OV_HYST. Once the voltage at the battery
exceeds VBAT_OV threshold, the boost charger is disabled. The charger will start again once the battery voltage
drops by VBAT_OV_HYST. When there is excessive input energy, the VBAT pin voltage will ripple between the
VBAT_OV and the VBAT_OV_HYST levels.
CAUTION
If VIN_DC is higher than VSTOR and VSTOR is equal to VBAT_OV, the input VIN_DC
is pulled to ground through a small resistance to stop further charging of the attached
battery or capacitor. It is critical that if this case is expected, the impedance of the
source attached to VIN_DC be higher than 20 Ω and not a low impedance source.
7.3.4 Battery Voltage within Operating Range (VBAT_OK Output)
The charger allows the user to set a programmable voltage independent of the overvoltage and undervoltage
settings to indicate whether the VSTOR voltage (and therefore the VBAT voltage when the PFET between the
two pins is turned on) is at an acceptable level. When the battery voltage is decreasing the threshold is set by
Equation 3:
æ
ö
R
VBAT_OK_PROG = VBIAS ç 1 + O K2 ÷
R
OK1 ø
è
(3)
When the battery voltage is increasing, the threshold is set by Equation 4:
æ
R
+ R O K3 ö
VBAT_OK_HYST = VBIAS ç 1 + OK2
÷
R O K1
è
ø
(4)
The sum of the resistors is recommend to be no higher than approximately i.e., ROK1 + ROK2 + ROK3= 13 MΩ.
Spreadsheet SLUC484 provides help on sizing and selecting the resistors. The logic high level of this signal is
equal to the VSTOR voltage and the logic low level is ground. The logic high level has ~20 KΩ internally in series
to limit the available current in order to prevent MCU damage until the MCU is fully powered. The
VBAT_OK_PROG threshold must be greater than or equal to the UV threshold.
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Feature Description (continued)
7.3.5 Storage Element / Battery Management
In this section the battery management functionality of the bq25570 integrated circuit (IC) is presented. The IC
has internal circuitry to manage the voltage across the storage element and to optimize the charging of the
storage element. For successfully extracting energy from the source, two different threshold voltages must be
programmed using external resistors, namely battery good threshold (VBAT_OK) and over voltage (OV)
threshold. The two user programmable threshold voltages and the internally set undervoltage threshold
determine the IC's region of operation. Figure 21 shows the relative position of the various threshold voltages.
Charging stops to
prevent
overcharge
VSTOR(ABS MAX) = 5.5 V
VBAT_OV = resistor programmable
VBAT_OV + internal VBAT_OV_HYST
Signal to turn on
system load on
VSTOR
VBAT_OK_HYST = resistor programmable
VBAT_OK = resistor programmable
VBAT connected
to VSTOR to
allow charging
Charger resumes
charging
VBAT_UV + internal VBAT_UV_HYST
VBAT_UV = internal
Main Boost Charger on
(if VIN_DC > 100 mV)
VSTOR_CHGEN = 1.8 V typical
GND
Signal to turn off
system load on
VSTOR
VBAT disconnected
from VSTOR to
prevent overdischarge
Cold Start Circuit on
(if VIN_DC > 600 mV)
P(harvester) x Kbq255xx < P(load)
P(harvester) x Kbq255xx > P(load)
Increasing
VSTOR voltage
Decreasing
VSTOR voltage
Figure 21. Summary of VSTOR Threshold Voltages
7.3.6 Programming OUT Regulation Voltage
To set the proper output regulation voltage and input voltage power good comparator, the external resistors must
be carefully selected.
The OUT regulation voltage is then given by Equation 5:
æR
+ ROUT1 ö
VOUT = VBIAS ç OUT2
÷
ROUT1
è
ø
(5)
Note that VBIAS is nominally 1.21 V per the electrical specification table. The sum of the resistors is
recommended to be no greater than 13 MΩ , that is, ROUT1 + ROUT2 = 13 MΩ. Higher resistors may result in poor
output voltage regulation and/or input voltage power good threshold accuracies due to noise pickup via the high
impedance pins or reduction of effective resistance due to parasitic resistances created from board assembly
residue. See Layout Considerations section for more details. SLUC484 provides help on sizing and selecting the
resistors.
16
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Feature Description (continued)
7.3.7 Step Down (Buck) Converter
The buck regulator input power is internally connected to VSTOR and steps the VSTOR voltage down to a lower
regulated voltage at the OUT pin. It employs pulse frequency modulation (PFM) control to regulate the voltage
close to the desired reference voltage. The voltage regulated at the OUT pin is set by the user programmed
resistor divider. The current through the inductor is controlled through internal current sense circuitry. The peak
current in the inductor is controlled to maintain high efficiency of the converter across a wide input current range.
The converter delivers an output current up to 110mA typical with a peak inductor current of 200 mA. The buck
converter is disabled when the voltage on VSTOR drops below the VBAT_UV condition. The buck converter
continues to operate in pass (100% duty cycle) mode, passing the input voltage to the output, as long as VSTOR
is greater than VBAT_UV and less than VOUT.
7.3.8 Nano-Power Management and Efficiency
The high efficiency of the bq25570 charger is achieved through the proprietary Nano-Power management
circuitry and algorithm. This feature essentially samples and holds the VSTOR voltage to reduce the average
quiescent current. That is, the internal circuitry is only active for a short period of time and then off for the
remaining period of time at the lowest feasible duty cycle. A portion of this feature can be observed in Figure 28
where the VRDIV node is monitored. Here the VRDIV node provides a connection to the VSTOR voltage (first
pulse) and then generates the reference levels for the VBAT_OV and VBAT_OK resistor dividers for a short
period of time. The divided down values at each pin are compared against VBIAS as part of the hysteretic
control. Because this biases a resistor string, the current through these resistors is only active when the NanoPower management circuitry makes the connection—hence reducing the overall quiescent current due to the
resistors. This process repeats every 64 ms.
The efficiency of the bq25570 boost charger is shown for various input power levels in Figure 1 through
Figure 7. All efficiency data points were captured by averaging 50 measurements of the input current in between
MPPT sampling events. This must be done due to the pulsing currents of the hysteretic, discontinuous mode
boost and buck converters. Quiescent currents into VSTOR, VBAT_SEC and VBAT_PRI over temperature and
voltage are shown at Figure 8 through Figure 9.
7.4 Device Functional Modes
The bq25570 has five functional modes: cold start operation, main boost charger disabled (ship mode), main
boost charger enabled, buck converter enabled mode and thermal shutdown. When VSTOR is greater than
VSTOR_CHGEN (1.8 V typical), the bq25570's two enable pins allow for flexibility in controlling the system. The
table below summarizes the functionality.
Table 2. Enable Functionality Table when VSTOR > VSTOR_CHGEN
EN PIN
LOGIC
LEVEL
VOUT_EN
PIN LOGIC
LEVEL
0
0
Buck standby mode: boost charger and VBAT_OK are enabled. Buck converter is disabled.
0
1
Boost charger, buck converter and VBAT_OK enabled.
1
x
Ship mode (lowest leakage state): boost charger, PFET between VSTOR and VBAT is off, buck converter and
VBAT_OK indication are disabled.
FUNCTIONAL MODE
The EN high voltage is relative to the VBAT pin voltage. VOUT_EN high voltage is relative to VSTOR. If it is not
desired to control EN, it is recommended that this pin be tied to VSS, or system ground. When EN is low,
VOUT_EN is used to enable and disable the buck converter. The high-level Functional Block Diagram highlights
most of the major functional blocks inside the bq25570. The cold start circuitry is powered from VIN_DC. The
main boost charger circuitry is powered from VSTOR while the boost power stage is powered from VIN_DC.
Details of entering and exiting each mode are explained below.
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7.4.1 Main Boost Charger Disabled (Ship Mode) - (VSTOR > VSTOR_CHGEN and EN = HIGH)
When taken high relative to the voltage on VBAT_SEC, the EN pin shuts down the IC including the boost
charger, buck converter and battery management circuitry. It also turns off the PFET that connects VBAT_SEC
to VSTOR. This can be described as ship mode, because it will put the IC in the lowest leakage state and
provides a long storage period without significantly discharging the battery on VBAT. If there is no need to control
EN, it is recommended that this pin be tied to VSS, or system ground.
7.4.2 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS), EN = don't
care)
Whenever VSTOR < VSTOR_CHGEN, VIN_DC ≥ VIN(CS) and PIN > PIN(CS), the cold-start circuit is on. This
could happen when there is not input power at VIN_DC to prevent the load from discharging the battery or during
a large load transient on VSTOR. During cold start, the voltage at VIN_DC is clamped to VIN(CS) so the energy
harvester's output current is critical to providing sufficient cold start input power, PIN(CS) = VIN(CS) X IIN(CS).
The cold-start circuit is essentially an unregulated, hysteretic boost converter with lower efficiency compared to
the main boost charger. None of the other features, including the EN pin, function during cold start operation.
The cold start circuit's goal is to charge VSTOR higher than VSTOR_CHGEN so that the main boost charger can
operate. When a depleted storage element is initially attached to VBAT, as shown in Figure 22 and the harvester
can provide a voltage > VIN(CS) and total power at least > PIN(CS), assuming no system load or leakage at
VSTOR and VBAT, the cold start circuit can charge VSTOR above VSTOR_CHGEN. Once the VSTOR voltage
reaches the VSTOR_CHGEN threshold, the IC
1. first performs an initialization pulse on VRDIV to reset the feedback voltages,
2. then disables the charger for 32 ms (typical) to allow the VIN_DC voltage to rise to the harvester's opencircuit voltage which will be used as the input voltage regulation reference voltage until the next MPPT
sampling cycle and
3. lastly performs its first feedback sampling using VRDIV, approximately 64 ms after the initialization pulse.
Figure 22. Charger Operation After a Depleted Storage Element is Attached and Harvester Power is
Available
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The energy harvester must supply sufficient power for the IC to exit cold start. Due to the body diode of the
PFET connecting VSTOR and VBAT, the cold start circuit must charge both the capacitor on CSTOR up to the
VSTOR_CHGEN and the storage element connected to VBAT up to VSTOR_CHGEN less a diode drop. When a
rechargeable battery with an open protector is attached, the initial charge time is typically short due to the
minimum charge needed to close the battery's protector FETs. When large, discharged super capacitors with
high DC leakage currents are attached, the intial charge time can be significant.
When the VSTOR voltage reaches VSTOR_CHGEN, the main boost charger starts up. When the VSTOR
voltage rises to the VBAT_UV threshold, the PMOS switch between VSTOR and VBAT turns on, which provides
additional loading on VSTOR and could result in the VSTOR voltage dropping below both the VBAT_UV
threshold and the VSTOR_CHGEN voltage, especially if system loads on VSTOR or VBAT are active during this
time. Therefore, it is not uncommon for the VSTOR voltage waveform to have incremental pulses (for example,
stair steps) as the IC cycles between cold-start and main boost charger operation before eventually maintaing
VSTOR above VSTOR_CHGEN.
The cold start circuit initially clamps VIN_DC to VIN(CS) = 600 mV typical. If sufficient input power (that is, output
current from the harvester clamped to VIN(CS)) is not available, it is possible that the cold start circuit cannot
raise the VSTOR voltage above VSTOR_CHGEN in order for the main boost conveter to start up. It is highly
recommended to add an external PFET between the system load and VSTOR. An inverted VBAT_OK signal
provided by VB_SEC_ON can be used to drive the gate of this system-isolating, external PFET. See the Energy
Harvester Selection applications section for guidance on minimum input power requirements.
7.4.3 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN and EN = LOW )
One way to avoid cold start is to attach a partially charged storage element as shown in Figure 23.
Figure 23. Charger Operation after a Partially Charged Storage Element is Attached and Harvester Power
is Available
When no input source is attached, the VSTOR node should be discharged to ground before attaching a storage
element. Hot-plugging a storage element that is charged (for example, the battery protector PFET is closed) and
with the VSTOR node more than 100 mV above ground results in the PFET between VSTOR and VBAT
remaining off until an input source is attached.
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Assuming the voltages on VSTOR and VBAT are both below 100 mV, when a charged storage element is
attached (that is, hot-plugged) to VBAT, the IC
1. first turns on the internal PFET between the VSTOR and VBAT pins for tBAT_HOT_PLUG (45 ms) in order to
charge VSTOR to VSTOR_CHGEN then turns off the PFET to prevent the battery from overdischarge,
2. then performs an initialization pulse on VRDIV to reset the feedback voltages,
3. then disables the charger for 32 ms (typical) to allow the VIN_DC voltage to rise to the harvester's opencircuit voltage which will be used as the input voltage regulation reference voltage until the next MPPT
sampling cycle and
4. lastly performs its first feedback sampling using VRDIV, approximately 64 ms after the initialization pulse.
If the VSTOR pin voltage remains above the internal under voltage threshold (VBAT_UV) for the additional 64 ms
after the VRDIV initialization pulse (following the 45-ms PFET on time), the internal PFET turns back on and the
main boost charger begins to charge the storage element assuming there is sufficient power available from the
harvester at the VIN_DC pin. If VSTOR does not reach the VBAT_UV threshold, then the PFET remains off until
the main boost charger can raise the VSTOR voltage to VBAT_UV. If a system load tied to VSTOR discharges
VSTOR below VSTOR_GEN or below VBAT_UV during the 32 ms initial MPPT reference voltage measurement
or within 110 ms after hot plug, it is recommended to add an external PFET between the system load and
VSTOR. An inverted VBAT_OK signal provided by VB_SEC_ONcan be used to drive the gate of this systemisolating, external PFET. Otherwise, the VSTOR voltage waveform will have incremental pulses as the IC turns
on and off the internal PFET controlled by VBAT_UV or cycles between cold-start and main boost charger
operation.
Once VSTOR is above VSTOR_CHGEN but less than VBAT_V and VIN_DC > VIN(DC)-MIN = 100 mV, the main
boost charger extracts power from its source by employing pulse frequency modulation (PFM) mode of control to
regulate the voltage at VIN_DC close to the desired reference voltage. The reference voltage is set by the MPPT
circuitry as described in the features section. Input voltage regulation is obtained by transferring charge from the
input to VSTOR only when the input voltage is higher than the voltage on pin VREF_SAMP. The current through
the inductor is controlled through internal current sense circuitry. The peak current in the inductor is incremented
internally in three pre-determined levels (~50 mA, ~100 mA and finally I-CHG(CBC_LIM)) in order to maintain
high efficiency of the charger across a wide input current range. When in discontinous mode, the boost charger
can transfer up to a maximum of 100 mA average input current with I-CHG(CBC_LIM) = 230mA typical peak
inductor current. The boost charger is disabled when the voltage on VSTOR reaches the user set VBAT_OV
threshold to protect the battery connected at VBAT from overcharging. In order for the battery to charge to
VBAT_OV, the input power must exceed the power needed for the load on VSTOR. See the Energy Harvester
Selection applications section for guidance on minimum input power requirements.
Steady state operation for the boost charger is shown in Figure 23. These plots highlight the inductor current, the
VSTOR voltage ripple, input voltage regulation and the LBOOST switching node. The cycle-by-cycle minor
switching frequency is a function of each the converter's inductor value, peak current limit and voltage levels on
each side of each inductor. Once the VSTOR capacitor, CSTOR, droops below a minimum value, the hysteretic
switching repeats.
7.4.3.1 Buck Converter Enabled (VSTOR > VBAT_UV, EN = LOW and VOUT_EN = HIGH )
The bq25570 buck converter is hysteretic, peak current, discontinuous mode buck converter as summarized in
Step Down (Buck) Converter. It has two startup responses: 1) from the ship-mode state (EN transitions from high
to low with VOUT_EN already high), and 2) from the standby state (VOUT_EN transitions from low to high). The
startup response out of ship-mode has the longest time duration due to the internal circuitry being disabled. This
response is shown in Figure 35. The startup time takes approximately 100 ms due to the internal Nano-Power
management circuitry needing to first complete the 64 ms sample and hold cycle.
Startup from the standby state is shown in Figure 37. This response is much faster due to the internal circuitry
being pre-enabled. The startup time from this state is entirely dependent on the size of the output capacitor. The
larger the capacitor, the longer it will take to charge during startup. With COUT = 22 µF, the startup time is
approximately 400 µs. The buck converter can startup into a pre-biased output voltage.
The buck converter is disabled when the voltage on VSTOR drops below the VBAT_UV condition. The buck
converter continues to operate in pass (100% duty cycle) mode, passing the input voltage to the output, as long
as VSTOR is greater than VBAT_UV and less than VOUT.
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7.4.4 Thermal Shutdown
Rechargeable Li-ion batteries need protection from damage due to operation at elevated temperatures. The
application should provide this battery protection and ensure that the ambient temperature is never elevated
greater than the expected operational range of 85°C.
The bq25570 uses an integrated temperature sensor to monitor the junction temperature of the device. Once the
temperature threshold is exceeded, the boost charger and buck converter are disabled. Once the temperature of
the device drops below this threshold, the boost charger and buck converter resume operation. To avoid
unstable operation near the overtemperature threshold, a built-in hysteresis of approximately 5°C has been
implemented. Care should be taken to not over discharge the battery in this condition since the boost charger is
disabled. However, if the supply voltage drops to the VBAT_UV setting, the switch between VBAT and VSTOR
will open and protect the battery even if the device is in thermal shutdown.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Energy Harvester Selection
The energy harvesting source (for example, solar panel, TEG, vibration element) must provide a minimum level
of power for the IC to operate as designed. The IC's minimum input power required to exit cold start can be
estimated as
(
)
I - STR _ ELM _ LEAK @1.8V ´ 1.8V +
PIN > PIN(CS) = VIN(CS) ´ IIN(CS) >
(1.8V )2
RSTOR(CS)
0.05
(6)
where I-STR_ELM_LEAK@1.8V is the storage element leakage current at 1.8 V and
RSTOR(CS) is the equivalent resitive load on VSTOR during cold start and 0.05 is an estimate of the worst case
efficiency of the cold start circuit.
Once the IC is out of cold start and the system load has been activated (for example, using the VBAT_OK
signal), the energy harvesting element must provide the main boost charger with at least enough power to meet
the average system load. Assuming RSTOR(AVG) represents the average resistive load on VSTOR, the
simplified equation below gives an estimate of the IC's minimum input power needed during system operation:
PIN ´ hEST > PLOAD =
(VBAT _ OV )2
RSTOR(AVG)
+ VBAT _ OV ´ I - STR _ ELM _ LEAK @ VBAT _ OV
(7)
where ηEST can be derived from the datasheet efficiency curves for the given input voltage and current and
VBAT_OV. The simplified equation above assumes that, while the harvester is still providing power, the system
goes into low power or sleep mode long enough to charge the storage element so that it can power the system
when the harvester eventually is down. Refer to SLUC461 for a design example that sizes the energy harvester.
8.1.2 Storage Element Selection
In order for the charge management circuitry to protect the storage element from over-charging or discharging,
the storage element must be connected to VBAT pin and the system load tied to the VSTOR pin. Many types of
elements can be used, such as capacitors, super capacitors or various battery chemistries. A storage element
with 100 µF equivalent capacitance is required to filter the pulse currents of the PFM switching charger. The
equivalent capacitance of a battery can be computed as computed as
2 ´ mAHrBAT(CHRGD) ´ 3600 s / Hr
CEQ =
VBAT(CHRGD)
(8)
In order for the storage element to be able to charge VSTOR capacitor (CSTOR) within the tVB_HOT_PLUG (50 ms
typical) window at hot-plug; therefore preventing the IC from entering cold start, the time constant created by the
storage element's series resistance (plus the resistance of the internal PFET switch) and equivalent capacitance
must be less than tVB_HOT_PLUG . For example, a battery's resistance can be computed as:
RBAT = VBAT / IBAT(CONTINUOUS) from the battery specifications.
(9)
The storage element must be sized large enough to provide all of the system load during periods when the
harvester is no longer providing power. The harvester is expected to provide at least enough power to fully
charge the storage element while the system is in low power or sleep mode. Assuming no load on VSTOR (i.e.,
the system is in low power or sleep mode), the following equation estimates charge time from voltage VBAT1 to
VBAT2 for given input power is:
PIN × ηEST × tCHRG = 1/2 × CEQ × (VBAT22 - VBAT12)
22
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Application Information (continued)
Refer to SLUC461 for a design example that sizes the storage element.
Note that if there are large load transients or the storage element has significant impedance then it may be
necessary to increase the CSTOR capacitor from the 4.7 µF minimum or add additional capacitance to VBAT in
order to prevent a droop in the VSTOR voltage. Refer to Inductor Selection for sizing capacitors.
8.1.3 Inductor Selection
The boost charger and the buck converter each need an appropriately sized inductor for proper operation. The
inductor's saturation current should be at least 25% higher than the expected peak inductor currents
recommended below if system load transients on VSTOR and/or VOUT are expected. Since this device uses
hysteretic control for both the boost charger and buck converter, both are considered naturally stable systems
(single order transfer function).
8.1.3.1 Boost Charger Inductor Selection
For the boost charger to operate properly, an inductor of appropriate value must be connected between
LBOOST, pin 20, and VIN_DC, pin 2. The boost charger internal control circuitry is designed to control the
switching behavior with a nominal inductance of 22 µH ± 20%. The inductor must have a peak current capability
of > 300 mA with a low series resistance (DCR) to maintain high efficiency.
A list of inductors recommended for this device is shown in Table 3.
Table 3. Boost Charger Inductor Selection
INDUCTANCE (µH)
DIMENSIONS (mm)
PART NUMBER
MANUFACTURER
22
4.0x4.0x1.7
LPS4018-223M
Coilcraft
22
3.8x3.8x1.65
744031220
Wuerth
8.1.3.2 Buck Converter Inductor Selection
For buck converter to operate properly, an inductor of appropriate value must be connected between LBUCK, pin
16, and VOUT, pin 14. The buck converter internal control circuitry is designed to control the switching behavior
with a nominal inductance of 10 µH ± 20%. The inductor must have a peak current capability of > 200 mA with a
low series resistance (DCR) to maintain high efficiency. The speed of the peak current detect circuit sets the
inductor's lower bound to 4.7 µH. When using a 4.7 µH, the peak inductor current will increase when compared
to that of a 10 µH inductor, resulting in slightly higher major frequency.
A list of inductors recommended for this device is shown in Table 4.
Table 4. Buck Converter Inductor Selection
INDUCTANCE (µH)
DIMENSIONS (mm)
PART NUMBER
10
2.0 x 2.5 x 1.2
DFE252012C-H-100M
MANUFACTURER
Toko
10
4.0x4.0x1.7
LPS4018-103M
Coilcraft
10
2.8x2.8x1.35
744029100
Wuerth
10
3.0x3.0x1.5
74438335100
Wuerth
10
2.5x2.0x1.2
74479889310
Wuerth
4.7
2.0 x 2.5 x 1.2
DFE252012R-H-4R7M
Toko
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8.1.4 Capacitor Selection
In general, all the capacitors need to be low leakage. Any leakage the capacitors have will reduce efficiency,
increase the quiescent current and diminish the effectiveness of the IC for energy harvesting.
8.1.4.1 VREF_SAMP Capacitance
The MPPT operation depends on the sampled value of the open circuit voltage and the input regulation follows
the voltage stored on the CREF capacitor. This capacitor is sensitive to leakage since the holding period is
around 16 seconds. As the capacitor voltage drops due to any leakage, the input regulation voltage also drops
preventing proper operation from extraction the maximum power from the input source. Therefore, it is
recommended that the capacitor be an X7R or COG low leakage capacitor.
8.1.4.2 VIN_DC Capacitance
Energy from the energy harvester input source is initially stored on a capacitor, CIN, connected to VIN_DC, pin
2, and VSS, pin 1. For energy harvesters which have a source impedance which is dominated by a capacitive
behavior, the value of the harvester capacitor should scaled according to the value of the output capacitance of
the energy source, but a minimum value of 4.7 µF is recommended.
8.1.4.3 VSTOR Capacitance
Operation of the bq25570 requires two capacitors to be connected between VSTOR, pin 19, and VSS, pin 1. A
high frequency bypass capacitor of at 0.01 µF should be placed as close as possible between VSTOR and VSS.
In addition, a low ESR capacitor of at least 4.7 µF should be connected in parallel.
8.1.4.4 VOUT Capacitance
The output capacitor is chosen based on transient response behavior and ripple magnitude. The lower the
capacitor value, the larger the ripple will become and the larger the droop will be in the case of a transient
response. It is recommended to use at least a 22 µF output capacitor between VOUT, pin 14 and VSS, pin 15,
for most applications.
8.1.4.5 Additional Capacitance on VSTOR or VBAT
If there are large, fast system load transients and/or the storage element has high resistance, then the CSTOR
capacitors may momentarily discharge below the VBAT_UV threshold in response to the transient. This causes
the bq25570 to turn off the PFET switch between VSTOR and VBAT and turn on the boost charger. The CSTOR
capacitors may further discharge below the VSTOR_CHGEN threshold and cause the bq25570 to enter Cold
Start. For instance, some Li-ion batteries or thin-film batteries may not have the current capacity to meet the
surge current requirements of an attached low power radio. To prevent VSTOR from drooping, either increasing
the CSTOR capacitance or adding additional capacitance in parallel with the storage element is recommended.
For example, if boost charger is configured to charge the storage element to 4.2 V and a 500 mA load transient
of 50 µs duration infrequently occurs, then, solving I = C x dv/dt for CSTOR gives :
500 mA ´ 50 ms
CSTOR ³
= 10.5 mF
(4.2 V - 1.8 V)
(11)
Note that increasing CSTOR is the recommended solution but will cause the boost charger to operate in the less
efficient cold start mode for a longer period at startup compared to using CSTOR = 4.7 µF. If longer cold start run
times are not acceptable, then place the additional capacitance in parallel with the storage element.
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8.2 Typical Applications
8.2.1 Solar Application Circuit
CSTOR
VOC_SAMP
L1
CIN
+
VSTOR
BAT
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
+
VSS
VIN_DC
COUT
Buck
Controller
MPPT
System
Load
VSS
Cold Start
VBAT
GPIO2
VOUT_EN
GPIO3
VBAT_OK
ROV2
VBAT_OV
EN
VRDIV
GPIO1
OK_HYST
Nano-Power
Management
Host
OK_PROG
VSTOR
L2
VOUT
CREF
-
ROK3
VOUT_SET
Solar
Cell
CBYP
bq25570
ROUT2
ROK2
ROV1
ROUT1
ROK1
Figure 24. Typical Solar Application Circuit
8.2.1.1 Design Requirements
The desired voltage levels are VBAT_OV = 4.2 V, VBAT_OK = 2.39 V, VBAT_OK_HYST = 2.80 V and MPP
(VOC) = 80% which is typical for solar panels. A 1.8-V, up to 100-mA power rail is also needed. There are no
large load transients expected on either rail.
8.2.1.2 Detailed Design Procedure
The recommended L1 = 22 µH with ISAT ≥ I-CHG(CBC_LIM)MAX, L2 = 10 µH with ISAT ≥ I-BUCK(CBC_LIM)MAX,
CBYP = 0.01 µF and low leakage CREF = 10 nF are selected. In order to ensure the fastest recovery of the
harvester output voltage to the MPPT level following power extraction, the minimum recommended CIN = 4.7 µF
is selected. Because no large system load transients are expected and to ensure fast charge time during cold
start, the minimum recommended CSTOR = 4.7 µF.
No MPPT resistors are required because VOC_SAMP can be tied to VSTOR to give 80% MPPT.
• Keeing in mind VBAT_UV < VBAT_OV ≤ 5.5 V, to size the VBAT_OV resistors, first choose RSUMOV = ROV1
+ ROV2 = 13 MΩ then solve Equation 2 for
3 RSUMOV ´ VBIAS 3 13 MW ´ 1.21 V
ROV1 = ´
´
= 5.61 MW ® 5.62 MW closest 1% value then
2
VBAT _ OV
2
4.2 V
(12)
• ROV2 = RSUMOV - ROV1 = 13 MΩ - 5.62 MΩ = 7.38 MΩ → 7.32 MΩ resulting in VBAT_OV = 4.18V due to
rounding to the nearest 1% resistor.
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Typical Applications (continued)
•
•
•
•
Keeping in mind VBAT_OV ≥ VBAT_OK_HYST > VBAT_OK ≥ VBAT_UV, to size the VBAT_OK and
VBAT_OK_HYST resistors, first choose RSUMOK = ROK1 + ROK2 + ROK3 = 13 MΩ then solve Equation 3 and
Equation 4 for
VBIAS ´ RSUMOK
æ 1.21 V ö
ROK1 =
=ç
´ 13 MW = 5.62 MW then
VBAT _ OK _ HYST è 2.8 V ÷ø
(13)
æ VBAT _ OK
ö
æ 2.39 V
ö
ROK2 = ç
- 1÷ ´ ROK1 = ç
- 1÷ ´ 5.62 MW = 5.479 MW ® 5.49 MW, then
V
VBIAS
1.21
è
ø
è
ø
(14)
ROK3 = RSUMOK - ROK1 - ROK2 = 13 MΩ - 5.62 MΩ - 5.479 MΩ = 1.904 MΩ → 1.87 MΩ to give VBAT_OK =
2.39 V and VBAT_OK_HYST = 2.80 V.
For VOUT, first choose ROUT1 + ROUT2 = RSUMOUT = 13 MΩ, then solve Equation 5 for ROUT1 = VBIAS /
VOUT x RSUMOUT = 1.21 V / 1.8 V x 13 MΩ = 8.74 MΩ → 8.66 MΩ after rounding to nearest 1% value.
ROUT2 = RSUM - ROUT1 = 13 MΩ - 8.66 MΩ = 4.34 MΩ → 4.22 MΩ after rounding.
SLUC484 provides help on sizing and selecting the resistors.
8.2.1.3 Application Curves
Sourcemeter with VSOURCE = 1.0 V and compliance of 8.5 mA
subsequently applied to VIN_DC
VBAT = 0.1 F capacitor charged to 2.0 V
Resistance on VSTOR = 100 kΩ
Figure 25. Startup by Battery Attach With Almost Depleted
Storage Element
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance
of 43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance
of 1 A
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance of
1A
IL = inductor current
Figure 26. Boost Charger Operational Waveforms
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 3.6 V and compliance
of 1 A
Figure 28. VRDIV Waveform
Figure 27. MPPT Operation
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Typical Applications (continued)
VIN_DC = 1.5 V with 75 Ω series resistance
No storage element on VBAT or VBAT_PRI
VSTOR artifically ramped from 0 V to 4.2 V to 0 V using a power
amp driven by a function generator
VIN_DC = 1.5 V with 75 Ω series resistance
VBAT = 4.2 V charged 0.5 F capacitor
R(VSTOR) = open to 84 Ω to open
Figure 29. VBAT_OK Operation
Figure 30. 50 mA Load Transient on VSTOR
VIN_DC = 1.5 V with 75 Ω series resistance
VBAT = 4.2 V charged 0.5 F capacitor
R(VSTOR) = open to 84 Ω to open
VIN_DC = source meter with 1.2 V compliance and ISC = 1.0
mA
120 mF super capacitor on VBAT
Figure 31. 50 mA Load Transient on VSTOR - Zoom Out
Figure 32. Charging a Super Capacitor on VBAT
VIN_DC = source meter with 1.2 V compliance and ISC = 1.0 mA
120 mF super capacitor on VOUT with VOUT regulation voltage changed to 4.2 V.
Figure 33. Charging a Super Capacitor on VOUT
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Typical Applications (continued)
8.2.2 TEG Application Circuit
CBYP
CSTOR
VOC_SAMP
L1
CIN
+
VSTOR
BAT
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
TEG
VOUT
CREF
VSS
Buck
Controller
MPPT
VIN_DC
VSTOR
L2
System
Load
COUT
VSS
Cold Start
VBAT
GPIO3
VBAT_OK
ROV2
VOUT_SET
VOUT_EN
OK_HYST
GPIO2
VBAT_OV
EN
VRDIV
GPIO1
OK_PROG
Nano-Power
Management
Host
ROK3
bq25570
ROUT2
ROK2
ROUT1
ROV1
ROK1
Figure 34. Typical TEG Application Circuit
8.2.2.1 Design Requirements
The desired voltage levels are VBAT_OV = 5.0 V, VBAT_OK = 3.5 V, VBAT_OK_HYST = 3.7 V and MPP (V OC)
= 50% which is typical for TEG harvesters. A 1.8-V, up to 100-mA power rail is also needed. There are no large
load transients expected on either rail.
8.2.2.2 Detailed Design Procedure
The recommended L1 = 22 µH with ISAT ≥ I-CHG(CBC_LIM)MAX, L2 = 10 µH with ISAT ≥ I-BUCK(CBC_LIM)MAX,
CBYP = 0.01 µF and low leakage CREF = 10 nF are selected. In order to ensure the fastest recovery of the
harvester output voltage to the MPPT level following power extraction, the minimum recommended CIN = 4.7 µF
is selected. Because no large system load transients are expected and to ensure fast charge time during cold
start, the minimum recommended CSTOR = 4.7 µF.
No MPPT resistors are required because VOC_SAMP can be tied to GND to give 50% MPPT.
Referring back to the procedure in Detailed Design Procedure or using the spreadsheet calculator at SLUC484
gives the following values:
• ROV1 = 4.75 MΩ, ROV2 = 8.25 MΩ resulting in VBAT_OV = 4.97 V due to rounding to the nearest 1% resistor.
• ROK1 = 4.22 MΩ, ROK2 = 8.06 MΩ, ROK3 = 0.698 MΩ resulting in VBAT_OK = 3.5 V and VBAT_OK_HYST =
3.7 V after rounding.
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Typical Applications (continued)
•
ROUT1 = 8.66 MΩ and ROUT2 = 4.22 MΩ resulting in VOUT = 1.8V.
8.2.2.3 Application Curves
VIN_DC = 1.0 V power supply 100Ω series resistance
VBAT = 3.4-V charged Li coin cell
Figure 35. Startup by Taking EN Low (From Ship Mode)
VIN_DC = 2.0 V power supply 100Ω series resistance
VBAT = 3.1-V charged Li coin cell
Figure 37. Startup by taking VOUT_EN high (from Standby
mode)
VIN_DC = 1.0 V power supply 100Ω series resistance
VBAT = 3.4-V charged Li coin cell
Figure 36. Startup by taking EN low (from Ship mode),
including VOUT
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance of 1
A
Figure 38. Boost Charger Operational Waveforms
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Typical Applications (continued)
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance
of 1 A
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 4.0 V and compliance
of 1 A
Figure 39. MPPT Operation
Figure 40. VRDIV Waveform
VIN_DC floating
No storage element on VBAT or VBAT_PRI
VSTOR artifically ramped from 0 V to 5.0 V to 0 V using a function generator
Figure 41. VBAT_OK Operation
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Typical Applications (continued)
8.2.3 Piezoelectric Application Circuit
CSTOR
ROC2
VOC_SAMP
L1
CIN
Vibration
Element
CBYP
+
BAT
ROC1
VSTOR
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
VOUT
CREF
VSS
Buck
Controller
MPPT
VIN_DC
VSTOR
L2
System
Load
COUT
VSS
Cold Start
VBAT
Nano-Power
Management
GPIO1
ROV2
ROK3
VOUT_SET
VBAT_OK
OK_HYST
GPIO3
OK_PROG
VOUT_EN
VBAT_OV
Host GPIO2
VRDIV
EN
bq25570
ROUT2
ROK2
ROUT1
ROV1
ROK1
Figure 42. Typical Externally Set MPPT Application Circuit
8.2.3.1 Design Requirements
The desired voltage levels are VBAT_OV = 3.30 V, VBAT_OK = 2.80 V, VBAT_OK_HYST = 3.10 V, and MPP
(VOC) = 40% for the selected piezoelectric harvester which provides a rectified VOC = 1 V. A 1.8-V, up to 100-mA
power rail is also needed. There are no large load transients expected on either rail.
8.2.3.2 Detailed Design Procedure
The recommended L1 = 22 µH, CBYP = 0.01 µF and low leakage CREF = 10 nF are selected. The rectifier
diodes are Panasonic DB3X316F0L. In order to ensure the fastest recovery of the harvester output voltage to the
MPPT level following power extraction, the minimum recommended CIN = 4.7 µF is selected. Because no large
system load transients are expected and to ensure fast charge time during cold start, the minimum
recommended CSTOR = 4.7 µF.
• Keeping in mind that VREF_SAMP stores the MPP voltage for the harvester, first choose RSUMOC = ROC1 +
ROC2 = 20 MΩ then solve Equation 1 for
•
•
æ VREF _ SAMP ö
0.14
´ 20 MW = 8 MW ® 8.06 MW closest 1% resistor, then
ROC1 = ç
÷ ´ RSUMOC =
1V
è VIN _ DC(OC) ø
(15)
ROC2 = RSUMOC x (1 - VREF_SAMP / VIN_DC(OC) = 20 MΩ x (1 - 0.4 V / 1 V ) = 12 MΩ → series 10 MΩ
and
2 MΩ easy to obtain 1% resistors.
Referring back to the procedure in Detailed Design Procedure or using using the spreadsheet calculator at
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Typical Applications (continued)
•
•
SLUC484 gives the following values
– ROV1 = 7.15 MΩ, ROV2 = 5.90 MΩ resulting in VBAT_OV = 3.31V due to rounding to the nearest 1%
resistor.
ROK1 = 4.99 MΩ, ROK2 = 6.65 MΩ, ROK3 = 1.24 MΩ resulting in VBAT_OK = 2.82 V and VBAT_OK_HYST =
3.12 V after rounding to the nearest 1% resistor value.
ROUT1 = 8.66 MΩ and ROUT2 = 4.22 MΩ resulting in VOUT = 1.8V.
8.2.3.3 Application Curves
Sourcemeter with VSOURCE = 1.0 V and compliance of 8.5 mA
subsequently applied to VIN_DC
VBAT = 0.1 F capacitor charged to 2.2 V
Resistance on VSTOR = 100 kΩ
Figure 43. Startup by Battery Attach With Partially
Charged Storage Element
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance
of 43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance
of 1 A
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance of
1A
Figure 44. Boost Charger Operational Waveforms
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of
43 mA
VBAT = sourcemeter with VSOURCE = 3.0 V and compliance of 1
A
Figure 46. VRDIV Waveform
Figure 45. MPPT Operation
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Typical Applications (continued)
VIN_DC floating
No storage element on VBAT or VBAT_PRI
VSTOR artifically ramped from 0 V to 3.3 V to 0 V using a function generator
Figure 47. VBAT_OK Operation
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9 Power Supply Recommendations
See Energy Harvester Selection and Storage Element Selection for guidance on sizing the energy harvester and
storage elements for the system load.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the PCB layout is an important step in the design, especially at high peak
currents and high switching frequencies. If the layout is not carefully done, the boost charger and buck converter
could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current
path and for the power ground paths. The input and output capacitors as well as the inductors should be placed
as close as possible to the IC. For the boost charger, first priority are the output capacitors, including the 0.1uF
bypass capacitor (CBYP), followed by CSTOR, which should be placed as close as possible between VSTOR,
pin 19, and VSS, pin 1. Next, the input capacitor, CIN, should be placed as close as possible between VIN_DC,
pin 2, and VSS, pin 1. Last in priority is the boost charger's inductor, L1, which should be placed close to
LBOOST, pin 20, and VIN_DC, pin 2. For the buck converter, the output capacitor COUT should be placed as
close as possible between VOUT, pin 14, and VSS, pin 15. The buck converter inductor (L2) should be placed as
close as possible beween the switching node LBUCK, pin 16, and VOUT, pin 14. It is best to use vias and
bottom traces for connecting the inductors to their respective pins instead of the capacitors.
To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, OK_PROG, OK_HYST,
VOUT_SET), the external resistors should be placed so that the traces connecting the midpoints of each divider
to their respective pins are as short as possible. When laying out the non-power ground return paths (for
example, from resistors and CREF), it is recommended to use short traces as well, separated from the power
ground traces and connected to VSS pin 15. This avoids ground shift problems, which can occur due to
superimposition of power ground current and control ground current. The PowerPAD should not be used as a
power ground return path.
The remaining pins are either NC pins, that should be connected to the PowerPAD as shown below, or digital
signals with minimal layout restrictions. See the EVM user's guide for an example layout (SLUUAA7).
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 MΩ is recommended. In
addition, the sample and hold circuit output capacitor on VREF_SAMP must hold the voltage for 16s. During
board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that
may form parasitic resistors across the physical resistors/capacitors and/or from one end of a resistor/capacitor
to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold
levels changing significantly from those expected per the installed components. Therefore, it is highly
recommended that no ground planes be poured near the voltage setting resistors or the sample and hold
capacitor. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and
then rinsed with de-ionized water until the ionic contamination of that water is well above 50 MOhm. If this is not
feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X below the
measured ionic contamination.
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10.2 Layout Example
To secondary
battery
TOP
GND
TOP
VIN
EN signal
VBAT_OK signal
BOT
GND
EN signal
VOUT_EN
signal
Figure 48. Layout Schematic
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10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power-dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
For more details on how to use the thermal parameters in the Thermal Table, check the Thermal Characteristics
Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• EVM User's Guide, SLUUAA7
• Thermal Characteristics Application Note, SZZA017
• IC Package Thermal Metrics Application Note, SPRA953
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ25570RGRR
ACTIVE
VQFN
RGR
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQ570
BQ25570RGRT
ACTIVE
VQFN
RGR
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQ570
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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