BQ25723
SLUSE64 – MAY 2021
BQ25723 I2C 1- to 4-Cell Narrow VDC Buck-Boost Battery Charge Controller With
System Power Monitor and Processor Hot Monitor
1 Features
•
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
Standard notebook PC,Chromebook
Tablet (multimedia), wireless speaker
Ultrasound scanner, ventilators
3 Description
The BQ25723 is a synchronous NVDC buck-boost
battery charge controller to charge a 1- to 4-cell
battery from a wide range of input sources including
USB adapter, high voltage USB-C Power Delivery
(PD) sources, and traditional adapters.
Device Information
PACKAGE(1)
PART NUMBER
BQ25723
(1)
WQFN (32)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VSYS
Q1
VBUS
3.5V-24V
Q2
Q3
HIDRV1 LODRV1 SW1
SW2
LODRV2
ACP
HIDRV2
SYS
VBUS
ACN
Q4
BQ25723
/BATDRV
SRP
SRN
CHRG_OK, PSYS
IBAT, IADPT
/PROCHOT
•
•
IIN/VIN, VBAT/ ICHG,IOTG/
VOTG
•
Pin-to-pin compatible to BQ25713
Buck-boost narrow voltage DC (NVDC) charger for
USB-C Power Delivery (PD) interface platform
– 3.5-V to 26-V input range to charge 1- to 4-cell
battery
– Charge current up to 16.2 A/8.1 A with 128mA/64-mA resolution based on 5-mΩ/10-mΩ
sensing resistor
– Input current limit up to 10 A/6.35 A with 100mA/50-mA resolution based on 5-mΩ/10-mΩ
sensing resistor
– Support USB 2.0, USB 3.0, USB 3.1 and USB
Power Delivery (PD)
– Input Current Optimizer (ICO) to extract max
input power without overloading the adapter
– Integrated Fast Role Swap (FRS) feature
following USB-PD specification
– Seamless transition between buck, buck-boost,
and boost operations
– Input current and voltage regulation (IINDPM
and VINDPM) against source overload
TI patented switching frequency dithering pattern
for EMI noise reduction
TI patented Pass Through Mode (PTM) for system
power efficiency improvement and battery fast
charging achieving 99% efficiency.
IMVP8/IMVP9 compliant system features for Intel
platform
– Enhanced Vmin Active Protection (VAP) mode
supplements battery from input capacitors
during system peak power spike following latest
Intel specification
– Comprehensive PROCHOT profile
– Two level discharge current limit PROCHOT
profile to avoid battery wire-out
– System power monitor
Input and battery current monitor through
dedicated pins
Integrated 8-bit ADC to monitor voltage, current
and power
Battery MOSFET ideal diode operation in
supplement mode to support system when adapter
is fully loaded
Power up USB port from battery (USB OTG)
– 3-V to 24-V OTG with 8-mV resolution
– Output current limit up to 12.7 A/6.35 A with
100-mA/50-mA resolution based on 5-mΩ/10mΩ sensing resistor
800-kHz/1.2-MHz programmable switching
frequency with 2.2-µH/1.0-µH inductor
I2C host control interface for flexible system
configuration
High accuracy for the regulation and monitor
– ±0.5% Charge voltage regulation
– ±3% Charge current regulation
– ±2.5% Input current regulation
– ±2% Input/charge current monitor
Safety
– Thermal shutdown
– Input, system, battery overvoltage protection
– Input, MOSFET, inductor overcurrent protection
Package: 32-Pin 4.0 mm × 4.0 mm WQFN
Host (I2C)
Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BATT
(1S-4S)
BQ25723
www.ti.com
SLUSE64 – MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 8
8.1 Absolute Maximum Ratings........................................ 8
8.2 ESD Ratings............................................................... 8
8.3 Recommended Operating Conditions.........................8
8.4 Thermal Information....................................................9
8.5 Electrical Characteristics.............................................9
8.6 Timing Requirements................................................ 20
8.7 Typical Characteristics.............................................. 21
9 Detailed Description......................................................24
9.1 Overview................................................................... 24
9.2 Functional Block Diagram......................................... 25
9.3 Feature Description...................................................26
9.4 Device Functional Modes..........................................37
9.5 Programming............................................................ 38
9.6 Register Map.............................................................43
10 Application and Implementation................................ 86
10.1 Application Information........................................... 86
10.2 Typical Application.................................................. 86
11 Power Supply Recommendations..............................96
12 Layout...........................................................................97
12.1 Layout Guidelines................................................... 97
12.2 Layout Example...................................................... 98
13 Device and Documentation Support........................100
13.1 Device Support..................................................... 100
13.2 Documentation Support........................................ 100
13.3 Receiving Notification of Documentation Updates100
13.4 Support Resources............................................... 100
13.5 Trademarks........................................................... 100
13.6 Electrostatic Discharge Caution............................100
13.7 Glossary................................................................100
14 Mechanical, Packaging, and Orderable
Information.................................................................. 101
4 Revision History
2
DATE
REVISION
NOTES
May 2021
*
Initial release.
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5 Description (continued)
The NVDC configuration allows the system to be regulated based on battery voltage, but not drop below system
minimum voltage. The system keeps operating even when the battery is completely discharged or removed.
When load power exceeds input source rating, the battery goes into supplement mode and prevents the system
from crashing.
During power up, the charger sets the converter to a buck, boost, or buck-boost configuration based on the input
source and battery conditions. The charger seamlessly transitions between the buck, boost, and buck-boost
operation modes without host control.
In the absence of an input source, the BQ25723 supports the USB On-the-Go (OTG) function from a 1- to 4-cell
battery to generate an adjustable 3-V to 24-V output on VBUS with 8-mV resolution. The OTG output voltage
transition slew rate can be configured to comply with the USB-PD 3.0 PPS specification.
When only a battery powers the system and no external load is connected to the USB OTG port, the BQ25723
implements the latest Intel Vmin Active Protection (VAP) feature, in which the device charges up the VBUS
voltage from the battery to store some energy in the input decoupling capacitors. During a system peak power
spike, the energy stored in the input capacitors supplements the system, to prevent the system voltage from
dropping below the minimum system voltage and causing a system crash.
The BQ25723 monitors adapter current, battery current, and system power. The flexibly programmed PROCHOT
output goes directly to the CPU for throttle back when needed.
The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping
occurs in a timely fashion so that the device(s) connected to the dock can avoid experiencing momentary power
loss or glitching. This device integrates FRS in compliance with the PD specification.
TI patented switching frequency dithering pattern can significantly reduce EMI noise over the whole conductive
EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide flexibility for
different applications to simplify EMI noise filter design.
The charger can be operated in the TI patented Pass Through Mode (PTM) to improve efficiency over the full
load range. In PTM, input power is directly passed through the charger to the system. Switching losses of the
MOSFETs and inductor core loss can be saved for high efficiency operation.
The BQ25723 is available in a 32-pin 4 mm × 4 mm WQFN package.
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6 Device Comparison Table
Interface
BQ25713
BQ25720
BQ25723
BQ25730
BQ25731
SMBus
I2C
SMBus
I2C
I2C
I2C
Device Address
09h
6Bh
09h
6Bh
6Bh
6Bh
Maximum Charge Current
8.128 A
8.128 A
16.256 A
16.256 A
16.256 A
16.256 A
Switching Frequency (Hz)
800 k/1.2 M
800 k/1.2 M
800 k/1.2 M
800 k/1.2 M
400 k/800 k
400 k/800 k
Cell Count
1s to 4s
1s to 4s
1s to 4s
1s to 4s
1s to 5s
1s to 5s
Input Current Sense Resistor
10 mΩ/20 mΩ
10 mΩ/20 mΩ
5 mΩ/10 mΩ
5 mΩ/10 mΩ
5 mΩ/10 mΩ
5 mΩ/10 mΩ
Independent Comparator Latch
4
BQ25710
Non Latch
Non Latch
Latch/Non latch Latch/Non latch Latch/Non latch Latch/Non latch
(default)
(default)
(default)
(default)
VSYS_UVP
2.4 V
2.4 V
2.4 V ~ 8.0 V
(0.8-V step
size) Default:
2.4 V
OTG Voltage Range
3.0 V to 20.8 V
3.0 V to 20.8 V
3.0 V to 24 V
3.0 V to 24 V
3.0 V to 24 V
3.0 V to 24 V
Frequency Dithering
No
No
Yes
Yes
Yes
Yes
BATFET Power Path
Yes
Yes
Yes
Yes
Yes
No
Pre-charge LDO Mode
Yes
Yes
Yes
Yes
Yes
No
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2.4 V ~ 8.0 V
(0.8-V step
size) Default:
2.4 V
2.4 V ~ 8.0 V
(0.8-V step
size) Default:
2.4 V
1.6 V
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SLUSE64 – MAY 2021
SW1
HIDRV1
BTST1
LODRV1
REGN
PGND
LODRV2
BTST2
32
31
30
29
28
27
26
25
7 Pin Configuration and Functions
VBUS
1
24
HIDRV2
ACN
2
23
SW2
ACP
3
22
VSYS
CHRG_OK
4
21
BATDRV
OTG/VAP/FRS
5
20
SRP
ILIM_HIZ
6
19
SRN
VDDA
7
18
CELL_BATPRESZ
IADPT
8
17
COMP2
Thermal
10
11
12
13
14
15
16
PSYS
PROCHOT
SDA
SCL
CMPIN
CMPOUT
COMP1
IBAT
9
Pad
Figure 7-1. RSN Package 32-Pin WQFN Top View
Table 7-1. Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
ACN
2
PWR
Input current sense amplifier negative input. The leakage on ACP and ACN are matched. A
RC low-pass filter is required to be placed between the sense resistor and the ACN pin to
suppress the high frequency noise in the input current signal. Refer to Section 10.2.2.1 for
ACP/ACN filter design.
ACP
3
PWR
Input current sense amplifier positive input. The leakage on ACP and ACN are matched. A
RC low-pass filter is required to be placed between the sense resistor and the ACP pin to
suppress the high frequency noise in the input current signal. Refer to Section 10.2.2.1 for
ACP/ACN filter design.
P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the
BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to
regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on
during fast charge and works as an ideal-diode in supplement mode.
BATDRV
21
O
BTST1
30
PWR
Buck mode high-side power MOSFET driver power supply. Connect a 0.047-µF capacitor
between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.
BTST2
25
PWR
Boost mode high-side power MOSFET driver power supply. Connect a 0.047-μF capacitor
between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.
I
Battery cell selection pin for 1- to 4- cell battery setting. CELL_BATPRESZ pin is biased
from VDDA through a resistor divider. CELL_BATPRESZ pin also sets SYSOVP thresholds
to 5 V for 1-cell, 12 V for 2-cell and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is
pulled below VCELL_BATPRESZ_FALL to indicate battery removal. After battery is removed the
charge voltage register REG0x05/04h() goes back to default. No external cap is allowed
at CELL_BATPRESZ pin. The device exits LEARN mode and disables charge when
CELL_BATPRESZ pin is pulled low (upon battery removal).
CELL_BATPRESZ
18
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Table 7-1. Pin Functions (continued)
PIN
NAME
CHRG_OK
4
I/O
DESCRIPTION
O
Open drain active high indicator to inform the system good power source is connected to
the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5
V and falls below 25.8 V, CHRG_OK is HIGH after 50-ms deglitch time. When VBUS falls
below 3.2 V or rises above 26.8 V, CHRG_OK is LOW. When one of SYSOVP, SYSUVP,
ACOC, TSHUT, BATOVP, BATOC or force converter off faults occurs, CHRG_OK is asserted
LOW.
CMPIN
14
I
Input of independent comparator. The independent comparator compares the voltage
sensed on CMPIN pin with internal reference, and its output is on CMPOUT pin. Internal
reference, output polarity and deglitch time is selectable by the host. With polarity HIGH
(CMP_POL = 1b), place a resistor between CMPIN and CMPOUT to program hysteresis.
With polarity LOW (CMP_POL = 0b), the internal hysteresis is 100 mV. If the independent
comparator is not in use, tie CMPIN to ground.
CMPOUT
15
O
Open-drain output of independent comparator. Place a pullup resistor from CMPOUT to
pullup supply rail. Internal reference, output polarity and deglitch time are selectable by the
host. If the independent comparator is not in use, float CMPOUT pin.
COMP2
17
I
Buck boost converter compensation pin 2. Refer to Section 9.3.13 for COMP2 pin RC
network.
COMP1
16
I
Buck boost converter compensation pin 1. Refer to Section 9.3.13 for COMP1 pin RC
network.
OTG/VAP/FRS
5
I
Active HIGH to enable OTG, VAP or FRS modes. 1) When OTG_VAP_MODE=1b and
EN_OTG=1b, pulling high this pin can enable OTG mode. 2) When OTG_VAP_MODE=1b
and EN_FRS=1b, pulling high this pin can enable FRS mode in forward operation. 3) When
OTG_VAP_MODE=0b, pulling high OTG/VAP/FRS pin is to enable VAP mode.
HIDRV1
31
O
Buck mode high-side power MOSFET (Q1) driver. Connect to high-side n-channel MOSFET
gate.
HIDRV2
24
O
Boost mode high-side power MOSFET(Q4) driver. Connect to high-side n-channel MOSFET
gate.
O
The adapter current monitoring output pin. VIADPT = 20 or 40 × (VACP – VACN) with ratio
selectable through IADPT_GAIN bit. This pin is also used to program the inductance used in
the application. Refer to Section 9.3.12 for selecting resistor from the IADPT pin to ground .
For a 2.2-µH inductance, the resistor is 137 kΩ. Place a 100-pF or less ceramic decoupling
capacitor from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.
O
The battery current monitoring output pin. VIBAT = 8 or 16 × (VSRP – VSRN) for charge
current, or VIBAT = 8 or 16 × (VSRN – VSRP) for discharge current, with ratio selectable
through IBAT_GAIN bit. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin
to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.
IADPT
IBAT
6
NUMBER
8
9
ILIM_HIZ
6
I
Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider
from VDDA rail to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM ×
Rac, in which IDPM is the target input current limit.
When EN_EXTILIM = 1b the input current limit used by the charger is the lower setting of
ILIM_HIZ pin and IIN_HOST register. When EN_EXTILIM = 0b input current limit is only
determined by IIN_HOST register.
When the pin voltage is below 0.4 V, the device enters high impedance (HIZ) mode with
low quiescent current. When the pin voltage is above 0.8 V, the device is out of HIZ mode.
The ILIM_HIZ pin voltage is continuous read and used for updating current limit setting (If
EN_EXTILIM=1b ), this allows dynamic change input current limit setting by adjusting this pin
voltage.
LODRV1
29
O
Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET
gate.
LODRV2
26
O
Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET
gate.
PGND
27
GND
PROCHOT
11
O
Device power ground.
Active low open drain output indicator. It monitors adapter input current, battery discharge
current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is
asserted. The minimum pulse width is adjustable through PROCHOT_WIDTH bits.
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Table 7-1. Pin Functions (continued)
PIN
NAME
NUMBER
I/O
DESCRIPTION
Current mode system power monitor. The output current is proportional to the total power
from the adapter and the battery. The gain is selectable through . Place a resistor from
PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output
voltage is clamped at 3.3 V. Place a capacitor in parallel with the resistor for filtering.
PSYS
10
O
REGN
28
PWR
SCL
13
I
clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ
pullup resistor according to specifications.
SDA
12
I/O
open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a
10-kΩ pullup resistor according to specifications.
SRN
19
PWR
Charge current sense amplifier negative input. SRN pin is for battery voltage sensing as
well. Connect a 0.1-μF filter cap cross battery charging sensing resistor and use 10-Ω
contact resistor between SRN pin and battery charging sensing resistor. The leakage current
on SRP and SRN are matched.
SRP
20
PWR
Charge current sense amplifier positive input. Connect a 0.1-μF filter cap cross battery
charging sensing resistor and use 10-Ω contact resistor between SRP pin and battery
charging sensing resistor. The leakage current on SRP and SRN are matched.
SW1
32
PWR
Buck mode switching node. Connect to the source of the buck half bridge high side nchannel MOSFET.
SW2
23
PWR
Boost mode switching node. Connect to the source of the boost half bridge high side
n-channel MOSFET.
VBUS
1
PWR
Charger input voltage. An input low pass filter of 1 Ω and 0.47 µF (minimum) is
recommended.
VDDA
7
PWR
Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF
ceramic capacitor from VDDA to power ground.
VSYS
22
PWR
Charger system voltage sensing. The system voltage regulation maximum limit is
programmed in ChargeVoltage register plus 150 mV and regulation minimum limit is
programmed in VSYS_MIN register.
Thermal pad
–
–
6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS
above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power
ground. REGN pin output is for power stage gate drive.
Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on
the thermal pad plane connecting to power ground planes. It serves as a thermal pad to
dissipate the heat.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
SRN, SRP, ACN, ACP, VBUS, VSYS
MIN
MAX
–0.3
32
–2
32
–0.3
38
SW1, SW2
BTST1, BTST2, HIDRV1, HIDRV2, BATDRV
LODRV1, LODRV2 (25nS)
–4
7
HIDRV1, HIDRV2 (25nS)
–4
38
SW1, SW2 (25nS)
–4
32
SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,
LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/
FRS,
–0.3
7
PROCHOT
–0.3
5.5
IADPT, IBAT, COMP1
–0.3
3.6
Differential
Voltage
BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2
–0.3
7
SRP-SRN, ACP-ACN
–0.5
0.5
Temperature
Junction temperature range, TJ
–40
150
Temperature
Storage temperature, Tstg
–55
150
Voltage
(1)
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
ACN, ACP, VBUS
SRN, SRP, VSYS
Differential
Voltage
26
0
19.2
26
BTST1, BTST2, HIDRV1, HIDRV2, BATDRV
0
32
SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,
LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/FRS
0
6.5
PROCHOT
0
5.3
IADPT, IBAT, COMP1
0
3.3
BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2
0
6.5
SRP-SRN, ACP-ACN
BATDRV-VSYS
8
MAX
–2
SW1, SW2
Voltage
NOM
0
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–0.5
0.5
0
10.8
UNIT
V
V
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8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
Temperature
NOM
MAX
Junction temperature range, TJ
–20
125
Storage temperature, Tstg
–20
85
UNIT
°C
8.4 Thermal Information
BQ25723
THERMAL
METRIC(1)
RSN (WQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance (JEDEC(1))
37.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.1
°C/W
RθJB
Junction-to-board thermal resistance
7.8
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
7.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VINPUT_OP
TEST CONDITIONS
Input voltage
operating range
MIN
TYP
MAX UNIT
3.5
26
V
1.024
19.2
V
MAX SYSTEM VOLTAGE REGULATION
VSYSMAX_RNG
System Voltage
Regulation, measured
on VSYS (charge
disabled)
VSRN +
150 mV
REG0x05/04() = 0x41A0H (16.800 V)
–2%
VSYSMAX_ACC
System voltage
regulation accuracy
(charge disabled and
EN_OOA=0b)
V
2%
VSRN +
150 mV
REG0x05/04() = 0x3138H (12.600 V)
–2%
V
2%
VSRN +
150 mV
REG0x05/04() = 0x20D0H (8.400 V)
–3%
V
3%
VSRN +
150 mV
REG0x05/04() = 0x1068H (4.200 V)
V
–3%
3%
1.00
19.2
MINIMUM SYSTEM VOLTAGE REGULATION
VSYS_MIN_RNG
System Voltage
Regulation, measured
on VSYS
V
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REG0x0D/0C() = 0x7B00H
VSYS_MIN_REG_ACC
Minimum System
REG0x0D/0C() = 0x5C00H
Voltage Regulation
Accuracy (VBAT
below REG0x0D/0C()
REG0x0D/0C() = 0x4200H
setting, EN_OOA=0b)
REG0x0D/0C() = 0x2400H
MIN
TYP
MAX UNIT
12.30
–2%
V
–2%
9.20
–2%
V
–2%
6.60
–3%
V
–3%
3.60
V
–3%
–3%
1.024
19.2
CHARGE VOLTAGE REGULATION
VBAT_RNG
Battery voltage
regulation
REG0x05/04() = 0x41A0H
VBAT_REG_ACC
Battery voltage
regulation accuracy
(charge enable) (0°C
to 85°C)
REG0x05/04() = 0x3138H
REG0x05/04() = 0x20D0H
REG0x05/04() = 0x1068H
16.8
–0.5%
V
V
0.5%
12.6
–0.5%
V
0.5%
8.4
–0.6%
V
0.6%
4.2
V
–1.1%
1.2%
0
81.28
CHARGE CURRENT REGULATION IN FAST CHARGE
VIREG_CHG_RNG
Charge current
regulation differential
voltage range
VIREG_CHG = VSRP – VSRN
REG0x03/02() = 0x1000H
ICHRG_REG_ACC
Charge current
regulation accuracy
10-mΩ sensing
resistor, VBAT above
0x0D/0C() setting
(0°C to 85°C)
REG0x03/02() = 0x0800H
REG0x03/02() = 0x0400H
REG0x03/02() = 0x0200H
4096
–3.0%
mV
mA
2.0%
2048
–4.0%
mA
3.0%
1024
–5.0%
mA
6.0%
512
–12.0%
mA
12.0%
CHARGE CURRENT REGULATION IN LDO MODE
ICLAMP
Pre-charge current
clamp
CELL(≥2 S) VSRN < VSYS_MIN
384
mA
CELL 1 S, VSRN < 3 V
384
mA
CELL 1 S, 3 V < VSRN < VSYS_MIN
10
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
REG0x03/02() = 0x0180H
IPRECHRG_REG_ACC
Pre-charge current
regulation accuracy
with 10-mΩ SRP/SRN
series resistor, VBAT
below
VSYS_MIN(REG0x0
D/0C()) setting (0°C
to 85°C)
MAX UNIT
384
mA
≥2S
–15.0%
15.0%
1S
–25.0%
25.0%
REG0x03/02() = 0x0100H
256
≥2S
–20.0%
1S
–35.0%
REG0x03/02() = 0x00C0H
mA
20.0%
35.0%
192
mA
≥2S
–25.0%
25.0%
1S
–50.0%
50.0%
REG0x03/02() = 0x0080H
≥2S
ILEAK_SRP_SRN
TYP
SRP, SRN leakage
current mismatch
(0°C to 85°C)
128
mA
–30.0%
30.0%
–13.5
10.0
µA
0.5
64
mV
INPUT CURRENT REGULATION
VIREG_DPM_RNG
Input current
regulation differential
voltage range with
10-mΩ ACP/ACN
series resistor
IIIN_DPM_REG_ACC
Input current
regulation accuracy
(-40°C to 105°C)
with 10-mΩ ACP/ACN
series resistor
VIREG_DPM = VACP – VACN
REG0x0F/0E() = 0x4E00H
3800
3900
4000
mA
REG0x0F/0E() = 0x3A00H
2800
2900
3000
mA
REG0x0F/0E() = 0x1C00H
1300
1400
1500
mA
REG0x0F/0E() = 0x0800H
300
400
500
mA
ILEAK_ACP_ACN
ACP, ACN leakage
current mismatch
–21
10
µA
VIREG_DPM_RNG_ILIM
Voltage range
for input current
regulation (ILIM_HIZ
Pin)
1.15
4
V
IIIN_DPM_REG_ACC_ILIM
Input Current
Regulation Accuracy
on ILIM_HIZ pin
VILIM_HIZ = 1 V + 40
× IDPM × RAC, with 10mΩ ACP/ACN series
resistor
ILEAK_ILIM
VILIM_HIZ = 2.6 V
3800
4000
4200
mA
VILIM_HIZ = 2.2 V
2800
3000
3200
mA
VILIM_HIZ = 1.6 V
1300
1500
1700
mA
VILIM_HIZ = 1.2 V
300
500
700
mA
–1
1
µA
3.2
19.52
V
ILIM_HIZ pin leakage
current
INPUT VOLTAGE REGULATION
VDPM_RNG
Input voltage
regulation range
Voltage on VBUS
REG0x0B/0A()=0x3C80H
18688
–3%
VDPM_REG_ACC
Input voltage
regulation accuracy
REG0x0B/0A()=0x1E00H
2%
10880
–4%
REG0x0B/0A()=0x0500H
mV
mV
2.5%
4480
mV
5.0%
OTG CURRENT REGULATION
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SLUSE64 – MAY 2021
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIOTG_REG_RNG
OTG output current
regulation differential
voltage range
IOTG_ACC
OTG output current
REG0x09/08() = 0x3C00H
regulation accuracy
REG0x09/08() = 0x1E00H
with 50-mA LSB
and 10-mΩ ACP/ACN
REG0x09/08() = 0x0A00H
series resistor
VIOTG_REG = VACP – VACN
MIN
TYP
0
MAX UNIT
81.28
mV
2800
3000
3200
mA
1300
1500
1700
mA
300
500
700
mA
OTG VOLTAGE REGULATION
VOTG_REG_RNG
OTG voltage
regulation range(OOA Voltage on VBUS
disabled)
3
REG0x07/06()=0x2CEC
VOTG_REG_ACC
OTG voltage
regulation
accuracy(OOA
disabled)
24.00
23.00
–2%
REG0x07/06()=0x1770H
V
2%
12.00
–2%
REG0x07/06()=0x09C4H
V
V
2%
5.00
–3%
V
3%
REGN REGULATOR
VREGN_REG
REGN regulator
voltage (0 mA – 60
mA)
VDROPOUT
IREGN_LIM_Charging
VVBUS = 10 V
5.7
6
6.3
V
REGN voltage in drop
VVBUS = 5 V, ILOAD = 20 mA
out mode
3.8
4.3
4.6
V
REGN current limit
when converter is
enabled
50
65
VVBUS = 10 V, force VREGN =4 V
mA
QUIESCENT CURRENT
IBAT_BATFET_ON
System powered by
battery. BATFET on.
ISRN + ISRP + ISW2 +
IBTST2 + ISW1 + IBTST1
+ IACP + IACN + IVBUS
+ IVSYS
VBAT = 18 V, REG0x01[7] = 1,REG0x31[6] = 0b, in
low-power mode, Disable PSYS
22
45
µA
VBAT = 18 V, REG0x01[7] = 1, REG0x31[6] =
1b, REG0x31[5:4] = 11b,REGN off, Disable PSYS,
Enable low power PROCHOT
35
60
µA
VBAT = 18 V, REG0x01[7]= 0,REG0x31[5:4]= 11b,
REGN on, Disable PSYS, In performance mode
880
1170
µA
VBAT = 18 V, REG0x01[7] = 0, REG0x31[5:4]
= 00b, REGN on, Enable PSYS, In performance
mode
980
1270
µA
VIN = 20 V, VBAT = 12.6 V, 3s, REG0x01[2] = 0;
MOSFET Qg = 4 nC
2.2
mA
2.7
mA
IAC_SW_LIGHT_buck
Input current during
PFM in buck mode,
no load, IVBUS + IACP
+ IACN + IVSYS + ISRP
+ ISRN + ISW1 + IBTST
+ ISW2 + IBTST2
IAC_SW_LIGHT_boost
Input current during
PFM in boost mode,
no load, IVBUS + IACP VIN = 5 V, VBAT = 8.4 V, 2s, REG0x01[2] = 0;
+ IACN + IVSYS + ISRP MOSFET Qg = 4 nC
+ ISRN + ISW1 + IBTST2
+ ISW2 + IBTST2
12
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IAC_SW_LIGHT_buckboost
Input current during
PFM in buck boost
mode, no load, IVBUS VIN = 12 V, VBAT = 12 V, REG0x01[2] = 0;
+ IACP + IACN + IVSYS MOSFET Qg = 4 nC
+ ISRP + ISRN + ISW1 +
IBTST1 + ISW2 + IBTST2
IOTG_STANDBY
Quiescent current
during PFM in OTG
mode IVBUS + IACP +
IACN + IVSYS + ISRP +
ISRN + ISW1 + IBTST2 +
ISW2 + IBTST2
MIN
TYP
MAX UNIT
2.4
mA
3
mA
VBAT = 8.4 V, VBUS = 12 V, 800 kHz switching
frequency, MOSFET Qg = 4nC
4.2
mA
VBAT = 8.4 V, VBUS = 20 V, 800 kHz switching
frequency, MOSFET Qg = 4nC
6.2
mA
VBAT = 8.4 V, VBUS = 5 V, 800 kHz switching
frequency, MOSFET Qg = 4nC
CURRENT SENSE AMPLIFIER
VACP_ACN_OP
Input common mode
range
VIADPT_CLAMP
IADPT output clamp
voltage
IIADPT
IADPT output current
AIADPT
Input current sensing
gain
Voltage on ACP/ACN
3.8
3.1
3.2
26
V
3.3
V
1
V(IADPT) / V(ACP-ACN), REG0x00[4] = 0
20
V(IADPT) / V(ACP-ACN), REG0x00[4] = 1
V(ACP-ACN) = 40.96 mV
40
V/V
–2%
2%
V(ACP-ACN) = 20.48 mV
–3%
3%
V(ACP-ACN) =10.24 mV
–6%
6%
V(ACP-ACN) = 5.12 mV
–10%
10%
VIADPT_ACC
Input current monitor
accuracy
CIADPT_MAX
Maximum
capacitance at IADPT
Pin
VSRP_SRN_OP
Battery common
mode range
VIBAT_CLAMP
IBAT output clamp
voltage
IIBAT
IBAT output current
AIBAT
Charge and
V(IBAT) / V(SRN-SRP), REG0x00[3] = 0,
discharge current
sensing gain on IBAT V(IBAT) / V(SRN-SRP), REG0x00[3] = 1,
pin
IIBAT_CHG_ACC
Charge and
discharge current
monitor accuracy on
IBAT pin
CIBAT_MAX
Maximum
capacitance at IBAT
Pin
Voltage on SRP/SRN
2.5
3.05
3.2
100
pF
19.2
V
3.3
V
1
V(SRN-SRP) = 40.96 mV
mA
V/V
mA
8
V/V
16
V/V
–2%
2%
V(SRN-SRP) = 20.48 mV
–4%
4%
V(SRN-SRP) =10.24 mV
–7%
7%
V(SRN-SRP) = 5.12 mV
–15%
15%
100
pF
SYSTEM POWER SENSE AMPLIFIER
VPSYS
PSYS output voltage
range
0
3.3
V
IPSYS
PSYS output current
0
160
µA
APSYS
PSYS system gain
I(PSYS) / (P(IN) +P(BAT)), REG0x31[5:4] =
00b;REG0x31[1] = 1b
1
µA/W
APSYS
PSYS system gain
I(PSYS) / P(IN), REG0x31[5:4]= 01b;REG0x31[1] = 1b
1
µA/W
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VPSYS_ACC
PSYS gain accuracy
(REG0x30[13:12] =
00b)
PSYS gain accuracy
(REG0x30[13:12] =
01b)
VPSYS_CLAMP
TEST CONDITIONS
MIN
Adapter only with system power = 19.5 V / 45 W, TA
= 0 to 85°C
–4%
4%
Battery only with system power = 11 V / 44 W, TA =
0 to 85°C
–3%
3%
Adapter only with system power = 19.5 V / 45 W, TA
= 0 to 85°C
–4%
4%
3
3.3
V
PSYS clamp voltage
TYP
MAX UNIT
VMIN ACTIVE PROTECTION(VAP) PROCHOT COMPARATOR
VSYS_TH1Z
VAP VSYS rising
threshold 1
VSYS_TH1 rising
6.4
6.6
6.75
V
VSYS_TH1
VAP VSYS falling
threshold 1
VSYS_TH1 falling REG36=100010b
6.3
6.5
6.65
V
VSYS_TH1_HYST
VAP VSYS threshold
1 hysteresis
tSYS_TH1_falling_DEG
VSYS threshold 1
falling deglitch for
VAP shooting
VSYS_TH2Z
VAP VSYS rising
threshold 2
VSYS_TH2 rising
6.1
6.3
6.45
V
VSYS_TH2
VAP VSYS falling
threshold 2
VSYS_TH2 falling REG3E=011111b
6.0
6.2
6.35
V
VSYS_TH2_HYST
VAP VSYS threshold
2 hysteresis
tSYS_TH2_falling_DEG
VSYS threshold 2
falling deglitch for
throttling
VBUS_VAP_THZ
VAP mode VBUS
rising threshold
VBUS_VAP_TH rising
VBUS_VAP_TH
VAP mode VBUS
falling threshold
VBUS_VAP_TH falling REG3F=0000000b
VBUS_VAP_TH_HYST
VAP mode VBUS
threshold hysteresis
tBUS_VAP_TH_falling_DEG
VBUS falling deglitch
for throttling
100
mV
4
us
100
mV
4
us
3.15
3.35
3.50
V
3.0
3.2
3.35
V
150
mV
4
us
VSYS UNDER VOLTAGE LOCKOUT COMPARATOR
VSYS_UVLOZ
VSYS undervoltage
rising threshold(≥1S)
VSYS_UVLO
VSYS undervoltage
VSYS falling REG3D=000b
falling threshold(≥1S)
VSYS_UVLO_HYST
VSYS undervoltage
hysteresis(≥1S)
VSYS rising
2.3
2.5
2.65
V
2.2
2.4
2.55
V
100
mV
VBUS UNDER VOLTAGE LOCKOUT COMPARATOR
VVBUS_UVLOZ
VBUS undervoltage
rising threshold
VBUS rising
2.35
2.55
2.80
V
VVBUS_UVLO
VBUS undervoltage
falling threshold
VBUS falling
2.2
2.4
2.6
V
VVBUS_UVLO_HYST
VBUS undervoltage
hysteresis
VVBUS_CONVEN
VBUS converter
enable rising
threshold
14
150
VBUS rising
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3.5
mV
3.9
V
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SLUSE64 – MAY 2021
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VVBUS_CONVENZ
VBUS converter
enable falling
threshold
VVBUS_CONVEN_HYST
VBUS converter
enable hysteresis
TEST CONDITIONS
VBUS falling
MIN
TYP
2.9
3.2
MAX UNIT
3.5
300
V
mV
BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR
VVBAT_UVLOZ
VBAT undervoltage
rising threshold
VSRN rising
2.35
2.55
2.80
V
VVBAT_UVLO
VBAT undervoltage
falling threshold
VSRN falling
2.2
2.4
2.6
V
VVBAT_UVLO_HYST
VBAT undervoltage
hysteresis
VVBAT_OTGEN
VBAT OTG enable
rising threshold
VSRN rising
3.25
3.55
3.85
V
VVBAT_OTGENZ
VBAT OTG enable
falling threshold
VSRN falling
2.15
2.4
2.65
V
VVBAT_OTGEN_HYST
VBAT OTG enable
hysteresis
150
mV
1150
mV
VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)
VVBUS_OTG_UV
VBUS undervoltage
falling threshold
tVBUS_OTG_UV
VBUS time
undervoltage deglitch
As percentage of REG0x07/06()
85%
7
ms
VBUS OVER VOLTAGE COMPARATOR (OTG MODE)
VVBUS_OTG_OV
VBUS overvoltage
rising threshold
tVBUS_OTG_OV
VBUS Time
Overvoltage Deglitch
As percentage of REG0x07/06()
110%
10
ms
PRE-CHARGE to FAST CHARGE TRANSITION(For ≥2S)
VBAT_VSYS_MIN_RISE
LDO mode to
fast charge mode
threshold, VSRN
rising
as percentage of 0x0D/0C()
VBAT_VSYS_MIN_FALL
LDO mode to
fast charge mode
threshold, VSRN
falling
as percentage of 0x0D/0C()
97.5%
VBAT_VSYS_MIN_HYST
Fast charge mode to
LDO mode threshold
hysteresis
as percentage of 0x0D/0C()
2.5%
98%
100%
102%
BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Threshold for 1S)
VBATLV_FALL
BATLOWV falling
threshold
2.8
V
VBATLV_RISE
BATLOWV rising
threshold
3
V
VBATLV_RHYST
BATLOWV hysteresis
200
mV
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV_RISE
VBUS overvoltage
rising threshold
VBUS rising
26.0
26.8
27.7
V
VACOV_FALL
VBUS overvoltage
falling threshold
VBUS falling
25.0
25.8
26.7
V
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VACOV_HYST
VBUS overvoltage
hysteresis
tACOV_RISE_DEG
VBUS deglitch
overvoltage rising
tACOV_FALL_DEG
VBUS deglitch
overvoltage falling
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.0
V
VBUS converter rising to stop converter
100
us
VBUS converter falling to start converter
1
ms
INPUT OVER CURRENT COMPARATOR (ACOC)
VACOC
ACP to ACN rising
Voltage across input sense resistor rising,
threshold, w.r.t. ILIM2
Reg0x32[2]= 1
in REG0x33[15:11]
VACOC_FLOOR
Measure between
ACP and ACN
VACOC_CEILING
180%
200%
220%
Set IIN_DPM to minimum
44
50
56
mV
Measure between
ACP and ACN
Set IIN_DPM to maximum
172
180
188
mV
tACOC_DEG_RISE
Rising deglitch time
Deglitch time to trigger ACOC
250
us
tACOC_RELAX
Relax time
Relax time before converter starts again
250
ms
SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)
VSYSOVP_RISE
System overvoltage
rising threshold to
turnoff converter
1s
5.8
6
6.1
V
2s
3s
11.7
12
12.2
V
19
19.5
20
4s
V
19
19.5
20
V
1s
VSYSOVP_FALL
ISYSOVP
System overvoltage
falling threshold
Discharge current
when SYSOVP
stop switching was
triggered
5.5
V
2s
11.7
V
3s
19.3
V
4s
19.3
V
on VSYS pin
20
mA
BAT OVER-VOLTAGE COMPARATOR (BATOVP)
VBATOVP_RISE
Overvoltage rising
threshold as
percentage of
VBAT_REG in
REG0x15()
VBATOVP_FALL
Overvoltage falling
threshold as
percentage of
VBAT_REG in
REG0x15()
VBATOVP_HYST
Overvoltage
hysteresis as
percentage of
VBAT_REG in
REG0x15()
IBATOVP
Discharge current
during BATOVP
1 s, 4.2 V
102.5%
104%
106%
≥2 s
102.5%
104%
105%
1s
100%
102%
104%
≥2 s
100%
102%
103%
1s
2%
≥2 s
2%
Discharge current through VSYS pin
40
mA
150
mV
210
mV
CONVERTER OVER-CURRENT COMPARATOR (Q2)
VOCP_limit_Q2
16
Converter OverReg0x32[5]=1
Current Limit across
Q2 MOSFET drain to Reg0x32[5]=0
source voltage
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SLUSE64 – MAY 2021
8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
VOCP_limit_SYSSHORT_Q
2
TEST CONDITIONS
MIN
System Short or SRN Reg0x32[5]=1
< 2.4 V
Reg0x32[5]=0
TYP
MAX UNIT
45
mV
60
mV
Reg0x32[4]=1; RSNS_RAC=0b
150
mV
Reg0x32[4]=0;RSNS_RAC=0b
280
mV
CONVERTER OVER-CURRENT COMPARATOR (ACX)
VOCP_limit_ACX
Converter OverCurrent Limit across
ACP-ACN input
current sensing
resistor
VOCP_limit_SYSSHORT_A System Short or SRN Reg0x32[4]=1
< 2.4 V
CX
Reg0x32[4]=0
90
mV
150
mV
THERMAL SHUTDOWN COMPARATOR
TSHUT_RISE
Thermal shutdown
rising temperature
Temperature increasing
155
°C
TSHUTF_FALL
Thermal shutdown
falling temperature
Temperature reducing
135
°C
TSHUT_HYS
Thermal shutdown
hysteresis
20
°C
tSHUT_RDEG
Thermal deglitch
shutdown rising
100
us
tSHUT_FHYS
Thermal deglitch
shutdown falling
12
ms
ICRIT PROCHOT COMPARATOR
IICRIT_PRO
Input current rising
threshold for throttling
Only when ILIM2 setting is higher than 2A
as 10% above ILIM2
(REG0x33[15:11])
105%
110%
117%
105%
110%
116%
INOM PROCHOT COMPARATOR
IINOM_PRO
INOM rising
threshold as 10%
above IIN_DPM
(REG0x22[15:8])
BATTERY DISCHARGE CURRENT LIMIT PROCHOT COMPARATOR(IDCHG)
IDCHG_TH1
IDCHG threshold1 for Reg0x39=010000b, with 10mΩ SRP/SRN
throttling CPU
current sensing resistor
IDCHG_DEG1
IDCHG threshold1
deglitch time
IDCHG_TH2
IDCHG threshold2 for Reg0x39=010000b 3C=001b,with 10mΩ
throttling CPU
SRP/SRN current sensing resistor
tDCHG_DEG2
IDCHG threshold2
deglitch time
8192
96%
Reg0x39h=01b
mA
103%
1.25
sec
12288
96%
Reg0x3C=01b
mA
103%
1.6
ms
INDEPENDENT COMPARATOR
VINDEP_CMP
Reg0x30h= 1, CMPIN falling
Independent
comparator threshold Reg0x30h= 0, CMPIN falling
VINDEP_CMP_HYS
Independent
comparator
hysteresis
1.17
1.2
1.23
V
2.27
2.3
2.33
V
CMPIN falling
100
mV
POWER MOSFET DRIVER
PWM OSCILLATOR AND RAMP
FSW
PWM switching
frequency
Reg0x01[1] = 0
1020
1200
1380
kHz
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
PWM switching
frequency
FSW
TEST CONDITIONS
Reg0x01[1] = 1
MIN
TYP
MAX UNIT
680
800
920
kHz
8.5
10
11.5
V
BATFET GATE DRIVER (BATDRV)
VBATDRV_ON
Gate drive voltage on
BATFET
VBATDRV_DIODE
Drain-source voltage
on BATFET during
ideal diode operation
RBATDRV_ON
Measured by
sourcing 10 µA
current to BATDRV
RBATDRV_OFF
Measured by sinking
10 µA current from
BATDRV
30
3
mV
4
6
kΩ
1.2
2.1
kΩ
PWM HIGH SIDE DRIVER (HIDRV Q1)
RDS_HI_ON_Q1
High-side driver
(HSD) turnon
resistance
VBTST1 - VSW1 = 5 V
6
RDS_HI_OFF_Q1
High-side driver
turnoff resistance
VBTST1 - VSW1 = 5 V
1.3
2.2
Ω
VBTST1_REFRESH
Bootstrap refresh
comparator falling
threshold voltage
VBTST1 - VSW1 when low-side refresh pulse is
requested
3.7
4.6
V
3.2
Ω
PWM HIGH SIDE DRIVER (HIDRV Q4)
RDS_HI_ON_Q4
High-side driver
(HSD) turnon
resistance
VBTST2 - VSW2 = 5 V
6
RDS_HI_OFF_Q4
High-side driver
turnoff resistance
VBTST2 - VSW2 = 5 V
1.5
2.4
Ω
VBTST2_REFRESH
Bootstrap refresh
comparator falling
threshold voltage
VBTST2 - VSW2 when low-side refresh pulse is
requested
3.7
4.6
V
3.3
Ω
PWM LOW SIDE DRIVER (LODRV Q2)
RDS_LO_ON_Q2
Low-side driver (LSD)
VBTST1 - VSW1 = 5.5 V
turnon resistance
RDS_LO_OFF_Q2
Low-side driver
turnoff resistance
6
VBTST1 - VSW1 = 5.5 V
1.7
RDS_LO_ON_Q3
Low-side driver (LSD)
VBTST2 - VSW2 = 5.5 V
turnon resistance
7.6
RDS_LO_OFF_Q3
Low-side driver
turnoff resistance
2.9
Ω
2.6
Ω
PWM LOW SIDE DRIVER (LODRV Q3)
VBTST2 - VSW2 = 5.5 V
Ω
4.6
Ω
INTERNAL SOFT START During Charge Enable
SSSTEP_SIZE
Charge current softstart step size
64
mA
SSSTEP_TIME
Charge current softstart duration time for
each step
8
us
0.8
V
INTEGRATED BTST DIODE (D1)
VF_D1
Forward bias voltage
IF = 20 mA at 25°C
VR_D1
Reverse breakdown
voltage
IR = 2 µA at 25°C
18
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INTEGRATED BTST DIODE (D2)
VF_D2
Forward bias voltage
IF = 20 mA at 25°C
VR_D2
Reverse breakdown
voltage
0.8
V
IR = 2 µA at 25°C
20
V
0.4
V
INTERFACE
LOGIC INPUT (SDA, SCL)
VIN_ LO
Input low threshold
I2C
VIN_ HI
Input high threshold
I2C
1.3
V
LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)
VOUT_ LO
Output saturation
voltage
5 mA drain current
VOUT_ LEAK
Leakage current
Voltage = 7 V
–1
0.4
V
1
µA
0.4
V
LOGIC INPUT (OTG/VAP/FRS pin)
VIN_ LO_OTG
Input low threshold
VIN_ HI_OTG
Input high threshold
1.3
V
LOGIC OUTPUT OPEN DRAIN SDA
VOUT_ LO_SDA
Output Saturation
Voltage
5 mA drain current
VOUT_ LEAK_SDA
Leakage Current
Voltage = 7 V
–1
0.4
V
1
µA
0.4
V
1
µA
0.4
V
1
µA
300
mV
1
µA
LOGIC OUTPUT OPEN DRAIN CHRG_OK
VOUT_ LO_CHRG_OK
Output Saturation
Voltage
5 mA drain current
VOUT_ LEAK _CHRG_OK
Leakage Current
Voltage = 7 V
–1
LOGIC OUTPUT OPEN DRAIN CMPOUT
VOUT_ LO_CMPOUT
Output Saturation
Voltage
5 mA drain current
VOUT_ LEAK _CMPOUT
Leakage Current
Voltage = 7 V
–1
LOGIC OUTPUT OPEN DRAIN (PROCHOT)
VOUT_ LO_PROCHOT
Output saturation
voltage
50 Ω pullup to 1.05 V / 5-mA
VOUT_ LEAK_PROCHOT
Leakage current
Voltage = 5.5 V
–1
ILIM_HIZ pin rising
0.8
ANALOG INPUT (ILIM_HIZ)
VHIZ_ LO
Voltage to get out of
HIZ mode
VHIZ_ HIGH
Voltage to enable HIZ
ILIM_HIZ pin falling
mode
V
0.4
V
ANALOG INPUT (CELL_BATPRESZ)
VCELL_4S
4S setting
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
68.4%
75%
81.5%
VCELL_3S
3S setting
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
51.7%
55%
65%
VCELL_2S
2S setting
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
35%
40%
48.5%
VCELL_1S
1S setting
CELL_BATPRESZ pin voltage as percentage of
REGN = 6 V
18.4%
25%
31.6%
VCELL_BATPRESZ_RISE
Battery is present
CELL_BATPRESZ rising
VCELL_BATPRESZ_FALL
Battery is removed
CELL_BATPRESZ falling
18%
15%
ANALOG INPUT (COMP1, COMP2)
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV_FALL, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ILEAK_COMP1
COMP1 Leakage
–120
120
nA
ILEAK_COMP2
COMP2 Leakage
–120
120
nA
8.6 Timing Requirements
MIN
NOM
MAX
UNIT
300
ns
TIMING CHARACTERISTICS
tr
SCL/SDA rise time
tf
SCL/SDA fall time
tHIGH
SCL pulse width high
0.6
300
ns
50
µs
tLOW
SCL pulse width low
1.3
µs
tSU:STA
Setup time for START condition
0.6
µs
tHD:STA
Start condition hold time after which first clock pulse is generated
0.6
µs
tSU:DAT
Data setup time
100
ns
tHD:DAT
Data hold time
300
ns
tSU:STO
Set up time for STOP condition
0.6
µs
tBUF
Bus free time between START and STOP conditions
1.3
fSCL
Clock frequency
10
400
35
µs
kHz
HOST COMMUNICATION FAILURE
tTIMEOUT
bus release timeout(1)
25
tBOOT
Deglitch for watchdog reset signal
10
tWDI
(1)
20
ms
ms
Watchdog timeout period, REG0x01[6:5]=01
4
5.5
7
s
Watchdog timeout period, REG0x01[6:5]=10
70
88
105
s
Watchdog timeout period, REG0x01[6:5]=11
140
175
210
s
Devices participating in a transfer timeout when any clock low exceeds the 25-ms minimum timeout period. Devices that have detected
a timeout condition must reset the communication no later than the 35-ms maximum timeout period. Both a host and a target must
adhere to the maximum value specified because it incorporates the cumulative stretch limit for both a host (10 ms) and a target (25
ms).
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8.7 Typical Characteristics
100
100
98
98
96
96
94
94
Efficiency(%)
Efficiency(%)
RAC = 5 mΩ, RSR = 5 mΩ, Inductance = 2.2 μH, CCM Frequency = 800 kHz
92
90
88
86
90
88
86
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
84
92
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
84
82
82
0
1
2
3
4
5
6
7
8
9
10
11
0
12
1
2
3
VIN = 5 V
CCM 800 kHz
VOUT = System voltage
VIN = 9 V
5
6
7
8
9
10
11
12
CCM 800 kHz
VOUT = System voltage
Figure 8-2. System Efficiency
100
100
98
98
96
96
94
94
Efficiency(%)
Efficiency(%)
Figure 8-1. System Efficiency
92
90
88
86
92
90
88
86
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
84
VOUT=3.7V
VOUT=7.4V
VOUT=11.1V
VOUT=14.8V
84
82
82
0
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
Output Current(A)
VIN = 15 V
CCM 800 kHz
VOUT = System voltage
VIN = 20 V
85
85
80
80
Efficiency(%)
90
75
70
65
VOUT=4.2V
VOUT=8.4V
VOUT=12.6V
VOUT=16.8V
55
5
6
7
8
9
10
11
12
CCM 800 kHz
VOUT = System voltage
Figure 8-4. System Efficiency
90
60
4
Output Current(A)
Figure 8-3. System Efficiency
Efficiency(%)
4
Output Current(A)
Output Current(A)
50
75
70
65
60
VOUT=4.2V
VOUT=8.4V
VOUT=12.6V
VOUT=16.8V
55
50
0
0.01
0.02
0.03
0.04
0.05
0
0.01
Output Current(A)
VIN = 5 V EN_OOA = 0b
0.02
0.03
0.04
0.05
Output Current(A)
VOUT = System voltage
Figure 8-5. Light Load System Efficiency
VIN = 12 V EN_OOA = 0b
VOUT = System voltage
Figure 8-6. Light Load System Efficiency
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8.7 Typical Characteristics (continued)
90
98
85
96
94
Efficiency(%)
Efficiency(%)
80
75
70
65
60
90
88
86
84
VOUT=4.2V
VOUT=8.4V
VOUT=12.6V
VOUT=16.8V
55
92
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
82
50
80
0
0.01
0.02
0.03
0.04
0.05
0
1
2
3
VIN = 20 V EN_OOA = 0b
VOUT = System voltage
VBAT = 4 V
98
98
96
96
94
94
92
92
90
88
86
84
6
7
8
9
10
CCM 800 kHz
90
88
86
84
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
82
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
82
80
80
0
1
2
3
4
5
6
7
8
9
0
10
1
2
VBAT = 8 V
3
4
5
6
7
8
9
10
Output Current(A)
Output Current(A)
CCM 800 kHz
VBAT = 12 V
Figure 8-9. OTG Efficiency with 2S Battery
CCM 800 kHz
Figure 8-10. OTG Efficiency with 3S Battery
98
100
96
95
94
90
92
Efficiency(%)
Efficiency(%)
5
Figure 8-8. OTG Efficiency with 1S Battery
Efficiency(%)
Efficiency(%)
Figure 8-7. Light Load System Efficiency
90
88
86
84
VOTG=5V
VOTG=9V
VOTG=15V
VOTG=20V
82
80
85
80
75
70
65
VBUS=20V
VBUS=15V
60
0
1
2
3
4
5
6
7
8
9
10
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Output Current(A)
VBAT = 16 V
0.1
Output Current(A)
CCM 800 kHz
VBAT = 8.4 V
Figure 8-11. OTG Efficiency with 4S Battery
22
4
Output Current(A)
Output Current(A)
VOUT = VBUS
Figure 8-12. PTM Mode Ligh Load System Efficiency
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8.7 Typical Characteristics (continued)
100
1.6
99
1.4
1.2
1
97
0.8
96
0.6
Error (%)
Efficiency(%)
98
95
94
0.4
0.2
0
-0.2
93
-0.4
92
VIN=5V
VIN=9V
VIN=15V
VIN=20V
-0.6
VBUS=20V
VBUS=15V
91
-0.8
90
-1
0
1
2
3
4
5
6
7
8
9
10
3
5
7
Output Current(A)
VBAT = 8.4 V
9
11
13
15
17
19 20
Charge Voltage setting(V)
VOUT = VBUS
ICHG = 1024 mA
Figure 8-13. PTM Mode Heavy Load System Efficiency
CCM 800 kHz
Figure 8-14. Battery Voltage Regulation Accuracy
2
3
2.5
1.5
2
1
Error (%)
Error (%)
1.5
0.5
0
-0.5
1
0.5
0
-0.5
-1
VBAT=3.7V
VBAT=7.4V
VBAT=11.1V
VBAT=14.8V
-1.5
VIN=5V
VIN=9V
VIN=15V
VIN=20V
-1
-1.5
-2
-2
3
5
7
9
11
13
15
17
19 20
3
5
ICHG = 1024 mA
CCM 800 kHz
7
9
11
13
15
17
19 20
VSYS_MIN setting(V)
VINDPM setting(V)
IBUS = 100 mA
Figure 8-15. Input Voltage(VINDPM) Regulation Accuracy
VBAT = 0.5 V
CCM 800 kHz
EN_OOA = 0b
Figure 8-16. Minimum System Voltage Regulation Accuracy
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9 Detailed Description
9.1 Overview
The BQ25723 is a narrow VDC buck-boost charger controller for portable electronics such as notebook,
detachable, ultrabook, tablet, and other mobile devices with rechargeable batteries. It provides seamless
transition between different converter operation modes (buck, boost, or buck-boost), fast transient response,
and high light load efficiency.
The BQ25723 supports a wide range of power sources, including USB-C PD ports, legacy USB ports, traditional
AC-DC adapters, and so forth. It takes input voltage from 3.5 V to 26 V and charges a battery of 1 to 4 cells in
series. In the absence of an input source, the BQ25723 supports the USB On-the-Go (OTG) function from a 1- to
4-cell battery to generate an adjustable 3 V to 24 V at the USB port with 8-mV resolution.
When only the battery powers the system and no external load is connected to the USB OTG port, the BQ25723
provides the Vmin Active Protection (VAP) feature. In VAP operation, the BQ25723 first charges up the voltage
of the input decoupling capacitors at VBUS to store a certain amount of energy. During the system peak power
spike, the huge current drawn from the battery introduces a larger voltage drop across the impedance from
the battery to the system. The energy stored in the input capacitors will supplement the system, to prevent the
system voltage from dropping below the minimum system voltage and leading the system to a black screen. This
VAP is designed to absorb system power peaks during the periods of high demand to improve system turbo
performance, which is highly recommended by Intel for the platforms with a 1S~2S battery.
The BQ25723 features Dynamic Power Management (DPM) to limit input power and avoid AC adapter
overloading. During battery charging, as system power increases, charging current is reduced to maintain total
input current below adapter rating. If system power demand temporarily exceeds adapter rating, the BQ25723
supports the NVDC architecture to allow battery discharge energy to supplement system power.
The BQ25723 monitors adapter current, battery current, and system power. The flexibility of the programmable
PROCHOT output goes directly to the CPU for throttling back when needed.
The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping
occurs in a timely fashion so that the device(s) connected to the dock never experience momentary power loss
or glitching. The device integrates FRS with compliance to the USB-C PD specification.
The TI patented switching frequency dithering pattern can significantly reduce EMI noise over the entire
conductive EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide
flexibility for different applications to simplify EMI noise filter design.
In order to be compliant with Intel IMVP8 / IMVP9, the BQ25723 includes a PSYS function to monitor the total
platform power from the adapter and battery. Besides PSYS, it provides both an independent input current buffer
(IADPT) and a battery current buffer (IBAT) with highly accurate current sense amplifiers. If the platform power
exceeds the available power from the adapter and battery, a PROCHOT signal is asserted to the CPU so that
the CPU optimizes its performance to the power available to the system.
The host controls input current, charge current, and charge voltage registers with high resolution, high accuracy
regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.
24
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9.2 Functional Block Diagram
CHRG_OK
4
CHRG_OK_DRV
50ms Rising
Deglitch
3.5V
VBUS
Block Diagram
50ms Rising
Deglitch
** programmable in register
EN_REGN
1
VREF_CMP**
CMP_DEG**
ACOV
26.8V
14
CMPIN
15
CMPOUT
VREF_VINDPM or VREF_VOTG
VDDA
16
VSNS_VINDPM or VSYS_VOTG
EN_HIZ
ILIM_HIZ
6
17
Decoder
2
ACN
3
COMP2
VREF_ILIM
VSYS
VREF_IIN_DPM, or VREF_IOTG
ACP
COMP1
20X/40X
VSNS_IIN_DPM, or VSNS_IOTG
LDO Mode
Gate Control
21
BATDRV
30
BTST1
31
HIDRV1
32
SW1
VSYS-10V
20X/40X
IADPT
8
IBAT
9
VSNS_IOTG
VSNS_IIN
VSNS_ICHG
Loop Selector
and
Error Amplier
VSNS_IDCHG
PWM
7
16X/8X
EN_REGN
VREF_ICHG
SRP
20
SRN
19
28
VDDA
REGN
EN_HIZ
VSNS_ICHG
16X/8X
EN_LEARN
EN_LDO
EN_CHRG
VREF_VBAT
EN_OTG
VSNS_VBAT
VSYS
REGN
LDO
22
PWM
Driver
Logic
29
LODRV1
27
PGND
25
BTST2
24
HIDRV2
23
SW2
26
LODRV2
Decoder
18
CELL_BATPRESZ
Processor
Hot
11
PROCHOT
VREF_VSYS
VSNS_VSYS
VSNS_VSYS
ACN
PSYS
10
VSNS_VBAT
VSNS_ICHG
(ACP-ACN)
SRN
VSNS_IDCHG
VSNS_IIN_DPM
(SRN-SRP)
Over Current
Over Voltage
Detect
VSNS_VINDPM
SDA
SCL
OTG/VAP/FRS
12
13
5
I2C
Interface
ChargeOpon0()
ChargeOp on1()
ChargeOpon2()
ChargeCurrent()
ChargeVoltage()
InputCurrent()
InputVoltage()
MinSysVoltage()
OTGVoltage()
OTGCurrent()
EN_HIZ
EN_LEARN
BATPRESZ
EN_LDO
EN_CHRG
CELL_CONFIG
EN_OTG
VREF_VSYS
Loop
Regulaon
Reference
VREF_VBAT
VREF_ICHG
VREF_IIN_DPM
IADPT
VREF_VINDPM
IBAT
VREF_IOTG
VSYS
VREF_VOTG
CHRG_OK
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9.3 Feature Description
9.3.1 Power-Up Sequence
The device powers up from the higher voltage of VBUS or VBAT through integrated power selector. The charger
starts POR (power on reset) when VBUS exceeds VVBUS_UVLOZ or VBAT exceeds VVBAT_UVLOZ. 5 ms after either
VBUS or VBAT becomes valid, the charger resets all the registers to the default state. Another 5 ms later, the
user registers become accessible to the host.
Power up sequence when the charger is powered up from VBUS:
•
•
•
•
After VBUS above VVBUS_UVLOZ, enable 6-V LDO REGN pin and VDDA pin voltage increase accordingly.
CHRG_OK pin goes HIGH and the AC_STAT is configured to 1.
After passing VBUS qualification, the REGN voltage is setup. VINDPM is detected in VBUS steady state
voltage and IIN_DPM is detected at ILIM_HIZ pin steady state voltage.
Battery CELL configuration is read at CELL_BATPRESZ pin voltage and compared to VDDA to determine
cell configuration. Corresponding the default value of ChargeVoltage register (REG0x05/04()), ChargeCurrent
register (Reg0x03/02), VSYS_MIN register (Reg0x0D/0C) and SYSOVP threshold are loaded.
Converter powers up.
Power up sequence when the charger is powered up from VBAT:
•
•
•
•
•
•
If only battery is present and the voltage is above VVBAT_UVLOZ , charger wakes up and the BATFET is turned
on and connecting the battery to system.
By default, the charger is in low power mode (EN_LWPWR = 1b) with lowest quiescent current. The
REGN LDO stays off. The Quiescent current is minimized. PROCHOT is available through the independent
comparator by setting EN_PROCHOT_LPWR=1b.
The adapter present comparator is activated, to monitor the VBUS voltage.
SDA and SDL lines stand by waiting for host commands.
Device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT
buffer through setting EN_IBAT=1b to monitor discharge current. The PSYS, PROCHOT or the independent
comparator also can be enabled by the host.
In performance mode, the REGN LDO is always available to provide an accurate reference and gate drive
voltage for the converter.
9.3.2 Vmin Active Protection (VAP) with Battery only
When operating in battery only mode, high system peak power can cause the VSYS to drop below the minimum
system voltage due to impedance of battery pack, charging sense resistor and BATFET. Device incorporates
VAP mode to help supplement the system during high peak power events by releasing energy previously stored
in the input capacitor. While the system is operating with normal power loads, the charger can be configured
to store energy in the input capacitors by charging them up to a programamble voltage level. During these
high system power spikes, the energy stored in the input capacitors will supplement the system, to prevent the
system voltage from dropping below the minimum system voltage. The VAP mode can help achieve much better
Turbo performance for Intel CPU under battery only condition. Please contact factory for more detail information
about VAP mode.
9.3.3 Two-Level Battery Discharge Current Limit
To prevent the triggering of battery overcurrent protection and avoid battery wear-out, two battery current
limit levels (IDCHG_TH1 and IDCHG_TH2) PROCHOT profiles are recommended to be enabled. Define
IDCHG_TH1 through REG0x39h[7:2], IDCHG_TH2 is set through REG0x3Ch[5:3] for fixed percentage of
IDCHG_TH1. There are dedicated de-glitch time setting registers(IDCHG_DEG1 and IDCHG_DEG2) for both
IDCHG_TH1 and IDCHG_TH2.
• When battery discharge current is continuously higher than IDCHG_TH1 for more than IDCHG_DEG1 deglitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH1,
then the time counter resets automatically. STAT_IDCHG1 bit will be set to 1 after PROCHOT is triggered.
Set PP_IDCHG1=1b to enable IDCHG_TH1 for triggering PROCHOT.
26
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When battery discharge current is continuously higher than IDCHG_TH2 for more than IDCHG_DEG2 deglitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH2,
then the time counter resets automatically. STAT_IDCHG2 bit will be set to 1 after PROCHOT is triggered.
Set PP_IDCHG2=1b to enable IDCHG_TH2 for triggering PROCHOT.
IDCHG_TH2
IDCHG_TH1
0A
/PROCHOT
IDCHG_DEG1
IDCHG_DEG1
IDCHG_DEG2
IDCHG_DEG2
Figure 9-1. Two-Level Battery Discharging Current Trigger PROCHOT Diagram
9.3.4 Fast Role Swap Feature
Fast Role Swap (FRS) means charger quickly swaps from power sink role to power source role to provide an
OTG output voltage to accessories when the original power source is disconnected. This feature is defined to
transfer the charger from forward mode to OTG mode quickly without dropping VBUS voltage per USB-C PD
specification requirement.Please contact factory for more detail information about FRS mode.
9.3.5 CHRG_OK Indicator
CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the
following conditions are valid:
•
•
•
VBUS is above VVBUS_CONVEN
VBUS is below VACOV_FALL
No faults triggered such as: SYSOVP/SYSUVP/ACOC/TSHUT/BATOVP/BATOC/force converter off.
9.3.6 Input and Charge Current Sensing
The charger supports 10 mΩ and 5 mΩ for both input current sensing and charge current sensing. By default, 10
mΩ is enabled by POR setting RSNS_RAC=0b and RSNS_RSR=0b, if 5 mΩ sensing is used please configure
RSNS_RAC=1b and RSNS_RSR=1b. Lower current sensing resistor can help improve overall charge efficiency
especially under heavy load. At same time PSYS,IADPT,IBAT pin accuracy and IINDPM/ICHG/IOTG regulation
accuracy get worse due to effective signal reduction in comparison to error signal components.
When RSNS_RAC=RSNS_RSR=0b and 10 mΩ is used for both input and charge current sensing, the precharge current clamp is 384 mA (2 A for 1S if VSYS_MIN>VBAT>3 V ), the maximum IIN_HOST setting is
clamped at 6.35 A, and the maximum charge current is clamped at 8.128 A.
When RSNS_RAC=RSNS_RSR=1b and 5 mΩ is used for both input and charge current sensing, the charger
will internally compensate pre-charge current clamp to be 384 mA (2 A for 1S if VSYS_MIN>VBAT>3 V )
under 5-mΩ current sensing which keeps consistent between 10 mΩ and 5 mΩ. Under 5-mΩ current sensing
application charge current range is doubled to 16.256 A. Based on EN_FAST_5MOHM register bit status and
IADPT pin resistor the maximum input current can be configured referring to Table 9-1:
For defined current sense resistors (10 mΩ/5 mΩ), PSYS function is still valid when unsymmetrical input current
sense and charge current sense resistors are used. But RSNS_RAC and RSNS_RSR bit status have to be
consistent with practical resistors used in the system.
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Table 9-1. Maximum Input Current Limit Configuration Table
INDUCTANCE (IADPT Pin
Resistance)
EN_FAST_5MOHM
RSR_RAC BIT
MAXIMUM INPUT CURRENT LIMIT
(IINDPM)
Xb
RSNS_RAC=0b
6.35 A
1b
RSNS_RAC=1b
6.35 A
0b
RSNS_RAC=1b
10 A
Xb
RSNS_RAC=0b
6.35 A
Xb
RSNS_RAC=1b
10 A
1.0 uH(90.9 kΩ)
1.5 uH(121 kΩ)
2.2 uH(137 kΩ)
3.3 uH(169 kΩ)
9.3.7 Input Voltage and Current Limit Setup
The actual input current limit being adopted by the device is the lower setting of IIN_DPM and ILIM_HIZ pin.
Register IIN_DPM input current limit setting will reset for below scenarios:
•
•
When adapter is removed (CHRG_OK is not valid). Note when adapter is removed IIN_HOST will be reset
one time to 3.25 A, under battery only host is still able to overwrite IIN_HOST register with a new value. If the
adapter plug back in and CHRG_OK is pulled up, IIN_HOST will not be reset again.
When input current optimization (ICO) is executed (EN_ICO_MODE=1b), the charger will automatically detect
the optimized input current limit based on adapter output characteristic. The final IIN_DPM register setting
could be different from IIN_HOST after ICO.
The voltage regulation loop of the charger regulates the input voltage to prevent the input adapter collapsing.
The VINDPM threshold should be configured based on no load input voltage level.Charger initiates a VBUS
voltage measurement without any load (VBUS at no load) right before the converter is enabled. The default
VINDPM threshold is VBUS at no load – 1.28 V. Host can adjust VINDPM threshold after device POR through
InputVoltage register(0x0B/0Ah[]), range from 3.2V to 19.52V with LSB 64mV.
After input current and voltage limits are set, the charger device is ready to power up. The host can always
program the input current and voltage limit after the charger being powered up based on the input source type.
9.3.8 Battery Cell Configuration
CELL_BATPRESZ pin is biased with a resistor divider from VDDA to GND. After REGN LDO is activated (VDDA
rise up), the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. No external
cap is allowed at CELL_BATPRESZ pin. When CELL_BATPRESZ pin is pulled down to GND (because of
battery removal) at the beginning of startup process, VSYS_MIN = 3.6 V and SYS_OVP = 25 V and Maximum
charge voltage (REG0x15) follow 1 cell default setting 4.2 V. . Refer to Table 9-2 for CELL_BATPRESZ pin
configuration typical voltage for swept cell count.
Table 9-2. Battery Cell Configuration
CELL COUNT
PIN VOLTAGE w.r.t.
VDDA
CHARGEVOLTAGE
(REG0x05/04h)
SYSOVP
VSYS_MIN
VSYS/VBAT
ADC OFFSET
4S
75%
16.800 V
19.5 V
12.3 V
2.88 V
3S
55%
12.600 V
19.5 V
9.2 V
2.88 V
2S
40%
8.400 V
12 V
6.6 V
2.88 V
1S
25%
4.200 V
6V
3.6 V
2.88 V
Battery removal
0%
4.200 V
25 V
3.6 V
2.88 V
9.3.9 Device HIZ State
When input source is present, the charger can enter HIZ mode (converter shuts off) when ILIM_HIZ pin voltage
is below 0.4 V or EN_HIZ is set to 1b. The charger is in the low quiescent current mode with REGN LDO
enabled, ADC circuits are disactivated to reduce quiescent current. In order to exit HIZ mode, ILIM_HIZ pin
voltage has to be higher than 0.8 V and EN_HIZ bit has to be set to 0b.
28
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9.3.10 USB On-The-Go (OTG)
The device supports USB OTG operation to deliver power from the battery to other portable devices through
USB port. The OTG mode output voltage is set in OTGVoltage register REG0x07/06() with 8-mV LSB range from
3.0 V to 24 V. The OTG mode output current is set in OTGCurrent register REG0x09() with 50-mA LSB range
from 0 A to 6.35 A under 10-mΩ input current sensing. Both OTG voltage and OTG current are qualified for
USB-C™ programed power supply (PPS) specification in terms of resolution and accuracy. The OTG mode can
be enabled following below steps:
•
•
•
•
Set target OTG current limit in OTGCurrent register, VBUS is below VVBUS_CONVENZ.
Set OTG_VAP_MODE = 1b and EN_OTG = 1b.
OTG/VAP/FRS pin is pulled high.
15 ms after the above conditions are valid, converter starts and VBUS ramps up to target voltage. CHRG_OK
pin goes HIGH if OTG_ON_CHRGOK= 1b.
OTG/VAP/FRS pin is used as multi-function to enable OTG, VAP and FRS mode.
9.3.11 Converter Operation
The charger operates in buck, buck-boost and boost mode under different VBUS and VSYS combination. The
buck-boost can operate seamlessly across the three operation modes. The 4 main switches operating status
under continuous conduction mode (CCM) are listed below for reference.
Table 9-3. MOSFET Operation
MODE
BUCK
BUCK-BOOST
BOOST
Q1
Switching
Switching
ON
Q2
Switching
Switching
OFF
Q3
OFF
Switching
Switching
Q4
ON
Switching
Switching
9.3.12 Inductance Detection Through IADPT Pin
The charger reads the inductance value through the resistance tied to IADPT pin before the converter starts up.
The resistances recommended for 1-μH (1200 kHz), 2.2-μH (800 kHz), and 3.3-μH (800 kHz) inductance are
90.9 kΩ, 137 kΩ, 169 kΩ, respectively. A surface mount chip resistor with ±2% or better tolerance must to be
used for an accurate inductance detection. In order to detect the correct IADPT pin pull down resistance and get
rid of disturbance from external circuit, before converter startup all the additional sensing circuit connecting to
IADPT pin should be high impedance.
Table 9-4. Inductor Detection through IADPT Resistance
INDUCTOR IN USE
RESISTOR ON IADPT PIN
1 µH (recommended for 1200 kHz)
90.9 kΩ
1.5 µH (recommended for 800 kHz)
121 kΩ
2.2 µH (recommended for 800 kHz)
137 kΩ or 140 kΩ
3.3 µH (recommended for 800 kHz)
169 kΩ
9.3.13 Converter Compensation
The charger employs two compensation pins COMP1 and COMP2 for converter compensation purpose,
appropriate RC network is needed to guarantee converter steady state and transient operation. Under different
operation frequency corresponding RC network value needs to be configured respectively as shown in below
table. The definition of these RC components can be referred to Figure 9-2. It is not recommended to change the
compensation network value due to the complexity of various operation modes.
Table 9-5. Compensation Configuration
COMPONENT
VALUE
INDUCTOR
COMP1 R1
COMP1 C11
COMP1 C12
COMP2 R2
COMP2 C21
COMP2 C22
800 kHz
3.3 μH
16.9 kΩ
3.3 nF
33 pF
15 kΩ
1200 pF
15 pF
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Table 9-5. Compensation Configuration (continued)
COMPONENT
VALUE
INDUCTOR
COMP1 R1
COMP1 C11
COMP1 C12
800 kHz
2.2 μH
16.9 kΩ
3.3 nF
800 kHz
1.5 μH
16.9 kΩ
3.3 nF
1200 kHz
1.0 μH
16.9 kΩ
3.3 nF
COMP1
COMP2 C21
COMP2 C22
33 pF
10 kΩ
1200 pF
15 pF
33 pF
6.8 kΩ
1200 pF
15 pF
33 pF
5 kΩ
1200 pF
15 pF
COMP2
R1
C12
COMP2 R2
R2
C22
C11
C21
Figure 9-2. Compensation RC Network
9.3.14 Continuous Conduction Mode (CCM)
With sufficient charge or system current, the inductor current does not cross 0 A, which is defined as CCM. The
controller starts a new cycle with ramp coming up from 200 mV. As long as the error amplifier output voltage
is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error
amplifier output voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle,
ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during
transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the
body-diode of the low-side power MOSFET conducts the inductor current.
During CCM, the inductor current always flows. Having the LSFET turn-on when the HSFET is off keeps the
power dissipation low and allows safe charging at high currents.
9.3.15 Pulse Frequency Modulation (PFM)
In order to improve converter light-load efficiency, BQ25723 switches to PFM operation at light load. The
effective switching frequency will decrease accordingly when system load decreases. The minimum frequency
can be limited to 25 kHz when the OOA feature is enabled (EN_OOA=1b) to avoid audible noise.
9.3.16 Switching Frequency and Dithering Feature
Normally, the IC switches in fixed frequency which can be adjusted through PWM_FREQ register bit. The
Charger also support frequency dithering function to improve EMI performance. This function is disabled by
default with setting EN_DITHER=00b. It can be enabled by setting EN_DITHER=01/10/11b, the switching
frequency is not fixed when dithering is enabled. It varies within determined range by EN_DITHER setting,
01/10/11b is corresponding to ±2%/4%/6% switching frequency. Please contact factory for more detail
information.
9.3.17 Current and Power Monitor
9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
A high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, or
output current during OTG (IADPT) and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the
differential voltage across ACP and ACN. IBAT voltage is 8×/16× of the differential across SRP and SRN. After
input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current
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monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be
achieved.
•
•
•
VIADPT = 20 or 40 × (VACP – VACN) during forward mode, or 20 or 40 × (VACN – VACP) during reverse OTG
mode.
VIBAT = 8 or 16 × (VSRP – VSRN) during forward charging mode.
VIBAT = 8 or 16 × (VSRN – VSRP) during forward supplement mode, reverse OTG mode and battery only
discharge scenario.
A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An
additional RC filter is optional. Note that RC filtering has additional response delay. The CSA output voltage is
clamped at 3.3 V.
9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
The charger monitors total system power. During forward mode, the input adapter powers the system. During
reverse OTG mode and battery only discharge scenario, the battery powers the system and VBUS output. The
ratio of PSYS pin output current and total system power, KPSYS, can be programmed in PSYS_RATIO register
bit with default 1 μA/W. The input and charge sense resistors (RAC and RSR) are selected in RSNS_RAC bit and
RSNS_RSR bit. By default, PSYS_CONFIG=00b and PSYS voltage can be calculated with Equation 1, where
IIN>0 when the charger is in forward charging and IIN0 when
the battery is in charging and IBAT
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