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bq27742-G1
SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
bq27742-G1 Single-Cell Li-Ion Battery Fuel Gauge
with Programmable Hardware Protection
1 Features
3 Description
•
The Texas Instruments bq27742-G1 is a fuel gauge
for single-cell Li-Ion battery packs that uses patented
Impedance Track™ technology to deliver rate-,
temperature-, and aging-compensated predictions of
remaining battery capacity and system runtime with
highest accuracy. The device also includes a fully
integrated high-side protector that eliminates the
need for a separate Li-Ion protection circuit and
provides a full suite of high-accuracy fault detections
for overvoltage, undervoltage, overcurrent in charge,
overcurrent in discharge, and short-circuit in
discharge conditions. The hardware protection
functions
offer
built-in
data
flash-based
programmability, allowing simple reconfiguration of
existing devices for varying end equipment needs.
1
•
•
•
•
•
•
Battery Fuel Gauge and Protector for Single-Cell
Li-Ion Applications
Microcontroller Peripheral Provides:
– Precision 16-Bit, High-Side Coulomb Counter
with Low-Value Sense Resistor
(5 mΩ to 20 mΩ)
– External and Internal Temperature Sensors for
Battery Temperature Reporting
– Lifetime and Current Data Logging
– 64 Bytes of Non-Volatile Scratch Pad Flash
– SHA-1 Authentication Capability
Battery Fuel Gauging Based on Patented
Impedance Track™ Technology
– Models Battery Discharge Curve for Accurate
Time-To-Empty Predictions
– Automatically Adjusts for Aging, SelfDischarge, and Temperature- and RateInduced Effects on Battery
Integrated High-side NMOS Protection FET Drive
Hardware-based Safety and Protection:
– Overvoltage (OVP)
– Undervoltage (UVP)
– Overcurrent in Charge (OCC)
– Overcurrent in Discharge (OCD)
– Short-Circuit in Discharge (SCD)
I2C and HDQ Interface Formats for
Communication with Host System
Ultra-Compact, 15-Ball NanoFree™ DSBGA
The fuel gauge provides information such as
remaining battery capacity (mAh), state-of-charge
(%), runtime to empty (minutes), voltage (mV),
current (mA), and temperature (°C), as well as
recording vital parameters throughout the lifetime of
the battery. The device also supports interrupts to the
host to indicate detection of a variety of important
battery conditions to the system.
The DSBGA is a 15-ball package (2.78 mm ×
1.96 mm) that is ideal for space-constrained
applications.
Device Information(1)
PART NUMBER
Smartphones
Tablets
Handheld Terminals
MP3 and Multimedia Players
Portable Gaming
BODY SIZE (NOM)
YZF (15)
BQ27742YZFT-G1
2.78 mm × 1.96 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
BQ27742YZFR-G1
Simplified Schematic
VBAT
VPACK
R SENSE
RSRN
C SRN
RSRP
CSRP
CDIFF
RCHG
RDSG
R PACKP
RVPWR
VPWR
RBAT
SRN
C VPWR
BAT
SRP
CBAT
REG25
CREG25
R THERM
CTHERM
PACKP
TS
CHG
NC
DSG
RC2
SDA
SDA
VSS
SCL
SCL
CPACKP
HDQ
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq27742-G1
SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Power-On Reset........................................................ 7
2.5-V LDO Regulator ............................................... 7
Charger Attachment and Removal Detection ........... 8
CHG and DSG FET Drive ......................................... 8
Overvoltage Protection (OVP) .................................. 8
Undervoltage Protection (UVP)............................... 8
Overcurrent in Discharge (OCD)............................. 9
Overcurrent in Charge (OCC) ................................. 9
Short-Circuit in Discharge (SCD) ............................ 9
Low Voltage Charging............................................. 9
Internal Temperature Sensor Characteristics ......... 9
High-Frequency Oscillator..................................... 10
Low-Frequency Oscillator ..................................... 10
Integrating ADC (Coulomb Counter)
Characteristics ......................................................... 10
6.19 ADC (Temperature and Cell Voltage)
Characteristics ......................................................... 10
6.20 Data Flash Memory Characteristics...................... 11
6.21 Timing Requirements ............................................ 11
6.22 Typical Characteristics .......................................... 13
7
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Battery Parameter Measurements ..........................
Communications .....................................................
Standard Data Commands .....................................
Extended Data Commands .....................................
15
15
16
18
21
22
24
26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
9
Power Supply Recommendation ........................ 35
9.1 Power Supply Decoupling ....................................... 35
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 37
11 Device and Documentation Support ................. 38
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receive Notification of Documentation Updates...
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (February 2016) to Revision D
Page
•
Changed Detailed Description ............................................................................................................................................. 15
•
Changed Standard Commands ........................................................................................................................................... 25
•
Added Receive Notification of Documentation Updates ...................................................................................................... 38
Changes from Revision B (August 2015) to Revision C
Page
•
Changed occurrences of the package label "CSP" to "DSBGA" ........................................................................................... 1
•
Changed Integrating ADC (Coulomb Counter) Characteristics ........................................................................................... 10
Changes from Revision A (December 2014) to Revision B
Page
•
Changed Pin Functions ......................................................................................................................................................... 3
•
Changed Absolute Maximum Ratings ................................................................................................................................... 6
•
Changed Recommended Operating Conditions..................................................................................................................... 7
•
Changed Functional Block Diagram .................................................................................................................................... 15
•
Changed VVPWR to VBAT in Figure 15 .................................................................................................................................... 19
•
Changed "VPWR" to "VBAT" in OVERVOLTAGE Mode and UNDERVOLTAGE Mode........................................................... 20
2
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SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
5 Pin Configuration and Functions
1
2
3
A
SRP
CHG
DSG
B
SRN
NC
PACKP
C
VPWR
BAT
SDA
D
VSS
HDQ
RC2
E
REG25
TS
SCL
Not to scale
Pin Functions
NUMBER
NAME
I/O
DESCRIPTION
A1
SRP
I
Analog input pin connected to the internal coulomb counter where SRP is nearest the PACK+
connection. Connect to a sense resistor.
A2
CHG
O
External high side N-channel charge FET driver
A3
DSG
O
External high side N-channel discharge FET driver
B1
SRN
I
Analog input pin connected to the internal coulomb counter where SRN is nearest the CELL+
connection. Connect to a sense resistor.
B2
NC
IO
B3
PACKP
I
C1
VPWR
—
C2
BAT
I
C3
SDA
IO
Slave I2C serial communications data line for communication with system. Open-drain I/O.
Use with a 10-kΩ pullup resistor (typical).
Not used. Reserved for future GPIO. It is recommended to connect to GND.
Pack voltage measurement input for protector operation
Power input. Decouple with 0.1-µF ceramic capacitor to VSS.
Cell-voltage measurement input. ADC input
D1
VSS
—
Device ground
D2
HDQ
I/O
HDQ serial communications line. Open-drain
D3
RC2
IO
General purpose IO. Push-pull output
E1
REG25
—
Regulator output and bq27742-G1 processor power. Decouple with 1.0-µF ceramic capacitor
to VSS.
E2
TS
I
E3
SCL
IO
Pack thermistor voltage sense (use 103AT-type thermistor). ADC input
Slave I2C serial communications clock input line for communication with system. Use with a
10-kΩ pullup resistor (typical).
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SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
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Table 1. Hardware Protection Thresholds (1)
OVERVOLTAGE
PROTECTION (VOVP)
UNDERVOLTAGE
PROTECTION (VUVP)
OVERCURRENT IN
CHARGE (VOCC)
6 mV
13 mV
4.450 V
2.438 V
18 mV
28 mV
6 mV
13 mV
4.425 V
2.422 V
18 mV
28 mV
6 mV
13 mV
4.400 V
2.409 V
18 mV
28 mV
6 mV
13 mV
4.375 V
2.395 V
18 mV
28 mV
6 mV
13 mV
4.350 V
2.381 V
18 mV
28 mV
(1)
4
OVERCURRENT IN
DISCHARGE (VOCD)
SHORT-CIRCUIT IN
DISCHARGE (VSCD)
14 mV
24 mV
34 mV
73 mV
44 mV
53 mV
63 mV
73 mV
148 mV
83 mV
13 mV
23 mV
33 mV
73 mV
43 mV
53 mV
63 mV
72 mV
148 mV
83 mV
13 mV
23 mV
33 mV
72 mV
43 mV
52 mV
62 mV
72 mV
147 mV
82 mV
13 mV
23 mV
33 mV
72 mV
42 mV
52 mV
62 mV
72 mV
146 mV
82 mV
13 mV
23 mV
32 mV
71 mV
42 mV
52 mV
62 mV
71 mV
145 mV
81 mV
Production tested in the following configuration: VOVP = 4.450 V, VUVP = 2.438 V, VOCC = 28 mV, VOCD = 83 mV, and VSCD = 148 mV.
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SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
Table 1. Hardware Protection Thresholds(1) (continued)
OVERVOLTAGE
PROTECTION (VOVP)
UNDERVOLTAGE
PROTECTION (VUVP)
OVERCURRENT IN
CHARGE (VOCC)
6 mV
13 mV
4.325 V
2.368 V
18 mV
27 mV
6 mV
13 mV
4.300 V
2.354 V
18 mV
27 mV
6 mV
13 mV
4.275 V
2.340 V
18 mV
27 mV
OVERCURRENT IN
DISCHARGE (VOCD)
SHORT-CIRCUIT IN
DISCHARGE (VSCD)
13 mV
22 mV
32 mV
71 mV
42 mV
52 mV
61 mV
71 mV
144 mV
81 mV
13 mV
22 mV
32 mV
71 mV
42 mV
51 mV
61 mV
70 mV
143 mV
80 mV
13 mV
22 mV
32 mV
70 mV
41 mV
51 mV
60 mV
70 mV
143 mV
80 mV
Table 2. Hardware Protection Delays
OVERVOLTAGE
PROTECTION DELAY
(tOVP)
UNDERVOLTAGE
PROTECTION DELAY
(tUVP)
OVERCURRENT IN
CHARGE DELAY (tOCC)
OVERCURRENT IN
DISCHARGE DELAY
(tOCD)
SHORT-CIRCUIT IN
DISCHARGE DELAY
(tSCD)
1.00 s
31.25 ms
7.81 ms
31.25 ms
312.50 µs
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SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VVPWR
Power input range
–0.3
5.5
V
VREG25
Supply voltage range
–0.3
2.75
V
PACKP input pin
–0.3
5.5
V
VPACKP
PACK+ input when external 2-kΩ resistor is in series with PACKP input pin (see
Figure 19 and Figure 20)
–0.3
28
V
VOUT
Voltage output pins (DSG, CHG)
–0.3
10
V
VIOD1
Push-pull IO pins (RC2)
–0.3
2.75
V
VIOD2
Open-drain IO pins (SDA, SCL, HDQ, NC)
–0.3
5.5
V
VBAT
BAT input pin
–0.3
5.5
V
VI
Input voltage range to all other pins (SRP, SRN)
–0.3
5.5
V
VTS
Input voltage range for TS
–0.3
2.75
V
TA
Operating free-air temperature
–40
85
°C
TF
Functional temperature
–40
100
°C
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
VVPWR
Supply voltage
TEST CONDITION
No operating restrictions
No FLASH writes
External input capacitor for internal
Nominal capacitor values
LDO between VPWR and VSS
specified. Recommend a 5%
External output capacitor for
ceramic X5R type capacitor
internal LDO between REG25 and located close to the device
VSS
CVPWR
CREG25
MIN
NOM
MAX
2.8
5.0
2.45
2.8
0.47
UNIT
V
0.1
µF
1.0
µF
ICC
NORMAL operating mode
current (1) (2) (VPWR)
Fuel gauge in NORMAL mode
ILOAD > Sleep Current with charge
pumps on (FETs on)
167
µA
ISLP
Fuel gauge in SLEEP+ mode.
SLEEP mode current (1) (2) (VPWR) ILOAD < Sleep Current with charge
pumps on (FETs on)
88
µA
IFULLSLP
FULLSLEEP mode current (1) (2)
(VPWR)
Fuel gauge in SLEEP mode.
ILOAD < Sleep Current with charge
pumps on (FETs on)
40
µA
(1)
(2)
6
All currents are specified with charge pump on (FETs on).
All currents are continuous average over 5-second period.
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Recommended Operating Conditions (continued)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
Fuel gauge in SHUTDOWN mode.
UVP tripped with fuel gauge and
protector turned off (FETs off)
VVPWR = 2.5 V
TA = 25°C
NOM
MAX
UNIT
0.1
0.2
µA
ISHUTDOWN
SHUTDOWN mode current (1) (2)
(VPWR)
TA = –40°C to 85°C
0.5
µA
VOL
Output voltage low (SCL, SDA,
HDQ, NC, RC2)
IOL = 1 mA
0.4
V
VOH(OD)
Output voltage high (SDA, SCL,
HDQ, NC, RC2)
External pullup resistor connected
to VREG25
VIL
Input voltage low (SDA, SCL,
HDQ, NC)
–0.3
0.6
V
VIH(OD)
Input voltage high (SDA, SCL,
HDQ, NC)
1.2
5.5
V
VA1
Input voltage range (TS)
VSS – 0.125
2
V
VA2
Input voltage range (BAT)
VSS – 0.125
5
V
VVPWR –
0.125
VVPWR +
0.125
V
VA3
Input voltage range (SRP, SRN)
Ilkg
Input leakage current (I/O pins)
tPUCD
Power-up communication delay
VREG25 – 0.5
V
0.3
250
µA
ms
6.4 Thermal Information
bq27742-G1
THERMAL METRIC (1)
YZF (DSBGA)
UNIT
15 PINS
RθJA
Junction-to-ambient thermal resistance
70
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
17
°C/W
RθJB
Junction-to-board thermal resistance
20
°C/W
ψJT
Junction-to-top characterization parameter
1
°C/W
ψJB
Junction-to-board characterization parameter
18
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
NA
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Power-On Reset
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Increasing battery voltage input at VREG25
VHYS
Power-on reset hysteresis
MIN
TYP
MAX
UNIT
2.09
2.20
2.31
V
45
115
185
mV
MIN
TYP
MAX
UNIT
2.3
2.5
2.6
6.6 2.5-V LDO Regulator (1)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.8 V ≤ VVPWR ≤ 4.5 V,
IOUT (1) ≤ 16 mA
VREG25
(1)
Regulator output voltage 2.45 V ≤ VVPWR < 2.8 V (low
battery),
IOUT (1) ≤ 3 mA
TA = –40°C to
85°C
2.3
V
V
LDO output current, IOUT, is the sum of internal and external load currents.
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2.5-V LDO Regulator(1) (continued)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
ISHORT (2)
(2)
Short-circuit current limit
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
mA
TYP
MAX
UNIT
2.7
3.0
TA = –40°C to
85°C
VREG25 = 0 V
Assured by characterization. Not production tested.
6.7 Charger Attachment and Removal Detection
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCHGATT
Voltage threshold for charger attachment
detection
VCHGREM
Voltage threshold for charger removal
detection
MIN
0.5
1.0
V
V
6.8 CHG and DSG FET Drive
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 × VVPWR – 0.4
2 × VVPWR – 0.2
2 × VVPWR
V
VFETON
CHG and DSG FETs on
IL = 1 µA
TA = –40°C to 85°C
VFETOFF
CHG and DSG FETs off
TA = –40°C to 85°C
0.2
V
VFETRIPPLE (1)
CHG and DSG FETs on
IL = 1 µA
TA = –40°C to 85°C
0.1
VPP
tFETON
FET gate rise time
(10% to 90%)
CL = 4 nF
TA = –40°C to 85°C
No series resistance
67
140
218
μs
tFETOFF
FET gate fall time
(90% to 10%)
CL = 4 nF
TA = –40°C to 85°C
No series resistance
10
30
60
μs
(1)
Assured by characterization. Not production tested.
6.9 Overvoltage Protection (OVP)
TA = 25°C and CREG25 = 1.0 µF (unless otherwise noted)
PARAMETER
OVP detection voltage
threshold
VOVP
VOVPREL
OVP release voltage
tOVP
OVP delay time
MIN
TYP
MAX
TA = 25°C
TEST CONDITIONS
VOVP – 0.016
VOVP
VOVP + 0.016
TA = 0°C to 25°C
VOVP – 0.033
VOVP
VOVP + 0.030
TA = 25°C to 50°C
VOVP – 0.028
VOVP
VOVP + 0.024
TA = –40°C to 85°C
VOVP – 0.063
VOVP
VOVP + 0.045
TA = 25°C
VOVPREL – 0.022
VOVP – 0.215
VOVPREL + 0.022
TA = 0°C to 25°C
VOVPREL – 0.033
VOVP – 0.215
VOVPREL + 0.030
TA = 25°C to 50°C
VOVPREL – 0.028
VOVP – 0.215
VOVPREL + 0.024
TA = –40°C to 85°C
VOVPREL – 0.063
VOVP – 0.215
VOVPREL + 0.045
TA = –40°C to 85°C
tOVP – 5%
tOVP
tOVP + 5%
MIN
TYP
MAX
TA = 25°C
VUVP – 0.022
VUVP
VUVP + 0.022
TA = –5°C to 50°C
VUVP – 0.030
VUVP
VUVP + 0.030
TA = –40°C to 85°C
VUVP – 0.050
VUVP
VUVP + 0.050
UNIT
V
V
s
6.10 Undervoltage Protection (UVP)
TA = 25°C and CREG25 = 1.0 µF (unless otherwise noted)
PARAMETER
VUVP
8
UVP detection voltage
threshold
TEST CONDITIONS
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UNIT
V
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Undervoltage Protection (UVP) (continued)
TA = 25°C and CREG25 = 1.0 µF (unless otherwise noted)
PARAMETER
VUVPREL
tUVP
UVP release voltage
UVP delay time
TEST CONDITIONS
MIN
TYP
MAX
TA = 25°C
VUVPREL – 0.022
VUVP + 0.105
VUVPREL + 0.022
TA = –5°C to 50°C
VUVPREL – 0.030
VUVP + 0.105
VUVPREL + 0.030
TA = –40°C to 85°C
VUVPREL – 0.050
VUVP + 0.105
VUVPREL + 0.050
TA = –40°C to 85°C
tUVP – 5%
tUVP
tUVP + 5%
MIN
TYP
MAX
VOCD – 3
VOCD
VOCD + 3
TA = –20°C to 60°C
VSRN – VSRP
0.98 * VOCD –
3.125
VOCD
1.02 * VOCD +
3.125
TA = –40°C to 85°C
VSRN – VSRP
0.98 * VOCD – 3.5
VOCD
1.02 * VOCD + 3.5
TA = –40°C to 85°C
tOCD – 5%
tOCD
tOCD + 5%
MIN
TYP
MAX
VOCC – 3
VOCC
VOCC + 3
TA = –20°C to 60°C
VSRP – VSRN
0.98 * VOCC –
3.125
VOCC
1.02 * VOCC +
3.125
TA = –40°C to 85°C
VSRP – VSRN
0.98 * VOCC – 3.5
VOCC
1.02 * VOCC + 3.5
TA = –40°C to 85°C
tOCC – 5%
tOCC
tOCC + 5%
UNIT
V
ms
6.11 Overcurrent in Discharge (OCD)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VSRN – VSRP
VOCD
tOCD
OCD detection voltage
threshold
OCD delay time
UNIT
mV
ms
6.12 Overcurrent in Charge (OCC)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VSRP – VSRN
VOCC
tOCC
OCC detection voltage
threshold
OCC delay time
UNIT
mV
ms
6.13 Short-Circuit in Discharge (SCD)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VSCD – 3
VSCD
VSCD + 3
TA = –20°C to 60°C
VSRN – VSRP
0.98 * VSCD –
3.125
VSCD
1.02 * VSCD +
3.125
TA = –40°C to 85°C
VSRN – VSRP
0.98 * VSCD –
3.5
VSCD
1.02 * VSCD +
3.5
TA = –40°C to 85°C
tSCD – 30%
tSCD
tSCD + 30%
TA = 25°C
VSRN – VSRP
VSCD
tSCD
SCD detection voltage
threshold
SCD delay time
UNIT
mV
µs
6.14 Low Voltage Charging
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
VLVDET
TEST CONDITIONS
Voltage threshold for low-voltage charging
detection
TA = –40°C to 85°C
MIN
TYP
MAX
1.4
1.55
1.7
MIN
TYP
MAX
UNIT
V
6.15 Internal Temperature Sensor Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V
PARAMETER
G(TEMP)
TEST CONDITIONS
Temperature sensor voltage gain
–2
UNIT
mV/°C
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6.16 High-Frequency Oscillator
2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
fOSC
MIN
TYP
TA = 0°C to 60°C
–2.0%
0.38%
2.0%
TA = –20°C to 70°C
–3.0%
0.38%
3.0%
TA = –40°C to 85°C
-4.5%
0.38%
4.5%
2.5
5
Operating frequency
Frequency error (1)
fEIO
tSXO
(1)
(2)
(3)
TEST CONDITIONS
Start-up time
MAX
8.389
(2)
(3)
TA = –40°C to 85°C
UNIT
MHz
ms
The frequency error is measured from 2.097 MHz.
The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3% of the typical oscillator frequency.
6.17 Low-Frequency Oscillator
2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (1)
t(LSXO)
(1)
(2)
(3)
Start-up time
TEST CONDITIONS
MIN
TYP
MAX
32.768
(2)
(3)
kHz
TA = 0°C to 60°C
–1.5%
0.25%
1.5%
TA = –20°C to 70°C
–2.5%
0.25%
2.5%
TA = –40°C to 85°C
-4.0%
0.25%
4.0%
TA = –40°C to 85°C
UNIT
500
μs
The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
The frequency error is measured from 32.768 kHz.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3% of the typical oscillator frequency.
6.18 Integrating ADC (Coulomb Counter) Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSR_IN
Input voltage range, VSRN and VSRP
VSR = VSRP – VSRN
tSR_CONV
Conversion time
Single conversion
MIN
Resolution
VSR_OS
Input offset
INL
Integral nonlinearity error
ZSR_IN
Effective input resistance (1)
ISR_LKG
Input leakage current (1)
(1)
TYP
VVPWR – 0.125
MAX
VVPWR + 0.125
1
UNIT
V
s
14
15
bits
±0.034%
FSR
10
μV
±0.007%
7
MΩ
0.3
μA
Assured by design. Not production tested.
6.19 ADC (Temperature and Cell Voltage) Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
VADC_IN
tADC_CONV
TEST CONDITIONS
ZADC1
UNIT
V
Input voltage range (other channels)
VSS – 0.125
1
V
Conversion time
14
Input offset
Effective input resistance (TS)
125
ms
15
bits
1
(1)
Effective input resistance (BAT) (1)
IADC_LKG
Input leakage current (1)
10
MAX
5
ZADC2
(1)
TYP
VSS – 0.125
Resolution
VADC_OS
MIN
Input voltage range (VBAT channel)
mV
55
Not measuring cell voltage
Measuring cell voltage
MΩ
55
MΩ
100
kΩ
0.3
μA
Assured by design. Not production tested.
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6.20 Data Flash Memory Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
tDR
Data retention
TEST CONDITIONS
Flash programming write-cycles
tWORDPROG
Word programming time (1)
ICCPROG
Flash-write supply current (1)
(1)
MIN
(1)
(1)
TYP
MAX
UNIT
10
years
20,000
cycles
5
2
ms
10
mA
Assured by design. Not production tested.
6.21 Timing Requirements
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
2
I C-Compatible Interface Timing Characteristics (see Figure 1)
tR
SCL or SDA rise time
300
ns
tF
SCL or SDA fall time
300
ns
tw(H)
SCL pulse width (high)
tw(L)
tsu(STA)
600
ns
SCL pulse width (low)
1.3
μs
Setup for repeated start
600
ns
td(STA)
Start to first falling edge of SCL
600
ns
tsu(DAT)
Data setup time
100
ns
th(DAT)
Data hold time
0
ns
tsu(STOP)
Setup time for stop
600
ns
tBUF
Bus free time between stop and start
fSCL
Clock frequency
66
μs
400
kHz
HDQ Communication Timing Characteristics (see Figure 2)
t(CYCH)
Cycle time, host to fuel gauge
190
t(CYCD)
Cycle time, fuel gauge to host
190
250
μs
t(HW1)
Host sends 1 to fuel gauge
0.5
50
μs
t(DW1)
Fuel gauge sends 1 to host
32
50
μs
t(HW0)
Host sends 0 to fuel gauge
86
145
μs
t(DW0)
Fuel gauge sends 0 to host
80
145
μs
t(RSPS)
Response time, fuel gauge to host
190
950
μs
t(B)
Break time
190
t(BR)
Break recovery time
40
t(RST)
HDQ reset
1.8
t(RISE)
HDQ line rise time to logic 1 (1.2 V)
tSU(STA)
tw(H)
tf
tw(L)
μs
205
μs
μs
tr
2.2
s
950
ns
t(BUF)
SCL
SDA
td(STA)
tsu(STOP)
tf
tr
th(DAT)
tsu(DAT)
REPEATED
START
STOP
START
Figure 1. I2C-Compatible Interface Timing Diagrams
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1.2V
t(RISE)
t(BR)
t(B)
(b) HDQ line rise time
(a) Break and Break Recovery
t(DW1)
t(HW1)
t(DW0)
t(CYCD)
t(HW0)
t(CYCH)
(d) Gauge Transmitted Bit
(c) Host Transmitted Bit
Break
1-bit
7-bit address
8-bit data
R/W
t(RSPS)
(e) Gauge to Host Response
t(RST)
(f) HDQ Reset
a. HDQ Breaking
b. Rise time of HDQ line
c. HDQ Host to fuel gauge communication
d. Fuel gauge to Host communication
e. Fuel gauge to Host response format
f . HDQ Host to fuel gauge reset
A.
HDQ Breaking
B.
Rise time of HDQ line
C.
HDQ Host to fuel gauge communication
D.
Fuel gauge to Host communication
E.
Fuel gauge to Host response format
F.
HDQ Host to fuel gauge reset
Figure 2. HDQ Communication Timing Diagrams
12
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4.500
2.490
4.490
2.480
VUVP - Undervoltage Detection Threshold (V)
VOVP - Overvoltage Detection Threshold (V)
6.22 Typical Characteristics
4.480
4.470
4.460
4.450
4.440
4.430
4.420
2.470
2.460
2.450
2.440
2.430
2.420
2.410
2.400
4.410
2.390
4.400
±40 ±30 ±20 ±10
0
10
20
30
40
50
60
70
80
±40 ±30 ±20 ±10
0
Temperature (ƒC)
10
20
30
40
50
60
70
80
Temperature (ƒC)
C001
C001
UVP threshold shown assumes an overvoltage setting of 4.450 V
Figure 3. Overvoltage Detection Threshold vs Temperature
Figure 4. Undervoltage Detection Threshold vs Temperature
85
VOCD - Overcurrent in Discharge Detection Threshold (mV)
VOCC - Overcurrent in Charge Detection Threshold (mV)
30
28
26
[OCC1, OCC0] = 11
24
22
[OCC1, OCC0] = 10
20
18
16
[OCC1, OCC0] = 01
14
12
10
[OCC1, OCC0] = 00
8
6
4
80
[OCD2, OCC1, OCD0] = 111
75
70
[OCD2, OCC1, OCD0] = 110
65
60
[OCD2, OCC1, OCD0] = 101
55
50
[OCD2, OCC1, OCD0] = 100
45
40
[OCD2, OCC1, OCD0] = 011
35
30
[OCD2, OCC1, OCD0] = 010
25
20
[OCD2, OCC1, OCD0] = 001
15
10
[OCD2, OCC1, OCD0] = 000
5
±40 ±30 ±20 ±10
0
10
20
30
40
50
60
70
80
±40 ±30 ±20 ±10
0
Temperature (ƒC)
10
20
30
40
50
60
70
OCC thresholds shown assume an overvoltage setting of 4.450 V
Figure 5. Overcurrent in Charge Detection Threshold vs
Temperature
C001
OCD thresholds shown assume an overvoltage setting of 4.450 V
Figure 6. Overcurrent in Discharge Detection Threshold vs
Temperature
1.05
150
145
1.04
[SCD] = 1
140
135
1.03
tOVP - Overvoltage Delay Time (s)
VSCD - Short-circuit Current in Discharge Detection Threshold (mV)
80
Temperature (ƒC)
C001
130
125
120
115
110
105
100
95
90
1.02
1.01
1.00
0.99
0.98
0.97
85
80
0.96
[SCD] = 0
75
0.95
70
±40 ±30 ±20 ±10
0
10
20
30
40
50
60
70
80
±40 ±30 ±20 ±10
0
10
20
30
40
50
60
70
80
Temperature (ƒC)
Temperature (ƒC)
C001
C001
SCD thresholds shown assume an overvoltage setting of 4.450 V
Figure 7. Short-Circuit in Discharge Detection Threshold vs
Temperature
Figure 8. Overvoltage Delay Time
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34.00
9.00
33.50
8.80
tOCC - Overcurrent in Charge Delay Time (ms)
tUVP - Undervoltage Delay Time (ms)
Typical Characteristics (continued)
33.00
32.50
32.00
31.50
31.00
30.50
30.00
29.50
8.60
8.40
8.20
8.00
7.80
7.60
7.40
7.20
7.00
29.00
6.80
±40 ±30 ±20 ±10
0
10
20
30
40
50
60
70
80
±40 ±30 ±20 ±10
0
Temperature (ƒC)
10
20
30
40
50
60
70
80
Temperature (ƒC)
C001
Figure 9. Undervoltage Delay Time
C001
Figure 10. Overcurrent in Charge Delay Time vs
Temperature
350
tSCD - Short-circuit Current in Discharge Delay Time (µs)
tOCD - Overcurrent in Discharge Delay Time (ms)
34.00
33.50
33.00
32.50
32.00
31.50
31.00
30.50
30.00
29.50
29.00
345
340
335
330
325
320
315
310
305
300
295
290
285
280
±40 ±30 ±20 ±10
0
10
20
30
40
50
60
70
80
±40 ±30 ±20 ±10
0
Temperature (ƒC)
10
20
30
40
50
60
70
80
Temperature (ƒC)
C001
C001
Figure 12. Short-Circuit in Discharge Delay vs Temperature
170
39
165
38
tFETOFF - FET Gate Fall Time (µs)
tFETON - FET Gate Rise Time (µs)
Figure 11. Overcurrent in Discharge Delay vs Temperature
160
155
150
145
140
37
36
35
34
VPWR = 2.8V
VPWR = 2.8V
33
135
VPWR = 3.7V
VPWR = 3.7V
VPWR = 4.2V
VPWR = 4.2V
32
130
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
-40 -30 -20 -10
Temperature (ƒC)
0
10
20
30
40
50
60
80
C021
C020
Performance with CL = 4 nF
Performance with CL = 4 nF
Figure 13. FET Gate Rise Time vs Temperature
14
70
Temperature (ƒC)
Figure 14. FET Gate Fall Time vs Temperature
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7 Detailed Description
7.1 Overview
The bq27742-G1 fuel gauge accurately predicts the battery capacity and other operational characteristics of a
single Li-based rechargeable cell. It can be interrogated by a system processor to provide cell information, such
as state-of-charge (SOC) and time-to-empty (TTE).
7.2 Functional Block Diagram
CC
POR
VPWR
+
–
0.3 V
Wake
Comparator
+
–
+
UVP
Delay
+
VOVP
–
+
VSCD
+
–
VOCD
SRN
+
BAT
HFO/128
+
–
+
VUVP
LDO
SCD
Delay
OCD
Delay
OVP
Delay
+
SRP
VPWR
HFO
20 kΩ
4R
2.5 V
REG25
HFO
OCC
Delay
Protector
FSM
LFO
VOCC
–
+
PACKP
+
R
360 kΩ
HFO/128
MUX
TS
CHG Drive
CHG
DSG Drive
DSG
ADC
VPWR
5 kΩ
Internal
Temp
Sensor
NC
HFO /4
RC2
SDA
22
Instruction
ROM
I2C Engine
22
CPU
VSS
SCL
I/O
Controller
Instruction
FLASH
HDQ
8
Wake
and
Watchdog
Timer
GP Timer
and
PWM
Data
SRAM
8
HDQ
Engine
Data
FLASH
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7.3 Feature Description
7.3.1 Configuration
Cell information is stored in the fuel gauge in non-volatile flash memory. Many of these data flash locations are
accessible during application development. They cannot, generally, be accessed directly during end-equipment
operation. Access to these locations is achieved by either use of the companion evaluation software, through
individual commands, or through a sequence of data-flash-access commands. To access a desired data flash
location, the correct data flash subclass and offset must be known.
The fuel gauge provides 64 bytes of user-programmable data flash memory, partitioned into two 32-byte blocks:
Manufacturer Info Block A and Manufacturer Info Block B. This data space is accessed through a data flash
interface.
7.3.2 Fuel Gauging
The key to the high-accuracy gas gauging prediction is Texas Instruments proprietary Impedance Track
algorithm. This algorithm uses cell measurements, characteristics, and properties to create state-of-charge
predictions that can achieve less than 1% error across a wide variety of operating conditions and over the
lifetime of the battery.
See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm Application Note
(SLUA364) for further details.
7.3.3 Power Modes
To minimize power consumption, the fuel gauge has different power modes: NORMAL, SLEEP, and
FULLSLEEP. The fuel gauge passes automatically between these modes, depending upon the occurrence of
specific events, though a system processor can initiate some of these modes directly.
7.3.3.1 NORMAL Mode
The fuel gauge is in NORMAL mode when not in any other power mode. During this mode, AverageCurrent(),
Voltage(), and Temperature() measurements are taken, and the interface data set is updated. Decisions to
change states are also made. This mode is exited by activating a different power mode.
Because the fuel gauge consumes the most power in NORMAL mode, the Impedance Track algorithm minimizes
the time the fuel gauge remains in this mode.
7.3.3.2 SLEEP Mode
SLEEP mode performs AverageCurrent(), Voltage(), and Temperature() less frequently which results in reduced
power consumption. SLEEP mode is entered automatically if the feature is enabled (Pack Configuration
[SLEEP] = 1) and AverageCurrent() is below the programmable level Sleep Current. Once entry into SLEEP
mode has been qualified, but prior to entering it, the fuel gauge performs an ADC autocalibration to minimize
offset.
During the SLEEP mode, the fuel gauge periodically takes data measurements and updates its data set.
However, a majority of its time is spent in an idle condition.
The fuel gauge exits SLEEP if any entry condition is broken, specifically when either:
• AverageCurrent() rises above Sleep Current or
• A current in excess of IWAKE through RSENSE is detected.
7.3.3.3 FULLSLEEP Mode
FULLSLEEP mode turns off the high-frequency oscillator and performs AverageCurrent(), Voltage(), and
Temperature() less frequently which results in power consumption that is lower than that of the SLEEP mode.
FULLSLEEP mode can be enabled by two methods:
• Setting the [FULLSLEEP] bit in the Control Status register using the FULL_SLEEP subcommand and Full
Sleep Wait Time (FS Wait) in data flash is set as 0.
• Setting the Full Sleep Wait Time (FS Wait) in data flash to a number larger than 0. This method is disabled
when the FS Wait is set as 0.
16
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Feature Description (continued)
FULLSLEEP mode is entered automatically when it is enabled by one of the methods above. When the first
method is used, the gauge enters the FULLSLEEP mode when the fuel gauge is in SLEEP mode. When the
second method is used, the FULLSLEEP mode is entered when the fuel gauge is in SLEEP mode and the timer
counts down to 0.
The fuel gauge exits the FULLSLEEP mode when there is any communication activity. Therefore, the execution
of SET_FULLSLEEP sets the [FULLSLEEP] bit. The FULLSLEEP mode can be verified by measuring the
current consumption of the gauge.
During FULLSLEEP mode, the fuel gauge periodically takes data measurements and updates its data set.
However, a majority of its time is spent in an idle condition.
The fuel gauge exits SLEEP if any entry condition is broken, specifically when either:
• AverageCurrent() rises above Sleep Current, or
• A current in excess of IWAKE through RSENSE is detected.
While in FULLSLEEP mode, the fuel gauge can suspend serial communications by as much as 4 ms by holding
the comm line(s) low. This delay is necessary to correctly process host communication, because the fuel gauge
processor is mostly halted in SLEEP mode.
7.3.4 Li-Ion Battery Protector Description
The battery protector controls two external high-side N-channel FETs in a back-to-back configuration for battery
protection. The protector uses two voltage doublers to drive the CHG and DSG FETs on.
7.3.4.1 High-Side NFET Charge and Discharge FET Drive
These FETs are automatically turned off by the protector based on the detected hardware protection faults or by
the fuel gauge based on detected firmware protection faults. This enables the gauge to be configured with
effectively two levels of safety: the first level employing conservative protection settings to keep the cell within a
safe operating area and the second level set to act as a fail-safe measure to prevent cell damage. Once the
protection fault(s) is deemed to be cleared, the protector or fuel gauge will re-enable the applicable FET(s).
Additionally, the FET drivers can be manually tested at production using the FETTest(0x74/0x75) extended
command if needed.
7.3.4.2 Protector Configuration
The integrated Li-Ion hardware protector includes full programmability of its fault detection thresholds, eliminating
the need to order several part variants to accommodate different system safety threshold needs. Configuration of
the thresholds is provided in the form of data flash parameters, Prot OV Config and Prot OC Config, which are
bit-mapped to two simple lookup tables that determine the protector safety thresholds. Table 3 through Table 6
detail the protection settings available for hardware overvoltage, overcurrent in charge, overcurrent in discharge,
and short-circuit in discharge, respectively. An added degree of flexibility is made possible in combining the
programmable thresholds with changes to the selected sense resistor value, enabling a wide variety of Li-Ion
protection options in a single device.
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Feature Description (continued)
Table 3. Hardware Overvoltage Protection Configuration
Prot OV Config
OVERVOLTAGE (VOVP) SETTING
[OVP2]
[OVP1]
[OVP0]
0
0
0
4.275 V
0
0
1
4.300 V
0
1
0
4.325 V
0
1
1
4.350 V
1
0
0
4.375 V
1
0
1
4.400 V
1
1
0
4.425 V
1
1
1
4.450 V (default)
Table 4. Hardware Overcurrent in Charge Configuration
Prot OC Config
OVERCURRENT IN CHARGE (VOCC) SETTING
[OCC1]
[OCC0]
0
0
0
1
13 mV
1
0
18 mV (default)
1
1
28 mV
6 mV
Table 5. Hardware Overcurrent in Discharge Configuration
Prot OC Config
OVERCURRENT IN DISCHARGE (VOCD) SETTING
[OCD1]
[OCD0]
[OCD0]
0
0
0
14 mV
0
0
1
24 mV
0
1
0
34 mV (default)
0
1
1
44 mV
1
0
0
53 mV
1
0
1
63 mV
1
1
0
73 mV
1
1
1
83 mV
Table 6. Hardware Short-Circuit in Discharge Configuration
Prot OC Config
[SCD]
SHORT-CIRCUIT IN DISCHARGE (VSCD) SETTING
0
73 mV (default)
1
148 mV
7.4 Device Functional Modes
7.4.1 Operating Modes
The battery protector has several operating modes depending on a variety of conditions. These modes are
described below:
• NORMAL Mode
• OVERVOLTAGE Mode
• UNDERVOLTAGE Mode
• OVERCURRENT IN CHARGE Mode
• OVERCURRENT IN DISCHARGE and SHORT-CIRCUIT IN DISCHARGE Mode
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Device Functional Modes (continued)
•
SHUTDOWN WAIT Mode
– ANALOG SHUTDOWN State
– LOW VOLTAGE CHARGING State
The relationships among these modes are shown in Figure 15.
UVP Fault
(POR State)
CHG FET on
DSG FET off
Fuel Gauge on
LDO is on
EL
PR
Normal
CHG FET off
DSG FET on
Fuel Gauge on
LDO on
Fuel Gauge in
Normal, SLEEP,
FULLSLEEP Modes
CHG FET on
DSG FET on
Fuel Gauge on
LDO is on
(VSRP – VSRN) > VOCC
OCC Fault
T
V BA
Fault recovery:
Charger removed
UV
>V
P
T<
V BA
V UV
FW(ROM) turns
FETs off briefly
POR
(Force UVP set)
Low Voltage Charging
(VSRN – VSRP) > VOCD
OR
(VSRN – VSRP) > VSCD
CHG FET control shorted to
Charger removed
PACKP pin
AND
DSG FET off
V
< Shutdown V
Protection off
Shutdown bit BAT
Fuel Gauge off
cleared
LDO is off
VBAT > VOVP
Fault recovery:
load removed
VBAT < VOVPREL
AND
Fault recovery:
Charger removed
OCD/SCD Fault
CHG FET on
DSG FET off
Fuel Gauge on
LDO on
Shutdown Bit
set
Charger removed
AND
V BAT < Shutdown V
Charger attached
AND
VBAT > VLVDET
Analog Shutdown
Shutdown Wait
OVP Fault
CHG FET off
DSG FET on
Fuel Gauge on
LDO on
CHG FET off
DSG FET off
Fuel Gauge on Charger removed
LDO is on
CHG FET off
DSG FET off
Fuel Gauge off
LDO is off
Virtual Shutdown
Figure 15. Operating Modes
7.4.1.1 NORMAL Mode
In this mode, the protector is fully powered and operational. Both CHG and DSG FETs are closed and the
protector continuously checks for fault conditions.
FET enable override capability is available to the fuel gauge to force the CHG or DSG FET open based on
firmware instruction. It is useful for firmware-defined safety features or other special functionality that requires
one or both FETs to be opened based on specific conditions. It cannot, however, be used to enforce FET turn-on
when the hardware protector is one of the protection fault modes, as the latter has ultimate authority over the
FET drive control circuitry.
Firmware can also command the fuel gauge to go into SHUTDOWN mode based on a dedicated Control()
subcommand from the host. In this case, firmware sets the shutdown bit, [SHUTDWN], to indicate intent to go
into SHUTDOWN mode. The fuel gauge then transitions to SHUTDOWN WAIT mode and waits for charger
removal prior to disabling the internal LDO and fully powering down the entire device.
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Device Functional Modes (continued)
7.4.1.2 OVERVOLTAGE Mode
In this mode, an overvoltage protection (OVP) fault mode is entered when the voltage on the VBAT pin
continuously exceeds the VOVP threshold for longer than the tOVP delay time. At this point, the fuel gauge enables
the fault recovery detection circuitry, which monitors the PACKP pin for charger removal. The OVP fault is
cleared once the pack voltage drops below the cell voltage by more than 300 mV and the cell voltage drops
below VOVPREL, which causes the fuel gauge to transition to NORMAL mode.
7.4.1.3 UNDERVOLTAGE Mode
In this mode, an undervoltage protection (UVP) fault mode is entered when the voltage on the VBAT pin
continuously falls below the VUVP threshold for longer than the tUVP delay time. The fuel gauge then enables the
charger attachment detection circuitry and, if no charger is found, sends the fuel gauge into ANALOG
SHUTDOWN mode to minimize power consumption and avoid further discharge of the battery. The UVP fault is
cleared once charger attachment is detected and the cell voltage rises above VUVPREL, which causes the fuel
gauge to transition to NORMAL mode.
The fuel gauge can enter this mode from LOW VOLTAGE CHARGING mode when the battery pack is being
charged from a deeply discharged state or from NORMAL mode when the battery pack is being discharged past
the UVP threshold.
7.4.1.4 OVERCURRENT IN CHARGE Mode
In this mode, an OVERCURRENT IN CHARGE (OCC) fault mode is entered when the voltage across the sense
resistor continuously exceeds the VOCC threshold for longer than the configured tOCC delay time. Recovery occurs
when the PACKP voltage drops to more than 300 mV below the cell voltage, indicating charger removal.
7.4.1.5 OVERCURRENT IN DISCHARGE and SHORT-CIRCUIT IN DISCHARGE Mode
In this mode, a short-circuit in discharge (SCD) or overcurrent in discharge (OCD) protection fault is detected
when the voltage across the sense resistor continuously exceeds the VOCD or VSCD thresholds for longer than the
tOCD or tSCD delay times. Recovery occurs when the PACKP voltage rises to within 300 mV of the cell voltage,
indicating load removal.
7.4.1.6 SHUTDOWN WAIT Mode
A transition to this mode occurs when the host sends the SET_SHUTDOWN command and the fuel gauge
subsequently initiated the shutdown sequence.
The shutdown sequence is as follows:
1. Open both CHG and DSG FETs.
2. Determine if any faults are set. If any faults are set, then go back to NORMAL mode.
3. Wait for charger removal. Once the charger is removed, turn off the LDO, which puts the fuel gauge into
ANALOG SHUTDOWN mode.
7.4.1.6.1 ANALOG SHUTDOWN State
In this mode, the fuel gauge is completely powered down and no portions of the device are functional. Once the
charger is connected, the fuel gauge will transition into either LOW VOLTAGE CHARGING mode (if below the
power-on reset voltage) or NORMAL mode (if above the POR voltage and no faults are detected).
7.4.1.7 LOW VOLTAGE CHARGING State
In this mode, the fuel gauge shorts the CHG FET gate to PACKP pin if the cell voltage is above the VLVDET
threshold, allowing the battery to be trickle charged with the CHG FET biased in the ohmic region. If below the
aforementioned threshold, low voltage charging is prohibited for safety reasons and the cell will likely be
permanently unrecoverable due to being dangerously depleted.
7.4.2 Firmware Control of Protector
The firmware has control to open the CHG FET or DSG FET independently by overriding hardware control.
However, it has no control to close the CHG FET or DSG FET and can only disable the FET override.
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Device Functional Modes (continued)
7.4.3 OVERTEMPERATURE FAULT Mode
Gauging firmware monitors temperature every second and will open either the CHG FET if Temperature() > OT
Chg for OT Chg Time in CHARGING mode or open the DSG FET if Temperature() > OT Dsg for OT Dsg Time
in DISCHARGING mode. Gauge determination of charge or discharge mode is based on Current() > Chg
Current Threshold for Quit Relax Time or Current() < Dsg Current Threshold for Quit Relax Time. Recovery
from the given overtemperature fault occurs when Temperature() < OT Chg Recovery or < OT Dsg Recovery,
depending on if a charge overtemperature or discharge overtemperature fault is present.
7.4.4 Wake-Up Comparator
The wake-up comparator indicates a change in cell current while the fuel gauge is in SLEEP mode. Wake
comparator threshold can be configured in firmware and set to the thresholds in Table 7. An internal event is
generated when the threshold is breached in either charge or discharge directions.
Table 7. IWAKE Threshold Settings(1)
RSNS1
RSNS0
IWAKE
Vth(SRP-SRN)
0
0
0
Disabled
0
0
1
Disabled
0
1
0
1.0 mV or –1.0 mV
0
1
1
2.2 mV or –2.2 mV
1
0
0
2.2 mV or –2.2 mV
1
0
1
4.6 mV or –4.6 mV
1
1
0
4.6 mV or –4.6 mV
1
1
1
9.8 mV or –9.8 mV
(1) The actual resistance value versus the setting of the sense resistor is not important just the actual voltage threshold when calculating
the configuration. The voltage thresholds are typical values under room temperature.
7.5 Battery Parameter Measurements
7.5.1 Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge or discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN pins. The integrating ADC measures bipolar
signals and detects charge activity when VSR = VSRP – VSRN is positive and discharge activity when VSR = VSRP –
VSRN is negative. The fuel gauge continuously integrates the signal over time using an internal counter.
7.5.2 Voltage
The fuel gauge updates cell voltages at 1-second intervals when in NORMAL mode. The internal ADC of the fuel
gauge measures the voltage, and scales and calibrates it appropriately. Voltage measurement is automatically
compensated based on temperature. This data is also used to calculate the impedance of the cell for Impedance
Track fuel gauging.
7.5.3 Current
The fuel gauge uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 5-mΩ to 20-mΩ typical sense resistor.
7.5.4 Auto-Calibration
The fuel gauge provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The fuel gauge performs auto-calibration before entering the SLEEP
mode.
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Battery Parameter Measurements (continued)
7.5.5 Temperature
The fuel gauge external temperature sensing is optimized with the use of a high-accuracy negative temperature
coefficient (NTC) thermistor with R25 = 10 kΩ ± 1% and B25/85 = 3435 kΩ ± 1% (such as Semitec 103AT for
measurement). The fuel gauge can also be configured to use its internal temperature sensor. The fuel gauge
uses temperature to monitor the battery-pack environment, which is used for fuel gauging and cell protection
functionality.
NOTE
Formatting Conventions in This Document:
Commands: italics with
RemainingCapacity()
parentheses
and
no
breaking
spaces,
for
example,
Data Flash: italics, bold, and breaking spaces; for example, Design Capacity
Register Bits and Flags: brackets only; for example, [TDA]
Data Flash Bits: italic and bold; for example, [XYZ1]
Modes and States: ALL CAPITALS; for example, UNSEALED mode
7.6 Communications
7.6.1 HDQ Single-Pin Serial Interface
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to
the fuel gauge. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted
first. The DATA signal on pin 12 is open-drain and requires an external pullup resistor. The 8-bit command code
consists of two fields: the 7-bit HDQ command code (bits 0 through 6) and the 1-bit RW field (MSB bit 7). The
RW field directs the fuel gauge either to:
• Store the next 8 bits of data to a specified register, or
• Output 8 bits of data from the specified register
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
HDQ serial communication is normally initiated by the host processor sending a break command to the fuel
gauge. A break is detected when the DATA pin is driven to a logic low state for a time t(B) or greater. The DATA
pin then is returned to its normal ready logic high state for a time t(BR). The fuel gauge is now ready to receive
information from the host processor.
The fuel gauge is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral.
7.6.2 I2C Interface
The fuel gauge supports the standard I2C read, incremental read, one-byte write quick read, and functions. The
7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively.
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Communications (continued)
GG Generated
Host Generated
S
0 A
ADDR[6:0]
CMD[7:0]
P
A P
DATA[7:0]
A
S
ADDR[6:0]
1 A
(a)
S
ADDR[6:0]
DATA[7:0]
N P
(b)
0 A
CMD[7:0]
A Sr
ADDR[6:0]
1 A
DATA[7:0]
N P
( c)
S
ADDR[6:0]
0 A
CMD[7:0]
A Sr
ADDR[6:0]
1 A
DATA[7:0]
A ...
DATA[7:0]
N P
(d)
A.
1-byte write; b. Quick read; c. 1-byte read; Incremental read (S = Start, Sr = Repeated Start, A = Acknowledge, N =
No Acknowledge, and P = Stop)
Figure 16. Supported I2C Formats
The quick read returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, increments whenever data is acknowledged by the fuel gauge or the
I2C master. Quick writes function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data).
Attempt to write a read-only address (NACK after data sent by master):
S
ADDR[6:0]
0 A
CMD[7:0]
A
DATA[7:0]
P
P
N P
Attempt to read an address above 0x7F (NACK command):
S
0 A
ADDR[6:0]
P
P
N P
CMD[7:0]
Attempt at incremental writes (NACK all extra data bytes sent):
S
ADDR[6:0]
0 A
CMD[7:0]
A
DATA[7:0]
A
DATA[7:0]
N
... N P
Incremental read at the maximum allowed read address:
S
ADDR[6:0]
0 A
CMD[7:0]
A Sr
ADDR[6:0]
1 A
DATA[7:0]
Address
0x7F
A
DATA[7:0]
Data from
addr 0x74
N P
Data from
addr 0x00
Figure 17. I2C Interfaces
The I2C engine releases both SDA and SCL if the I2C bus is held low for t(BUSERR). If the fuel gauge was holding
the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines
low, the I2C engine enters the low-power SLEEP mode.
7.6.2.1 I2C Time Out
The I2C engine releases both SDA and SCL lines if the I2C bus is held low for about 2 seconds. If the fuel gauge
was holding the lines, releasing them frees the master to drive the lines.
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Communications (continued)
7.6.2.2 I2C Command Waiting Time
To ensure the correct results of a command with the 400-kHz I2C operation, a proper waiting time must be added
between issuing a command and reading the results. For subcommands, the following diagram shows the
waiting time required between issuing the control command and reading the status with the exception of the
checksum command. A 100-ms waiting time is required between the checksum command and reading the result.
For read-write standard commands, a minimum of 2 seconds is required to get the result updated. For read-only
standard commands, there is no waiting time required, but the host must not issue any standard command more
than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the
watchdog timer.
xx
xxxxxxxx
xx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xx
S ADDR[6:0] 0 A
CMD[7:0]
A
DATA[7:0]
A
DATA[7:0]
A P
66Ps
xx
xxxxxxxx
xx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xx
xxx
xxxxxxxx
xx
xxx
xx
xxxxxxxx
xx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xx
S ADDR[6:0] 0 A
CMD[7:0]
A Sr ADDR[6:0] 1 A
DATA[7:0]
A
DATA[7:0] xxx
N xx
P
xx
xxxxxxxx
xx
xxxxxxxxx
xxx
xxxxxxxx
xx
xxx
xxx
xx
xx
xxxxxxxx
xx xxxxxxxxx
xxx
xxxxxxxx
xx
xxx
xxx
xx
Waiting time between control subcommand and reading results
xx
xxxxxxxx
xx
xxxxxxxxx
xxx
xxxxxxx
xxx
Sxxxxxxxx
ADDR[6:0] xx
0 A xxxxxxxxx
CMD[7:0]
Axxx
Sr xxxxxxx
ADDR[6:0]xxx
1 A
xx
xx
xxxxxxxx
xxxxxxxxx
xxx
xxxxxxx
xxx
xx
xxx
xx
DATA[7:0] xx
A
DATA[7:0] xxx
Nxx
P
66Ps
xx
xxx
xx
DATA[7:0]
xxx
A
xxx
xxx
DATA[7:0]
66Ps
xx
A
xx
xx
Waiting time between continuous reading results
Figure 18. I2C Command Waiting Time
The I2C clock stretch could happen in a typical application. A maximum 80-ms clock stretch could be observed
during the flash updates. There is up to a 270-ms clock stretch after the OCV command is issued.
7.7 Standard Data Commands
The fuel gauge uses a series of 2-byte standard commands to enable system reading and writing of battery
information. Each standard command has an associated command-code pair, as indicated in Table 8. Each
protocol has specific means to access the data at each Command Code. Data RAM is updated and read by the
gauge only once per second. Standard commands are accessible in NORMAL operation mode.
Table 8. Standard Commands
COMMAND CODE
UNIT
SEALED ACCESS
Control()
COMMAND NAME
0x00 and 0x01
—
RW
AtRate()
0x02 and 0x03
mA
RW
UnfilteredSOC()
0x04 and 0x05
%
R
Temperature()
0x06 and 0x07
0.1°K
R
Voltage()
0x08 and 0x09
mV
R
Flags()
0x0A and 0x0B
—
R
NomAvailableCapacity()
0x0C and 0x0D
mAh
R
FullAvailableCapacity()
0x0E and 0x0F
mAh
R
RemainingCapacity()
0x10 and 0x11
mAh
R
FullChargeCapacity()
0x12 and 0x13
mAh
R
AverageCurrent()
0x14 and 0x15
mA
R
TimeToEmpty()
0x16 and 0x17
min
R
FilteredFCC()
0x18 and 0x19
mAh
R
SafetyStatus()
0x1A and 0x1B
—
R
UnfilteredFCC()
0x1C and 0x1D
mAh
R
Imax()
0x1E and 0x1F
mA
R
UnfilteredRM()
0x20 and 0x21
mAh
R
FilteredRM()
0x22 and 0x23
mAh
R
24
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Standard Data Commands (continued)
Table 8. Standard Commands (continued)
COMMAND CODE
UNIT
SEALED ACCESS
BTPSOC1Set()
COMMAND NAME
0x24 and 0x25
mAh
RW
BTPSOC1Clear()
0x26 and 0x27
mAh
RW
InternalTemperature()
0x28 and 0x29
0.1°K
R
CycleCount()
0x2A and 0x2B
Counts
R
StateofCharge()
0x2C and 0x2D
%
R
StateofHealth()
0x2E and 0x2F
%/num
R
ChargingVoltage()
0x30 and 0x31
mV
R
ChargingCurrent)
0x32 and 0x33
mA
R
PassedCharge()
0x34 and 0x35
mAh
R
DOD0()
0x36 and 0x37
hex
R
SelfDischargeCurrent()
0x38 and 0x39
mA
R
7.7.1 Control(): 0x00 and 0x01
Issuing a Control() command requires a subsequent 2-byte subcommand. These additional bytes specify the
particular control function desired. The Control() command allows the system to control specific features of the
fuel gauge during normal operation and additional features when the fuel gauge is in different access modes, as
described in Table 9.
Table 9. Control() Subcommands
SUBCOMMAND
CODE
SEALED
ACCESS
CONTROL_STATUS
0x0000
Yes
Reports the status of DF Checksum, Impedance Track, and so on.
DEVICE_TYPE
0x0001
Yes
Reports the device type of 0x0742 (indicating bq27742-G1).
FW_VERSION
0x0002
Yes
Reports the firmware version on the device type.
HW_VERSION
0x0003
Yes
Reports the hardware version on the device type.
PROTECTOR_VERSION
0x0004
Yes
Reports the hardware protector version on the device type.
RESET_DATA
0x0005
Yes
Returns reset data.
PREV_MACWRITE
0x0007
Yes
Returns previous Control() subcommand code.
CHEM_ID
0x0008
Yes
Reports the chemical identifier of the Impedance Track configuration.
BOARD_OFFSET
0x0009
No
Forces the device to measure and store the board offset.
SUBCOMMAND NAME
DESCRIPTION
CC_OFFSET
0x000A
No
Forces the device to measure the CC offset.
DF_VERSION
0x000C
Yes
Reports the data flash version of the device.
SET_FULLSLEEP
0x0010
Yes
Sets the CONTROL_STATUS[FULLSLEEP] bit to 1.
SET_SHUTDOWN
0x0013
Yes
Sets the CONTROL_STATUS[SHUTDWN] bit to 1.
CLEAR_SHUTDOWN
0x0014
Yes
Clears the CONTROL_STATUS[SHUTDWN] bit to 1.
STATIC_CHEM_CHKSUM
0x0017
Yes
Calculates chemistry checksum.
ALL_DF_CHKSUM
0x0018
Yes
Reports checksum for all data flash excluding device specific variables.
STATIC_DF_CHKSUM
0x0019
Yes
Reports checksum for static data flash excluding device specific variables.
PROTECTOR_CHKSUM
0x001A
Yes
Reports checksum for protector configuration data flash excluding device
specific variables.
SEALED
0x0020
No
Places the fuel gauge in SEALED access mode.
IT_ENABLE
0x0021
No
Enables the Impedance Track algorithm.
IMAX_INT_CLEAR
0x0023
Yes
Clears an Imax interrupt that is currently asserted on the RC2 pin.
START_FET_TEST
0x0024
No
Starts FET Test based on data entered in FETTest() register. Sets and
clears the [FETTST] bit in CONTROL_STATUS.
CAL_ENABLE
0x002D
No
Toggle CALIBRATION mode.
RESET
0x0041
No
Forces a full reset of the fuel gauge.
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Table 9. Control() Subcommands (continued)
SUBCOMMAND
CODE
SEALED
ACCESS
EXIT_CAL
0x0080
No
Exit CALIBRATION mode.
ENTER_CAL
0x0081
No
Enter CALIBRATION mode.
OFFSET_CAL
0x0082
No
Reports internal CC offset in CALIBRATION mode.
SUBCOMMAND NAME
DESCRIPTION
7.8 Extended Data Commands
Extended commands offer additional functionality beyond the standard set of commands. They are used in the
same manner; however unlike standard commands, extended commands are not limited to 2-byte words. The
number of command bytes for a given extended command ranges in size from single to multiple bytes, as
specified in Table 10. For details on the SEALED and UNSEALED states, see the Access Modes section in the
bq27742-G1 Technical Reference Manual (SLUUAX0).
Table 10. Extended Commands
NAME
COMMAND CODE
UNIT
SEALED
ACCESS (1) (2)
UNSEALED
ACCESS (1) (2)
PackConfiguration()
0x3A and 0x3B
Hex
R
R
DesignCapacity()
0x3C and 0x3D
mAh
R
R
(2)
0x3E
NA
NA
RW
DataFlashBlock() (2)
0x3F
NA
RW
RW
0x40 to 0x53
NA
RW
RW
DataFlashClass()
BlockData()/Authenticate() (3)
BlockData()/AuthenticateCheckSum()
(3)
0x54
NA
RW
RW
0x55 to 0x5F
NA
R
RW
BlockDataCheckSum()
0x60
NA
RW
RW
BlockDataControl()
0x61
NA
NA
RW
BlockData()
DODatEOC()
0x62 and 0x63
NA
R
R
Qstart()
0x64 and 0x65
mAh
R
R
FastQmax()
0x66 and 0x67
mAh
R
R
0x68 to 0x6C
NA
R
R
0x6D
Hex
R
R
Reserved
0x6E and 0x6F
NA
R
R
SimultaneousCurrent()
0x70 and 0x71
mA
R
R
Reserved
0x72 and 0x73
NA
R
R
FETTest()
0x74 and 0x75
Hex
R
RW
AveragePower()
0x76 and 0x77
mW or cW
R
R
ProtectorState()
0x78
Hex
R
R
AN_COUNTER
0x79
AN_CURRENT_LSB
0x7A
Reserved
ProtectorStatus()
AN_CURRENT_MSB
0x7B
AN_VCELL_LSB
0x7C
AN_VCELL_MSB
0x7D
AN_TEMP_LSB
0x7E
AN_TEMP_MSB
0x7F
(1)
(2)
(3)
26
SEALED and UNSEALED states are entered via commands to Control() 0x00 and 0x01
In SEALED mode, data flash cannot be accessed through commands 0x3E and 0x3F.
The BlockData() command area shares functionality for accessing general data flash and for using Authentication. See Authentication in
the bq27742-G1 Technical Reference Manual (SLUUAX0) for more details.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The bq27742-G1 is a single-cell fuel gauge with integrated Li-Ion protection circuitry for highly accurate detection
of overvoltage, undervoltage, overcurrent in charge, overcurrent in discharge, and short-circuit in discharge fault
conditions. If the detected fault continues to be present for a specific delay time (preconfigured in the device), the
protection front-end will disable the applicable charge pump circuit, resulting in opening of the FET until the
provoking safety condition resolves. The integrated 16-bit delta-sigma converters provide accurate, high precision
measurements for voltage, current, and temperature in order to accomplish effective battery monitoring,
protection, and gauging. To allow for optimal performance in the end application, special considerations must be
taken to ensure minimization of measurement error through proper printed circuit board (PCB) board layout and
correct configuration of battery characteristics in the fuel gauge data flash. Such requirements are detailed in
Design Requirements.
8.2 Typical Applications
8.2.1 Pack-Side, Single-Cell Li-Ion Fuel Gauge and Protector
0.1 µF 0.1 µF
5 mΩ
200 Ω
PACK+
200 Ω
0.1 µF 0.1 µF
0.1 µF
0.1 µF
1 kΩ
1 kΩ
2 kΩ
0.1 µF
10 Ω
10 Ω
VPWR
SRN
BAT
SRP
0.1 µF
0.1 µF
REG25
1 µF
10 kΩ
(25°C)
0.47 µF
PACKP
TS
CHG
NC
DSG
RC2
SDA
VSS
SCL
0.1 µF
100 Ω
100 Ω
SDA
100 Ω
100 Ω
SCL
HDQ
PACK–
Copyright © 2017, Texas Instruments Incorporated
2
Figure 19. I C Mode Schematic
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Typical Applications (continued)
0.1 µF 0.1 µF
5 mΩ
200 Ω
PACK+
200 Ω
0.1 µF 0.1 µF
0.1 µF
0.1 µF
1 kΩ
1 kΩ
2 kΩ
0.1 µF
10 Ω
10 Ω
VPWR
SRN
BAT
SRP
0.1 µF
0.1 µF
REG25
1 µF
10 kΩ
(25°C )
0.47 µF
PACKP
TS
CHG
NC
DSG
RC2
SDA
VSS
SCL
0.1 µF
100 Ω
100 Ω
HDQ
HDQ
4.7 kΩ
PACK –
Copyright © 2017, Texas Instruments Incorporated
Figure 20. HDQ Mode Schematic
8.2.2 Design Requirements
Several key parameters must be updated to align with a given application's battery characteristics. For highest
accuracy gauging, it is important to follow-up this initial configuration with a learning cycle to optimize resistance
and maximum chemical capacity (Qmax) values prior to sealing and shipping packs to the field. Successful and
accurate configuration of the fuel gauge for a target application can be used as the basis for creating a "golden"
gas gauge (.GG) file that can be written to all production packs, assuming identical pack design and Li-Ion cell
origin (chemistry, lot, and so on). Calibration data can be included as part of this golden GG file to cut down on
battery pack production time. If going this route, it is recommended to average the calibration data from a large
sample size and use these in the golden file. Ideally, it is recommended to calibrate all packs individually as this
will lead to the highest performance and lowest measurement error in the end application on a per-pack basis. In
addition, the integrated protection functionality should be correctly configured to ensure activation based on the
fault protection needs of the target pack design, or else accidental trip could be possible if using defaults.
Table 11, Key Data Flash Parameters for Configuration, shows the items that should be configured to achieve
reliable protection and accurate gauging with minimal initial configuration.
Table 11. Key Data Flash Parameters for Configuration
NAME
28
DEFAULT
UNIT
RECOMMENDED SETTING
Design Capacity
1000
mAh
Set based on the nominal pack capacity as interpreted from cell manufacturer's
datasheet. If multiple parallel cells are used, should be set to N * Cell Capacity.
Design Energy
3800
mWh
Set based on the nominal pack energy (nominal cell voltage * nominal cell
capacity) as interpreted from the cell manufacturer's datasheet. If multiple parallel
cells are used, should be set to N * Cell Energy.
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Typical Applications (continued)
Table 11. Key Data Flash Parameters for Configuration (continued)
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Set to 10 to convert all power values to cWh or to 1 for mWh. Design Energy is
divided by this value.
Design Energy Scale
1
—
Reserve Capacity
0
mAh
Set to desired runtime remaining (in seconds/3600) * typical applied load
between reporting 0% SOC and reaching Terminate Voltage, if needed.
Design Voltage
3800
mV
Set to nominal cell voltage per manufacturer datasheet.
Cycle Count Threshold
900
mAh
Set to 90% of configured Design Capacity
Should be configured using TI-supplied Battery Management Studio software.
Default open-circuit voltage and resistance tables are also updated in conjunction
with this step. Do not attempt to manually update reported Device Chemistry as
this does not change all chemistry information! Always update chemistry using
the appropriate software tool (that is, BMS).
Device Chemistry
0354
hex
Load Mode
1
—
Set to applicable load model, 0 for constant current or 1 for constant power.
Load Select
1
—
Set to load profile which most closely matches typical system load.
Qmax Cell 0
1000
mAh
Set to initial configured value for Design Capacity. The gauge will update this
parameter automatically after the optimization cycle and for every regular Qmax
update thereafter.
V at Chg Term
4350
mV
Set to nominal cell voltage for a fully charged cell. The gauge will update this
parameter automatically each time full charge termination is detected.
Terminate Voltage
3000
mV
Set to empty point reference of battery based on system needs. Typical is
between 3000 and 3200 mV.
Ra Max Delta
43
mΩ
Set to 15% of Cell0 R_a 4 resistance after an optimization cycle is completed.
Charging Voltage
4350
mV
Set based on nominal charge voltage for the battery in normal conditions (25°C,
for example). Used as the reference point for offsetting by Taper Voltage for full
charge termination detection.
Taper Current
100
mA
Set to the nominal taper current of the charger + taper current tolerance to ensure
that the gauge will reliably detect charge termination.
Taper Voltage
100
mV
Sets the voltage window for qualifying full charge termination. Can be set tighter
to avoid or wider to ensure possibility of reporting 100% SOC in outer JEITA
temperature ranges that use derated charging voltage.
Dsg Current Threshold
60
mA
Sets threshold for gauge detecting battery discharge. Should be set lower than
minimal system load expected in the application and higher than Quit Current.
Chg Current Threshold
75
mA
Sets the threshold for detecting battery charge. Can be set higher or lower
depending on typical trickle charge current used. Also should be set higher than
Quit Current.
Quit Current
40
mA
Sets threshold for gauge detecting battery relaxation. Can be set higher or lower
depending on typical standby current and exhibited in the end system.
Avg I Last Run
–299
mA
Current profile used in capacity simulations at onset of discharge or at all times if
Load Select = 0. Should be set to nominal system load. Is automatically updated
by the gauge every cycle.
Avg P Last Run
–1131
mW
Power profile used in capacity simulations at onset of discharge or at all times if
Load Select = 0. Should be set to nominal system power. Is automatically
updated by the gauge every cycle.
Sleep Current
15
mA
Sets the threshold at which the fuel gauge enters SLEEP Mode. Take care in
setting above typical standby currents else entry to SLEEP may be
unintentionally blocked.
Shutdown V
0
mV
If auto-shutdown of fuel gauge is required prior to protect against accidental
discharge to undervoltage condition, set this to desired voltage threshold for
completely powering down the fuel gauge. Recovery occurs when a charger is
connected.
T1 Temp
0
°C
Sets the boundary between charging inhibit/suspend and charging with T1-T2
parameters. Defaults set based on recommended values from JEITA standard.
T2 Temp
10
°C
Sets the boundary between charging with T1-T2 or T2-T3 parameters. Defaults
set based on recommended values from JEITA standard.
T3 Temp
45
°C
Sets the boundary between charging with T2-T3 or T3-T4 parameters. Defaults
set based on recommended values from JEITA standard.
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Typical Applications (continued)
Table 11. Key Data Flash Parameters for Configuration (continued)
NAME
30
DEFAULT
UNIT
RECOMMENDED SETTING
T4 Temp
50
°C
Sets the boundary between charging with T4-T5 or T4-T5 parameters. Also
serves as charge inhibit boundary if initiating new charging event. Defaults set
based on recommended values from JEITA standard.
T5 Temp
60
°C
Sets the boundary between charging suspend and charging with T4-T5
parameters. Refer to JEITA standard for compliance.
Temp Hys
1
°C
Adds temperature hysteresis for boundary crossings to avoid oscillation if
temperature is changing by a degree or so on a given boundary.
T1-T2 Chg Voltage
4350
mV
Sets reported charge voltage when inside of T1 Temp and T2 Temp range.
Defaults set based on recommended values from JEITA standard.
T2-T3 Chg Voltage
4350
mV
Sets reported charge voltage when inside of T2 Temp an d T3 Temp range.
Defaults set based on recommended values from JEITA standard.
T3-T4 Chg Voltage
4300
mV
Sets reported charge voltage when inside of T3 Temp and T4 Temp range.
Defaults set based on recommended values from JEITA standard.
T4-T5 Chg Voltage
4250
mV
Sets reported charge voltage when inside of T4 Temp and T5 Temp range.
Defaults set based on recommended values from JEITA standard.
T1-T2 Chg Current
50
%
Sets reported charge current when inside of T1 Temp and T2 Temp range.
Defaults set based on recommended values from JEITA standard.
T2-T3 Chg Current
80
%
Sets reported charge current when inside of T2 Temp and T3 Temp range.
Defaults set based on recommended values from JEITA standard.
T3-T4 Chg Current
80
%
Sets reported charge current when inside of T3 Temp and T4 Temp range.
Defaults set based on recommended values from JEITA standard.
T4-T5 Chg Current
80
%
Sets reported charge current when inside of T4 Temp and T5 Temp range.
Defaults set based on recommended values from JEITA standard.
OV Prot Threshold
4390
mV
OV Prot Delay
1
s
Set to required OVP duration prior to fault detection and FET disable. Setting of 0
disables firmware-based OVP feature. Default of 1s is recommended.
OV Prot Recovery
4290
mV
Set to desired OVP recovery threshold. 100 to 200 mV below OVP trip threshold
is common.
OV Prot Threshold
2800
mV
Set to minimum allowable cell voltage due to overdischarge in normal operation.
OV Prot Delay
1
s
Set to required UVP duration prior to fault detection and FET disable. Setting of 0
disables firmware-based UVP feature. Default of 1s is recommended.
OV Prot Recovery
2900
mV
Set to desired UVP recovery threshold. 100 to 200 mV above UVP trip threshold
is common.
Set to maximum allowable cell voltage due to overcharge in normal operation.
Body Diode Current
Threshold
60
mA
Varies based on FET selection. Use the max DC current for the forward-biased
body diode from the FET datasheet and derate based on the operating
temperature range to arrive at the minimum current value (and add some margin)
that the fuel gauge should use to re-enable FET when disabled during a fault
condition.
OT Chg
55.0
°C
Set to desired temperature at which charging is prohibited to prevent cell damage
due to excessive ambient temperature.
OT Chg Time
5
s
OT Chg Recovery
50.0
°C
Set to the temperature threshold at which charging is no longer prohibited.
OT Dsg
60.0
°C
Set to desired temperature at which discharging is prohibited to prevent cell
damage due to excessive ambient temperature.
OT Dsg Time
5
s
Set to desired time before DSG FET is disabled based on overtemperature. Since
temperature changes much more slowly than other fault conditions, the default
setting is sufficient for most application.
OT Dsg Recovery
55.0
°C
Set to the temperature threshold at which cell discharging is no longer prohibited.
Prot OC Config
0A
hex
Set based on required trip thresholds for overcurrent in charge, overcurrent in
discharge, and short-circuit in discharge. When setting this parameter, be sure to
account for charger tolerance and maximum load spikes expected in the end
system to avoid accidental trip of these fault conditions
Set to desired time before CHG FET is disabled based on overtemperature.
Since temperature changes much more slowly than other fault conditions, the
default setting is sufficient for most application.
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Typical Applications (continued)
Table 11. Key Data Flash Parameters for Configuration (continued)
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Prot OV Config
07
hex
Set to maximum tolerable cell voltage before cell is permanently damaged.
Serves as a second level OVP protection mechanism.
Prot Checksum
11
hex
Set to sum of Prot OC Config and Prot OV Config. Improper setting will cause
FETs to open and warning flag assertion in SafetyStatus(), until corrected.
CC Gain
5
mΩ
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines conversion of coulomb counter measured
sense resistor voltage to current.
CC Delta
5.074
mΩ
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines conversion of coulomb counter measured
sense resistor voltage to passed charge.
CC Offset
6.874
mA
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines native offset of coulomb counter hardware
that should be removed from conversions.
Board Offset
0.66
uA
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines native offset of the printed circuit board
parasitics that should be removed from conversions.
Pack V Offset
0
mV
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines voltage offset between cell tab and ADC input
node to incorporate back into or remove from measurement, depending on
polarity.
8.2.3 Detailed Design Procedure
8.2.3.1 BAT Voltage Sense Input
A ceramic capacitor at the input to the BAT pin is used to bypass AC voltage ripple to ground, greatly reducing
its influence on battery voltage measurements. It proves most effective in applications with load profiles that
exhibit high frequency current pulses (that is, cell phones) but is recommended for use in all applications to
reduce noise on this sensitive high impedance measurement node.
The series resistor between the battery and the BAT input is used to limit current that could be conducted
through the chip-scale package's solder bumps in the event of an accidental short during the board assembly
process. The resistor is not likely to survive a sustained short condition (depends on power rating), however, it
sacrifices the much cheaper resistor component over suffering damage to the fuel gauge die itself.
8.2.3.2 SRP and SRN Current Sense Inputs
The filter network at the input to the coulomb counter is intended to improve differential mode rejection of voltage
measured across the sense resistor. These components should be placed as close as possible to the coulomb
counter inputs and the routing of the differential traces length-matched in order to best minimize impedance
mismatch-induced measurement errors. The single-ended ceramic capacitors should be tied to the battery
voltage node (preferably to a large copper pour connected to the SRN side of the sense resistor) in order to
further improve common-mode noise rejection. The series resistors between the CC inputs and the sense
resistor should be at least 200 Ω in order to mitigate SCR-induced latch-up due to possible ESD events.
8.2.3.3 Sense Resistor Selection
Any variation encountered in the resistance present between the SRP and SRN pins of the fuel gauge will affect
the resulting differential voltage, and derived current, it senses. As such, it is recommended to select a sense
resistor with minimal tolerance and temperature coefficient of resistance (TCR) characteristics. The standard
recommendation based on best compromise between performance and price is a 1% tolerance, 50-ppm drift
sense resistor with a 1-W power rating.
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8.2.3.4 TS Temperature Sense Input
Similar to the BAT pin, a ceramic decoupling capacitor for the TS pin is used to bypass AC voltage ripple away
from the high-impedance ADC input, minimizing measurement error. Another helpful advantage is that the
capacitor provides additional ESD protection since most thermistors are handled and manually soldered to the
PCB as a separate step in the factory production flow. As before, it should be placed as close as possible to the
respective input pin for optimal filtering performance.
8.2.3.5 Thermistor Selection
The fuel gauge temperature sensing circuitry is designed to work with a negative temperature coefficient-type
(NTC) thermistor with a characteristic 10-kΩ resistance at room temperature (25°C). The default curve-fitting
coefficients configured in the fuel gauge specifically assume a 103AT-2 type thermistor profile and so that is the
default recommendation for thermistor selection purposes. Moving to a separate thermistor resistance profile (for
example, JT-2 or others) requires an update to the default thermistor coefficients in data flash to ensure highest
accuracy temperature measurement performance.
8.2.3.6 VPWR Power Supply Input Filtering
A ceramic capacitor is placed at the input to the fuel gauge's internal LDO in order to increase power supply
rejection (PSR) and improve effective line regulation. It ensures that voltage ripple is rejected to ground instead
of coupling into the device's internal supply rails.
8.2.3.7 REG25 LDO Output Filtering
A ceramic capacitor is also needed at the output of the internal LDO in order to provide a current reservoir for
fuel gauge load peaks during high peripheral utilization. It acts to stabilize the regulator output and reduce core
voltage ripple inside of the device.
8.2.3.8 Communication Interface Lines
A protection network composed of resistors and zener diodes is recommended on each of the serial
communication inputs to protect the fuel gauge from dangerous ESD transients. The Zener should be selected to
break down at a voltage larger than the typical pullup voltage for these lines but less than the internal diode
clamp breakdown voltage of the device inputs (~6 V). A zener voltage of 5.6 V is typically recommended. The
series resistors are used to limit the current into the Zener diode and prevent component destruction due to
thermal strain once it goes into breakdown. 100 Ω is typically recommended for these resistance values.
For HDQ-based designs, a pullup resistor is normally designed in on the battery pack PCB and can be
connected to the RC2 input since a 1.8-V pullup voltage is readily available and provided by the fuel gauge.
8.2.3.9 PACKP Voltage Sense Input
Inclusion of a 2-kΩ series resistor on the PACKP input allows it to tolerate a charger overvoltage event up to 28
V without device damage. The resistor also protects the device in the event of a reverse polarity charger input,
since the substrate diode will be forward biased and attempt to conduct charger current through the fuel gauge
(as well as the high FETs). An external reverse charger input FET clamp can be added to short the DSG FET
gate to its source terminal, forcing the conduction channel off when negative voltage is present at PACK+ input
to the battery pack and preventing large battery discharge currents. A ceramic capacitor connected at the
PACKP pin helps to filter voltage into the comparator sense lines used for checking charger and load presence.
In addition, in the Low Voltage Charging State, the minimal circuit elements that are operational are powered
from this input pin and require a stable supply.
8.2.3.10 CHG and DSG Charge Pump Voltage Outputs
The series resistors used at the DSG and CHG output pins serve to protect them from damaging ESD events or
breakdown conditions, allowing the resistors to be sacrificed in place of the fuel gauge itself. An added bonus is
that they also help to limit in-rush currents due to use of FETs with large gate capacitance, allowing smooth ramp
of power-path connection turn-on to the system.
32
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8.2.3.11 NFET Selection
The choice in NFETs for a single-cell battery pack design will depend on a variety of factors including package
type, size, and device cost as well as performance metrics such as drain-to-source resistance (rDS(on)), gate
capacitance, maximum current and power handling, and similar. At a bare minimum, it is recommended that the
selected FETs have a drain-to-source voltage (VDS) and gate-to-source (VGS) voltage tolerance of 12 V. Some
FETs can are designed to handle as much as 24 V between the drain and source terminals and this would
provide an increased safety margin for the pack design. Further, the DC current rating should be high enough to
safely handle sustained current in charge or discharge direction just below the maximum threshold tolerances of
the configured OCC and OCD protections and the lowest possible sense resistance value based on tolerance
and TCR considerations, or vice-versa. This ensures that there is sufficient power dissipation margin given a
worst case scenario for the fault detections. In addition, striving for minimal FET resistance at the expected gate
bias as well as lowest gate capacitance will help reduce conduction losses and increase power efficiency as well
as achieve faster turn-on and turn-off times for the FETs. Many of these FETs are now offered as dual, backback NFETs in wafer-chip scale (WCSP) packaging, decreasing both BOM count and shrinking necessary board
real estate to accommodate the components. Last, one should always refer to the safe operating area (SOA)
curves of the target FETs to ensure that the boundaries are never violated based on all possible load conditions
in the end application. The CSD83325L is an excellent example of a FET solution that meets all of the
aforementioned criteria, offering rDS(on) of 10.3 mΩ and VDS of 12 V with back-to-back NFETs in a chip-scale
package, a perfect fit for battery pack designs.
8.2.3.12 Additional ESD Protection Components
The additional capacitors placed across the CHG and DSF FET source pins as well as between PACK+ and
ground help to bolster and greatly improve the ESD robustness of the pack design. The former components
shunt damaging transients around the FETs and the latter components attempt to bypass such pulses to PACK–
before they couple further into the battery pack PCB. Two series capacitors are used for each of these protection
areas to prevent a battery short in the event of a single capacitor failure.
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8.2.4 Application Curves
2V / div
2V / div
2V / div
2V / div
5V / div
5V / div
5V / div
5V / div
50ms / div
500ms / div
Figure 21. Overvoltage Protection Set and Clear
Figure 22. Undervoltage Protection Set and Clear
2V / div
2V / div
2V / div
2V / div
5V / div
5V / div
5V / div
5V / div
20ms / div
20ms / div
Figure 23. Overcurrent in Charge Protection Set and Clear
34
Figure 24. Overcurrent in Discharge Protection Set and
Clear
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2V / div
2V / div
5V / div
5V / div
100µ s / div
Figure 25. Short-Circuit in Discharge Protection Set and Clear
9 Power Supply Recommendation
9.1 Power Supply Decoupling
Both the VPWR input pin and the REG25 output pin require low equivalent series resistance (ESR) ceramic
capacitors placed as closely as possible to the respective pins to optimize ripple rejection and provide a stable
and dependable power rail that is resilient to line transients. A 0.1-µF capacitor at the VPWR and a 1-µF
capacitor at REG25 will suffice for satisfactory device performance.
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10 Layout
10.1 Layout Guidelines
10.1.1 Li-Ion Cell Connections
For highest voltage measurement accuracy, it is critical to connect the BAT pin directly to the battery terminal
PCB pad. This avoids measurement errors caused by IR drops when high charge or discharge currents are
flowing. Connecting right at the positive battery terminal with a Kelvin connection ensures the elimination of
parasitic resistance between the point of measurement and the actual battery terminal. Likewise the low current
ground return for the fuel gauge and all related passive components should be star-connected right at the
negative battery terminal. This technique minimizes measurement error due to current-induced ground offsets
and also improves noise performance through prevention of ground bounce that could occur with high current
and low current returns intersecting ahead of the battery ground. The bypass capacitor for this sense line needs
to be placed as close as possible to the BAT input pin.
10.1.2 Sense Resistor Connections
Kelvin connections at the sense resistor are just as critical as those for the battery terminals themselves. The
differential traces should be connected at the inside of the sense resistor pads and not anywhere along the high
current trace path in order to prevent false increases to measured current that could result when measuring
between the sum of the sense resistor and trace resistance between the tap points. In addition, the routing of
these leads from the sense resistor to the input filter network and finally into the SRP and SRN pins needs to be
as closely matched in length as possible else additional measurement offset could occur. It is further
recommended to add copper trace or pour-based "guard rings" around the perimeter of the filter network and
coulomb counter inputs to shield these sensitive pins from radiated EMI into the sense nodes. This prevents
differential voltage shifts that could be interpreted as real current change to the fuel gauge. All of the filter
components need to be placed as close as possible to the coulomb counter input pins.
10.1.3 Thermistor Connections
The thermistor sense input should include a ceramic bypass capacitor placed as close to the TS input pin as
possible. The capacitor helps to filter measurements of any stray transients as the voltage bias circuit pulses
periodically during temperature sensing windows.
10.1.4 FET Connections
The battery current transmission path through the FETs should be routed with large copper pours to provide the
lowest resistance path possible to the system. Depending on package type, thermal vias can be placed in the
package land pattern's thermal pad to reduce thermal impedance and improve heat dissipation from the package
to the board, protecting the FETs during high system loading conditions. In addition, it is preferable to locate the
FETs and other heat generating components away from the low power pack electronics to reduce the chance of
temperature drift and associated impacts to data converter measurements. In the event of FET overheating,
keeping reasonable distance between the most critical components, such as the fuel gauge, and the FETs helps
to decrease the risk of thermal breakdown to the more fragile components.
10.1.5 ESD Component Connections
The ESD components included in the reference design that connect across the back-to-back FETs as well as
from PACK+ to ground require trace connections that are as wide and short as possible in order to minimize loop
inductance in their return path. This ensures impedance is lowest at the AC loop through the series capacitors
and makes this route most attractive for ESD transients such that they are conducted away from the vulnerable
low voltage, low power fuel gauge and passive components. The series resistors and Zener diodes connected to
the serial communications lines should be placed as close as possible to the battery pack connector to keep
large ESD currents confined to an area distant from the fuel gauge electronics. Further, all ESD components
referred to ground should be single-point connected to the PACK– terminal if possible. This reduces the
possibility of ESD coupling into other sensitive nodes well ahead of the PACK– ground return.
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Layout Guidelines (continued)
10.1.6 High Current and Low Current Path Separation
For best possible noise performance, it is extremely important to separate the low current and high current loops
to different areas of the board layout. The fuel gauge and all support components should be situated on one side
of the boards and tap off of the high current loop (for measurement purposes) at the sense resistor. Routing the
low current ground around instead of under high current traces will further help to improve noise rejection. Last,
the high current path should be confined to a small loop from the battery, through the FETs, into the PACK
connector, and back.
10.2 Layout Example
Use short and wide
traces to minimize
inductance
CESD1
CESD2
Use copper pours for
battery power path to
minimize IR losses
RSENSE
PACK+
S1
G1
S1
S2
G2
S2
RSRP
RSRN
CSRP
CDIFF
CSRN
SRP
CHG
DSG
SRN
NC
PACK
P
Keep differential
traces length
matched
RDSG
CESD3
RCHG
Use short and wide
traces to minimize
inductance
RPACKP
CESD4
RVPWR
RBAT
VPWR
BAT
SDA
VSS
HDQ
RC2
REG25
TS
SCL
CVPWR
CPACKP
CBAT
Kelvin connect BAT
sense line right at
positive battery
terminal
Star ground right at
negative battery
terminal for low current
return path
CREG25
RTHERM
Use short and wide
traces to minimize
inductance
CTHERM
RESD1
RESD2
SDA
RESD3
RESD4
SCL
Star ground right at PACKfor ESD return path
PACKVia connects to Power Ground
Via connects between two layers
Figure 26. bq27742-G1 Board Layout
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Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: bq27742-G1
37
bq27742-G1
SLUSBV9D – MARCH 2014 – REVISED JANUARY 2018
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
1. bq27742-G1 Technical Reference Manual (SLUUAX0)
2. bq27742EVM Single Cell Impedance Track™ Technology Evaluation Module User's Guide (SLUUAH1)
11.2 Receive Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
Impedance Track, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: bq27742-G1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ27742YZFR-G1
ACTIVE
DSBGA
YZF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ27742
BQ27742YZFT-G1
ACTIVE
DSBGA
YZF
15
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ27742
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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