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bq28550-R1
SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
bq28550-R1 Single Cell Li-Ion Battery Gas Gauge and Protection
Check for Samples: bq28550-R1
1
1 Features
•
•
•
•
•
•
•
•
A Comprehensive Single-Cell Li-Ion Battery Gas
Gauge and Protection Integrates All Essential
Functions:
– Low-Side N-CH FET Protection Control
– JEITA/Enhanced Charging
– Authentication
Records Battery Gas Gauge Information
Protection Functions Help to Prevent:
– Short-Circuit
– Overcurrent Charge and Discharge
– Overvoltage Charge (Overcharge)
– Undervoltage (Over-Discharge)
Firmware Control of Discharge FET
SHA-1/HMAC Battery Authentication
General Purpose I/O Configurable for One of the
Following:
– CFET Control
– ALERT Output
I2C Communications Interface with SBS
Command Set Operation
12-pin, 2.50-mm x 4.00-mm SON Package
2 Applications
•
•
•
•
•
3 Description
The Texas Instruments bq28550-R1 battery gas
gauge provides current and voltage protection, and
secure, SHA-1/HMAC authentication for single-cell
Lithium-Ion battery packs. Designed for battery-pack
integration,
the
bq28550-R1
requires
host
microcontroller firmware support for implementation.
A system processor communicates with the bq28550R1 using a serial interface to obtain remaining battery
capacity, system run-time predictions, and other
critical battery information.
The bq28550-R1 gas gauge uses an accurate gas
gauging algorithm to report the status of the cell. The
gauge provides information such as state-of-charge
(%), run-time-to-empty (min.), charge-time to full
(min.),
battery
voltage
(V),
and
pack
temperature (°C).
The bq28550-R1 gas gauge also features integrated
support for secure battery-pack authentication, using
the SHA-1/HMAC authentication algorithm.
Device Information(1)
DEVICE NAME
PACKAGE
BODY SIZE
bq28550-R1
VSON (12)
4.00 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Tablet PCs
Slates
Digital Still and Video Cameras
Handheld Terminals
MP3 or Multimedia Players
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq28550-R1
SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
Handling Ratings ...................................................... 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics: Battery Protection ............ 5
Electrical Characteristics: Voltage Regulator............ 6
Electrical Characteristics: Power-On Reset .............. 7
Electrical Characteristics: Internal Temperature
Sensor Characteristics............................................... 7
6.9 Electrical Characteristics: High Frequency
Oscillator .................................................................... 7
6.10 Electrical Characteristics: Low Frequency
Oscillator .................................................................... 7
6.11 Electrical Characteristics: Integrating ADC
(Coulomb Counter) Characteristics............................ 7
6.12 Electrical Characteristics: ADC (Temperature and
Cell Voltage) Characteristics...................................... 8
6.13 Electrical Characteristics: Data Flash Memory
Characteristics ........................................................... 8
6.14 Electrical Characteristics: Serial Communication
Timing Characteristics................................................ 8
7
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
7.5
7.6
Overview .................................................................
Data Acquisition ......................................................
Over-Temperature Indication ..................................
Gas Gauging ...........................................................
Protection ................................................................
Feature Description.................................................
10
10
11
11
11
17
8
Application and Implementation ........................ 30
9
Device and Documentation Support.................. 33
8.1 Typical Application .................................................. 30
9.1
9.2
9.3
9.4
Related Documentation...........................................
Trademarks .............................................................
Electrostatic Discharge Caution ..............................
Glossary ..................................................................
33
33
33
33
10 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2012) to Revision A
Page
•
Changed the document format per updated Texas Instruments data sheet standards ........................................................ 1
•
Deleted Ordering Information Table ...................................................................................................................................... 1
2
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SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
DOUT
1
12
GPIO
COUT
2
11
SCL
VM
3
10
SDA
BAT
4
9
TS
VREG
5
8
SRN
VSS
6
7
SRP
Pin Functions
PIN NUMBER
PIN NAME
I/O (1)
1
DOUT
IA
The output of gate drive for discharge FET
DESCRIPTION
2
COUT
IA
The output of gate drive for charge FET
3
VM
IA
Analog input pin connected to the PACKN through a 510-Ω resistor. Overcurrent and shortcircuit protection circuits use the voltage across VM and VSS to detect if excessive charge or
discharge current is flowing through the protection FETs.
4
BAT
IA
Cell voltage measurement input. ADC input. Connect a 0.1-µF ceramic capacitor to VSS.
5
VREG
P
2.5-V output voltage of the internal integrated LDO. Connect a 0.1-µF ceramic capacitor to
VSS.
6
VSS
P
Device ground
7
SRP
IA
Analog input pin connected to the internal Coulomb counter where SRP is nearest the
CELL– connection. Connect to a 5-mΩ to 20-mΩ sense resistor.
8
SRN
IA
Analog input pin connected to the internal Coulomb counter where SRN is nearest the
PACKN connection. Connect to a 5-mΩ to 20-mΩ sense resistor.
9
TS
IA
Pack thermistor voltage sense (use 103AT-type thermistor), ADC input
10
SDA
I/O
Serial Data interface for SMBus
11
SCL
I
Serial Clock interface for SMBus
12
GPIO
I/O
General Purpose I/O for configurable function (CFET Control or ALERT output)
13
PWPD
I/O
Texas Instruments recommends connecting the power pad to VSS on the PCB.
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6 Specifications
6.1
Absolute Maximum Ratings
All voltages are referenced to the VSS pin. Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
VBAT
Regulator input voltage, BAT (Pin 4)
–0.3
12
V
VVM
VM terminal voltage (Pin 3)
VBAT – 32
VBAT + 0.3
V
VCOUT
COUT terminal input voltage (Pin 2)
VBAT – 32
VBAT + 0.3
V
VDOUT
DOUT terminal input voltage (Pin 1)
VSS – 0.3
VBAT + 0.3
V
VIOD
All other pins (Pins 5, 7, 8, and 9)
–0.3
6
V
VSDATA
SDA (Pin 10)
VSS – 0.3
VBAT + 0.3
V
VSCLK
SCL (Pin 11)
VSS – 0.3
VBAT + 0.3
V
VGPIO
GPIO (Pin 12)
–0.3
ESD
Human body model
ESD
Machine model
TA
Operating free-air temperature range
–40°C
85
°C
Tstg
Storage temperature range
–65°C
150
°C
(1)
TYP
(1)
6
±2
V
kV
±200
V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
TSTG
V(ESD) Rating
(1)
(2)
MIN
MAX
UNIT
Storage temperature range
–65
150
°C
HBM (1)
–2
2
kV
CDM (2)
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25ºC, VBAT = 3.6 V (unless otherwise noted)
PARAMETER
VBAT
TEST CONDITIONS
BAT
MIN
TYP
MAX
UNIT
2.45
3.6
5.5
V
Gas gauge in NORMAL mode. ILOAD > Sleep
Normal operating mode
Current
ICC
141
Low-power (SLEEP)
Gas gauge in SLEEP mode. ILOAD < Sleep
Current
70
Sleep (FULL SLEEP)
Gas gauge in FULLSLEEP mode. ILOAD < Sleep
Current
31
Hibernate
Gas gauge in HIBERNATE mode. ILOAD <
Hibernate Current
16
Shutdown
Gas gauge in SHUTDOWN mode
1
µA
ISS
Maximum current
CREG
Regulator output
capacitor
CBAT
VBAT input filter
capacitor
0.1
µF
RPACKN
Resistor from VM to
PACKN
510
Ω
RPU_
SCL, SDA or GPIO pull
up resistor
3.3
kΩ
VPU_
SCL, SDA or GPIO pull
up voltage
4
20
0.1
1.8
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mA
µF
4.2
V
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SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
Recommended Operating Conditions (continued)
TA = 25ºC, VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL_
GPIO, SDA and SCL
Input voltage low
–0.3
0.6
V
VIH_
GPIO, SDA and SCL
Input voltage high
1.2
6
V
VOL_
GPIO, SDA output
voltage low
IOH = 3 mA (open drain)
0
0.4
V
CI
Capacitance for each
I/O pin
SDA and SCL input capacitance
10
pF
tPUCD
Power Up
Communication Delay
VAI2
Input voltage range
(SRP, SRN)
250
ms
VSS – 0.25
0.25
V
6.4 Thermal Information
bq28550-R1
THERMAL METRIC (1)
SON
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance (2)
186.4
(3)
RθJC(top)
Junction-to-case(top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
RθJC(bottom)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
90.4
(4)
110.7
(5)
Junction-to-case(bottom) thermal resistance
°C/W
96.7
(6)
90
(7)
n/a
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
6.5 Electrical Characteristics: Battery Protection
TA = –40 to +85ºC, VBAT =1.5 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT =3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.2
V
VST
Minimum operating
voltage for 0 V charging
VST = VBAT – VM
RSHORT
Overcurrent release
resistance
VBAT = 4.0 V, VM = 1 V
30
50
100
kΩ
RDS
DS pin pull-down
resistance
VBAT = 4.0 V
6.5
13.0
26.0
kΩ
VOL1
COUT Low Level Output
voltage (referenced to
VM)
IOL = 30 µA, VBAT = 4.5 V
0.4
0.5
V
VOH1
COUT High Level Output
voltage (referenced to
IOH = 30 µA, VBAT = 4.0 V
VM)
3.4
3.7
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Electrical Characteristics: Battery Protection (continued)
TA = –40 to +85ºC, VBAT =1.5 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT =3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOL2
DOUT Low Level Output
voltage (referenced to
Vss)
VOH2
DOUT High Level Output
voltage (referenced to
IOH = 30 µA, VBAT = 4.0 V
Vss)
VDET1
Overcharge detection
MIN
IOL = 30 µA, VBAT = 2.0 V
TYP
MAX
UNIT
0.2
0.5
V
3.4
3.7
V
TA = 25°C detection voltage
4.230
4.250
4.270
TA = –10 to 60°C
4.225
4.250
4.275
TA = –40 to 85°C
4.200
4.250
4.300
TA = 25°C
4.040
4.070
4.100
TA = –10 to 60°C
4.025
4.070
4.115
V
VREL1
Overcharge release
voltage
TA = –40 to 85°C
4.010
4.070
4.130
tDET1
Overcharge detection
delay time
VBAT = 3.5 V ≥ 4.5 V
0.60
1.00
1.50
s
tREL1
Overcharge release
delay time
VBAT = 4.5 V ≥ 3.5 V
4.8
8.0
12.0
ms
TA = 25°C
Over-discharge detection
TA = –10 to 60°C
voltage
TA = –40 to 85°C
2.265
2.300
2.335
VDET2
2.242
2.300
2.358
2.220
2.300
2.380
tDET2
Over-discharge detection
VBAT = 3.5 V ≥ 2.00 V
delay time
14.4
24.0
36.0
ms
tREL2
Over-discharge release
delay time
VBAT = 3 V
V_ = 3 V ≥ 0 V
2.4
4.0
6.0
ms
VDET3
Overcurrent detection
voltage on discharge
VBAT = 4 V
0.130
0.150
0.170
V
VDET4
Overcurrent detection
voltage on charging
VBAT = 4 V
–0.137
–0.112
–0.087
V
tOCD
Overcurrent detection
delay time
VBAT = 3 V
V_ = 0 V ≥ 1 V
7.2
12.0
18.0
ms
tOCR
Overcurrent release
delay time
VBAT = 3 V
V_ = 3 V ≥ 0 V
2.4
4.0
6.0
ms
VSHORT
Short detection voltage
VBAT = 4 V, RPACKN = 510 Ω
VBAT – 1.2
VBAT – 0.9
VBAT – 0.6
V
tSHORT
Short detection delay
time
VBAT = 3 V
V_ = 0V ≥ 3 V
200
400
800
µs
V
V
6.6 Electrical Characteristics: Voltage Regulator
TA = –40 to +85ºC, VBAT =1.5 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT =3.6 V (unless otherwise noted)
PARAMETER
VREG
Output voltage
ΔVLINE
Line regulation
ΔVLOAD
Load regulation
VDO
Dropout voltage
ΔVREG/ΔT
Output voltage
temperature coefficient
ΔVLINE
Current limit
VOFF
Regulator off voltage
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7 V < VBAT < 5.5 V, IOUT = 16 mA
2.45
2.50
2.55
V
2.45 V < VBAT < 2.7 V, IOUT = 3 mA
2.40
2.7 V< VBAT < 5.5 V, IOUT = 16 mA
100
200
mV
VREG = 2.45 V, 100 µA < IOUT < 3 mA
30
50
VBAT = 2.7 V, 3 mA < IOUT < 16 mA
30
50
VBAT = 2.45 V, IOUT = 3 mA
30
50
VBAT = 2.7 V, IOUT = 16 mA
224
290
VBAT = 3.5 V, IOUT = 100 µA
100
mV
ppm/°C
VBAT = 3.5 V, IREG = 2.0 V
16
VBAT = 3.5 V, IREG = 0 V
10
35
60
7.0
8.0
9.0
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130
mA
V
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Electrical Characteristics: Voltage Regulator (continued)
TA = –40 to +85ºC, VBAT =1.5 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT =3.6 V (unless otherwise noted)
PARAMETER
tVOFF
TEST CONDITIONS
Regulator off voltage
delay time
MIN
TYP
MAX
UNIT
50
100
µs
MIN
TYP
MAX
UNIT
No external loading on VREG
2.125
2.200
2.275
V
No external loading on VREG
75
125
175
mV
VBAT = 3.6 V → 5.5 V, Rload = 100 Ω
VREG = 2.5 V → 2.3 V, Cload = 0.1 µF,
TA = 25°C
6.7 Electrical Characteristics: Power-On Reset
TA = –40 to +85ºC; Typical Values at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive-going battery
voltage input at VREG
VIT+
VHYS
6.8 Electrical Characteristics: Internal Temperature Sensor Characteristics
TA = –40 to +85ºC; VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
GTEMP
TEST CONDITIONS
MIN
Temperature Sensor
Voltage Gain
TYP
MAX
–2
UNIT
mV/°C
6.9 Electrical Characteristics: High Frequency Oscillator
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
f(OSC)
f(EIO)
t(SXO)
(1)
(2)
(3)
TEST CONDITIONS
MIN
TYP
TA = 0°C to 60°C
–2.0%
0.38%
2.0%
TA = –20°C to 70°C
–3.0%
0.38%
3.0%
TA = –40°C to 85°C
–4.5%
0.38%
4.5%
2.5
5
Operating frequency
Frequency error
Start-up time
(1) (2)
,
MAX
2.097
(3)
UNIT
MHz
ms
The frequency error is measured from 2.097 MHz.
The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.10 Electrical Characteristics: Low Frequency Oscillator
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f(LOSC)
Operating frequency
f(LEIO)
Frequency error
t(LSXO)
(1)
(2)
(3)
Start-up time
(1) (2)
,
MIN
TYP
MAX
UNIT
32.768
kHz
TA = 0°C to 60°C
–1.5%
0.25%
1.5%
TA = –20°C to 70°C
–2.5%
0.25%
2.5%
TA = –40°C to 85°C
–4.0%
0.25%
4.0%
(3)
500
μs
The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
The frequency error is measured from 32.768 kHz.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.11 Electrical Characteristics: Integrating ADC (Coulomb Counter) Characteristics
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
VIN(SR)
tCONV(SR)
TEST CONDITIONS
Input voltage range,
V(SRN) and V(SRP)
VSR = V(SRN) – V(SRP)
Conversion time
Single conversion
Resolution
MIN
TYP
–0.125
MAX
UNIT
0.125
V
15
bits
1
14
s
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Electrical Characteristics: Integrating ADC (Coulomb Counter) Characteristics (continued)
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOS(SR)
Input offset
INL
Integral nonlinearity error
ZIN(SR)
Effective input
resistance (2)
Ilkg(SR)
Input leakage current (2)
(1)
(2)
MIN
TYP
MAX
UNIT
±0.034
FSR (1)
10
±0.007
µV
2.5
MΩ
0.3
µA
Full-scale reference
Specified by design. Not production tested.
6.12 Electrical Characteristics: ADC (Temperature and Cell Voltage) Characteristics
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
VIN(ADC)
tCONV(ADC)
TEST CONDITIONS
Input voltage range
TYP
Conversion time
Resolution
14
VOS(ADC)
Input offset
Z(ADC1)
Effective input
resistance (TS)
Z(ADC2)
Effective input
resistance (BAT)
Ilkg(ADC)
Input leakage current
(1)
MIN
–0.2
MAX
V
125
ms
15
bits
1
mV
8
(1)
bq28550-R1 is not measuring cell voltage.
(1)
MΩ
8
bq28550-R1 is measuring cell voltage.
UNIT
1
MΩ
100
(1)
kΩ
0.3
µA
Specified by design. Not production tested.
6.13 Electrical Characteristics: Data Flash Memory Characteristics
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted)
PARAMETER
Data retention
tDR
Flash programming
write-cycles (1)
tWORDPROG
ICCPROG
(1)
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
10
Years
20,000
Cycles
Word programming time
(1)
Flash-write supply
current (1)
5
2
ms
10
mA
Specified by design. Not production tested.
6.14 Electrical Characteristics: Serial Communication Timing Characteristics
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted).
Capacitance on serial interface pins SCL and SDA are 10 pF unless otherwise specified (1).
MAX
UNIT
tr
PARAMETER
SCL/SDA rise time
300
ns
tf
SCL/SDA fall time
300
ns
tw(H)
SCL pulse width (high)
600
tw(L)
SCL pulse width (low)
1.3
μs
tsu(STA)
Setup for repeated start
600
ns
td(STA)
Start to first falling edge
of SCL
600
ns
tsu(DAT)
Data setup time
1
μs
th(DAT)
Data hold time
0
ns
(1)
8
TEST CONDITIONS
MIN
TYP
ns
Parameters assured by worst case test program execution in fast mode.
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Electrical Characteristics: Serial Communication Timing Characteristics (continued)
TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted).
Capacitance on serial interface pins SCL and SDA are 10 pF unless otherwise specified (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu(STOP)
Setup time for stop
600
ns
t(BUF)
Bus free time between
stop and start
1.3
μs
f(SCL)
Clock frequency
100
t su (STA)
tw(H)
tw(L)
tf
tr
kHz
t(BUF)
SCL
SDA
td (STA)
tr
th(DAT)
tsu (DAT)
REPEATED
START
tf
t su(STOP)
STOP
START
Figure 1. Timing
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7 Detailed Description
7.1 Overview
The bq28550-R1 gas gauge accurately predicts the battery capacity and other operational characteristics of a
single Li-Ion based rechargeable cell, while it also provides a state-of-the-art protection function against short
circuit, overcurrent, and overvoltage. It can be integrated by a system processor to provide cell information, such
as state-of-charge (SOC), Remaining Capacity, and Full Charge Capacity (FCC).
NOTE
Formatting conventions in this document:
Commands: Italics
RemainingCapacity()
with
parentheses
and
no
breaking
spaces;
for
example,
Data Flash: Italics, bold, and breaking spaces; for example, Design Capacity
Register Bits and Flags: Brackets only; for example, [TDA]
Data Flash Bits: Italic and bold; for example, [NR]
Modes and States: All capitals; for example, SEALED mode
7.2 Data Acquisition
7.2.1 Cell Voltage
The bq28550-R1 gas gauge samples the single cell voltage from the BAT input terminal. The cell voltage is
sampled and updated every 1 s in normal mode. The VSS ground connection of the bq28550-R1 gas gauge
should be connected to the negative terminal of the sense resistor. This will prevent any error in short circuit and
overcurrent measurements across the external CHG and DSG FETs.
7.2.2 Charge Measurement
The device samples the charge into and out of the single cell using a low value sense resistor. The resistor
(typically 5 mΩ to 20 mΩ) is connected between SRP and SRN to form a differential input to an integrating ADC
(Coulomb counter). Charge activity is detected when VSR = V(SRP) – V(SRN) is positive, and discharge activity is
detected when VSR = V(SRP) – V(SRN) is negative. This data is integrated over a period of time, using an internal
counter, and updates Remaining Capacity with charge and discharge amount every 1 s in normal mode.
7.2.3 Current Measurement
The device has a FIFO buffer, which uses the last four Coulomb counter readings to calculate the current. The
current is updated every 1 s in normal mode.
7.2.4 Temperature Measurement and the TS Input
The bq28550-R1 gas gauge measures external temperature via the TS pin in order to supply battery temperature
status information to the gas gauging algorithm and charger-control sections of the gauge. Alternatively, the
gauge can also measure internal temperature via its on-chip temperature sensor. Refer to the Pack
Configuration[TEMPS] control bit.
Regardless of which sensor is used for measurement, a system processor can request the current battery
temperature by calling the Temperature() function (see Data Commands for more information). The temperature
information is updated every 1 s in normal mode.
The bq28550-R1 external temperature sensing is optimized with the use of a high accuracy negative temperature
coefficient (NTC) thermistor with R25 = 10 KΩ ± 1% and B25/85 = 3435 KΩ ± 1% (such as Semitec 103AT for
measurement). The shows additional circuit information for connecting this thermistor to the bq28550-R1 gas
gauge.
10
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7.3 Over-Temperature Indication
7.3.1 Over-Temperature: Charge
If during charging Temperature() reaches the threshold of OT Chg for a period of OT Chg Time and
AverageCurrent() > Chg Current Threshold, then the [OC] bit is set based on the charge fault configuration
setting of the CHG bit in the Control Status Register. When Temperature() falls to OT Chg Recovery, the [OC]
bit is reset.
If OT Chg Time = 0, the feature is completely disabled.
7.3.2 Over-Temperature: Discharge
If during discharging Temperature() reaches the threshold of OT Dsg for a period of OT Dsg Time, and
AverageCurrent() ≤ –Dsg Current Threshold, then the [DSGOFFREQ] bit is set. When Temperature() falls to
OT Dsg Recovery, the [DSGOFFREQ] bit is reset.
If OT Dsg Time = 0, the feature is completely disabled.
7.4 Gas Gauging
Gas gauging information is accessed through a series of commands called Standard Commands. Further
capabilities are provided by the additional Extended Commands set. Both sets of commands, indicated by the
general format Command(), are used to read and write information contained within the bq28550-R1 device
control and status registers, as well as their data flash locations. Commands are sent from the system to the
gauge using the bq28550-R1 device’s serial interface and can be executed during application development, pack
manufacture, or end-equipment operation.
Cell information is stored in the bq28550-R1 non-volatile data flash memory. Many of these data flash locations
are accessible during application development. They cannot, generally, be accessed directly during endequipment operation. Access to these locations is achieved by using the bq28550-R1 device’s companion
evaluation software, through individual commands, or through a sequence of data-flash-access commands. To
access a desired data flash location, the correct data flash subclass and offset must be known. The bq28550-R1
device provides 96 bytes of user-programmable data flash memory, partitioned into three, 32-byte blocks:
Manufacturer Info Block A, Manufacturer Info Block B, and Manufacturer Info Block C. For specifics on
accessing the data flash, see Manufacturer Information Blocks.
The bq28550-R1 device’s gas gauging prediction uses a Compensated End of Discharge Voltage (CEDV)
method. This algorithm mathematically models the cell voltage as a function of the battery state-of-charge (SOC),
temperature, and current. The algorithm also models the battery impedance (Z) as a function of SOC and
temperature, with other parameters included in the calculation. The battery voltage model is used to calibrate full
charge capacity (FCC), and the compensated battery voltage can be used to indicate low battery voltage or
alarm function through firmware settings (Low Battery %, Fully Discharged).
The bq28550-R1 device measures discharge activity by monitoring the voltage across a small-value series sense
resistor (5 mΩ to 20 mΩ typ) located between the CELL– and the battery’s PACKN terminal. This information is
used to integrate the battery discharge capacity and to estimate state of charge Q. This is then calculated as a
percentage of maximum capacity Qmax to indicate remaining state-of-charge (RSOC). The maximum capacity
parameter is updated on every full discharge cycle. There are other factors to be considered in estimating RSOC,
such as battery impedance, temperature, and aging due to number of charge/discharge cycles. The equations
used to determine the battery capacity factor these variables into the calculation based on battery chemistry.
7.5 Protection
7.5.1 Overcharge Detector
When charging a battery, if the VBAT voltage becomes greater than the overcharge detection voltage
(VDET1 = 4.250 V typ) for a period up to the overcharge detection delay time (tDET1 = 1.00 s typ), the bq28550-R1
device detects the overcharge state of the battery, and the COUT pin transitions to a low level. This prohibits
charging the battery by turning off the external charge control N-channel MOSFET.
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Protection (continued)
In the overcharge state, if a charger is removed and a load is connected, the external charge control MOSFET
conducts the load current through its parasitic body diode. If the VBAT voltage becomes lower than the
overcharge release voltage (VREL1 = 4.070 V typ) for a period up to the overcharge release delay time
(tREL1 = 8 ms typ), the COUT pin transitions to a high level, enabling charge of the battery by turning on the
external charge control N-channel MOSFET.
7.5.2 Over-Discharge Detector
When discharging a battery, if the VBAT voltage becomes lower than the over-discharge detection voltage
(VDET2 = 2.3 V typ) for a period up to the over-discharge detection delay time (tDET2 = 24 ms typ), the bq28550R1 device detects the over-discharge state of the battery, and the DOUT pin transitions to a low level. This
prohibits discharging the battery by turning off the external discharge control N-channel MOSFET.
In the over-discharge state, if a charger is connected, the external discharge control MOSFET conducts the
charge current through its parasitic body diode. If the VBAT voltage becomes greater than the over-discharge
detection voltage (VDET2 = 2.3 V typ) for a period up to the overcharge release delay time (tREL2 = 4 ms typ), the
DOUT pin transitions to a high level, enabling discharge of the battery by turning on the external discharge
control N-channel MOSFET. After detecting over-discharge, the device stops all operations and enters standby,
which reduces the current consumed by the IC to its lowest mode (standby current).
12
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Protection (continued)
Overcharge
BAT
Normal
Normal
Over-Discharge
Shutdown
Normal
VDET1
VREL1
DOUT
VDET2
BAT
COUT
V
SS
BAT
VSS
VM
PACK–
BAT
V
DET3
VSS
PACK –
t
t
DET1
Charger
Connected
REL1
tDET2
Load
Connected
tREL2
Charger
Connected
7.5.3 Discharge Overcurrent Detector and Short-Circuit Detector
If the voltage across both protection MOSFETs (VM – VSS) becomes higher than the discharge overcurrent
detection voltage (VDET3 = 0.150 V typ) for a period of up to the discharge overcurrent detection delay time
(tDET3 = 12 ms typ), the bq28550-R1 device detects the discharge overcurrent state of the battery and the DOUT
pin transitions to a low level. This prohibits discharging the battery by turning off the external discharge control Nchannel MOSFET.
Additionally, if the voltage across both protection MOSFETs (VM – VSS) becomes higher than the short-circuit
voltage (VSHORT = VBAT – 0.9 V typ) for a period of up to the discharge short-circuit detection delay time
(tSHORT = 400 µs typ), the bq28550-R1 device detects a short-circuit of the battery and the DOUT pin transitions
to a low level. This prohibits discharging the battery by turning off the external discharge control N-channel
MOSFET.
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Protection (continued)
In both the discharge overcurrent and short-circuit states, an internal discharge overcurrent release resistor (20
kΩ typ) is turned on (switched in between VM and VSS), allowing the VM pin to be pulled down to the VSS
potential if the load is released. If the VM – VSS voltage becomes lower than the discharge overcurrent detection
voltage (VDET3 = 0.150 V typ) for a period up to the discharge overcurrent release delay time (tREL3 = 4 ms typ),
the discharge overcurrent release resistor is turned off and the DOUT pin transitions to a high level, enabling
discharge of the battery by turning on the external discharge control N-channel MOSFET.
Discharge
Overcurrent
BAT
Normal
Discharge
Overcurrent
Normal
Normal
VDET1
VREL1
DOUT
VDET2
BAT
COUT
VSS
BAT
VSS
VM
PACK–
BAT
VSHORT
VDET3
VSS
tOCD
Load
Connected
14
tOCR
Load
Disconnected
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tSHORT
t OCR
Load Short
Circuit
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Protection (continued)
7.5.4 Charge Overcurrent Detector
If the voltage across both protection MOSFETs (VM – VSS) becomes more negative than the charge overcurrent
detection voltage (VDET4 = –0.112 V typ) for a period up to the charge overcurrent detection delay time
(tDET4 = 12 ms typ) due to an abnormal charging current or abnormal charging voltage, the bq28550-R1 device
detects the overcurrent charge state of the battery and the COUT pin transitions to a low level. This prohibits
charging the battery by turning off the external charge control N-channel MOSFET. The bq28550-R1 device
releases from the charge overcurrent detection state on by detecting the connection of a load for a period up to
the overcharge release delay time (tREL4 = 4 ms typ).
Table 1. Hardware Control Due to Fault Detection
Fault Condition
Overcharge Voltage
Protection
Overcurrent
Protection During
Charging
Over Discharging
Voltage Protection
Overcurrent
Protection During
Discharging
Short-Circuit
Protection
DOUT COUT
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
Delay
(typ)
Comment
1s
Once OVP occurs for longer than the specified duration (1 s typ), the CHG FET is turned
OFF and bus communication is NOT valid. The system will support power to the load with
current flow through the CHG FET parasitic diode. This can cause the cell to discharge;
once the cell voltage reaches the overcharge release voltage for the specified duration (8
ms typ), the CHG FET is turned ON and bus communication is valid.
12 ms
If the cell is being charged with excessive current, the threshold will be based on a
hardware limit measurement of –112 mV typ across the CHG + DSG FET (VM – Vss) for
a duration longer than 12 ms (typ), the CHG FET is turned OFF and bus communication
is not valid. This will prevent further charging of the cell. The setting of the CHG bit in the
control Status Register is dependent on the OC bit setting in the Charge Fault Register
selection. The FET bit in the Control between the charger is removed and cell voltage
falls below the threshold for greater than 8 ms (typ). COUT is turned back ON. Once the
host MCU takes corrective action OR if the battery charger is removed AND there is a
load detected for a period of 4 ms (typ), the CHG FET is turned ON and bus
communication is valid.
24 ms
If the cell voltage falls to lower than 2.3 V for a duration of 24 ms (typ), the DSG FET is
turned OFF, and bus communication is not valid. The system requires if the charger is
connected and cell voltage rises above threshold for greater than 4 ms (typ), DOUT is
turned back ON and bus communication is valid.
12 ms
If the cell is being discharged with excessive current, the threshold will be based on a
hardware limit measurement of 150 mV typ across the DSG + CHG FET (VM – Vss) for a
duration longer than 12 ms (typ) the DSG FET is turned OFF and bus communication is
NOT valid. This will prevent further discharging of the cell, and the DSG bit in the control
Status Register will be set. If the drop across the DSG + CHG FET is less than the
threshold OR there is no load detected for a duration of 4 ms (typ), the DSG FET is
turned ON and bus communication is valid.
400 µs
Detection of cell short circuit is measured at VM input. Shorted cell detection is VBAT –
0.9 V for greater than 400 µs at the VM terminal, and the DSG FET is turned OFF, and
bus communication is NOT valid. The DSG bit in the control Status Register will be set.
The system will turn the DSG FET ON if the voltage at VM is below 150 mV OR no load
is detected.
7.5.5 Gas Gauge Control of Discharge DOUT Pin
Firmware Control of DOUT for Protection
The gas gauge firmware can override the hardware-based protection by forcing DOUT low to turn OFF the
discharge FET. However, the firmware cannot override the hardware protection to force discharge.
There are three conditions that enable firmware to force DOUT low:
1. The HOST_DISCONNECT (DSG FET OFF) subcommand: This feature is useful for the system to disable
the discharge FET from the battery pack if it fails to authenticate.
2. Pack removal detection by the SDA and SCL pins falling low for more than 2 seconds: The DOUT pin
override condition is released upon detection of PACK insertion.
3. Firmware-based undervoltage detection: The DOUT pin is forced low if voltage of the cell falls below the Set
Voltage threshold. The DOUT override condition is released when the voltage is above Clear Voltage.
Any one of the above three conditions will force the DOUT pin low. However, all three corresponding release
conditions must be satisfied before the DOUT override is returned to hardware-based protection control.
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7.5.6 Zero Voltage Charging
When the cell voltage is 0 V and if the charger voltage is above the minimum operating voltage for 0 V charging
(1.2-V max), the COUT output transitions to a high level and charge current can flow.
7.5.7 FET Control Protection
Figure 2 shows an overview of the FET Control Protection operation.
Shutdown
CHG: OFF
DSG: OFF
VREG: OFF
Attach a Charge
Short-Circuit
Protection
CHG: ON
DSG: OFF
VREG: ON
Overcurrent Protection
During Discharging
CHG: ON
DSG: OFF
VREG: ON
CHG: OFF
DSG: ON
VREG: ON
CHG: ON
DSG: OFF
VREG: OFF
VBAT > 2.3 V
for a period of
t > 4.0 ms
VBAT < 2.3 V
for a period of t > 24 ms
VM > 0.15 V for a period
of 12 ms
Normal
CHG: ON
DSG: ON
VREG: ON
VM < 0.15 V or
No Load detected
for a period of 4.0 ms
VM < –0.112 V
for a period of 12 ms
Overcurrent Protection
During Charging
Over-Discharge
Protection
VM > VBAT – 0.9 V
for a period of t > 400 µs
VM < 0.15 V
or
No Load detected
No Charger
Charger removed and
Load detected
for a period of 4.0 ms
VBAT > 4.25 V
for a period
of 1.0 s
VBAT < 4.07 V
for a period of 8.0 ms
Overcharge
Voltage Protection
CHG: OFF
DSG: ON
VREG: ON
Figure 2. FET Control Protection
16
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NOTE
When the CHG FET or DSG FET is turned OFF due to fault conditions, bus
communication is not valid. The bus communication will only be activated by removal of
the fault condition (see Table 1).
7.5.8 Regulator
Regulator out voltage is fixed at typically 2.5 V with a minimum output capacitance of 0.1 µF (0.47 µF typ). There
is an internal current limit designed for 60 mA (typ) when output is shorted to GND. When VDD is over 8.0 V
(typ), the regulator is turned off for the safety of the package dissipation.
7.6 Feature Description
7.6.1 Auto-Calibration
The bq28550-R1 device provides an auto-calibration feature that measures the voltage offset error across SRP
and SRN from time-to-time as operating conditions change. It subtracts the resulting offset error from the normal
sense resistor voltage, VSR, for maximum measurement accuracy.
Auto-calibration of the ADC begins on entry to SLEEP mode, except if Temperature() is ≤ 5°C or Temperature()
≥ 45°C.
The gas gauge also performs a single offset when (1) the condition of AverageCurrent() ≤ 100 mA and (2) {cell
voltage change since the last offset calibration ≥ 256 mV} or {temperature change since last offset calibration is
greater than 80°C for ≥ 60 s}.
Capacity and current measurements continue at the last measured rate during the offset calibration when these
measurements cannot be performed. If the battery voltage drops more than 32 mV during the offset calibration,
the load current has likely increased considerably and the offset calibration will be stopped.
7.6.2 Serial 2-Wire Communication System
The 2-wire communication bus supports a slave-only device in a single- or multi-slave configuration with a singleor multi-master configuration. The device can be part of a shared bus by the unique setting of the 7-bit slave
address. The 2-wire communication is bi-directional, consisting of a serial data line (SDA) and a clock line (SCL).
In receive mode, the SDA terminal operates as an input; whereas, when the device is returning data to the
master, the SDA operates as an open-drain output with an external resistive pull-up. The master device controls
the initiation of the transaction on the bus line.
Data Transfer: Each data bit is transferred during an SCL clock cycle (transition from low-to-high and then highto-low). The data signal on the SDA (logic level) must be stable during the high period of the SCL clock pulse. A
change in the SDA logic when SCL is high is interpreted as a START or STOP control signal. If a transfer is
interrupted by a STOP condition, the partial byte transmission shall not be latched. Only the prior messages
transmitted and acknowledged are latched.
Data Format: The data is an 8-bit format with the most significant bit (MSB) first and the least significant bit
(LSB) followed by an Acknowledge bit. If the slave cannot receive or transmit any byte of data until it services a
priority interrupt, it can pull the SCL line low to force the master device into wait state. The slave, once ready to
resume data transfer, can release the SCL line (get out of wait state).
Bus Idle: The bus is considered idle or busy when no master device has control of this device. The SDA and
SCL lines are high when the bus is idle. The appropriate method to go into the STOP condition is to ensure the
bus returns to idle state.
START (S) and STOP (P) Conditions: To initiate communications, the master device transitions the SDA line
from high-to-low when the SCL is high. Conversely, to STOP the communication, the SDA goes low-to-high
when the SCL is high. To continue communication without terminating one transaction and beginning another, a
repeated START (Sr) method can be used without a STOP condition being initiated. These are the only
conditions (START or STOP) when SDA transitions when SCL is high.
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Feature Description (continued)
Acknowledge Bits: An Acknowledge bit (A) is required after each data transfer byte to ensure correct
communications. This occurs when the receiving device pulls the SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse), and keeps it low until the SCL returns low. There is also a NoAcknowledge bit (N), which occurs when the receiver releases the SDA line (high) before the rising edge of
acknowledge-related clock pulse, and maintains the SDA line high until SCL returns low. The Acknowledge bit
indicates if a successful data transfer has occurred between the master and slave device. Monitoring this bit also
indicates an unsuccessful data transfer due to the receiving device being busy or as system fault occurrence.
Communication Format
A START command immediately followed by a STOP command is an illegal format.
MSB
S
Slave Address
R/W
A
Data
A
P
S = START Command
R/W = Read from slave device ("1") or Write to slave device ("0")
A = Acknowledge bit
P = STOP Command
Slave Address = 7-bit address field for register address
DATA = 8-bit data field
PEC = Packet Error Checking
Slave to Master
Master to Slave
Communication Format for Multi-Word with Packet Error Checking (PEC)
Table 2. Write Byte with PEC
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
W
A
Command
Code
A
Data Byte
A
PEC
A
P
Table 3. Write Word with PEC
1
7
1
1
8
1
8
1
8
1
8
1
1
S
Slave
Address
W
A
Command
Code
A
Data Byte
Low
A
Data Byte
High
A
PEC
A
P
Table 4. Read Byte with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
Slave
Address
W
A
Command
Code
A
S
Slave
Address
R
A
Data Byte
A
PEC
A
P
Table 5. Read Word with PEC
18
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
W
A
Command
Code
A
S
Slave
Address
R
A
Data
Byte
Low
A
Data
Byte
High
A
PEC
A
P
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The communication format and protocol complies with the SMBus.
7.6.3 Programming
7.6.3.1 General Purpose Input-Output
7.6.3.1.1 CFET Control
The GPIO can be configured to provide a signal called Charge FET control (CFET) using firmware. This output
controls external circuitry to change the state of the external CHG FET. A low signal on this pin in association
with recommended external components turns OFF the CHG FET. A high output maintains or turns ON the CHG
FET after a valid turn OFF activity. The state of the GPIO on power-up will be low until the system is initialized
and an internal power supply is active. The CFET control bit is located in the Control status register. If this output
is not used, then connect this pin to VREG externally.
The following parameters can be programmed in firmware for monitoring and protection using CFET control
circuitry, providing the limits are set within the boundaries of the hardware thresholds:
• Cell Overvoltage Condition
• Overcurrent Charging Condition
• Overtemperature Charging Condition
7.6.3.1.2 ALERT Output
Another option for the GPIO is to be configured as an ALERT output to indicate any one of the following fault
conditions, and to provide an interrupt signal to the host microprocessor:
• Overcurrent Charging Condition
• Overcurrent Discharging Condition
• Overtemperature Condition
• Overvoltage Condition
• Undervoltage Condition
The threshold trigger for these conditions is set through firmware registers, with each fault condition to be
selectable for detection. The output is an open drain output with an external pull-up (through a 3.3k resistor). The
ALERT output can be reset after the fault condition is removed OR can be latched and reset only by the host
MCU resetting the ALERT register value to zeroes. If this output is not used, then connect this pin to VREG
externally.
7.6.4 Communications
7.6.4.1 Authentication
The bq28550-R1 device can act as a SHA-1/HMAC authentication slave by using its internal engine. Refer to the
Application Note SLUA359 for SHA-1/HMAC for information.
By sending a 160-bit SHA-1 challenge message to the bq28550-R1 device, it causes the gauge to return a 160bit digest, based upon the challenge message and a hidden, 128-bit plain-text authentication key. If this digest
matches an identical one generated by a host or dedicated authentication master, and when operating on the
same challenge message and using the same plain text keys, the authentication process is successful.
7.6.4.1.1 Key Programming (Data Flash Key)
By default, the bq28550-R1 device contains a default plain-text authentication key of
0x0123456789ABCDEFFEDCBA9876543210. This default key is intended for development purposes. It should
be changed to a secret key and the part immediately sealed before putting a pack into operation. Once written, a
new plain-text key cannot be read again from the gas gauge while in SEALED mode.
Once the bq28550-R1 device is FULL ACCESS, the authentication key can be changed from its default value by
writing to the Authentication() Extended Data Command locations. A 0x00 is written to BlockDataControl() to
enable the authentication data commands. The bq28550-R1 device is now prepared to receive the 16-byte plaintext key, which must begin at the command location 0x40 and ending at 0x4f. Once written, the key is accepted
when a successful checksum for the key has been written to AuthenticateChecksum(). The gauge can then be
SEALED again.
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7.6.4.1.2 Key Programming (The Secure Memory Key)
As the name suggests, the bq28550-R1 secure-memory authentication key is stored in the secure memory of the
bq28550-R1 device. If a secure-memory key has been established and the Data Flash Key is
0x00000000000000000000000000000000, only this key can be used for authentication challenges (the
programmable data flash key is not available). The selected key can only be established/programmed by special
arrangements with TI, using TI’s Secure B-to-B Protocol. The secure-memory key can never be changed or read
from the bq28550-R1 device.
7.6.5 Device Functional Modes
The bq28550-R1 device has four power modes: NORMAL, SLEEP, HIBERNATE, and SHUTDOWN. In NORMAL
mode, the bq28550-R1 device is fully powered and can execute any allowable task. In SLEEP mode, the gas
gauge exists in a reduced-power state, periodically taking measurements and performing calculations. In
HIBERNATE mode, the gas gauge is in a low power state, but can be awakened by communication or certain I/O
activity. The device enters SHUTDOWN mode if there is a UVP condition detected or power down of the system.
The relationship between these modes is shown in Figure 3. Details are described in the sections that follow.
POR
NORMAL
Fuel gauging and data
updated every 1 s
Exit From HIBERNATE
VBAT < POR threshold
Exit From HIBERNATE
Communication Activity
OR
Entry to SLEEP
the gas gauge clears Control Status
Pack Configuration[ SLEEP] = 1
[ HIBERNATE ] = 0
AND
Recommend Host also set Control
| AverageCurrent( ) | =Sleep Current
Status [HIBERNATE] = 0
Exit From SLEEP
Pack Configuration [SLEEP ] =0
OR
| AverageCurrent( ) | > Sleep Current
OR
Exit from SHUTDOWN
Charger Detected
AND
Protection FETs closed
Current is Detected above I WAKE
HIBERNATE
SLEEP
SHUTDOWN
Fuel gauging and data
updated every 20 seconds
Disable all gas gauge
subcircuits except GPIO
Exit from PRE - SHUTDOWN
Wakeup From HIBERNATE
Communication Activity
AND
Comm address is NOT for the gas gauge
Entry to WAITFULLSLEEP
Full Sleep Wait Time > 0
Exit From WAITFULLSLEEP
Any Communication Cmd
Communication Activity
OR
Current Detected > I
WAKE
Entry to SHUTDOWN
Exit From WAIT _ HIBERNATE
Cell relaxed
AND
V
BAT < Hibernate Voltage
No Charger Present
WAITFULLSLEEP
Cell relaxed
AND
| AverageCurrent () | < Hibernate
Current
OR
FULLSLEEP Count Down
Exit From WAIT HIBERNATE
_
Host must set Control Status
[ HIBERNATE ] = 0
Entry to FULLSLEEP
AND
Host must set Control Status
V
BAT > Hibernate Voltage
[FULLSLEEP] = 1
WAIT_HIBERNATE
Entry to FULLSLEEP
Count < 1
Exit From FULLSLEEP
Any Communication Cmd
PRE - SHUTDOWN
FULLSLEEP
Fuel gauging and data
updated every 20 s
System HIBERNATION
Fuel Gauge is OFF
VBAT = 0 V
Entry to PRE-SHUTDOWN
Exit From SLEEP
(Host has set Control Status
[HIBERNATE ] = 1
OR
V
< Hibernate Voltage
In low-power state of SLEEP
mode. Gas gauging and data
are updated every 20 s.
[SHUTDOWN ] = 1
Fuel Gauging stopped
Discharge FET opened
IBAT = Hibernate
System SHUTDOWN
BAT
System SLEEP
Figure 3. Power Mode Diagram
7.6.5.1 NORMAL Mode
The gas gauge is in NORMAL mode when not in any other power mode. During this mode, AverageCurrent(),
Voltage(), and Temperature() measurements are taken, and the interface data set is updated. Decisions to
change states are also made. This mode is exited by activating a different power mode.
Because the gauge consumes the most power in NORMAL mode, the algorithm minimizes the time the gas
gauge remains in this mode.
20
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NOTE
When the battery is connected for the first time, discharging may not be enabled. For this
case, the following procedure is required:
• Short the VM pin and Vss pin, or
• Connect the charger to the system such that the IC returns to normal status.
7.6.5.2 SLEEP Mode
SLEEP mode is entered automatically if the feature is enabled (Operation Configuration [SLEEP]) = 1) and
AverageCurrent() is below the programmable level Sleep Current. Once entry into SLEEP mode has been
qualified, but prior to entering it, the bq28550-R1 device performs an ADC auto-calibration to minimize offset.
While in SLEEP mode, the gas gauge can suspend serial communications as much as 4 ms by holding the
comm line(s) low. This delay is necessary to correctly process host communication, because the gas gauge
processor is mostly halted in SLEEP mode.
During SLEEP mode, the bq28550-R1 device periodically takes data measurements and updates its data set.
However, a majority of its time is spent in an idle condition. The bq28550-R1 device exits SLEEP if any entry
condition is broken, specifically when (1) AverageCurrent() rises above Sleep Current, or (2) a current in excess
of IWAKE through RSENSE is detected.
7.6.5.3 FULLSLEEP Mode
FULLSLEEP mode is entered automatically if the feature is enabled by setting the Configuration [FULLSLEEP]
bit in the Control Status register when the bq28550-R1 device is in SLEEP mode. The gauge exits FULLSLEEP
mode when there is any communication activity. Therefore, the execution of SET_FULLSLEEP sets the
[FULLSLEEP] bit, but EVSW might still display the bit clear. FULLSLEEP mode can be verified by measuring the
current consumption of the gauge. In this mode, the high frequency oscillator is turned off. The power
consumption is further reduced in this mode compared to the SLEEP mode.
FULLSLEEP mode can also be entered by setting the Full Sleep Wait Time to be a number larger than 0.
FULLSLEEP will be entered when the timer counts down to 0. This feature is disabled when the data flash is set
as 0.
During FULLSLEEP mode, the bq28550-R1 device periodically takes data measurements and updates its data
set. However, a majority of its time is spent in an idle condition.
The bq28550-R1 device exits SLEEP if any entry condition is broken, specifically when (1) AverageCurrent()
rises above Sleep Current, or (2) a current in excess of IWAKE through RSENSE is detected.
While in FULLSLEEP mode, the gas gauge can suspend serial communications as much as 4 ms by holding the
comm line(s) low. This delay is necessary to correctly process host communication, because the gas gauge
processor is mostly halted in SLEEP mode.
7.6.5.3.1 Clearing FULLSLEEP Mode
FULLSLEEP mode will stay on permanently if Full Sleep Wait Time is not set to 0.
Clearing FULLSLEEP mode:
• If Full Sleep Wait Time is set to 0, the CLEAR condition clears the flag. If it is not set to 0, the CLEAR
condition resets the timer.
• The CLEAR condition determines that there is I2C™ communication while FULLSLEEP is active. I2C
communication while not in FULLSLEEP will NOT clear the flag. This means if there is current flowing when
the FULLSLEEP command is sent, there is no way to clear it until after the device enters SLEEP mode.
7.6.5.4 HIBERNATE Mode
HIBERNATE mode should be used when the host system needs to enter a low-power state, and minimal gauge
power consumption is required. This mode is ideal when the host is set to its own HIBERNATE, SHUTDOWN, or
OFF modes. The gas gauge can enter HIBERNATE due to either low cell voltage or low load current.
• HIBERNATE due to the load current—If the gas gauge enters HIBERNATE mode due to the load current, the
[HIBERNATE] bit of the CONTROL_STATUS register must be set. The gauge waits to enter HIBERNATE
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mode until it has taken a valid OCV measurement and the magnitude of the average cell current has fallen
below Hibernate Current.
HIBERNATE due to the cell voltage—When the cell voltage drops below the Hibernate Voltage and a valid
OCV measurement has been taken, the gas gauge enters HIBERNATE mode. The [HIBERNATE] bit of the
CONTROL register has no impact for the gas gauge to enter the HIBERNATE mode. If the [SHUTDOWN] bit
of CONTROL _STATUS is also set.
The gauge will remain in HIBERNATE mode until communication activity appears on the communication lines.
Upon exiting HIBERNATE mode, the [HIBERNATE] bit of CONTROL_STATUS is cleared.
Because the gas gauge is dormant in HIBERNATE mode, the battery should not be charged or discharged in this
mode, because any changes in battery charge status will not be measured. If necessary, the host equipment can
draw a small current (generally infrequent and less than 1 mA, for purposes of low-level monitoring and
updating); however, the corresponding charge drawn from the battery will not be logged by the gauge. Once the
gauge exits to NORMAL mode, the algorithm re-establishes the correct battery capacity.
If a charger is attached, the host should immediately take the gas gauge out of HIBERNATE mode before
beginning to charge the battery.
CAUTION
Charging the battery in HIBERNATE mode results in a notable gauging error that will
take several hours to correct.
7.6.5.5 SHUTDOWN Mode
The device enters SHUTDOWN mode if there is a UVP condition detected or if there is a power down of the
system, and alternatively by setting the SHUTRQ bit to 1, if appropriate conditions are met. The device can also
disable SHUTDOWN by using the CLEAR_SHUTDOWN (0x0014) option.
•
•
NOTE
A SHUTDOWN command should NOT be invoked if charger voltage is present.
Sending a SHUTDOWN command while charger voltage is present causes a 1–2 s
time of DSG FET off, and may or may not cause a watchdog reset. (If current is ≤ 0
after the DSG FET is opened, it will attempt to shutdown and start a watchdog;
otherwise, it will only clear the shutdown flag without a reset).
Figure 4 shows an overview of the hardware controlled SHUTDOWN operation.
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Shutdown
CHG: OFF
DSG: OFF
VREG: OFF
No Charger
Charger attached
Over - Discharge
Voltage
CHG: ON
DSG: OFF
VREG OFF
VBAT < 2.3 V
for a period
of t > 24 ms
VBAT > 2.3 V
for a period
of t > 4.0 ms
Normal
CHG: ON
DSG: ON
VREG: ON
VBAT< 2.3 V
for a period
of t > 24 ms
FG shutdown
FG turn
on DSG
FG turn
off DSG
DSG "OFF”
CHG: ON
DSG: OFF
VREG: ON
Figure 4. Shutdown Operation
7.6.5.6 Operational Modes
The sequence of the operational modes is as follows: NORMAL to SLEEP to FULLSLEEP; FULLSLEEP to either
HIBERNATE or SHUTDOWN; or SLEEP to SHUTDOWN.
Table 6. Operational Modes
Mode
NORMAL
Enter Mode
Exit Mode
If ALL conditions such as Average
Current, Cell Voltage, and
Temperature are satisfied.
Go into other modes like SLEEP,
FULLSLEEP, HIBERNATE, or
SHUTDOWN mode if conditions are
satisfied.
Comment
In this mode, power consumption is
the highest. Measurements are taken
and updated every 1 s.
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Table 6. Operational Modes (continued)
Mode
SLEEP
FULLSLEEP
HIBERNATION
SHUTDOWN
Enter Mode
Exit Mode
Comment
SLEEP bit set = 1 in operation
register AND AverageCurrent
measured is equal to Sleep current
value.
Change SLEEP bit = 0 OR
AverageCurrent measurement > Sleep The data is measured every 20 s to
current value OR Current detected is
reduce current consumption.
above the IWAKE setting.
From SLEEP mode if the
WAIT_FULLSLEEP wait is
programmed, this is the time the
system must be in SLEEP mode
before it can go to FULLSLEEP
mode.
The system exits the FULLSLEEP
mode if there are any communication
commands set on the bus to the
device.
The wait time to enter FULLSLEEP
from SLEEP is 1 s to 240 s with the
default at 15 s.
From FULLSLEEP mode, the system
will go into HIBERNATE mode if the
load current decreases to the
programmed value,
OR if the cell voltage falls below the
programmed value,
OR the host sets the command in
MAC.
The system exits this mode is the
VCELL > programmed threshold,
OR load current is > programmed
threshold,
OR communication activity on bus line,
OR host sets the command in MAC.
Enters hibernation if VCELL range is
2.4 V to 3 V with default at 2.55 V.
The load current threshold range is 0
to 0.7 A with a default value of 8 mA.
From SLEEP mode, the system will
enter this mode if the VCELL < 2.4 V
for a period longer than 24 ms and
the charger is not attached. The
system can also be put in
SHUTDOWN mode through MAC.
Exit from this mode if there is bus
activity,
OR the load current detected is >
IWAKE ,
OR the charger is connected to the
system.
In this mode, the VREG and DSG
FET are turned OFF and the system
will only wake up if the charger is
attached on the Pack+, Pack–
terminals.
7.6.5.7 Data Commands
7.6.5.7.1 Standard Data Commands
The bq28550-R1 device uses the following Command Code. Data RAM is updated and read by the gauge only
once per second. Standard commands are accessible in NORMAL operation mode.
Table 7. Standard Commands
24
Name
Command Code
Min Value
Max Value
Default value
Units
Sealed Access
ManufacturerAccess()
0x00
BatteryMode()
0x03
0x0000
0xffff
—
—
R/W
0x0000
0xe383
—
—
Temperature()
0x08
R/W
0
65535
—
0.1K
R
Voltage()
Current()
0x09
0
65535
—
mV
R
0x0a
–32768
32767
—
mA
R
AverageCurrent()
0x0b
–32768
32767
—
mA
R
MaxError()
0x0c
0%
100%
—
RelativeStateOfCharge()
0x0d
0%
100%
—
R
R
RemainingCapacity()
0x0f
0
65535
—
mAh or 10
mWh
FullChargeCapacity()
0x10
0
65535
7200
mA
R
ChargingCurrent()
0x14
0
65534
2500
mA
R
ChargingVoltage()
0x15
0
65534
12600
mV
R
BatteryStatus()
0x16
0x0000
0xdbff
—
—
R
R/W
CycleCount()
0x17
0
65535
0
—
R/W
DesignCapacity()
0x18
0
65535
7200
mAh
R/W
DesignVoltage()
0x18
0
65535
3600
mV
R/W
SpecificationInfo()
0x1a
0x0000
0xffff
0x0031
—
R/W
ManufactureDate()
0x1b
—
—
0
ASCII
R/W
SerialNumber()
0x1c
0x0000
0xffff
0x0001
—
R/W
ManufacturerName
0x20
—
—
Texas Inst
ASCII
R/W
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Table 7. Standard Commands (continued)
Name
Command Code
Min Value
Max Value
Default value
Units
Sealed Access
DeviceName()
0x21
—
—
bq28550-R1
ASCII
R/W
DeviceChemistry()
0x22
—
—
LION
ASCII
R/W
ManufacturerData()
0x23
—
—
—
ASCII
R/W
Authenticate()
0x2f
—
—
—
ASCII
R
CellVoltage1()
0x3f
0
65535
—
mV
R
OperationStatus()
0x54
0x0000
0xffff
—
0xf7f7
R
ChargingStatus()
0x55
0x0000
0xffff
—
—
R
UnSealKey()
0x60
0x00000000
0xffffffff
—
—
R/W
FullAccessKey()
0x61
0x00000000
0xffffffff
—
—
R/W
AuthenKey0()
0x63
0x00000000
0xffffffff
—
—
R/W
AuthenKey1()
0x64
0x00000000
0xffffffff
—
—
R/W
AuthenKey2()
0x65
0x00000000
0xffffffff
—
—
R/W
AuthenKey3()
0x66
0x00000000
0xffffffff
—
—
R/W
ManufacturerInfo()
0x70
—
—
—
ASCII
R/W
SenseResistor()
0x71
0
65535
—
µΩ
R/W
Temperature()
0x72
0x0000
0xffff
—
—
R
ManufacturerStatus()
0xB1
—
—
R
Extended SBS Data Commands
7.6.5.7.2 Run-Time-to-Empty
Battery pack run-time-to-empty can be calculated using the following method—the host system reads and stores
the following information during a discharge period and averages the data over a user-determined period of time:
• The DSG bit of the BatteryStatus register is set to ensure DOUT terminal is high (ensure the system is in
discharge mode).
• AverageCurrent (mA)
– Positive value = Charge Current
– Negative value = Discharge Current
– One minute rolling average of current value (the user can accumulate this time for improved granularity)
• RemainingCapacity (mAh)
Run-Time-to-Empty = RemainingCapacity (avg mAh) ÷ AverageCurrent (mA). This result will be in hours, and
therefore to convert to minutes, divide the results by 60.
7.6.5.7.3 Charging Time To Full
This is a read-only function that predicts the remaining time until battery reaches full charge in minutes based on
Average Current(). The computation accounts for the taper current time extension from the linear TTF
computation based on a fixed Average Current() rate of change of accumulation. A value of 65,535 indicates a
battery is NOT being charged.
7.6.5.7.4 Remaining Capacity Alert
To set a notification when battery capacity is below a pre-determined value, the user can set a Remaining
Capacity alarm alert in the system side. The Remaining Capacity value determined by the bq28550-R1 device is
compared to the user-selected value. If the Remaining Capacity value < the user-selected Remaining Capacity
threshold, the host system should instruct the user on what action is needed.
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7.6.5.7.5 Remaining Time Alert
Similar to the Remaining Capacity notification, a system may require an alarm based on time rather than
Remaining Capacity. To set a notification when remaining time to empty is less than the user-set value, the user
can set a remaining time to empty alarm alert in the system side. The remaining time to empty value determined
by the bq28550-R1 device is compared to the user-selected value. If the Remaining Time to Empty value < the
user-selected Remaining Time to Empty threshold, the host system should instruct the user of what action to
take.
7.6.5.7.6 Data Flash Interface
7.6.5.7.6.1 Accessing the Data Flash
The bq28550-R1 data flash is a non-volatile memory that contains bq28550-R1 initialization, default, cell status,
calibration, configuration, and user information. The data flash can be accessed in several different ways,
depending on what mode the bq28550-R1 device is operating in and what data is being accessed.
Commonly accessed data flash memory locations, frequently read by a system, are conveniently accessed
through specific instructions, as described in . These commands are available when the bq28550-R1 device is
either in FULL ACCESS, UNSEALED, or SEALED modes.
Most data flash locations, however, are only accessible in FULL ACCESS or UNSEALED mode by using the
bq28550-R1 evaluation software or by data flash block transfers. These locations should be optimized and/or
fixed during the development and manufacture processes. They become part of a golden image file and can then
be written to multiple battery packs. Once established, the values generally remain unchanged during endequipment operation.
7.6.5.7.6.2 Read-Write Access of Data Flash
To read and write commands in data flash, the following method is used:
Command Type
SBS Command
SBS Data
Description
Write Word
0x00
0x1yy
ManufacturerAccess() command to set up the data flash (DF) address
in order to write a row (32-byte) of data. Yy = the row number where
the target DF address is located.
Read/Write Block
0x2F
32-byte of data
ManufacturerInput() command. Issue this command after setting up the
DF address to read/write the 32-byte data to the DF.
The following is an example procedure to update a parameter in data flash.
1. Identify the physical byte location of the target parameter using the class and subclass ID information. This is
typically the subclass ID + Offset.
2. Identify the target row number by truncating the division of the byte location and the row length; for example,
a byte location 27 would be in row: 27 divided by 32 = row number 0.
3. Byte location within the target row is determined by: Byte Index = physical location – (row number * row
length)
Byte Index = 27 – (0 *32) = 27
The target byte is in row 0 byte 27.
4. Using MAC command 0x1yy, where yy = row number. In this example, the SMBus write command would be
0x100.
5. Read the original target row first through a block read command 0x2F before updating.
6. Store original data in memory array, so the appropriate byte(s) can be updated.
SMBus block read cmd = 0x2F, length = 32 byte
7. Store the read data into a memory array (for example, yRowDataArray).
8. Update the target byte (yRowDataArray(27).
9. Write the updated yRowDataArray() array back to the device data flash. To do this, repeat Step 4. Issue
SMBus block write cmd = 0 × 27, length 32.
10. A read verify is recommended to ensure the data flash has been re-programmed correctly. To do a read
verify, repeat Steps 4 and 5.
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7.6.5.7.6.2.1 Flash Updates
Data flash can only be updated if Voltage() ≥ Flash Update OK Voltage. Flash programming current can cause
an increase in LDO dropout. The value of Flash Update OK Voltage should be selected so that the bq28550-R1
VCC voltage does not fall below its minimum of 2.4 V during flash write operations.
7.6.5.7.7 Manufacturer Information Blocks
The bq28550-R1 device contains 96 bytes of user-programmable data flash storage: Manufacturer Info Block
A, Manufacturer Info Block B, Manufacturer Info Block C. The method for accessing these memory locations
is slightly different, depending on whether the device is in FULL ACCESS, UNSEALED, or SEALED mode.
7.6.5.7.8 Access Modes
The bq28550-R1 device provides three security modes (FULL ACCESS, UNSEALED, and SEALED) that control
data flash access permissions. Data flash refers to those data flash locations that are accessible to the user, as
specified in Table 8.
Table 8. Data Flash Access
Security Mode
SBS Commands
Data Flash
Device Programming
FULL ACCESS
Standard and Extended
Commands R/W
R/W
Yes
UNSEALED
Standard and some Extended
Commands R/W
R/W
No
SEALED
Standard Commands R/W
None
No
7.6.6 Charging and Charge Termination Indication
7.6.6.1 Detection Charge Termination
For proper bq28550-R1 operation, the user must specify cell charging voltage. The default value for this variable
is in the data flash Charging Voltage.
The bq28550-R1 device detects charge termination when:
The battery current drops below the Taper Current for two consecutive Current Taper Window time periods
during charging AND battery voltage is equal to or higher than the Charging Voltage – Taper Voltage. Full
Charge is set when the taper condition is met.
7.6.6.2 Charge Suspend
The bq28550-R1 device suspends charging when:
• Temperature < JT1, OR
• Temperature > JT4 in CHARGE-SUSPEND mode, if the [CHGSUSP] bit in OperationConfiguration is set.
This will set the charging current to zero and the charging voltage to zero in the Safety Status Register. Also, the
CHG bit is reset in ControlStatus register. The bq28550-R1 device can indicate to resume charging if:
• Temperature ≥ JT1 + Temp Hys, AND
• Temperature ≤ JT3 – Temp Hys.
On resuming, the bq28550-R1 device sets the CHG bit in the ControlStatus Register, and sets ChargingCurrent
according to the appropriate charging mode entered. The bq28550-R1 device also leaves the charge-suspend
mode when the battery is removed in removable battery mode ([NR] = 0).
7.6.6.3 MANUFACTURER ACCESS(): 0x00/0x01
Issuing a Control() command requires a subsequent 2-byte subcommand. These additional bytes specify the
particular control function desired. The Control() command allows the system to control specific features of the
bq28550-R1 device during normal operation, and additional features when the device is in an access mode
(described in Table 9).
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Table 9. Control() Subcommands
CNTL Function
CNTL Data
Sealed Access
Description
SET_FULLSLEEP
0x0010
Yes
Set the [FullSleep] bit in Control
Status register to 1
SET_HIBERNATE
0x0011
Yes
Forces CONTROL_STATUS
[HIBERNATE] to 1
CLEAR_HIBERNATE
0x0012
Yes
Forces CONTROL_STATUS
[HIBERNATE] to 0
SET_SHUTDOWN
0x0013
Yes
Forces CONTROL_STATUS
[SHUTDOWN] to 1
CLEAR_SHUTDOWN
0x0014
Yes
Forces CONTROL_STATUS
[SHUTDOWN] to 0
HOST_DISCONNECT
0x0017
Yes
Forces the DOUT pin low to
disable discharge.
HOST_Enable
0x0018
Yes
Forces the DOUT pin high to
enable discharge.
7.6.6.4 CONTROL STATUS: 0x0000
Instructs the gas gauge to return status information to Control Status 0x00/0x01. The status word should include
the following information.
Table 10. CONTROL STATUS Flags
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High Byte
RSVD
RSVD
RSVD
RSVD
CCA
BCA
RSVD
RSVD
Low Byte
SHUTRQ
HIBERNATE
FULLSLEEP
SLEEP
DSGOFFREQ
RSVD
CHG
DSG
Low Byte
Bit 0 = DSG FET Status, 1 = Discharging allowed (DSG FET ON), 0 = Discharging NOT allowed ( DSG FET
Turned OFF).
Bit 1 = CHG FET Status, 1 = Charging allowed (CHG FET ON), 0 = Charging NOT allowed action to be taken by
Host MCU.
Bit 2 = RSVD (Reserved)
Bit 3 = DSGOFFREQ, DSG FET OFF requested
Bit 4 = SLEEP, Status bit indicating the device is in SLEEP mode. True when set.
Bit 5 = FULLSLEEP, Status bit indicating the device is in FULLSLEEP mode. True when set. The state can be
detected by monitoring the power used by the device because any communication will automatically clear it.
Bit 6 = HIBERNATE, Status bit indicating a request for entry into HIBERNATE from SLEEP mode has been
issued. True when set. Default is 0. Control bit when set will put the device into the lower power state of SLEEP
mode. It is not possible to monitor this bit. Bit 7 = SHUTRQ. Status bit indicating the gas gauge is enabled to
enter SHUTDOWN mode. True when set. Default is 0.
Bit 7 = SHUTRQ, 1 = SHUTDOWN requested
High Byte
Bit 0, 1 = RSVD (Reserved)
Bit 2 = BCA = Status bit indicating the device Board Calibration routine is active. Active when set.
Bit 3 = CCA = Status bit indicating the device Coulomb Counter Calibration routine is active. Active when set.
Bit 4, 5, 6, 7 = RSVD (Reserved)
The following MAC commands are also available.
28
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7.6.6.4.1 SET_FULLSLEEP: 0X0010
Instructs the gas gauge to set the FULLSLEEP bit in the Control Status register to 1. This allows the gauge to
enter the FULLSLEEP power mode after the transition to SLEEP power state is detected. In FULLSLEEP mode,
less power is consumed by disabling an oscillator circuit used by the communication engines. A communication
to the device in FULLSLEEP forces it back to SLEEP mode.
7.6.6.4.2 SET_HIBERNATE: 0x0011
Instructs the gas gauge to force the CONTROL_STATUS [HIBERNATE] bit to 1. This allows the gauge to enter
the HIBERNATE power mode after the transition to SLEEP power state is detected. The [HIBERNATE] bit is
automatically cleared upon exiting from HIBERNATE mode.
7.6.6.4.3 CLEAR_HIBERNATE: 0x0012
Instructs the gas gauge to force the CONTROL_STATUS [HIBERNATE] bit to 0. This prevents the gauge from
entering the HIBERNATE power mode after the transition to SLEEP power state is detected. It can also be used
to force the gauge out of HIBERNATE mode.
7.6.6.4.4 SET_SHUTDOWN: 0x0013
Sets the CONTROL_STATUS [SHUTDOWN] bit to 1, enabling the device to enter SHUTDOWN mode if the
appropriate conditions are met.
7.6.6.4.5 CLEAR_SHUTDOWN: 0X0014
Clears the CONTROL_STATUS [SHUTDOWN] bit to 1, disabling the device from entering SHUTDOWN mode.
7.6.6.4.6 DSG FET OFF (HOST_DISCONNECT): 0x0017
Instructs the gas gauge to force the protection DOUT pin to low level. This prohibits discharging the battery by
turning off the external discharge control N-channel MOSFET.
7.6.6.4.7 DSG FET ON (HOST_CONNECT): 0x0018
Instructs the gas gauge to force the protection DOUT pin to high level. This allows discharging the battery by
turning on the external discharge control N-channel MOSFET.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Typical Application
FUSE
PACK+
SCL
SDA
100 Ω
12
COUT 2
11
VM 3
10
0.1 µF
5M
0.1 µF
5M
VREG
100 Ω
SCL
100 Ω
SDA
8
CELLN
SRN
5V6
13
PWPD
0.1 µF
CHG
S
100 Ω
100 Ω
D
S
5V6
7 SRP
6
0.1 µF
PACK–
CELLP
9 TS
4
VREG 5
VSS
100 Ω
100 k
10 mΩ
0.1 µF
BAT
510 Ω
GPIO
0.47 µF
DOUT 1
VREG
DSG
BC847BPDXV6
12k
5k
Figure 5. Application—CFET
30
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R1
0.005
0.1uF
R4
5M
TR-BC847BPDXV6T1
Q3-B
SRN
0.1 µF
S
Copyright © 2012–2014, Texas Instruments Incorporated
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0.1 µF
13
PWPD
100 Ω
8
100 Ω
5
0.47 µF
100 Ω
5V6
5V6
CSD16340Q3
CSD16340Q3
Q1
R16
5.1k
USB mini-AB
9
100 Ω
SDA
R15
12k
7
GND
5
10
4
SCL
S1
R17
100k
VBUS
D–
D+
11
WAKE
VREG
J8
ID
6
4
3
2
1
0.1 µF
3
100 Ω
Q3-A
SCL
EARTH_GND
J1
SDA
GND
TP3
PACK–
VSS 6
EARTH_GND
EARTH_GND
1
2
3
4
COUT 2
GPIO
1K
0.1uF
HDQ
D2
GND SIDE
GND SIDE
100 R12 100
MM3Z5V6C
D1
R11
R10 100
PACK+/LOAD+
PACK–/LOAD–
12
C4
R9 100
3
DOUT 1
R13
0.1uF
R6
510
0.1uF
C8
TP4
PACK+
TB2
2
1
100 Ω
100 Ω
100 Ω
SDA
C3
R5
5M
7
J7
GND SIDE
GND
HDQ
0.1 µF
C2
TP6
VM
SRP
SRN
EARTH_GND
1
2
3
HDQ
5M
0.1uF
C1
VSS
VREG
9
8
MM3Z5V6C
D3
4
BAT
100
100
1uF
C6
6
TS
10
2
1
R18 100
VREG
R2
R3
0.1uF
C5
PWPD
TP1
CELL–
TB1
1
SCL
SDA
11
12
R19 100
D
CELL–
BAT
VM
COUT
HDQ
R14
3.3K
GND SIDE
5
4
3
U1
BQ28550 R1
DOUT
2
5M
2
3
1
2
2
1
CHG
CELL+
TP7 DOUT
J6
J5
R7
3.3K
1
R8
3.3K
2
J4
1
2
J3
1
S
TP5 COUT
0.47uF
J2
PACK–
CELL+
TP2
C7
RT1
10K
510 Ω
CASE
VM
CASE
VREG
TP8
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SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
bq28550-R1
Typical Application (continued)
PACK+
FUSE
SCL
VREG
ALERT
3.3K
VREG
TS
5V6
CELLP
7 SRP
CELLN
0.1 µF
DSG
10 mΩ
Figure 6. Application—ALERT
TR-BC847BPDXV6T1
13
Q2
Note: R4 and R5 must be greater than 3 MΩ.
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Typical Application (continued)
Figure 7. Typical Application Schematic
32
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SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014
9 Device and Documentation Support
9.1 Related Documentation
9.1.1 Documentation Support
For more information, see the bq28551-R1 Technical Reference Manual (SLUU889).
9.2 Trademarks
I2C is a trademark of NXP B.V. Corporation.
9.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ28550DRZR
ACTIVE
SON
DRZ
12
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
2855
BQ28550DRZR-R1
ACTIVE
SON
DRZ
12
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ28
50R1
BQ28550DRZT
ACTIVE
SON
DRZ
12
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ
2855
BQ28550DRZT-R1
ACTIVE
SON
DRZ
12
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ28
50R1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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