BQ294713DSGT

BQ2947 SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 BQ2947 Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries with External Delay Capacitor 1 Features 3 Description • • • The BQ2947 family is an overvoltage monitor and protector for Li-Ion battery pack systems. Each cell is monitored independently for an overvoltage condition. • • • • • 2-, 3-, and 4-series cell overvoltage protection External capacitor-programmed delay timer Factory programmed OVP threshold (threshold range 3.85 V to 4.6 V) Output options: active high or open drain active low High-accuracy overvoltage protection: ±10 mV Low power consumption ICC ≈ 1 µA (VCELL(ALL) < VPROTECT) Low leakage current per cell input < 100 nA Small package footprint – 8-pin WSON (2.00 mm x 2.00 mm) 2 Applications • • In the BQ2947 device, an external delay timer is initiated upon detection of an overvoltage condition on any cell. Upon expiration of the delay timer, the output is triggered into its active state (either high or low, depending on the configuration). The external delay timer feature also includes the ability to detect an open or shorted delay capacitor on the CD pin, which will similarly trigger the output driver in an overvoltage condition. For quicker production-line testing, the BQ2947 device provides a Customer Test Mode with 67 reduced delay time. Notebooks UPS battery backup Device Information PART NUMBER(1) BQ294700 (1) PACKAGE BODY SIZE (NOM) WSON (8) 2.00 mm × 2.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Pack+ 100 Ω VCELL4 VCELL3 VCELL2 1k 0.1µF 1k 0.1µF 1k OUT VDD 1k 0.1µF V4 CD V3 VSS V2 V1 PWPD 0.1 µF VCELL1 0.1 µF 0.1µF Pack– Copyright © 2017, Texas Instruments Incorporated Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................5 7.4 Thermal Information....................................................5 7.5 Electrical Characteristics.............................................6 7.6 Typical Characteristics................................................ 7 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description.....................................................9 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 13 9.1 Application Information............................................. 13 9.2 Typical Applications.................................................. 13 10 Power Supply Recommendations..............................16 11 Layout........................................................................... 16 11.1 Layout Guidelines................................................... 16 11.2 Layout Example...................................................... 16 12 Device and Documentation Support..........................17 12.1 Third-Party Products Disclaimer............................. 17 12.2 Documentation Support.......................................... 17 12.3 Receiving Notification of Documentation Updates..17 12.4 Support Resources................................................. 17 12.5 Trademarks............................................................. 17 12.6 Electrostatic Discharge Caution..............................17 12.7 Glossary..................................................................17 13 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History Changes from Revision I (June 2018) to Revision J (May 2021) Page • Updated the BQ294712 and BQ294713 devices in the Device Options table ...................................................3 Changes from Revision H (February 2018) to Revision I (June 2018) Page • Added BQ294713 to the Device Options table .................................................................................................. 3 • Added BQ294713 to the Electrical Characteristics ............................................................................................6 Changes from Revision G (November 2017) to Revision H (February 2018) Page • Changed BQ294712 to Production Data in the Device Options table ............................................................... 3 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 5 Device Comparison Table PART NUMBER OVP (V) OV HYSTERESIS OUTPUT DRIVE BQ294700 4.350 0.300 CMOS Active High BQ294701 4.250 0.300 CMOS Active High BQ294702 4.300 0.300 CMOS Active High BQ294703 4.325 0.300 CMOS Active High BQ294704 4.400 0.300 CMOS Active High BQ294705 4.450 0.300 CMOS Active High BQ294706 4.550 0.300 CMOS Active High BQ294707 4.225 0.050 NCH Open Drain Active Low BQ294708 4.500 0.300 CMOS Active High BQ294711 4.220 0.300 CMOS Active High BQ294712 4.125 0.300 CMOS Active High BQ294713 4.600 0.300 CMOS Active High BQ2947 3.850–4.60 0–0.300 CMOS Active High or Open Drain Active Low Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 3 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 6 Pin Configuration and Functions VDD 1 V4 2 V3 3 V2 4 Thermal Pad 8 OUT 7 CD 6 VSS 5 V1 Not to scale Figure 6-1. DSG Package 8-Pin WSON Top View Table 6-1. Pin Functions NUMBER NAME TYPE(1) 1 VDD P Power supply input 2 V4 IA Sense input for positive voltage of the fourth cell from the bottom of the stack 3 V3 IA Sense input for positive voltage of the third cell from the bottom of the stack 4 V2 IA Sense input for positive voltage of the second cell from the bottom of the stack 5 V1 IA Sense input for positive voltage of the lowest cell in the stack 6 VSS P Electrically connected to IC ground and negative terminal of the lowest cell in the stack 7 CD OA OUT OA 8 PowerPAD™ (1) 4 DESCRIPTION P External capacitor connection for delay timer Analog Output drive for overvoltage fault signal. Active High or Open Drain Active Low TI recommends connecting the exposed pad to VSS on the PCB. IA = Input Analog, OA = Output Analog, P = Power Connection Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD–VSS –0.3 30 V Input voltage V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS –0.3 30 V Output voltage OUT–VSS –0.3 30 V Supply voltage Continuous total power dissipation, PTOT See Section 7.4 Lead temperature (soldering, 10 s), TSOLDER 300 Storage temperature, Tstg (1) –65 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101(2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over-operating free-air temperature range (unless otherwise noted) Supply voltage, VDD Input voltage range V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS Operating ambient temperature range, TA MIN MAX UNIT 3 20 V 0 5 V –40 110 °C 7.4 Thermal Information BQ2947 THERMAL METRIC(1) WSON UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 62 °C/W RθJC(top) Junction-to-case(top) thermal resistance 72 °C/W RθJB Junction-to-board thermal resistance 32.5 °C/W ψJT Junction-to-top characterization parameter 1.6 °C/W ψJB Junction-to-board characterization parameter 33 °C/W RθJC(bottom) Junction-to-case(bottom) thermal resistance 10 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 5 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 7.5 Electrical Characteristics Typical values stated where TA = 25°C and VDD = 14.4V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3 V to 20 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE PROTECTION THRESHOLDS V(PROTECT) Overvoltage Detection VOV BQ294700, RIN = 1 kΩ 4.350 V BQ294701, RIN = 1 kΩ 4.250 V BQ294702, RIN = 1 kΩ 4.300 V BQ294703, RIN = 1 kΩ 4.325 V BQ294704, RIN = 1 kΩ 4.400 V BQ294705, RIN = 1 kΩ 4.450 V BQ294706, RIN = 1 kΩ 4.550 V BQ294707, RIN = 1 kΩ 4.225 V BQ294708, RIN = 1 kΩ 4.500 V BQ294711, RIN = 1 kΩ 4.220 V BQ294712, RIN = 1 kΩ 4.125 V BQ294713, RIN = 1 kΩ 4.600 V VHYS OV Detection Hysteresis BQ2947(1) 250 400 mV VOA OV Detection Accuracy TA = 25°C –10 10 mV TA = –40°C –40 40 mV TA = 0°C –20 20 mV TA = 60°C –24 24 mV TA = 110°C –54 54 mV 2 µA 0.1 µA VOADRIFT OV Detection Accuracy Across Temperature 300 SUPPLY AND LEAKAGE CURRENT IDD Supply Current (V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V at TA = 25°C (See Figure 8-4.) IIN Input Current at Vx Pins (V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V at TA = 25°C (See Figure 8-4.) ICELL Input Current (ALL Vx and VDD Input Pins) Current Consumption at Power down, (V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 2.30 V at TA = 25°C 1 –0.1 1.1 µA OUTPUT DRIVE OUT, CMOS ACTIVE HIGH VERSIONS ONLY (V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD = 14.4 V, IOH = 100 µA VOUT Output Drive Voltage, Active High 6 If three of four cells are short circuited, only one cell remains powered and > VOV, VDD = Vx (cell voltage), IOH = 100 µA VDD – 0.3 (V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV, VDD = 14.4 V, IOL = 100 µA measured into OUT pin. IOUTH OUT Source Current (during OV) (V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD = 14.4 V, OUT = 0 V, measured out of OUT pin. IOUTL OUT Sink Current (no OV) (V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV, VDD = 14.4 V, OUT = VDD, measured into OUT pin .Pull resistor RPU = 5 kΩ to VDD = 14.4 V V 250 0.5 V 400 mV 4.5 mA 14 mA 400 mV OUTPUT DRIVE OUT, CMOS OPEN DRAIN ACTIVE LOW VERSIONS ONLY VOUT 6 Output Drive Voltage, Active High (V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV, VDD = 14.4 V, IOL = 100 µA measured into OUT pin. Submit Document Feedback 250 Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 7.5 Electrical Characteristics (continued) Typical values stated where TA = 25°C and VDD = 14.4V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3 V to 20 V (unless otherwise noted). PARAMETER TEST CONDITIONS IOUTL OUT Sink Current (no OV) (V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV, VDD = 14.4 V, OUT = VDD, measured into OUT pin. Pull resistor RPU = 5 kΩ to VDD = 14.4 V MIN IOUTLK OUT pin leakage (V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV, VDD = 14.4 V, OUT = VDD, measured into OUT pin. TYP 0.5 MAX UNIT 14 mA 100 nA DELAY TIMER tCD OV Delay Time CCD = 0.1 µF (see External Delay Capacitor, CD) 1 tCD_GND OV Delay Time with CD pin = 0 V Delay due to CCD capacitor shorted to ground for Customer Test Mode 20 (1) 1.5 2 170 s ms Future option, contact TI. 7.6 Typical Characteristics Figure 7-1. Overvoltage Threshold (Nominal = 4.35 V) vs. Temperature Figure 7-2. Hysteresis VHYS vs. Temperature Figure 7-3. IDD Current Consumption vs. Temperature at VDD = 16 V Figure 7-4. ICELL vs. Temperature at VCELL= 9.2 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 7 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 Figure 7-5. Output Current IOUT vs. Temperature 8 Submit Document Feedback Figure 7-6. VOUT vs. VDD Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 8 Detailed Description 8.1 Overview The BQ2947 is a second level overvoltage (OV) protector. Each cell is monitored independently by comparing the actual cell voltage to a protection voltage threshold, VOV. The protection threshold is preprogrammed at the factory with a range between 3.85 V and 4.65 V. 8.2 Functional Block Diagram The Functional Block Diagram shows a CMOS Active High configuration. PACK+ RVD CVD VDD 1 RIN V4 2 RIN V3 3 CIN RIN V2 4 Sensing Circuit CIN VOV Enable OUT Active Delay Charge/ Discharge Circuit CIN RIN V1 8 5 CIN VSS 6 PWPD 9 7 CD CCD PACK– Note In the case of an Open Drain Active Low configuration, an external pull-up resistor is required on the OUT terminal. 8.3 Feature Description In the BQ2947 family of devices, if any cell voltage exceeds the programmed OV value, a timer circuit is activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed current back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes from inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin successfully begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is detected in either direction, it will similarly trigger the OUT pin to become active. See Figure 8-2 for details on CD and OUT pin behavior during an overvoltage event. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 9 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 Cell Voltage (V) (V4–V3, V3 3 –V2, V2 – V1, V1–VSS) For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present) and is high impedance when inactive (no OV). VOV VOV –VHYS tCD OUT (V) Figure 8-1. Timing for Overvoltage Sensing (OUT Pin Is Active High) Figure 8-2 shows the behavior of CD pin during an OV sequence. Fault condition present Fault response becomes active VCD V(CD) tCHGDELAY tCD VOUT1 V(OUT) Note: Active High OUT version shown Figure 8-2. CD Pin Mechanism (OUT Pin Is Active High) Note In the case of an Open Drain Active Low version, the VOUT signal will be high and transition to low state when the voltage on the VCD capacitor discharges to the set level based on the tCD timer. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 8.3.1 Pin Details 8.3.1.1 Input Sense Voltage, Vx These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is required for noise filtering and stable voltage monitoring. 8.3.1.2 Output Drive, OUT This terminal serves as the fault signal output, and may be ordered in either Active High or Open Drain Active Low options. 8.3.1.3 Supply Input, VDD This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current, and a capacitor is connected to ground for noise filtering. 8.3.1.4 External Delay Capacitor, CD This terminal is connected to an external capacitor that sets the delay timer during an overvoltage fault event. The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or open capacitor during an overvoltage event. The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor discharges below a set voltage, the OUT transitions from an inactive to active state. To calculate the delay, use the following equation: tCD (sec) = K × CCD (µF), where K = 10 to 20 range. (1) Example: If CCD= 0.1 µF (typical), then the delay timer range is tCD (s) = 10 × 0.1 = 1 s (Minimum) tCD (s) = 20 × 0.1 = 2 s (Maximum) Note The tolerance on the capacitor used for CCD increases the range of the tCD timer. 8.4 Device Functional Modes 8.4.1 NORMAL Mode When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode. The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3). The OUT pin is inactive, and is low if configured active high, or, if configured active low, is an open drain being externally pulled up. 8.4.2 OVERVOLTAGE Mode OVERVOLTAGE mode is detected if any of the cell voltage exceeds the overvoltage threshold, VOV for configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The OUT pin will either pull high internally, if configured as active high, or will be pulled low internally if configured as active low. An external FET is then turned on, shorting the fuse to ground, which allows the battery and/or charger power to blow the fuse. When all of the cell voltages fall below the (VOV–VHYS), the device returns to NORMAL mode. 8.4.3 Customer Test Mode It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD capacitor to VSS. In this case, the OV delay would be reduced to the t(CD_GND) value, which has a maximum of 170 ms. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 11 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 Figure 8-3 shows the timing for the Customer Test Mode. OV Condition V(VCELL) ≤ 170 ms V(OUT) CD pin held low V(CD) Figure 8-3. Timing for Customer Test Mode Figure 8-4 shows the measurement for current consumption of the product for both VDD and Vx. IDD 1 VDD IIN4 I IN3 OUT 8 2 V4 CD 7 3 V3 VSS 6 4 V2 V1 5 ICELL IIN2 IIN1 ICELL = IDD + IIN1 + I IN2 + IIN3 + I IN4 Figure 8-4. Configuration for IC Current Consumption Test 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The BQ2947 devices are a family of second-level protectors used for overvoltage protection of the battery pack in the application. The device, when configuring the OUT pin with active high, drives a NMOS FET that connects the fuse to ground in the event of a fault condition. This provides a shorted path to use the battery and/or charger power to blow the fuse and cut the power path. The OUT pin, when configured as active low, can be used to drive a PMOS FET to connect the fuse to ground instead. 9.2 Typical Applications 9.2.1 Application Configuration for Active High Figure 9-1 shows the recommended reference design components. Pack+ 100 Ω VCELL4 VCELL3 VCELL2 1k 0.1µF 1k 0.1µF 1k OUT VDD 1k 0.1µF V4 CD V3 VSS V2 V1 PWPD 0.1 µF VCELL1 0.1 µF 0.1µF Pack– Copyright © 2017, Texas Instruments Incorporated Figure 9-1. Application Configuration for Active High 9.2.1.1 Design Requirements Note In the case of an Open Drain Active Low configuration, an external pull-up resistor is required on the OUT terminal. Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements. Table 9-1. Parameters PARAMETER EXTERNAL COMPONENT MIN NOM MAX UNIT Voltage monitor filter resistance RIN 900 1000 4700 Ω Voltage monitor filter capacitance CIN 0.01 0.1 1.0 µF 100 Supply voltage filter resistance RVD 1000 Ω Supply voltage filter capacitance CVD 0.1 1.0 µF CD external delay capacitance CCD 0.1 1.0 µF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 13 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 Note The device is calibrated using an RIN value = 1 kΩ. Using a value other than this recommended value changes the accuracy of the cell voltage measurements and VOV trigger level. 9.2.1.2 Detailed Design Procedure 1. Determine the number of cell in series. The device supports 2-S to 4-S cell configuration. For 2S and 3S, the top unused pin(s) should be shorted as shown in Figure 9-2 and Figure 9-3. 2. Determine the overvoltage protection delay. Follow the calculation example described in CD pin description. Select the right capacitor to connect to the CD pin. 3. Follow the application schematic to connect the device. If the OUT pin is configured to open drain, an external pull up resistor should be used. Pack+ 100 Ω VDD 1k VCELL2 0.1µF 0.1µF 1k OUT V4 CD V3 VSS V2 V1 PWPD VCELL1 0.1µF 0.1µF 0.1µF Pack– Copyright © 2017, Texas Instruments Incorporated Figure 9-2. 2-Series Cell Configuration Pack+ 100 Ω OUT VDD 1k VCELL3 1k VCELL2 1k 0.1µF V4 CD V3 VSS V2 0.1µF V1 PWPD 0.1µF VCELL1 0.1µF 0.1µF Pack– Copyright © 2017, Texas Instruments Incorporated Figure 9-3. 3-Series Cell Configuration 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 9.2.1.3 Application Curves Figure 9-4. Overvoltage Threshold (OVT) vs. Temperature Figure 9-5. Hysteresis VHYS vs. Temperature Figure 9-6. IDD Current Consumption vs. Temperature at VDD = 16 V Figure 9-7. VOUT vs. VDD Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 15 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 10 Power Supply Recommendations The maximum power of this device is 20 V on VDD. 11 Layout 11.1 Layout Guidelines 1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal, reducing the tracing loop area. 2. The capacitor for CD should be placed close to the IC terminals. 3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand the current during fuse blown event. 11.2 Layout Example Place the RC filters close to the device terminals Power Trace Line VDD OUT V4 CD V3 Pack + VSS Pack - PWPD VCELL3 V2 V1 VCELL2 VCELL1 Ensure trace can support sufficient current flow for fuse blow Figure 11-1. Layout Example 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 BQ2947 www.ti.com SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021 12 Device and Documentation Support 12.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see BQ2945xy and BQ2947xy Cascade Voltage Monitoring (SLUA662). 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ2947 17 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ294700DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 700 Samples BQ294700DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 700 Samples BQ294701DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 701 Samples BQ294701DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 701 Samples BQ294702DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 702 Samples BQ294702DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 702 Samples BQ294703DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 703 Samples BQ294703DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 703 Samples BQ294704DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 704 Samples BQ294704DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 704 Samples BQ294705DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 705 Samples BQ294705DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 705 Samples BQ294706DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 706 Samples BQ294706DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 706 Samples BQ294707DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 707 Samples BQ294707DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 707 Samples BQ294708DSGR ACTIVE WSON DSG 8 3000 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 85 708 Samples BQ294708DSGT ACTIVE WSON DSG 8 250 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 85 708 Samples BQ294711DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 711 Samples BQ294711DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 711 Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Jul-2023 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ294712DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 110 712 Samples BQ294712DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 110 712 Samples BQ294713DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 110 713 Samples BQ294713DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 110 713 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of