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bq3060
SLUS928B – MARCH 2009 – REVISED JULY 2016
bq3060 SBS 1.1-Compliant Gas Gauge and Protection With CEDV
1 Features
3 Description
•
The Texas Instruments bq3060 Battery Manager is a
fully integrated, single-chip, pack-based solution that
provides a rich array of features for gas gauging,
protection, and authentication for 2, 3, or 4 series cell
Li-Ion battery packs. With a footprint of merely 7.8
mm × 6.4 mm in a compact 24-pin TSSOP package,
the bq3060 maximizes functionality and safety while
dramatically cutting the solution cost and size for
smart batteries.
1
•
•
•
•
•
•
•
•
•
•
Advanced CEDV (Compensated End-of-Discharge
Voltage) Gauging
Fully Integrated 2, 3, and 4 Series Li-Ion or LiPolymer Cell Battery Pack Manager
8-Bit RISC CPU With Ultra-Low Power Modes
Full Array of Programmable Protection Features
– Voltage, Current, and Temperature
SHA-1 Authentication
Flexible Memory Architecture With Integrated
Flash Memory
Supports Two-Wire SMBus v1.1 Interface With
High-speed 400kHz Programming Option
P-CH High Side Protection FET Drive
Low Power Consumption Sleep Mode: < 69 μA
High-Accuracy Analog Front End With Two
Independent ADCs
– High-Resolution, 15~22-bit Integrator for
Coulomb Counting
– 16-Bit Delta-Sigma ADC With a 16-Channel
Multiplexer for Voltage, Current, and
Temperature
Ultra Compact Package: 24-Pin TSSOP PW
Using its integrated high-performance analog
peripherals, the bq3060 measures and maintains an
accurate record of available capacity, voltage,
current, temperature, and other critical parameters in
Li-Ion or Li-Polymer batteries, and reports the
information to the system host controller over an
SMBus 1.1-compatible interface.
The bq3060 provides software-first level and second
level safety protection on overvoltage, undervoltage,
overtemperature, and overcharge, as well as
hardware-overcurrent in discharge, short circuit in
charge, and discharge protection.
Device Information(1)
PART NUMBER
bq3060
BODY SIZE (NOM)
4.4 mm × 7.8 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
PACKAGE
TSSOP (24)
Netbook and Notebook PCs
Medical and Test Equipment
Portable Instruments
System Partitioning Diagram
Pack +
FUSE
SMBD
Fuse Blow &
Detection
Logic
SMBD
SMBC SMBC
ZVCHG
CHG
DSG
PACK BAT
RBI
Oscillator
Pre Charge
FET Drive
P-Channel
FET Drive
Power Mode
Control
VSS
SMB 1.1
System
Control
PRES PRES
AFE HW
Control
Data Flash
Memory
Charging
Algorithm
SHA-1
Authentication
Over
Temperature
Protection
Temperature
Measurement
TS1
TS2
Watchdog
Voltage
Measurement
Cell Voltage Mux
& Translation
Over- &
UnderVoltage
Protection
CEDV
Gas Gauging
External Cell
Balancing Driver
Over
Current
Protection
Coloumb
Counter
VC1
VC1
VDD
VC2
VC2
OUT
VC3
VC3
VC4
VC4
CD
GND
bq294xz
SRN
HW Over
Current &
Short Circuit
Protection
SRP
Regulator
REG27
bq3060
Pack RSNS
5mW –20mW typ.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq3060
SLUS928B – MARCH 2009 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
7
Detailed Description ............................................ 11
7.1 Feature Description................................................. 11
7.2 Device Functional Modes........................................ 13
8
Device and Documentation Support.................. 14
8.1
8.2
8.3
8.4
8.5
8.6
9
Documentation Support ......................................... 14
Receiving Notification of Documentation Updates.. 14
Community Resources............................................ 14
Trademarks ............................................................. 14
Electrostatic Discharge Caution .............................. 14
Glossary .................................................................. 14
Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2009) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Changed Device From: Production To: NRND....................................................................................................................... 1
Changes from Original (March 2009) to Revision A
•
2
Page
Changed Device From: Product Preview To: Production....................................................................................................... 1
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bq3060
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SLUS928B – MARCH 2009 – REVISED JULY 2016
5 Pin Configuration and Functions
PW Package
24-Pin TSSOP
Top View
BAT
DSG
VC1
VC2
VC3
VC4
SRP
SRN
TS1
TS2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PACK
CHG
ZVCHG
FUSE
REG27
VSS
RBI
PRES
SMBC
NC
SMBD
NC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BAT
1
P
Power input from battery
DSG
2
O
P-CH FET Drive controlling discharge
VC1
3
IA
Sense voltage input terminal and external cell balancing drive output for most positive cell, and
battery stack measurement input.
VC2
4
IA
Sense voltage input terminal and external cell balancing drive output for second most positive
cell.
VC3
5
IA
Sense voltage input terminal and external cell balancing drive output for third most positive cell.
VC4
6
IA
Sense voltage input terminal and external cell balancing drive output for least positive cell.
SRP
7
IA
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRP is the top of the sense resistor.
SRN
8
IA
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRN is the bottom of the sense resistor.
TS1
9
I/O,IA
Thermistor input TS1
TS2
10
I/O,IA
Thermistor input TS2
NC
11
—
Keep this pin floating
NC
12
—
Keep this pin floating
NC
13
—
Keep this pin floating
SMBD
14
I/OD
NC
15
—
SMBC
16
I/OD
SMBus clock pin
PRES
17
I/OD
Active low input to sense system insertion and typically requires additional ESD protection
RBI
18
P
RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily
lost by using a capacitor attached between RBI and VSS
VSS
19
P
Device ground
REG27
20
P
Internal power supply 2.7V bias output
FUSE
21
I/OD
ZVCHG
22
O
P-CH precharge FET Drive controlling pre-charge and zero-volt charge
CHG
23
O
P-CH FET Drive controlling charge
PACK
24
P
PACK positive terminal and alternative power source
SMBus data pin
Keep this pin floating
Push-pull fuse drive and secondary protector activation input sensing
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SLUS928B – MARCH 2009 – REVISED JULY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
VMAX
Supply voltage
range
MIN
MAX
UNIT
–0.3
34
V
VVC2–0.3
VVC2+8.5 or 34,
whichever is lower
V
VC2
VVC3–0.3
VVC3+8.5
V
VC3
VVC4–0.3
VVC4+8.5
V
VC4
VSRP–0.3
VSRP+8.5
V
SRP, SRN
–0.3
VREG27
V
SMBD, SMBC
–0.3
6
V
TS1, TS2, /PRES
–0.3
VREG27 + 0.3
V
CHG, DSG, ZVCHG, FUSE
–0.3
BAT
V
RBI, REG27
–0.3
2.75
V
50
mA
PACK w.r.t. Vss
VC1, BAT
Input voltage
range
VIN
VO
Output voltage
range
ISS
Maximum combined sink current for input pins
TFUNC
Functional temperature
–40
110
°C
TSTG
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
BAT
VSTARTUP
Start up voltage at PACK
Vshutdown
VPACK or VBAT, whichever is higher
VIN
Input voltage range
25
3.8
3
Operating temperature
4
V
5.5
V
3.2
3.3
V
VC2
VVC3
VVC3+5
VC3
VVC4
VVC4+5
VC4
VSRP
VSRP+5
0
5
V
25
–0.3
1
1
–40
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UNIT
5.2
VVC2+5
SRP to SRN
TOPR
VVC2+5
VVC2
PACK
External 2.7V REG capacitor
MAX
VC1, BAT
VCn – VC(n+1), (n=1, 2, 3, 4 )
CREG27
TYP
PACK
V
μF
85
°C
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: bq3060
bq3060
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SLUS928B – MARCH 2009 – REVISED JULY 2016
6.4 Thermal Information
bq3060
THERMAL METRIC (1)
PW (TSSOP)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
83.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.5
°C/W
RθJB
Junction-to-board thermal resistance
39.4
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
38.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to
85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
GENERAL PURPOSE I/O
VIH
High-level input voltage
/PRES, SMBD, SMBC, TS1, TS2
VIL
Low-level input voltage
/PRES, SMBD, SMBC, TS1, TS2
VOH
Output voltage high
/PRES, SMBD, SMBC, TS1, TS2, IL = –0.5
mA
VOH(FUSE)
High level fuse output
tR(FUSE)
FUSE output rise time
ZO(FUSE)
FUSE output impedance
VFUSE_DET
FUSE detect input voltage
VOL
Low-level output voltage
CIN
Input capacitance
VBAT = 3.8 V to 9 V, CL = 1 nF
VBAT = 9 V to 25 V, CL = 1nF
2
V
0.8
VREG27–0.5
V
3
VBAT–0.3
8.6
7.5
8
9
CL = 1 nF,
VOH(FUSE) = 0 V to 5 V
0.8
μs
2
6
kΩ
2
3.2
V
0.4
V
5
Ilkg
Input leakage current
RPD(SMBx)
SMBD and SMBC pull-down
TA = –40°C to 100°C
RPAD
Pad resistance
TS1, TS2
600
V
10
/PRES, SMBD, SMBC, TS1, TS2, IL = 7 mA
/PRES, SMBD, SMBC, TS1, TS2
SMBD and SMBC pull-down disabled
V
pF
1
μA
950
1300
kΩ
87
110
Ω
SUPPLY CURRENT
ICC
ISLEEP
ISHUTDOWN
Normal mode
Sleep mode
Shutdown mode
Firmware running, no flash writes
441
μA
Discharge FET ON, Charge FET ON
([NR]=1, [NRCHG]=1)
69
Discharge FET ON, Charge FET OFF
([NR]=1, [NRCHG]=0)
66
Discharge FET OFF, Charge FET OFF
([NR]=0, System not present)
61
TA = –40°C to 110°C
0.5
1
μA
μA
REG27 POWER ON RESET
VREG27IT–
Negative-going voltage input
At REG27
2.22
2.35
2.34
V
VREG27IT+
Positive-going voltage input
At REG27
2.25
2.5
2.6
V
2.5
2.7
2.75
V
INTERNAL LDO
VREG
Regulator output voltage
IREG27 = 10 mA; TA = –40°C to 85°C
ΔV(REGTEMP)
Regulator output change
with temperature
IREG = 10 mA; TA = –40°C to 85°C
ΔV(REGLINE)
Line regulation
IREG = 10 mA
ΔV(REGLOAD)
Load regulation
IREG = 0.2 to 10 mA
±0.5%
±2
±4
mV
±20
±40
mV
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to
85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER
I(REGMAX)
TEST CONDITION
Current limit
MIN
TYP
25
MAX
50
UNIT
mA
SRx WAKE FROM SLEEP
VWAKE = 1.2 mV
0.2
1.2
2
VWAKE = 2.4 mV
0.4
2.4
3.6
2
5
6.8
5.3
10
13
VWAKE_ACR
Accuracy of VWAKE
VWAKE_TCO
Temperature drift of VWAKE
accuracy
0.5
tWAKE
Time from application of
current and wake of bq3060
0.2
VWAKE = 5 mV
VWAKE = 10 mV
mV
%/°C
1
ms
COULOMB COUNTER
Input voltage range
–0.20
Conversion time
Single conversion
Effective resolution
Single conversion
Integral nonlinearity
TA = –25°C to 85°C
Offset error
(1)
Bits
±0.007
TA = –25°C to 85°C
±0.034
%FSR
0.3
0.5
μV/°C
0.2%
0.8%
10
–0.8%
Full-scale error drift
μV
150
Effective input resistance
V
ms
15
Offset error drift
Full-scale error (2)
0.25
250
2.5
PPM/°C
MΩ
ADC
Input voltage range
0.8×VRE
–0.2
V
G27
Conversion time
31.5
Resolution (no missing
codes)
16
Effective resolution
14
Bits
15
Integral nonlinearity
Offset error
Bits
±0.020
(3)
70
Offset error drift
Full-scale error
ms
160
1
VIN = 1 V
–0.8%
±0.2%
Full –scale error drift
M μV
μV/°C
0.4%
150
Effective input resistance
%FSR
8
PPM/°C
MΩ
EXTERNAL CELL BALANCE DRIVE
Cell balance ON for VC1, VCi-VCi+1 = 4 V,
where i = 1~4
RBAL_drive
Cell balance ON for VC2, VCi-VCi+1 = 4 V,
Internal pull-down resistance where = i = 1~4
for external cell balance
Cell balance ON for VC3, VCi-VCi+1 = 4 V,
where = i = 1~4
5.7
3.7
kΩ
1.75
Cell balance ON for VC4, VCi-VCi+1 = 4 V,
where = i = 1~4
0.85
TA = –10°C to 60°C
±10
±20
TA = –40°C to 85°C
±10
±35
CELL VOLTAGE MONITOR
CELL Voltage Measurement
Accuracy (4)
(1)
(2)
(3)
(4)
6
mV
Post Calibration Performance
Uncalibrated performance. This gain error can be eliminated with external calibration.
Channel to channel offset
This is the performance expected for non-calibrated device.
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SLUS928B – MARCH 2009 – REVISED JULY 2016
Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to
85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
INTERNAL TEMPERATURE SENSOR
T(TEMP)
Temperature sensor
accuracy
±3%
°C
THERMISTOR MEASUREMENT
SUPPORT
RERR
Internal resistor drift
R
Internal resistor
–230
TS1, TS2
17
ppm/°C
20
kΩ
175
°C
INTERNAL THERMAL SHUTDOWN (5)
TMAX
Maximum REG27
temperature
TRECOVER
Recovery hysteresis
temperature
125
10
°C
HIGH FREQUENCY OSCILLATOR
f(OSC)
Operating frequency of CPU
clock
f(EIO)
Frequency error (6)
t(SXO)
Start-up time (7)
2.097
MHz
TA = –20°C to 70°C
–2%
±0.25%
2%
TA = –40°C to 85°C
–3%
±0.25%
3%
3
6
TA = –25°C to 85°C
ms
LOW FREQUENCY OSCILLATOR
f(LOSC)
f(LEIO)
t(LSXO)
Operating frequency
Frequency error (6)
Start-up time
(8)
32.768
MHz
TA = –20°C to 70°C
–1.5%
±0.25%
1.5%
TA = –40°C to 85°C
–2.5%
±0.25%
2.5%
TA = –25°C to 85°C
100
ms
FLASH (9)
Data retention
Flash programming writecycles
t(ROWPROG)
Row programming time
t(MASSERASE)
Mass-erase time
t(PAGEERASE)
Page-erase time
ICC(PROG)
Flash-write supply current
ICC(ERASE)
Flash-erase supply current
10
Years
20k
Cycles
2
ms
250
ms
25
ms
4
6
mA
TA = –40°C to 0°C
8
22
TA = 0°C to 85°C
3
15
20
1500
mA
RAM BACKUP
I(RBI)
V(RBI)
RBI data-retention input
current
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA =
70°C to 110°C
nA
VRBI > V(RBI)MIN, VREG27 < VREG27IT-, TA =
–40°C to 70°C
RBI data-retention voltage (9)
500
1
V
CURRENT PROTECTION THRESHOLDS
V(OCD)
(5)
(6)
(7)
(8)
(9)
OCD detection threshold
voltage range, typical
RSNS = 0; RSNS is set in STATE_CTL
register
50
200
RSNS = 1; RSNS is set in STATE_CTL
register
25
100
mV
Parameters assured by design. Not production tested.
The frequency drift is included and measured from the trimmed frequency at VBAT = VPACK = 14.4 V, TA = 25°C
The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
Specified by design. Not production tested
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to
85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER
ΔV(OCDT)
OCD detection threshold
voltage program step
SCC detection threshold
voltage range, typical
V(SCCT)
ΔV(SCCT)
SCC detection threshold
voltage program step
SCD detection threshold
voltage range, typical
V(SCDT)
ΔV(SCDT)
SCD detection threshold
voltage program step
TEST CONDITION
MIN
TYP
RSNS = 0; RSNS is set in STATE_CTL
register
10
RSNS = 1; RSNS is set in STATE_CTL
register
5
MAX
UNIT
mV
RSNS = 0; RSNS is set in STATE_CTL
register
–100
–300
RSNS = 1; RSNS is set in STATE_CTL
register
–50
–225
mV
RSNS = 0; RSNS is set in STATE_CTL
register
–50
RSNS = 1; RSNS is set in STATE_CTL
register
–25
mV
RSNS = 0; RSNS is set in STATE_CTL
register
100
450
RSNS = 1; RSNS is set in STATE_CTL
register
50
225
mV
RSNS = 0; RSNS is set in STATE_CTL
register
50
RSNS = 1; RSNS is set in STATE_CTL
register
25
mV
V(OFFSET)
SCD, SCC and OCD offset
–10
10
V(Scale_Err)
SCD, SCC and OCD scale
error
–10%
10%
1
31
mV
CURRENT PROTECTION TIMING
t(OCDD)
Overcurrent in discharge
delay
t(OCDD_STEP)
OCDD step options
t(SCDD)
Short circuit in discharge
delay
t(SCDD_STEP)
SCDD step options
t(SCCD)
Short circuit in charge delay
t(SCCD_STEP)
SCCD step options
t(DETECT)
Current fault detect time
tACC
Overcurrent and short circuit
delay time accuracy
2
ms
AFE.STATE_CNTL[SCDDx2] = 0
0
915
AFE.STATE_CNTL[SCDDx2] = 1
0
1830
AFE.STATE_CNTL[SCDDx2] = 0
61
AFE.STATE_CNTL[SCDDx2] = 1
122
0
915
35
µs
µs
61
VSRP-SRN = VTHRESH + 12.5 mV,
TA = –40°C to 85°C
ms
µs
µs
160
Accuracy of typical delay time with WDI
active
–20%
20%
Accuracy of typical delay time with no WDI
input
–50%
50%
VO(FETONDSG) = V(BAT)–V(DSG), RGS = 1MΩ,
TA = –40°C to 110°C, BAT = 20 V (10)
12
15
18
VO(FETONCHG) = V(PACK)–V(CHG), RGS =1MΩ,
TA = –40°C to 110°C, PACK = 20 V (10)
12
15
18
µs
P-CH FET DRIVE
VO(FETON)
VO(FETOFF)
tr
Output voltage, charge and
discharge FETs on
Output voltage, charge and
discharge FETs off
Rise time
V
VO(FETOFFDSG) = V(BAT)–V(DSG),
TA = –40°C to 110°C, BAT = 16 V
0.2
VO(FETOFFCHG) = V(PACK)–V(CHG),
TA = –40°C to 110°C, PACK = 16 V
0.2
V
CL = 4700 pF; VDSG: 10% to 90%
70
200
CL = 4700 pF; VCHG: 10% to 90%
70
200
µs
(10) For a VBAT or VPACK input range of 3.8 V to 25 V, MIN VO(FETON) voltage is 12 V or V(BAT)–1 V, whichever is less.
8
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to
85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER
tf
Fall time
TYP
MAX
CL = 4700 pF; VDSG: 10% to 90%
TEST CONDITION
MIN
70
200
UNIT
CL = 4700 pF; VCHG: 10% to 90%
70
200
15
18
V
VBAT–0.
5
V
200
µs
µs
PRE-CHARGE/ZVCHG FET DRIVE
V(PreCHGON)
VO(PreCHGON) =
V(PACK)–V(ZVCHG), pre-charge RGS =1 MΩ, TA = –40°C to 110°C
FET on (11)
V(PreCHGOFF)
Output voltage, pre-charge
FET off (11)
RGS =1 MΩ, TA = –40°C to 110°C
tr
Rise time
CL = 4700 pF, RG = 5.1 kΩ, VZVCHG: 10% to
90%
80
tf
Fall time
CL = 4700 pF, RG = 5.1 kΩ, VZVCHG : 90%
to 10%
1.7
fSMB
SMBus operating frequency
Slave mode, SMBC 50% duty cycle
fMAS
SMBus master clock
frequency
Master mode, no clock low slave extend
tBUF
Bus free time between start
and stop
tHD:STA
12
ms
SMBus
10
100
51.2
kHz
kHz
4.7
µs
Hold time after (repeated)
start
4
µs
tSU:STA
Repeated start setup time
4.7
µs
tSU:STO
Stop setup time
4
µs
tHD:DAT
Data hold time
tSU:DAT
Data setup time
tTIMEOUT
Error signal/detect
tLOW
Clock low period
tHIGH
Receive mode
0
Transmit mode
300
ns
250
See
(12)
Clock high period
See
(13)
tLOW:SEXT
Cumulative clock low slave
extend time
See
tLOW:MEXT
tF
25
ns
35
4.7
µs
50
µs
(14)
10
ms
Cumulative clock low master
See
extend time
(15)
300
ns
Clock/data fall time
See
(16)
300
ns
Clock/data rise time
See
(17)
1000
ns
fSMBXL
SMBus XL operating
frequency
Slave mode
400
kHz
tBUF
Bus free time between start
and stop
tHD:STA
tR
4
ms
SMBus XL
40
4.7
µs
Hold time after (repeated)
start
4
µs
tSU:STA
Repeated start setup time
4.7
µs
tSU:STO
Stop setup time
4
µs
(11) For a VBAT or VPACK input range of 3.8 V to 25 V, MIN V(PreCHGON) voltage is 12 V or V(BAT)–1V, whichever is less.
(12) The bq3060 times out when any clock low exceeds tTIMEOUT
(13) tHIGH, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 μs causes reset of any transaction involving bq3060 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). If NC_SMB is set then
the timeout is disabled.
(14) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(15) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(16) Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
(17) Fall time tF = 0.9VDD to (VILMAX – 0.15)
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VBAT = VPACK = 14.4 V, Minimum/Maximum values stated where TA = –40°C to
85°C and VBAT = VPACK = 3.8 V to 25 V (unless otherwise noted)
PARAMETER
TEST CONDITION
tTIMEOUT
Error signal/detect
tLOW
Clock low period
tHIGH
Clock high period
See
(12)
See
(13)
MIN
TYP
MAX
UNIT
25
35
ms
1
1
µs
1
2
µs
Timing Measurement Intervals
t LOW
tR
tF
t HD:STA
SCLK
t SU:STA
t HIGH
t HD:STA
t HD:DAT
t SU:STO
t SU:DAT
SDATA
t BUF
P
S
S
P
t TIMEOUT Measurement Intervals
Start
Stop
t LOW:SEXT
SCLK ACK1
t LOW:MEXT
SCLK ACK1
t LOW:MEXT
t LOW:MEXT
SCLK
SDATA
(1)
10
SCLKACK is the acknowledge-related clock pulse generated by the master.
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7 Detailed Description
7.1 Feature Description
7.1.1 Battery Parameter Measurements
The bq3060 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage, and temperature measurement.
7.1.1.1 Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from -0.20 V to 0.25 V. The bq3060 detects charge activity when VSR = V(SRP)- V(SRN)is positive, and
discharge activity when VSR = V(SRP) - V(SRN) is negative. The bq3060 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
7.1.1.2 Voltage
The bq3060 updates the individual series cell voltages at one second intervals. The internal ADC of the bq3060
measures the voltage, scales, and offsets, and calibrates it appropriately. To ensure an accurate differential
voltage sensing, the IC ground should be connected directly to the most negative terminal of the battery stack,
not to the positive side of the sense resistor. This minimizes the voltage drop across the PCB trace.
7.1.1.3 Voltage Calibration and Accuracy
The bq3060 is calibrated for voltage prior to shipping from TI. The bq3060 voltage measurement signal chain
(ADC, high voltage translation, circuit interconnect) will be calibrated for each cell. The external filter resistors,
connected from each cell to the VCx input of the bq3060, are required to be 1kΩ. The accuracy of the factorycalibrated devices is +/- 10mV per cell at room temperature at 4V cell voltage. Without any customer voltage
calibration, this is the level of accuracy expected as long as the filter resistor value is 1kΩ. If better voltage
accuracy is desired, customer voltage calibration is required. An application note on calibrating and programming
the bq3060 is available in the product web folder. See Data Flash Programming and Calibrating the bq3060 Gas
Gauge (SLUA502) for more details.
7.1.1.4 Current
The bq3060 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5 mΩ to 20 mΩ typ. sense resistor.
7.1.1.5 Auto Calibration
The bq3060 can automatically calibrate its offset between the A to D converter and the output of the high voltage
translation circuit. Also, the bq3060 provides an auto-calibration for the coulomb counter to cancel the voltage
offset error across SRN and SRP for maximum charge measurement accuracy. The bq3060 performs autocalibration when the SMBus lines stay low continuously for a minimum of 5 s.
7.1.1.6 Temperature
The bq3060 has an internal temperature sensor and inputs for 2 external temperature sensor inputs TS1 and
TS2 used in conjunction with two identical NTC thermistors (default is Semitec 103AT) to sense the battery cell
temperature. The bq3060 can be configured to use internal or up to 2 external temperature sensors.
7.1.2 Primary (1st Level) Safety Features
The bq3060 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
• Cell over/undervoltage protection
• Charge and discharge overcurrent
• Short circuit
• Charge and discharge overtemperature
• AFE Watchdog
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Feature Description (continued)
7.1.3 Secondary (2nd Level) Safety Features
The secondary safety features of the bq3060 can be used to indicate more serious faults via the FUSE (pin 21).
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging and
discharging. This pin is also used as an input to sense the state of the fuse. The secondary safety protection
features include:
• Safety overvoltage
• Safety overcurrent in charge and discharge
• Safety overtemperature in charge and discharge
• Charge FET and Zero-Volt Charge FET fault
• Discharge FET fault
• Cell imbalance detection
• Fuse blow by a secondary voltage protection IC
• AFE register integrity fault (AFE_P)
• AFE communication fault (AFE_C)
7.1.4 Charge Control Features
The bq3060 charge control features include:
• Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range.
• Handles more complex charging profiles. Allows for splitting the standard temperature range into 2 subranges and allows for varying the charging current according to the cell voltage.
• Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
• Reduce the charge difference of the battery cells in fully charged state of the battery pack gradually using a
voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to
be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination
• Supports pre-charging/zero-volt charging
• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
• Reports charging fault and also indicate charge status via charge and discharge alarms.
7.1.5 Gas Gauging
The bq3060 uses advanced CEDV (Compensated End-of-Discharge Voltage) technology to measure and
calculate the available capacity in battery cells. The bq3060 accumulates a measure of charge and discharge
currents and compensates the charge current measurement for temperature and state-of-charge of the battery.
The bq3060 estimates self-discharge of the battery and also adjusts the self-discharge estimation based on
temperature.
See bq3060 Technical Reference (SLUU319) for further details.
7.1.6 Lifetime Data Logging Features
The bq3060 offers limited lifetime data logging for the following critical battery parameters for analysis purposes:
• Lifetime maximum temperature
• Lifetime minimum temperature
• Lifetime maximum battery cell voltage
• Lifetime minimum battery cell voltage
7.1.7 Authentication
The bq3060 supports authentication by the host using SHA-1.
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Feature Description (continued)
7.1.8 Configuration
7.1.8.1 System Present Operation
The bq3060 checks the PRES pin periodically (1 second). If PRES input is pulled to ground by external system,
the bq3060 detects the presence of the system.
7.1.8.2 2-, 3-, or 4-Cell Configuration
In a 2-cell configuration, VC1 is shorted to VC2 and VC3. In a 3-cell configuration, VC1 is shorted to VC2.
7.1.8.3 Cell Balance Control
If cell balancing is required, the bq3060 cell balance control allows a weak, internal pull-down for each VCx pin.
The purpose of this weak pull-down is to enable an external FET for current bypass. Series resistors placed
between the input VCx pins and the positive battery cell terminals control the VGS of the external FET. See
bq3060 Cell balancing using external MOSFET (SLUA509) or bq3060 Gas Gauge Circuit Design (SLUA507) for
more details.
7.1.9 Communications
The bq3060 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBS
specification.
7.1.9.1 SMBus On and Off State
The bq3060 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.
7.1.10 SBS Commands
See bq3060 Technical Reference (SLUU319) for further details.
7.2 Device Functional Modes
7.2.1 Power Modes
The bq3060 supports 3 different power modes to reduce power consumption:
• In Normal Mode, the bq3060 performs measurements, calculations, protection decisions and data updates in
1 second intervals. Between these intervals, the bq3060 is in a reduced power stage.
• In Sleep Mode, the bq3060 performs measurements, calculations, protection decisions and data update in
adjustable time intervals. Between these intervals, the bq3060 is in a reduced power stage. The bq3060 has
a wake function that enables exit from Sleep mode, when current flow or failure is detected.
• In Shutdown Mode the bq3060 is completely disabled.
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
• bq3060 Technical Reference (SLUU319)
• bq3060 Cell balancing using external MOSFET (SLUA509)
• bq3060 Gas Gauge Circuit Design (SLUA507)
• Data Flash Programming and Calibrating the bq3060 Gas Gauge (SLUA502)
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ3060PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3060
BQ3060PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3060
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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