BQ3285LFSS-A1

bq3285LF Y2K-Enhanced Real-Time Clock (RTC) Features General Description ➤ ACPI-compliant day-of-month alarm The CMOS bq3285LF is a low-power microprocessor peripheral providing a time-of-day clock and 100-year calendar with alarm features and battery operation. The architecture is based on the bq3285 RTC with added features: century bit, low-voltage operation, 32.768kHz output, 126 additional bytes of CMOS, two shadow registers of last address used, and a day-of-month alarm to be compliant with the ACPI RTC specification. ➤ Y2K century bit ➤ Direct clock/calendar replacement for IBM® AT-compatible computers and other applications ➤ 2 index shadow registers ➤ 2.7–5.5V operation ➤ 240 bytes of general nonvolatile storage ➤ Dedicated 32.768kHz output pin ➤ System wake-up capability— alarm interrupt output active in battery-backup mode ➤ Less than 0.55µA load under battery operation ➤ Selectable Intel or Motorola bus timing A 32.768kHz output is available for sustaining power-management activities. The bq3285LF 32kHz output is always on whenever VCC is valid. In V CC standby mode, the 32kHz is active, and the bq3285LF typically draws 100µA. Wake-up capability is provided by an alarm interrupt, which is active in batterybackup mode. In battery-backup mode, current drain is less than 550nA. The bq3285LF write-protects the clock, calendar, and storage registers during power failure. A backup battery then maintains data and operates the clock and calendar. The bq3285LF is a fully compatible real-time clock for IBM ATcompatible computers and other applications. The only external components are a 32.768kHz crystal and a backup battery. The bq3285LF is intended for use in 3V systems; however, it may also operate at 5V and then go into a 3V power-down state, write-protecting as if in a 3V system. ➤ 24-pin plastic SSOP Pin Connections Pin Names AD0–AD7 Multiplexed address/ data input/output MOT Bus type select input CS Chip select input AS Address strobe input DS Data strobe input R/W Read/write input INT Interrupt request output RST Reset input 32K 32.768kHz output EXTRAM Extended RAM enable MOT X1 X2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC 32k EXTRAM RCL BC INT RST DS VSS R/W AS CS RCL RAM clear input BC 3V backup cell input X1–X2 Crystal inputs VCC Supply voltage input VSS Ground 24-Pin SSOP PN3285ED/LD.eps 6/99 B 1 bq3285LF Block Diagram X1 TimeBase Oscillator X2 4 3 RST ÷8 ÷ 64 ÷ 64 16 : 1 MUX MOT 32K 32K Driver Control/Status Registers CS µP Bus I/F R/W AS AD0–AD7 DS MUX EXTRAM INT Interupt Generator Clock/Calendar, Alarm and Control Bytes User Buffer (14 Bytes) Control/Calendar Update Storage Registers (114 Bytes) RCL Storage Registers (126 Bytes) CS VCC BC PowerFail Control Index Registers (2 Bytes) VOUT Write Protect BD3285ID.eps AD0–AD7 Pin Descriptions MOT Bus type select input The bq3285LF bus cycle consists of two p h a s e s : th e a d d re s s p h a s e a n d the data-transfer phase. The address phase precedes the data-transfer phase. During the address phase, an address placed on AD0–AD7 is latched into the bq3285LF on the falling edge of the AS signal. During the data-transfer phase of the bus cycle, the AD0–AD7 pins serve as a bidirectional data bus. MOT selects bus timing for either Motorola or Intel architecture. This pin should be tied to VCC for Motorola timing or to VSS for Intel timing (see Table 1). The setting should not be changed during system operation. MOT is internally pulled low by a 30K Ω resistor. Table 1. Bus Setup AS Bus Type MOT DS R/W AS Level Equivalent Equivalent Equivalent Motorola VCC DS, E, or Φ2 R/W Intel VSS RD, MEMR, or I/OR WR, MEMW, or ALE I/OW Multiplexed address/data input/output Address strobe input AS serves to demultiplex the address/data bus. The falling edge of AS latches the address on AD0–AD7. This demultiplexing process is independent of the CS signal. For DIP and SOIC packages with MOT = VSS, the AS input is provided a signal similar to ALE in an Intel-based system. AS 2 bq3285LF A low input on EXTRAM during the falling e dg e o f AS lat che s t he add re s s i n to standard bank address latch. A high input on the EXTRAM input during the falling edge of AS latches the address into the extended bank address latch. The contents of the address latches are copied into the standard bank index and the extended bank index registers respectively. EXTRAM is not latched. DS INT INT is an open-drain output. This allows alarm INT to be valid in battery-backup mode. To use this feature, connect INT through a resistor to a power supply other than VCC. INT is asserted low when any event flag is set and the corresponding event enable bit is also set. INT becomes high-impedance whenever register C is read (see the Control/Status Registers section). Data strobe input 32K When MOT = VCC, DS controls data transfer during a bq3285LF bus cycle. During a read cycle, the bq3285LF drives the bus after the rising edge on DS. During a write cycle, the falling edge on DS is used to latch write data into the chip. EXTRAM Extended RAM enable Enables 128 bytes of additional nonvolatile SRAM. It is connected internally to a 30kΩ pull-down resistor. To access the RTC registers, EXTRAM must be low. The input on this pin also selects the latch to be used in the data transfer. A low value selects the standard bank latch. A high value selects the extended the bank latch. EXTRAM should be valid for complete address, read or write cycle. The state of the EXTRAM input selects the address latch used during data access. A low input on EXTRAM selects the standard bank latch and the location in the standard bank pointed to by the value in this latch. A high input on the EXTRAM selects the extended bank latch and the location in the extended bank pointed to by the value in this latch. RCL RAM clear input A low level on the RCL pin causes the contents of each of the 240 storage bytes to be set to FF(hex). RCL clears the shadow index registers to 00(hex). The contents of the clock and control registers are unaffected. This pin should be used as a user-interface input (pushbutton to ground) and not connected to the output of any active component. RCL input is only recognized when held low for at least 125ms in the presence of VCC. Using RAM clear does not affect the battery load. This pin is connected internally to a 30kΩ pull-up resistor. Read/write input When MOT = VCC, the level on R/W identifies the direction of data transfer. A high level on R/W indicates a read bus cycle, whereas a low on this pin indicates a write bus cycle. When MOT = VSS, R/W is provided a signal similar to WR, MEMW, or I/OW in an Intelbased system. The rising edge on R/W latches data into the bq3285LF. CS 32.768 kHz output 32K provides a buffered 32.768 kHz output. The frequency remains on and fixed at 32.768kHz as long as VCC is valid. When MOT = VSS, the DS input is provided a signal similar to RD, MEMR, or I/OR in an Intel-based system. The falling edge on DS is used to enable the outputs during a read cycle. R/W Interrupt request output BC Chip select input 3V backup cell input BC should be connected to a 3V backup cell for RTC operation and storage register nonvolatility in the absence of system power. When VCC slews down past VBC (3V typical), the integral control circuitry switches the power source to BC. When VCC returns above VBC, the power source is switched to VCC. CS should be driven low and held stable during the data-transfer phase of a bus cycle accessing the bq3285LF. On power-up, a voltage within the V BC range must be present on the BC pin for the oscillator to start up. 3 bq3285LF RST Reset input Functional Description The bq3285LF is reset when RST is pulled low. When reset, INT becomes high impedance, and the bq3285LF is not accessible. Table 4 in the Control/Status Registers section lists the register bits that are cleared by a reset. Address Map The bq3285LF provides 14 bytes of clock and control/status registers and 242 bytes of general nonvolatile storage. Figure 1 illustrates the address map for the bq3285LF. Reset may be disabled by connecting RST to VCC. This allows the control bits to retain their states through power-down/power-up cycles. X1–X2 Update Period Crystal inputs The update period for the bq3285LF is one second. The bq3285LF updates the contents of the clock and calendar locations during the update cycle at the end of each update period (see Figure 2). The alarm flag bit may also be set during the update cycle. The X1–X2 inputs are provided for an external 32.768kHz quartz crystal, Daiwa DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation. The bq3285LF copies the local register updates into the user buffer accessed by the host processor. When a 1 is written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes re- In the absence of a crystal, a 32.768kHz waveform can be fed into the X1 input. 0 14 Bytes 13 Clock and Control Status Registers 14 00 0 1 0D 0E Storage Registers with EXTRAM = 0 114 Bytes 2 Minutes 02 3 Minutes Alarm 03 4 Hours 04 5 Hours Alarm 05 127 7F 6 Day of Week 06 0 00 7 Date of Month 07 8 Month 08 9 Year 09 10 Register A 0A 11 Register B Register C Day of Month Alarm 0B Storage Registers with EXTRAM = 1 126 Bytes 12 125 2 Bytes 00 Seconds Seconds Alarm 01 126 127 13 7D Index Registers 7E BCD or Binary Format 0C 0D Standard Index Register 7F Extended Index Register plus Century bit FG3285ID.eps Figure 1. Address Map Update Period (1 sec.) UIP tUC (Update Cycle) tBUC TD3285e1.eps Figure 2. Update Period Timing and UIP 4 bq3285LF mains unchanged, while the local copy of the same bytes continues to be updated every second. a. Write a 1 to the UTI bit to prevent transfers between RTC bytes and user buffer. The update-in-progress bit (UIP) in register A is set tBUC time before the beginning of an update cycle (see Figure 2). This bit is cleared and the update-complete flag (UF) is set at the end of the update cycle. b. Write the appropriate value to the data format (DF) bit to select BCD or binary format for all time, alarm, and calendar bytes. c. Write the appropriate value to the hour format (HF) bit. Programming the RTC The time-of-day, alarm, and calendar bytes can be written in either the BCD or binary format (see Table 2). 2. Write new values to all the time, alarm, and calendar locations. 3. The CENT bit in location 7Fh (bit 7) of the extended SRAM bank is read only. Writing year in location 09h automatically updates CENT. 4. Clear the UTI bit to allow update transfers. These steps may be followed to program the time, alarm, and calendar: 1. Modify the contents of register B: Table 2. Time, Alarm, Calendar, and Index Formats Range Address RTC Bytes Decimal Binary Binary-Coded Decimal 0 Seconds 0–59 00H–3BH 00H–59H 1 Seconds alarm 0–59 00H–3BH 00H–59H 2 Minutes 0–59 00H–3BH 00H–59H 3 Minutes alarm 0–59 00H–3BH 00H–59H Hours, 12-hour format 1–12 01H–OCH AM; 81H–8CH PM 01H–12H AM; 81H–92H PM Hours, 24-hour format 0–23 00H–17H 00H–23H Hours alarm, 12-hour format 1–12 01H–OCH AM; 81H–8CH PM 01H–12H AM; 81H–92H PM Hours alarm, 24-hour format 0–23 00H–17H 00H–23H 6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H 7 Day of month 1–31 01H–1FH 01H–31H 8 Month 1–12 01H–0CH 01H–12H 9 Year (see note) 0–99 00H–63H 00H–99H D Day of month alarm 1–31 01H-1FH 01–31H 4 5 Note: Century for “Year” is shown in location 7Fh (Extended Index Register, bit 7) . 5 bq3285LF Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt request is generated. The interrupt request flag bit (INTF) of register C is set with every interrupt request. Reading register C clears all flag bits, including INTF, and makes INT high-impedance. On the next update cycle, the RTC updates all 10 bytes in the selected format. 32kHz Output The bq3285LF provides for a 32.768kHz output, and the output is always active whenever VCC is valid (VPFD + tCSR). The bq3285LF output is not affected by the bit settings in Register A. Time-keeping aspects, however, still require setting OS0-OS2. Two methods can be used to process bq3285LF interrupt events:
Interrupts
The bq3285LF allows three individually selected interrupt events to generate an interrupt request. These three interrupt events are:


Enable interrupt events and use the interrupt request output to invoke an interrupt service routine. Do not enable the interrupts and use a polling routine to periodically check the status of the flag bits. The individual interrupt sources are described in detail in the following sections. The periodic interrupt, programmable to occur once every 122µs to 500ms. Periodic Interrupt The alarm interrupt, programmable to occur once per second to once per day, is active in battery-backup mode, providing a “wake-up” feature. If the periodic interrupt event is enabled by writing a 1 to the periodic interrupt enable bit (PIE) in register C, an interrupt request is generated once every 122µs to 500ms. The period between interrupts is selected with bits RS3-RS0 in register A (see Table 3). The update-ended interrupt, which occurs at the end of each update cycle. Table 3. Periodic Interrupt Rate Register A Bits Periodic Interrupt OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 3.90625 ms 0 1 0 0 0 1 0 7.8125 ms 0 1 0 0 0 1 1 122.070 µs 0 1 0 0 1 0 0 244.141 µs 0 1 0 0 1 0 1 488.281 µs 0 1 0 0 1 1 0 976.5625 0 1 0 0 1 1 1 1.95315 ms 0 1 0 1 0 0 0 3.90625 ms 0 1 0 1 0 0 1 7.8125 ms 0 1 0 1 0 1 0 15.625 ms 0 1 0 1 0 1 1 31.25 ms 0 1 0 1 1 0 0 62.5 0 1 0 1 1 0 1 125 ms 0 1 0 1 1 1 0 250 ms 0 1 0 1 1 1 1 500 ms 0 1 1 X X X 6 X Period Units None µs ms same as above defined by RS3–RS0 bq3285LF inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle. Alarm Interrupt The alarm interrupt is active in battery-backup mode, providing a “wake-up” capability. During each update cycle, the RTC compares the day-of-the-month, hours, minutes, and seconds bytes with the four corresponding alarm bytes. If a match of all bytes is found, the alarm interrupt event flag bit, AF in register C, is set to 1. If the alarm event is enabled, an interrupt request is generated. Accessing RTC bytes The EXTRAM pin must be low to access the RTC registers. Time and calendar bytes read during an update cycle may be in error. Three methods to access the time and calendar bytes without ambiguity are: An alarm byte may be removed from the comparison by setting it to a “don't care” state. The seconds, minutes, and hours alarm bytes are set to a “don't care” state by writing a 1 to each of its two most-significant bits. The day-of-the-month alarm byte is set to a “don’t care” state by setting DA5–DA0, in register D, to all zeros. A “don't care” state may be used to select the frequency of alarm interrupt events as follows:






If none of the four alarm bytes is “don't care,” the frequency is once per month, when day-of-the-month, hours, minutes, and seconds match.
If only the day-of-the-month alarm byte is “don’t care”, the frequency is once per day, when hours, minutes, and seconds match. Enable the update interrupt event to generate interrupt requests at the end of the update cycle. The interrupt handler has a maximum of 999ms to access the clock bytes before the next update cycle begins (see Figure 3). Poll the update-in-progress bit (UIP) in register A. If UIP = 0, the polling routine has a minimum of tBUC time to access the clock bytes (see Figure 3). Use the periodic interrupt event to generate interrupt requests every tPI time, such that UIP = 1 always occurs between the periodic interrupts. The interrupt handler has a minimum of tPI/2 + tBUC time to access the clock bytes (see Figure 3). Oscillator Control If only the day-of-the-month and hour alarm byte is “don't care,” the frequency is once per hour, when minutes and seconds match. When power is first applied to the bq3285LF and VCC is above VPFD, the internal oscillator and frequency divider are turned on by writing a 010 pattern to bits 4 through 6 of register A. A pattern of 11X turns the oscillator on but keeps the frequency divider disabled. Any other pattern to these bits keeps the oscillator off. A pattern of 010 must be set for the bq3285LF to keep time in battery backup mode. If only the day-of-the-month, hour and minute alarm bytes are “don't care,” the frequency is once per minute, when seconds match. If the day-of-the-month, hour, minute, and second alarm bytes are “don't care,” the frequency is once per second. Update Cycle Interrupt Power-Down/Power-Up Cycle The update cycle ended flag bit (UF) in register C is set to a 1 at the end of an update cycle. If the update interrupt enable bit (UIE) of register B is 1, and the update transfer The bq3285LF continuously monitors VCC for out-oftolerance. During a power failure, when VCC falls below 1 Sec. UIP tUC (tPl)/2 (tPl)/2 tPl tBUC PF UF T3285L02.eps Figure 3. Update-Ended/Periodic Interrupt Relationship 7 bq3285LF VPFD (2.53V typical), the bq3285LF write-protects the clock and storage registers. The power source is switched to BC when VCC is less than VPFD and BC is greater than VPFD, or when VCC is less than VBC and VBC is less than VPFD. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VPFD, the power source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD. RS0–RS3 - Frequency Select 7 - 6 - 5 - 4 - 3 RS3 2 RS2 1 RS1 0 RS0 These bits select the periodic interrupt rate, as shown in Table 3. OS0–OS2 - Oscillator Control Control/Status Registers 7 - The four control/status registers of the bq3285LF are accessible regardless of the status of the update cycle (see Table 4). 6 OS2 5 OS1 Register A Bits 4 3 2 OS0 RS3 RS2 1 RS1 5 OS1 4 OS0 3 - 2 - 1 - 0 - These three bits control the state of the oscillator and divider stages. A pattern of 010 or 011 enables RTC operation by turning on the oscillator and enabling the frequency divider. This pattern must be set to turn the oscillator on and to ensure that the bq3285LF keeps time in battery-backup mode. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When 010 is written, the RTC begins its first update after 500ms. Register A 7 UIP 6 OS2 0 RS0 Register A programs:
The frequency of the periodic event rate.
Oscillator operation.
Time-keeping UIP - Update Cycle Status 7 UIP 5 - 4 - 3 - 2 - 1 - 0 - This read-only bit is set prior to the update cycle. When UIP equals 1, an RTC update cycle may be in progress. UIP is cleared at the end of each update cycle. This bit is also cleared when the update transfer inhibit (UTI) bit in register B is 1. Register A provides:
6 - Status of the update cycle. Table 4. Control/Status/Index Registers Loc. Reg. (Hex) Read Write A 0A Yes Yes1 B 0B Yes C 0C Yes D 0D SI EI Notes: Bit Name and State on Reset 7 (MSB) 6 5 4 3 1 0 (LSB) na OS2 na OS1 na OS0 na Yes UTI na PIE 0 AIE 0 UIE 0 - 0 DF na HF No INTF 0 PF 0 AF 0 UF 0 - 0 - na - Yes Yes2 VRT na - 0 7E Yes No NMI 0 SI6 0 SI5 0 SI4 0 SI3 0 SI2 0 SI1 0 SI0 0 7F Yes No CENT 0 EI6 0 EI5 0 EI4 0 EI3 0 EI2 0 EI1 0 EI0 0 DA5 na DA4 na na = not affected. x = unknown 1. Except bit 7. 2. Except bits 6 and 7. 8 RS3 2 UIP DA3 na RS2 na RS1 na RS0 na na DSE na 0 na DA2 na DA1 na - 0 DA0 na bq3285LF Register B 7 UTI 6 PIE UIE - Update Cycle Interrupt Enable 5 AIE Register B Bits 4 3 2 UIE DF 1 HF 7 - 0 DSE
Update cycle transfer operation
Interrupt events
Daylight saving adjustment 7 - 0 - 4 - 6 - 5 AIE 4 - 3 - 2 - 1 - 0 - This bit enables an interrupt request due to an alarm interrupt event: DSE - Daylight Saving Enable 3 - 2 - 1 - 0 DSE 1 = Enabled 0 = Disabled This bit enables daylight-saving time adjustments when written to 1:
1 - AIE - Alarm Interrupt Enable Bit 3 is unused.
2 - 0 = Disabled All bits of register B are read/write. 5 - 3 - The UIE bit is automatically cleared when the UTI bit equals 1. Clock and calendar data formats 6 - 4 UIE 1 = Enabled Register B selects: 7 - 5 - This bit enables an interrupt request due to an update ended interrupt event: Register B enables:
6 - PIE - Periodic Interrupt Enable On the last Sunday in October, the first time the bq3285LF increments past 1:59:59 AM, the time falls back to 1:00:00 AM. 7 - 6 PIE 5 - 4 - 3 - 2 - 1 - 0 - This bit enables an interrupt request due to a periodic interrupt event: On the first Sunday in April, the time springs forward from 2:00:00 AM to 3:00:00 AM. 1 = Enabled HF - Hour Format 0 = Disabled 7 - 6 - 5 - 4 - 3 - 2 - 1 HF 0 - UTI - Update Transfer Inhibit 7 UTI This bit selects the time-of-day and alarm hour format: 1 = 24-hour format 0 = 12-hour format 6 - 5 - 5 - 4 - 3 - 2 - 1 - 0 - This bit inhibits the transfer of RTC bytes to the user buffer: DF - Data Format 7 - 6 - 1 = Inhibits transfer and clears UIE 4 - 3 - 2 DF 1 - 0 - 0 = Allows transfer Register C This bit selects the numeric format in which the time, alarm, and calendar bytes are represented: 7 INTF 1 = Binary 0 = BCD 6 PF 5 AF Register C Bits 4 3 UF 0 2 - 1 0 Register C is the read-only event status register. 9 0 0 bq3285LF Bits 0, 1, 2, 3 - Unused Bits 7 - 6 - 5 - 4 - Bits 6 - Unused Bit 3 0 2 - 1 0 0 0 7 - 6 0 5 - 4 - These bits are always set to 0. This bit is always set to 0. UF - Update Event Flag VRT - Valid RAM and Time 7 - 6 - 5 - 4 UF 3 - 2 - 1 - 0 - 7 VRT This bit is set to a 1 at the end of the update cycle. Reading register C clears this bit. 6 - 5 AF 4 - 3 - 2 - 1 - 5 - 4 - 3 - 2 - 1 - 0 - 7 - 5 - 4 - 2 - 1 - 1 - 0 - 6 - 5 DA5 4 DA4 3 DA3 2 DA2 1 DA1 0 DA0 Standard Bank Index 7 NMI 3 - 2 - These bits store the value for the day-of-the-month alarm. If DA0–DA5 are set to zero, then the day-of-themonth alarm is disabled . These bits are not affected by a reset. 0 - INTF - Interrupt Request Flag 6 - 3 - DA0–DA5 This bit is set to a 1 every tPI time, where tPI is the time period selected by the settings of RS0–RS3 in register A. Reading register C clears this bit. 7 INTF 0 - When the backup energy source is depleted (VRT = 0), data integrity of the RTC and storage registers is not guaranteed. PF - Periodic Event Flag 6 PF 4 - 1 - 0 = Backup energy source is depleted This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit. 7 - 5 - 2 - 1 = Valid backup energy source AF - Alarm Event Flag 7 - 6 - 3 - 0 - 6 SI6 5 SI5 4 SI4 3 SI3 2 SI2 1 SI1 0 SI0 This register contains a copy of the last index value used for the standard bank of SRAM, and non-maskable interrupt, and is read only. This flag is set to a 1 when any of the following is true: Extended Bank Index AIE = 1 and AF = 1 7 CENT PIE = 1 and PF = 1 UIE = 1 and UF = 1 Register D 6 0 5 DA5 Register D Bits 4 3 2 DA4 DA3 DA2 5 EI5 4 EI4 3 EI3 2 EI2 1 EI1 0 EI0 This register contains a copy of the last index value used for the extended bank of SRAM and century bit. For years 80–90, set CENT = 1. For years 00–79, set CENT = 0. Reading register C clears this bit. 7 VRT 6 EI6 1 DA1 0 DA0 Register D provides for the read-only data integrity status bit, and the day-of-the-month alarm. 10 bq3285LF Absolute Maximum Ratings Value Unit VCC Symbol DC voltage applied on VCC relative to VSS -0.3 to 7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to 7.0 V VT ≤ VCC + 0.3 TOPR Operating temperature 0 to +70 °C Commercial TSTG Storage temperature -55 to +125 °C TBIAS Temperature under bias -40 to +85 °C TSOLDER Soldering temperature 260 °C Note: Parameter Conditions For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Recommended DC Operating Conditions (TA = TOPR, VCC = 3V unless otherwise noted) Symbol Parameter Minimum Typical Maximum Unit VCC Supply voltage 2.7 3.0 5.5 V VSS Supply voltage 0 0 0 V VIL Input low voltage -0.3 - 0.6 V VIH Input high voltage VBC Backup cell voltage Note: 2.2 - VCC + 0.3 V 2.8 - VCC + 0.3 V 2.4 - 4.0 V Notes VCC = 5V Typical values indicate operation at TA = 25°C. Crystal Specifications (DT-26 or Equivalent) Symbol Parameter fO Oscillation frequency CL Load capacitance TP Temperature turnover point k Parabolic curvature constant Q Quality factor R1 Minimum Typical Maximum Unit - 32.768 - kHz - 6 - pF 20 25 30 °C ppm/°C - - -0.042 40,000 70,000 - Series resistance - - 45 KΩ C0 Shunt capacitance - 1.1 1.8 pF C0/C1 Capacitance ratio - 430 600 DL Drive level - - 1 µW ∆f/fO Aging (first year at 25°C) - 1 - ppm 11 bq3285LF DC Electrical Characteristics (TA = TOPR, VCC = 3V) Symbol Parameter Minimum Typical1 Maximum Unit Conditions/Notes ILI Input leakage current - - ±1 µA VIN = VSS to VCC ILO Output leakage current - - ±1 µA AD0–AD7 and INT in high impedance, VOUT = VSS to VCC VOH Output high voltage 2.2 - - V IOH = -1.0 mA VOL Output low voltage - - 0.4 V IOL = 2.0 mA ICC Operating supply current - 52 9 mA Min. cycle, duty = 100%, IOH = 0mA, IOL = 0mA ICCSB Standby supply current - 1003 - µA VIN = VSS or VCC, CS ≥ VCC - 0.2 - VPFD - V VBC > VPFD VSO Supply switch-over voltage - VBC - V VBC < VPFD VBC = 3V, TA = 25°C, VCC < VBC ICCB Battery operation current - 0.4 0.55 µA VPFD Power-fail-detect voltage 2.4 2.53 2.65 V IRCL Input current when RCL = VSS. - - 120 µA Internal 30K pull-up Input current when MOT = VCC - - -120 µA Internal 30K pull-down Input current when MOT = VSS - - 0 µA Internal 30K pull-down Input current when EXTRAM = VCC - - -120 µA Internal 30K pull-down Input current when EXTRAM = VSS - - 0 µA Internal 30K pull-down IMOTH IXTRAM Notes: 1. Typical values indicate operation at TA = 25°C, VCC = 3V. 2. 7mA at VCC = 5V 3. 300µA at VCC = 5V 12 bq3285LF Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V) Symbol Parameter Minimum Typical Maximum Unit Conditions CI/O Input/output capacitance - - 7 pF VOUT = 0V CIN Input capacitance - - 5 pF VIN = 0V Note: This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin. AC Test Conditions Parameter Test Conditions 0 to 2.3 V, VCC = 3V Input pulse levels Input rise and fall times 5 ns Input and output timing reference levels 1.2 V (unless otherwise specified) Output load (including scope and jig) See Figures 6 and 7 +3.3V +3.3V 1238 1.45k For all outputs except INT 1164 INT 130pF 50pF Figure 6. Output Load Figure 7. Output Load B 13 bq3285LF Read/Write Timing (TA = TOPR, VCC = 3V) Symbol Parameter Minimum Typical Maximum Unit tCYC Cycle time 285 - - ns tDSL DS low or RD/WR high time 135 - - ns tDSH DS high or RD/WR low time 90 - - ns tRWH R/W hold time 0 - - ns tRWS R/W setup time 15 - - ns tCS Chip select setup time 8 - - ns tCH Chip select hold time 0 - - ns tDHR Read data hold time 0 - 40 ns tDHW Write data hold time 0 - - ns tAS Address setup time 30 - - ns tAH Address hold time 15 - - ns tDAS Delay time, DS to AS rise 30 - - ns tASW Pulse width, AS high 50 - - ns tASD Delay time, AS to DS rise (RD/WR fall) 55 - - ns tOD Output data delay time from DS rise (RD fall) - - 100 ns tDW Write data setup time 50 - - ns tBUC Delay time before update cycle - 244 - µs tPI Periodic interrupt time interval - - - - tUC Time of update cycle - 1 - µs tEXT EXTRAM input setup and hold time 15 - - ns 14 Notes See Table 3 bq3285LF Motorola Bus Read/Write Timing EXTRAM tEXT tASW tEXT AS tDAS tASD tCYC DS tDSL tDSH tRWS tRWH R/W tCS tCH CS tAS tAH tDW tDHW AD0 -AD7 (WRITE) tOD tAS tAH tDHR AD0 -AD7 (READ) T3285LF3.eps 15 bq3285LF Intel Bus Read Timing tCYC EXTRAM tEXT AS (ALE) tASW tASD tEXT DS (RD) tDSH tDSL R/W (WR) tOD tCS tDAS tCH CS tAS tAH tDHR AD0 -AD7 T3285LF4.eps Intel Bus Write Timing tCYC EXTRAM tEXT tEXT AS (ALE) tDAS tASW tASD DS (RD) tDSL tDSH R/W (WR) tCS tCH CS tAS tAH AD0 -AD tDW tDHW T3285LF5.eps 16 bq3285LF Power-Down/Power-Up Timing (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tF VCC slew from 2.7V to 0V 300 - - µs tR VCC slew from 0V to 2.7V 100 - - µs tCSR CS at VIH after power-up 20 - 200 ms Conditions Internal write-protection period after VCC passes VPFD on power-up. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing tF tR 2.7 VCC 2.7 VPFD VPFD VSO VSO tCSR CS INT (Alarm) T3285L06.eps 17 bq3285LF Interrupt Delay Timing (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tRSW Reset pulse width 5 - - µs tIRR INT release from RST - - 2 µs tIRD INT release from DS - - 2 µs Interrupt Delay Timing RD (Intel) DS (Mot) tRSW RST INT tIRD tIRR T3285L07.eps 18 bq3285LF 24-Pin SSOP (SS) 24-Pin SS (0.150" SSOP) Inches Dimension Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.010 0.10 0.25 B 0.008 0.012 0.20 0.30 C 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e .025 BSC Page No. 1 All Notes: 0.230 0.244 5.84 6.20 L 0.016 0.035 0.41 0.89 Description of Change “Final” changes from “Preliminary” Change 1 = June 1999 B “Final” changes from April 1999 “Preliminary.” Ordering Information bq3285LF Temperature: blank = Commercial (0 to +70°C) Package Option: SS= 24-pin SSOP (0.150) Device: bq3285LF Real-Time Clock with 240 bytes of general storage 19 0.64 BSC H Data Sheet Revision History ChangeNo. Millimeters Min. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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Copyright  1999, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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