BQ34Z100-R2
SLUSF37 – DECEMBER 2022
BQ34Z100-R2 Wide Range Fuel Gauge with Impedance Track™ Technology
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports Li-ion, LiFePO4, PbA, NiMH, and NiCd
chemistries
Capacity estimation using patented Impedance
Track™ technology for batteries from 3 V to
16.7 KV
– Aging compensation
– Self-discharge compensation
Supports battery capacities up to 7000 Ah with
standard configuration options
Supports charge and discharge currents up to
8160 A with standard configuration options
External NTC thermistor support
Supports two-wire I2C and HDQ single-wire
communication interfaces with host system
SHA-1/HMAC authentication
One- or four-LED direct display control
Five-LED and higher display through port
expander
Reduced power modes (typical battery pack
operating range conditions)
– NORMAL operation: < 145-µA average
– SLEEP: < 84-µA average
– FULL SLEEP: < 30-µA average
Package: 14-pin TSSOP
Light electric vehicles
Medical instrumentation
Mobile radios
Power tools
Uninterruptible power supplies (UPS)
3 Description
The BQ34Z100-R2 device is an Impedance Track™
fuel gauge for Li-ion, PbA, NiMH, and NiCd
batteries, and works independently of battery seriescell configurations. Batteries from 3 V to 16.7 KV
can be easily supported through an external voltage
translation circuit that is controlled automatically to
reduce system power consumption.
The BQ34Z100-R2 device provides several interface
options, including an I2C peripheral, an HDQ
peripheral, one or four direct LEDs, and an ALERT
output pin. Additionally, the BQ34Z100-R2 provides
support for an external port expander for more than
four LEDs.
Device Information
PART
NUMBER(1)
BQ34Z100-R2
(1)
PACKAGE
BODY SIZE (NOM)
TSSOP (14)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ34Z100-R2
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Power-On Reset................ 5
6.6 Electrical Characteristics: LDO Regulator...................5
6.7 Electrical Characteristics: Internal Temperature
Sensor Characteristics.................................................. 5
6.8 Electrical Characteristics: Low-Frequency
Oscillator....................................................................... 6
6.9 Electrical Characteristics: High-Frequency
Oscillator....................................................................... 6
6.10 Electrical Characteristics: Integrating ADC
(Coulomb Counter) Characteristics............................... 6
6.11 Electrical Characteristics: ADC (Temperature
and Cell Measurement) Characteristics........................ 6
6.12 Electrical Characteristics: Data Flash Memory
Characteristics...............................................................7
6.13 Timing Requirements: HDQ Communication............ 7
6.14 Timing Requirements: I2C-Compatible Interface...... 8
6.15 Typical Characteristics.............................................. 9
7 Functional Block Diagram............................................ 10
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Applications...................................................11
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................21
11.1 Documentation Support.......................................... 21
11.2 Receiving Notification of Documentation Updates.. 21
11.3 Support Resources................................................. 21
11.4 Trademarks............................................................. 21
11.5 Electrostatic Discharge Caution.............................. 21
11.6 Glossary.................................................................. 21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
P2
1
14
P3/SDA
VEN
2
13
P4/SCL
P1
3
12
P5/HDQ
BAT
4
11
P6/TS
CE
5
10
SRN
REGIN
6
9
SRP
REG25
7
8
VSS
Not to scale
Table 5-1. Pin Functions
PIN
NAME
NUMBER
TYPE
DESCRIPTION
P2
1
O
LED 2 or Not Used (connect to VSS)
VEN
2
O
Active High Voltage Translation Enable. This signal is optionally used to switch the input voltage
divider on/off to reduce the power consumption (typ 45 µA) of the divider network. If not used,
then this pin can be left floating or tied to VSS.
P1
3
O
LED 1 or Not Used (connect to VSS). This pin is also used to drive an LED for single-LED mode.
Use a small signal N-FET (Q1) in series with the LED as shown on Figure 8-4.
BAT
4
I
Translated Battery Voltage Input
CE
5
I
Chip Enable. Internal LDO is disconnected from REGIN when driven low.
REGIN
6
P
Internal integrated LDO input. Decouple with a 0.1-µF ceramic capacitor to VSS.
REG25
7
P
2.5-V output voltage of the internal integrated LDO. Decouple with 1-µF ceramic capacitor to
VSS.
VSS
8
P
Device ground
SRP
9
I
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRP is nearest the BAT– connection.
SRN
10
I
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRN is nearest the PACK– connection.
P6/TS
11
I
Pack thermistor voltage sense (use a 103AT-type thermistor)
P5/HDQ
12
I/O
Open-drain HDQ Serial communication line (target). If not used, then this pin can be left floating
or tied to VSS.
P4/SCL
13
I
Target I2C serial communication clock input. Use with a 10-kΩ pullup resistor (typical). This pin is
also used for LED 4 in the four-LED mode. If not used, then this pin can be left floating or tied to
VSS.
P3/SDA
14
I/O
Open-drain target I2C serial communication data line. Use with a 10-kΩ pullup resistor (typical).
This pin is also used for LED 3 in the four-LED mode. If not used, then this pin can be left floating
or tied to VSS.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VREGIN
Regulator Input Range
–0.3
5.5
V
VCC
Supply Voltage Range
–0.3
2.75
V
VIOD
Open-drain I/O pins (SDA, SCL, HDQ, VEN)
–0.3
5.5
V
VBAT
Bat Input pin
–0.3
5.5
V
VI
Input Voltage range to all other pins (P1, P2, SRP, SRN)
–0.3
VCC + 0.3
V
1.5
kV
2
kV
Human-body model (HBM), BAT pin
ESD
Human-body model (HBM), all other pins
TA
Operating free-air temperature range
–40
85
°C
TF
Functional temperature range
–40
100
°C
Storage temperature range
–65
150
°C
Lead temperature (soldering, 10 s)
–40
100
°C
TSTG
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA =–40°C to 85°C; Typical Values at TA = 25°C CLDO25 = 1.0 µF, and VREGIN = 3.6 V (unless otherwise noted)
MIN
4
No operating restrictions
NOM
MAX
UNIT
2.7
4.5
V
2.45
2.7
V
VREGIN
Supply Voltage
CREGIN
External input capacitor for
internal LDO between REGIN
and VSS
CLDO25
External output capacitor for
internal LDO between VCC and
VSS
ICC
NORMAL operating-mode
current
Gas Gauge in NORMAL mode,
ILOAD > Sleep Current
ISLP
SLEEP operating-mode current
Gas Gauge in SLEEP mode,
ILOAD < Sleep Current
84
μA
ISLP+
FULLSLEEP operating-mode
current
Gas Gauge in FULL SLEEP mode,
ILOAD < Sleep Current
30
μA
VOL
Output voltage, low (SCL, SDA,
HDQ, VEN)
IOL = 3 mA
VOH(PP)
Output voltage, high
IOH = –1 mA
VOH(OD)
Output voltage, high (SDA, SCL,
External pull-up resistor connected to VCC
HDQ, VEN)
VIL
Input voltage, low
No FLASH writes
Nominal capacitor values specified.
Recommend a 10% ceramic X5R type
capacitor located close to the device.
μF
1
μF
0.47
145
μA
0.4
V
VCC – 0.5
V
VCC – 0.5
V
–0.3
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0.1
0.6
V
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6.3 Recommended Operating Conditions (continued)
TA =–40°C to 85°C; Typical Values at TA = 25°C CLDO25 = 1.0 µF, and VREGIN = 3.6 V (unless otherwise noted)
MIN
VIH(OD)
Input voltage, high (SDA, SCL,
HDQ)
VA1
NOM
MAX
UNIT
1.2
6
V
Input voltage range (TS)
VSS – 0.05
1
V
VA2
Input voltage range (BAT)
VSS – 0.125
5
V
VA3
Input voltage range (SRP, SRN)
VSS – 0.125
0.125
V
ILKG
Input leakage current (I/O pins)
tPUCD
Power-up communication delay
0.3
μA
250
ms
6.4 Thermal Information
BQ34Z100-R2
THERMAL
METRIC(1)
TSSOP (PW)
UNIT
14 PINS
RθJA, High K
Junction-to-ambient thermal resistance
103.8
RθJC(top)
Junction-to-case(top) thermal resistance
31.9
RθJB
Junction-to-board thermal resistance
46.6
ψJT
Junction-to-top characterization parameter
2.0
ψJB
Junction-to-board characterization parameter
45.9
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report, SPRA953.
6.5 Electrical Characteristics: Power-On Reset
TA = –40°C to 85°C; Typical Values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going battery voltage
input at REG25
VHYS
Power-on reset hysteresis
MIN
TYP
MAX UNIT
2.05
2.20
2.31
V
45
115
185
mV
MIN
TYP
2.5
6.6 Electrical Characteristics: LDO Regulator
TA = 25°C, CLDO25 = 1.0 µF, VREGIN = 3.6 V (unless otherwise noted)(1)
PARAMETER
VREG25
ISHORT (2)
(1)
(2)
TEST CONDITIONS
Regulator output
voltage
Short Circuit
Current Limit
2.7 V ≤ VREGIN ≤ 4.5 V,
IOUT ≤ 16 mA
TA= –40°C to 85°C
2.3
2.45 V ≤ VREGIN < 2.7 V
(low battery), IOUT ≤ 3 mA
TA = –40°C to 85°C
2.3
VREG25 = 0 V
TA = –40°C to 85°C
MAX UNIT
2.7
V
250
mA
LDO output current, IOUT, is the sum of internal and external load currents.
Specified by design. Not production tested.
6.7 Electrical Characteristics: Internal Temperature Sensor Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
GTEMP
TEST CONDITIONS
Temperature sensor voltage gain
MIN
TYP
–2
MAX UNIT
mV/°C
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6.8 Electrical Characteristics: Low-Frequency Oscillator
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
f(LOSC)
t(LSXO)
MIN
Operating frequency
Start-up
TYP
MAX UNIT
32.768
Frequency error(1) (2)
f(LEIO)
(1)
(2)
(3)
TEST CONDITIONS
kHz
TA = 0°C to 60°C
–1.5%
0.25%
1.5%
TA = –20°C to 70°C
–2.5%
0.25%
2.5%
TA = –40°C to 85°C
–4%
0.25%
4%
time(3)
500
μs
The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
The frequency error is measured from 32.768 kHz.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.9 Electrical Characteristics: High-Frequency Oscillator
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f(OSC)
Operating frequency
f(EIO)
Frequency error(1) (2)
TYP
MAX UNIT
8.389
MHz
TA = 0°C to 60°C
–2%
0.38%
TA = –20°C to 70°C
–3%
0.38%
3%
TA = –40°C to 85°C
–4.5%
0.38%
4.5%
2.5
5
Start-up time(2)
t(SXO)
(1)
(2)
MIN
2%
ms
The frequency error is measured from 2.097 MHz.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.10 Electrical Characteristics: Integrating ADC (Coulomb Counter) Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
V(SR)
tSR_CONV
TEST CONDITIONS
Input voltage range, V(SRN) and V(SRP)
V(SR) = V(SRN) – V(SRP)
Conversion time
Single conversion
Resolution
Input offset
INL
Integral nonlinearity error
ZIN(SR)
Effective input resistance(1)
(1)
(2)
Input leakage
TYP
MAX UNIT
0.125
V
1
14
VOS(SR)
Ilkg(SR)
MIN
–0.125
s
15
bits
10
±0.007%
µV
±0.034%
FSR(2)
2.5
MΩ
current(1)
0.3
µA
Specified by design. Not tested in production.
Full-scale reference
6.11 Electrical Characteristics: ADC (Temperature and Cell Measurement) Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
VIN(ADC)
tADC_CONV
VOS(ADC)
ZADC1
ZADC2
6
TEST CONDITIONS
Input voltage range
MIN
TYP
0.05
1
Conversion time
Resolution
14
Input offset
Effective input resistance
1
(TS)(1)
Effective input resistance (BAT)(1)
BQ34Z100-R2 not measuring cell
voltage
BQ34Z100-R2 measuring cell
voltage
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MAX UNIT
V
125
ms
15
bits
mV
8
MΩ
8
MΩ
100
KΩ
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6.11 Electrical Characteristics: ADC (Temperature and Cell Measurement) Characteristics
(continued)
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
Ilkg(ADC)
(1)
TEST CONDITIONS
Input leakage
MIN
TYP
current(1)
MAX UNIT
0.3
µA
Specified by design. Not tested in production.
6.12 Electrical Characteristics: Data Flash Memory Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
tDR
ICCPROG
MIN
TYP
cycles(1)
Years
20,000
Cycles
Word programming time(1)
Flash-write supply
MAX UNIT
10
Flash-programming write
tWORDPROG
(1)
TEST CONDITIONS
Data retention(1)
current(1)
5
2
ms
10
mA
Specified by design. Not tested in production.
6.13 Timing Requirements: HDQ Communication
TA = –40°C to 85°C, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
t(CYCH)
Cycle time, host to BQ34Z100-R2
190
μs
t(CYCD)
Cycle time, BQ34Z100-R2 to host
190
t(HW1)
Host sends 1 to BQ34Z100-R2
0.5
t(DW1)
BQ34Z100-R2 sends 1 to host
t(HW0)
Host sends 0 to BQ34Z100-R2
t(DW0)
BQ34Z100-R2 sends 0 to host
t(RSPS)
Response time, BQ34Z100-R2 to host
t(B)
Break time
190
μs
t(BR)
Break recovery time
40
μs
t(RISE)
HDQ line rising time to logic 1 (1.2 V)
t(RST)
HDQ Reset
250
μs
50
μs
32
50
μs
86
145
μs
80
145
μs
190
950
μs
1.8
205
950
ns
2.2
s
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1.2V
t(BR)
t(B)
t(RISE)
(b) HDQ line rise time
(a) Break and Break Recovery
t(DW1)
t(HW1)
t(DW0)
t(CYCD)
t(HW0)
t(CYCH)
(d) Gauge Transmitted Bit
(c) Host Transmitted Bit
1-bit
R/W
7-bit address
Break
8-bit data
t(RSPS)
(e) Gauge to Host Response
Figure 6-1. Timing Diagrams
6.14 Timing Requirements: I2C-Compatible Interface
TA = –40°C to 85°C, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise
noted)
PARAMETER
tr
SCL/SDA rise time
tf
SCL/SDA fall time
tw(H)
SCL pulse width (high)
tw(L)
tsu(STA)
TEST CONDITIONS
MIN
NOM
MAX
UNIT
300
ns
300
ns
600
ns
SCL pulse width (low)
1.3
μs
Setup for repeated start
600
ns
td(STA)
Start to first falling edge of SCL
600
ns
tsu(DAT)
Data setup time
100
ns
th(DAT)
Data hold time
0
ns
tsu(STOP)
Setup time for stop
600
ns
tBUF
Bus free time between stop and start
fSCL
Clock frequency
66
μs
400
tSU(STA)
tw(H)
tf
tw(L)
tr
kHz
t(BUF)
SCL
SDA
td(STA)
tsu(STOP)
tf
tr
th(DAT)
tsu(DAT)
REPEATED
START
STOP
START
Figure 6-2. I2C-Compatible Interface Timing Diagrams
8
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6.15 Typical Characteristics
15
200
160
120
Voltage Error (mV)
Total Battery Voltage
Voltage Error (mV)
10
5
0
-5
-10
80
40
0
-40
-80
-120
-15
-40qC
-20qC
-20
2800
3000
25qC
65qC
3200
-200
25.2
3400 3600 3800
Battery Voltage (mV)
4000
4200
2
20
1
30.6 32.4 34.2
Battery Voltage (V)
36
37.8
39.6
D002
0
Temperature Error (qC)
15
Current Error (mA)
28.8
85°C
Figure 6-4. V(Err) Across VIN (0 mA) 9 s
D001
25
10
5
0
-5
-10
-15
-25
-3000
27
25°C
65°C
4400
Figure 6-3. V(Err) Across VIN (0 mA)
-20
-40°C
-20°C
-160
85qC
-1
-2
-3
-4
-5
-6
-7
-40qC
-20qC
-2000
25qC
65qC
-1000
85qC
0
1000
Current (mA)
-8
2000
3000
-9
-40
-20
D003
Figure 6-5. I(Err)
0
20
40
Temperature (qC)
60
80
100
D004
Figure 6-6. T(Err)
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7 Functional Block Diagram
10
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The BQ34Z100-R2 is a flexible gas gauge device with many options. The major configuration choices comprise
the battery chemistry, digital interface, and display.
8.2 Typical Applications
Figure 8-1 is a simplified diagram of the main features of the BQ34Z100-R2. Specific implementations detailing
the main configuration options are shown later in this section.
Figure 8-1. BQ34Z100-R2 Simplified Implementation
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11
12
TB3
2
3
BAT -
1
PACK -
BAT +
GND
AGND
REGIN
AGND
R30
.010 75ppm
C2
0.1uF
AGND
R5
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100
R6
100
1K
R1
C6
C5
LED Display
SW1
P1
U2
0.1uF
C8
REG25
REGIN
CE
BAT
P1
VEN
P2
1uF
C7
8
9
10
11
12
13
14
0.1uF
VSS
SRP
SRN
P6/TS
P5/HDQ
P4/SCL
P3/SDA
BQ34Z100PW
0.1uF
7
6
5
4
2
3
P2
C1
0.1uF
1
AGND
LED0
LED1
LED2
LED3
LED4
REGIN
R14
100
GND
D3
QTLP610C-4 GRN
R12
R11
R10
D11 QTLP610C-4 GRN
D12 QTLP610C-4 GRN
R9
R8
P1
470
470
470
470
470
GND
GND
GND
J9
4
7
6
5
4
3
2
1
1
2
3
U3
GND
GND
QD
QC
QB
QA
B
A
CLK
~CLR
QE
QF
QG
QH
VCC
SN74HC164PW
J10
8
9
10
11
12
13
14
REGIN
HDQ or ALERT
GND
SDA
SCLor ALERT
1
2
4
3
P2
C3
0.1uF
Copyright © 2016 , Texas Instruments Incorporated
R13
100
AZ23C5V6-7
D2
GND
R55
100
R53
100
D10 QTLP610C-4 GRN
D9 QTLP610C-4 GRN
RT1
10K
D1
AZ23C5V6-7
R56
100
R54
100
GND
SLUSF37 – DECEMBER 2022
BQ34Z100-R2
www.ti.com
The BQ34Z100-R2 can be used to provide a single Li-ion cell gas gauge with a 5-bar LED display.
Figure 8-2. 1-Cell Li-ion and 5-LED Display
The BQ34Z100-R2 can also be used to provide a gas gauge for a multi-cell Li-ion battery with a 5-bar LED
display.
Copyright © 2023 Texas Instruments Incorporated
SH1 SH2
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: BQ34Z100-R2
SH1
SH2
GND
AGND
R30
.010 75ppm *
* Optimize for required voltage and current
3
PACK TB3
1
2
BAT +
BAT -
10k *
R3
R1
Q3
2N7002
0.1uF
C2
AGND
GND
BZT52C5V6T
R7
D
AGND
3
REGIN
16.5 K .1% 25PPM *
VOLTAGE DIVIDER .1% 25PPM *
D7
Q5
BSS84
R4
165K *
G
1
R2
100K *
2 S
AGND
R6
R5
LED Display
SW1
3300 pF
C1
GND
Q4
2N7002
100
100
P2
1k
R15
P1
C6
C5
REG25
2
1
VEN
P2
0.1uF
C8
REG25
REGIN
CE
BAT
P1
0.1uF
7
6
5
4
3
U2
1uF
14
13
C7
8
9
10
11
12
0.1uF
VSS
SRP
SRN
P6/TS
P5/HDQ
P4/SCL
P3/SDA
BQ34Z100PW
AGND
REG25
RT1
10K
LED0
LED1
LED2
LED3
LED4
REGIN
D1
GND
GND
R11
R12
QTLP610C-4 GRN
D3
D12 QTLP610C-4 GRN
R9
R10
D11 QTLP610C-4 GRN
R8
P1
AZ23C5V6-7
D2
D10 QTLP610C-4 GRN
D9 QTLP610C-4 GRN
R14
100
R13
100
1k
1k
1k
1k
1k
GND
7
6
5
4
3
2
1
GND
QD
QC
QB
QA
B
A
U3
CLK
~CLR
QE
QF
QG
QH
VCC
SN74HC164PW
8
9
10
11
12
13
14
GND
GND
J9
4
3
REGIN
1
2
P2
C3
J10
0.1uF
GND
GND
HDQ or ALERT
GND
SDA
1
SCLor ALERT
4
3
2
Copyright © 2016, Texas Instruments Incorporated
R55
100
R56
100
AZ23C5V6-7
R53
100
R54
100
www.ti.com
SLUSF37 – DECEMBER 2022
BQ34Z100-R2
Figure 8-3. Multi-Cell and 5-LED Display
Submit Document Feedback
13
BAT -
BAT +
PACK -
TB3
1
2
3
GND
R30
.010 75ppm
AGND
Submit Document Feedback
Product Folder Links: BQ34Z100-R2
R12
R18
R20
R22
R23
R24
D13 QTLP610C-3 YEL
D14 QTLP610C-3 YEL
D15 QTLP610C-4 GRN
D16 QTLP610C-4 GRN
D17 QTLP610C-4 GRN
D6
6
TP4
U3
U1
CLK
~CLR
QE
QF
QG
QH
VCC
GND
QD
QC
QB
QA
B
A
CLK
~CLR
QE
QF
QG
QH
VCC
SN74HC164PW
GND
QD
QC
QB
QA
B
A
0.1uF
TP6
TP5
8
9
11
TP7
TP8
GND
C5
REGIN
0.1uF
C8
REG25
REGIN
CE
BAT
P1
VEN
1uF
8
9
10
11
12
13
14
0.1uF
C7
VSS
SRP
SRN
P6/TS
P5/HDQ
P4/SCL
P3/SDA
U2
BQ34Z1X0 PW
P2
0.1uF
7
6
5
4
3
2
1
Optimize for required LED power dissipation
AGND
QTLP610C-4 GRN
GND
R32
1M
Q1
2SK3019
LED A
Open for I2C
J1
2
I2C pullups normally implemented in the host. Duplicated here since EV2300 does not provide
C6
R38
1k
REG25
GND
P2
100
R6
0.1uF
100
C4
P1
P2
LED Display
R5
C3
AGND
0.1uF
SW1
GND
P4
LED B
GND
GND
R33
1M
Q2
2SK3019
D8
1.5K
R15
1uF
C1
R7
2M
2SK3019
Q7
GND
P3
3
GND
D3
R16
1.5K
R21
220K
D4
R17
1.5K
GND
R29
10k
LED C
Q6
2SK3019
RT1
10K
REGIN
P2
REG25
A
B
P1
P2
P3
P4
D
D5
R19
1.5K
C
R14
100
GND
1
2
3
4
5
6
7
8
9
10
J6
EXT
A
B
C
D
100
R13
AZ23C5V6-7
D2
GND
LED CONFIGURATION OPTIONS
ALERT CONFIGURATION
200
R25
D1
AZ23C5V6-7
R34
100
100
R36
1
J7
4
3
1
2
2
3
TB1
J4
GND
ALERT
GND
HDQ
GND
SCL
1
SDA
4
3
2
Fiducial Marks
GND
GND
GND
Copyright © 2016 , Texas Instruments Incorporated
REGIN
LED D
J3
R31
10k
R37
100
R35
100
BQ34Z100-R2
4
3
48V
10
12
13
14
8
9
10
11
12
13
14
>5V
>5V