bq34z110
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SLUSB55B – JUNE 2012 – REVISED MAY 2013
Wide Range Fuel Gauge with Impedance Track™ for Lead-Acid Batteries
Check for Samples: bq34z110
FEATURES
1
•
•
23
•
•
•
•
•
•
•
Supports Lead-Acid Chemistries
Capacity Estimation Using Patented
Impedance Track™ Technology for Batteries
from 4 V to 64 V
– Aging Compensation
– Self-Discharge Compensation
Supports Battery Capacities Above 65 Ahr
Supports Charge and Discharge Currents
Above 32 A
External NTC Thermistor Support
Supports Two-Wire I2C™ and HDQ Single-Wire
Communication Interfaces with Host System
SHA-1, HMAC Authentication
One- or Four-LED Direct Display Control
Five-LED and Higher Display Through Port
Expander
•
•
Reduced Power Modes (Typical Battery Pack
Operating Range Conditions)
– Normal Operation: < 140 µA Average
– Sleep: < 64 µA Average
– Full Sleep: < 19 µA Average
Package: 14-Pin TSSOP
APPLICATIONS
•
•
•
•
•
Light Electric Vehicles
Power Tools
Medical Instrumentation
Uninterruptible Power Supplies (UPS)
Mobile Radios
DESCRIPTION
The Texas Instruments bq34z110 is a fuel gauge solution that works independently of battery series-cell
configurations, and supports Lead-Acid battery chemistries. Batteries from 4 V to 64 V can be supported through
an external voltage translation circuit that can be controlled automatically to reduce system power consumption.
The bq34z110 device provides several interface options, including an I2C slave, an HDQ slave, one or four direct
LEDs, and an Alert output pin. Additionally, the bq34z110 provides support for an external port expander for
more than four LEDs.
ORDERING INFORMATION
TA
PART NUMBER
PACKAGE
(TSSOP)
TUBE
TAPE AND REEL
–40°C to 85°C
bq34z110PW or
bq34z110PWR
14-Pin
PW
PWR
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Impedance Track is a trademark of Texas Instruments.
I2C is a trademark of NXP B.V Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
bq34z110
SLUSB55B – JUNE 2012 – REVISED MAY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN DETAILS
PINOUT DIAGRAM
P2
1
14
P3/SDA
VEN
2
13
P4/SCL
P1
3
12
P5/HDQ
BAT
4
11
P6/TS
CE
5
10
SRN
REGIN
6
9
SRP
REG25
7
8
VSS
Figure 1. bq34z110 Pinout Diagram
Table 1. bq34z110 External Pin Functions
PIN NAME
PIN
NUMBER
TYPE (1)
P2
1
O
LED 2 or Not Used (connect to Vss)
VEN
2
O
Active High Voltage Translation Enable. This signal is optionally used to switch the input voltage
divider on/off to reduce the power consumption (typ 45 µA) of the divider network.
P1
3
O
LED 1 or Not Used (connect to Vss). This pin is also used to drive an LED for single-LED mode.
Use a small signal N-FET (Q1) in series with the LED as shown on Figure 9.
BAT
4
I
Translated Battery Voltage Input
(1)
2
DESCRIPTION
CE
5
I
Chip Enable. Internal LDO is disconnected from REGIN when driven low.
REGIN
6
P
Internal integrated LDO input. Decouple with a 0.1-µF ceramic capacitor to Vss.
REG25
7
P
2.5-V Output voltage of the internal integrated LDO. Decouple with 1-µF ceramic capacitor to Vss.
VSS
8
P
Device ground
SRP
9
I
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRP is nearest to the BAT– connection.
SRN
10
I
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRN is nearest to the PACK– connection.
P6/TS
11
I
P5/HDQ
12
I/O
Pack thermistor voltage sense (use 103AT-type thermistor)
P4/SCL
13
I
Slave I2C serial communication clock input. Use with a 10-K pull-up resistor (typical). Also used
for LED 4 in the four-LED mode.
P3/SDA
14
I/O
Open drain slave I2C serial communication data line. Use with a 10-kΩ pull-up resistor (typical).
Also used for LED 3 in the four-LED mode.
Open drain HDQ Serial communication line (slave)
I = Input, O = Output, P = Power, I/O = Digital input/output
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TYPICAL IMPLEMENTATION
**
I 2C
PROG
HDQ COMM
CE
BAT
REGIN
VEN
P1
REG25
P2
P6/TS
P3/DAT
SRP
P4/CLK
SRN
P5/HDQ
VSS
**
n Series Cells
PACK+
Sense
Resistor
ALERT
PACK–
** optional to reduce divider power consumption
Figure 2. bq34z110 Typical Implementation
THERMAL INFORMATION
bq34z110
THERMAL METRIC (1)
TSSOP (14-Pins)
θJA, High K
Junction-to-ambient thermal resistance
103.8
θJC(top)
Junction-to-case(top) thermal resistance
31.9
θJB
Junction-to-board thermal resistance
46.6
ψJT
Junction-to-top characterization parameter
2.0
ψJB
Junction-to-board characterization parameter
45.9
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
VALUE
PARAMETER
MIN
UNIT
MAX
VREGIN
Regulator Input Range
–0.3
5.5
V
VCC
Supply Voltage Range
–0.3
2.75
V
VIOD
Open-drain I/O pins (SDA, SCL, HDQ)
–0.3
5.5
V
VBAT
Bat Input pin
–0.3
5.5
V
VI
Input Voltage range to all other pins (P1, P2, SRP, SRN)
–0.3
VCC + 0.3
V
1.5
kV
2
kV
Human-body model (HBM), BAT pin
ESD
Human-body model (HBM), all other pins
TA
Operating free-air temperature range
–40
85
°C
TF
Functional temperature range
–40
100
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25ºC, CLDO25 = 1 µF, and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
VREGIN
Supply Voltage
CREGIN
External input capacitor for internal
LDO between REGIN and VSS
CLDO25
External output capacitor for
internal LDO between VCC and
VSS
ICC
Normal operating-mode current
ISLP
MAX
UNIT
No operating restrictions
CONDITIONS
MIN
2.7
TYP
4.5
V
No FLASH writes
2.45
2.7
V
0.1
μF
1
μF
Gas Gauge in NORMAL mode,
ILOAD > Sleep Current
140
μA
SLEEP operating-mode current
Gas Gauge in SLEEP mode,
ILOAD < Sleep Current
64
μA
ISLP+
FULL SLEEP operating-mode
current
Gas Gauge in FULL SLEEP mode,
ILOAD < Sleep Current
19
μA
VOL
Output voltage, low (SCL, SDA,
HDQ)
IOL = 3 mA
VOH(PP)
Output voltage, high
IOH = –1 mA
VCC – 0.5
V
VOH(OD)
Output voltage, high (SDA, SCL,
HDQ)
External pull-up resistor connected to VCC
VCC – 0.5
V
Nominal capacitor values specified.
Recommend a 10% ceramic X5R type
capacitor located close to the device.
0.47
0.4
V
VIL
Input voltage, low
–0.3
0.6
V
VIH(OD)
Input voltage, high (SDA, SCL,
HDQ)
1.2
6
V
V
VA1
Input voltage range (TS)
VSS – 0.05
1
VA2
Input voltage range (BAT)
VSS – 0.125
5
V
VA3
Input voltage range (SRP, SRN)
VSS – 0.125
0.125
V
ILKG
Input leakage current (I/O pins)
tPUCD
Power-up communication delay
4
0.3
250
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μA
ms
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POWER-ON RESET
TA = –40°C to 85°C; Typical Values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going battery voltage input at REG25
VHYS
Power-on reset hysteresis
MIN
TYP
MAX
UNIT
2.05
2.20
2.31
V
45
115
185
mV
LDO REGULATOR
TA = 25°C, CLDO25 = 1 µF, VREGIN = 3.6 V (unless otherwise noted) (1)
PARAMETER
VREG25
ISHORT (2)
(1)
(2)
Regulator output
voltage
Short Circuit Current
Limit
TEST CONDITION
MIN
NOM
MAX
2.5
2.7
2.7 V ≤ VREGIN ≤ 4.5 V,
IOUT ≤ 16 mA
TA= –40°C to 85°C
2.3
2.45 V ≤ VREGIN < 2.7 V
(low battery), IOUT ≤ 3 mA
TA = –40°C to 85°C
2.3
VREG25 = 0 V
TA = –40°C to 85°C
UNIT
V
250
mA
LDO output current, I, is the sum of internal and external load currents.
Specified by design. Not production tested.
INTERNAL TEMPERATURE SENSOR CHARACTERISTICS
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
GTEMP
TEST CONDITIONS
MIN
Temperature sensor voltage gain
TYP
MAX
–2
UNIT
mV/°C
LOW-FREQUENCY OSCILLATOR
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
f(LOSC)
Operating frequency
f(LEIO)
Frequency error (1) (2)
t(LSXO)
(1)
(2)
Start-up time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.768
kHz
TA = 0°C to 60°C
–1.5%
0.25%
1.5%
TA = –20°C to 70°C
–2.5%
0.25%
2.5%
TA = –40°C to 85°C
–4%
0.25%
4%
(2)
μs
500
The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
The startup time is defined as the time it takes for the frequency error is measured from 32.768 kHz.
HIGH-FREQUENCY OSCILLATOR
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
f(OSC)
TEST CONDITIONS
t(SXO)
(1)
(2)
Frequency error (1)
TYP
MAX
8.389
TA = 0°C to 60°C
f(EIO)
MIN
Operating frequency
–2%
0.38%
MHz
2%
TA = –20°C to 70°C
–3%
0.38%
3%
TA = –40°C to 85°C
–4.5%
0.38%
4.5%
2.5
5
Start-up time (2)
UNIT
ms
The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
INTEGRATING ADC (COULOMB COUNTER) CHARACTERISTICS
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
V(SR)
tSR_CONV
TEST CONDITIONS
Input voltage range, V(SRN) and V(SRP)
V(SR) = V(SRN) – V(SRP)
Conversion time
Single conversion
Resolution
MIN
TYP
–0.125
MAX
UNIT
0.125
V
15
bits
1
14
s
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INTEGRATING ADC (COULOMB COUNTER) CHARACTERISTICS (continued)
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
VOS(SR)
Input offset
INL
Integral nonlinearity error
ZIN(SR)
Effective input resistance (1)
Ilkg(SR)
Input leakage current (1)
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.034
% FSR
10
±0.007
µV
2.5
MΩ
0.3
µA
Specified by design. Not tested in production.
ADC (TEMPERATURE AND CELL MEASUREMENT) CHARACTERISTICS
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
VIN(ADC)
Input voltage range
tADC_CON
Conversion time
V
Resolution
VOS(ADC)
Input offset
ZADC1
Input leakage current
TYP
14
MAX
UNIT
1
V
125
ms
15
bits
1
(1)
Effective input resistance (BAT) (1)
Ilkg(ADC)
MIN
0.05
Effective input resistance (TS)
ZADC2
(1)
TEST CONDITIONS
mV
8
bq34z110 not measuring cell voltage
MΩ
8
bq34z110 measuring cell voltage
MΩ
100
(1)
KΩ
0.3
µA
Specified by design. Not tested in production.
DATA FLASH MEMORY CHARACTERISTICS
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
tDR
ICCPROG
MIN
TYP
20,000
(1)
UNIT
Years
Cycles
Word programming time (1)
Flash-write supply current
MAX
10
Flash-programming write cycles (1)
tWORDPROG
(1)
TEST CONDITIONS
Data retention (1)
5
2
ms
10
mA
Specified by design. Not tested in production.
HDQ COMMUNICATION TIMING CHARACTERISTICS
TA = –40°C to 85°C, CREG = 0.47 μF, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
205
250
μs
50
μs
μs
t(CYCH)
Cycle time, host to bq34z110
190
t(CYCD)
Cycle time, bq34z110 to host
190
t(HW1)
Host sends 1 to bq34z110
0.5
t(DW1)
bq34z110 sends 1 to host
32
50
μs
t(HW0)
Host sends 0 to bq34z110
86
145
μs
t(DW0)
bq34z110 sends 0 to host
80
145
μs
t(RSPS)
Response time, bq34z110 to host
190
950
μs
t(B)
Break time
190
t(BR)
Break recovery time
40
t(RISE)
HDQ line rising time to logic 1 (1.2 V)
t(RST)
HDQ Reset
6
1.8
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μs
μs
950
ns
2.2
s
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1.2V
t(RISE)
t(BR)
t(B)
(b) HDQ line rise time
(a) Break and Break Recovery
t(DW1)
t(HW1)
t(DW0)
t(CYCD)
t(HW0)
t(CYCH)
(d) Gauge Transmitted Bit
(c) Host Transmitted Bit
1-bit
R/W
7-bit address
Break
8-bit data
t(RSPS)
(e) Gauge to Host Response
Figure 3. Timing Diagrams
I2C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS
TA = –40°C to 85°C, CREG = 0.47 μF, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
ns
300
ns
tr
SCL/SDA rise time
tf
SCL/SDA fall time
tw(H)
SCL pulse width (high)
600
ns
tw(L)
SCL pulse width (low)
1.3
μs
tsu(STA)
Setup for repeated start
600
ns
td(STA)
Start to first falling edge of SCL
600
ns
tsu(DAT)
Data setup time
100
ns
th(DAT)
Data hold time
0
ns
tsu(STOP)
Setup time for stop
600
ns
tBUF
Bus free time between stop and start
66
μs
fSCL
Clock frequency
400
tSU(STA)
tw(H)
tf
tw(L)
tr
kHz
t(BUF)
SCL
SDA
td(STA)
tsu(STOP)
tf
tr
th(DAT)
tsu(DAT)
REPEATED
START
STOP
START
Figure 4. I2C-Compatible Interface Timing Diagrams
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GENERAL DESCRIPTION
The bq34z110 accurately predicts the battery capacity and other operational characteristics of multiple
rechargeable cells blocks, which are voltage balanced when resting. It supports lead-acid chemistries. It can be
interrogated by a host processor to provide cell information, such as Remaining Capacity, Full Charge Capacity,
and Average Current.
Information is accessed through a series of commands, called Standard Commands. Further capabilities are
provided by the additional Extended Commands set. Both sets of commands, indicated by the general format
Command(), are used to read and write information contained within the bq34z110 device’s control and status
registers, as well as its data flash locations. Commands are sent from host to gauge using the bq34z110 serial
communications engines, HDQ, and I2C, and can be executed during application development, pack
manufacture, or end-equipment operation.
Cell information is stored in the bq34z110 in non-volatile flash memory. Many of these data flash locations are
accessible during application development and pack manufacture. They cannot, generally, be accessed directly
during end-equipment operation. Access to these locations is achieved by either use of the bq34z110 device’s
companion evaluation software, through individual commands, or through a sequence of data-flash-access
commands. To access a desired data flash location, the correct data flash subclass and offset must be known.
The bq34z110 provides 32 bytes of user-programmable data flash memory. This data space is accessed through
a data flash interface. For specifics on accessing the data flash, refer to DATA FLASH INTERFACE.
The key to the bq34z110 device’s high-accuracy gas gauging prediction is Texas Instrument’s proprietary
Impedance Track algorithm. This algorithm uses voltage measurements, characteristics, and properties to create
state-of-charge predictions that can achieve accuracy with as little as 1% error across a wide variety of operating
conditions.
The bq34z110 measures charge and discharge activity by monitoring the voltage across a small-value series
sense resistor connected in the low side of the battery circuit. When an application’s load is applied, cell
impedance is measured by comparing its Open Circuit Voltage (OCV) with its measured voltage under loading
conditions.
The bq34z110 can use an NTC thermistor (default is Semitec 103AT or Mitsubishi BN35-3H103FB-50) for
temperature measurement, or can also be configured to use its internal temperature sensor. The bq34z110 uses
temperature to monitor the battery-pack environment, which is used for fuel gauging and cell protection
functionality.
To minimize power consumption, the bq34z110 has three power modes: NORMAL, SLEEP, and FULL SLEEP.
The bq34z110 passes automatically between these modes, depending upon the occurrence of specific events.
Multiple modes are available for configuring from one to 16 LEDs as an indicator of remaining state of charge.
More than four LEDs require the use of one or two inexpensive SN74HC164 shift register expanders.
A SHA-1 or HMAC-based battery pack authentication feature is also implemented on the bq34z110. When the IC
is in UNSEALED mode, authentication keys can be (re)assigned. Alternatively, keys can also be programmed
permanently in secure memory by Texas Instruments. A scratch pad area is used to receive challenge
information from a host and to export SHA-1/HMAC encrypted responses. See the AUTHENTICATION section
for further details.
NOTE
Formatting conventions in this document:
Commands: italic with parentheses and no breaking spaces, e.g. RemainingCapacity().
Data Flash: italic, bold, and breaking spaces, e.g. Design Capacity.
Register Bits and Flags: brackets only, e.g. [TDA] Data
Flash Bits: italic and bold, e.g. [LED1]
Modes and states: ALL CAPITALS, e.g. UNSEALED mode.
8
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DATA COMMANDS
STANDARD DATA COMMANDS
The bq34z110 uses a series of 2-byte standard commands to enable host reading and writing of battery
information. Each standard command has an associated command-code pair, as indicated in Table 2. Because
each command consists of two bytes of data, two consecutive HDQ or I2C transmissions must be executed both
to initiate the command function and to read or write the corresponding two bytes of data. Standard commands
are accessible in NORMAL operation. Also, two block commands are available to read Manufacturer Name and
Device Chemistry. Read and Write permissions depend on the active access mode.
Table 2. Standard Commands
NAME
COMMAND CODE
UNITS
SEALED ACCESS
UNSEALED
ACCESS
Control()
CNTL
0x00/0x01
N/A
R/W
R/W
StateOfCharge()
SOC
0x02/0x03
%
R
R
RemainingCapacity()
RM
0x04/0x05
mAh
R
R
FullChargeCapacity()
FCC
0x06/0x07
mAh
R
R
Voltage()
VOLT
0x08/0x09
mV
R
R
AverageCurrent()
AI
0x0a/0x0b
mA
R
R
Temperature()
TEMP
0x0c/0x0d
0.1ºK
R
R
Flags()
FLAGS
0x0e/0x0f
N/A
R
R
Mfr Date
DATE
0x6B/0x6c
N/A
R
R
Mfr Name Length
NAMEL
0x6d
N/A
R
R
Mfr Name
NAME
0x6e–0x78
N/A
R
R
Device Chemistry
Length
CHEML
0x79
N/A
R
R
Device Chemistry
CHEM
0x7a–0x7d
N/A
R
R
Serial Number
SERNUM
0x7e/0x7f
N/A
R
R
Control(): 0x00/0x01
Issuing a Control() command requires a subsequent two-byte sub-command. These additional bytes specify the
particular control function desired. The Control() command allows the host to control specific features of the
bq34z110 during normal operation, and additional features when the bq34z110 is in different access modes, as
described in Table 3.
Table 3. Control() Subcommands
CNTL FUNCTION
CNTL DATA
SEALED ACCESS
DESCRIPTION
CONTROL_STATUS
0x0000
Yes
Reports the status of DF Checksum, IT, for example.
DEVICE_TYPE
0x0001
Yes
Reports the device type of 0x0541 (indicating
bq34z110)
FW_VERSION
0x0002
Yes
Reports the firmware version on the device type
HW_VERSION
0x0003
Yes
Reports the hardware version of the device type
RESET_DATA
0x0005
No
Returns reset data
PREV_MACWRITE
0x0007
No
Returns previous MAC command code
CHEM_ID
0x0008
Yes
Reports the chemical identifier of the Impedance Track
configuration
BOARD_OFFSET
0x0009
No
Forces the device to measure and store the board offset
CC_OFFSET
0x000A
No
Forces the device to measure the internal CC offset
CC_OFFSET_SAVE
0x000B
No
Forces the device to store the internal CC offset
DF_VERSION
0x000C
Yes
Reports the data flash version on the device
SET_FULLSLEEP
0x0010
No
Sets the [FULLSLEEP] bit in the control register to 1
STATIC_CHEM_CHKSUM
0x0017
Yes
Calculates chemistry checksum
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Table 3. Control() Subcommands (continued)
CNTL FUNCTION
CURRENT
CNTL DATA
SEALED ACCESS
DESCRIPTION
0x0018
Yes
Returns the instantaneous current measured by the
gauge
SEALED
0x0020
No
Places the device in SEALED access mode
IT_ENABLE
0x0021
No
Enables the Impedance Track algorithm
CAL_ENABLE
0x002D
No
Toggles calibration mode
RESET
0x0041
No
Forces a full reset of the bq34z110
EXIT_CAL
0x0080
No
Exits calibration mode
ENTER_CAL
0x0081
No
Enters calibration mode
OFFSET_CAL
0x0082
No
Reports internal CC offset in calibration mode
CONTROL_STATUS: 0x0000
Instructs the fuel gauge to return status information to Control addresses 0x00/0x01. The status word includes
the following information.
Table 4. CONTROL_STATUS Flags
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
High Byte
—
FAS
SS
CALMODE
CCA
BCA
CSV
Bit 0
—
Low Byte
—
—
FULLSLEEP
SLEEP
LDMD
RUP_DIS
VOK
QEN
FAS: Status bit that indicates the bq34z110 is in FULL ACCESS SEALED state. Active when set.
SS: Status bit that indicates the bq34z110 is in the SEALED State. Active when set.
CSV: Status bit that indicates a valid data flash checksum has been generated. Active when set.
CALMODE: Status bit that indicates the bq34z110 calibration function is active. True when set.
Default is 0.
CCA: Status bit that indicates the bq34z110 Coulomb Counter Calibration routine is active. Active
when set.
BCA: Status bit that indicates the bq34z110 Board Calibration routine is active. Active when set.
FULLSLEEP: Status bit that indicates the bq34z110 is in FULLSLEEP mode. True when set. The state
can only be detected by monitoring the power used by the bq34z110 because any
communication will automatically clear it.
SLEEP: Status bit that indicates the bq34z110 is in SLEEP mode. True when set.
LDMD: Status bit that indicates the bq34z110 Impedance Track algorithm using constant-power
mode. True when set. Default is 0 (constant-current mode).
RUP_DIS: Status bit that indicates the bq34z110 Ra table updates are disabled. True when set.
VOK: Status bit that indicates cell voltages are OK for Qmax updates. True when set.
QEN: Status bit that indicates the bq34z110 Qmax updates are enabled. True when set.
DEVICE TYPE: 0x0001
Instructs the fuel gauge to return the device type to addresses 0x00/0x01.
FW_VERSION: 0x0002
Instructs the fuel gauge to return the firmware version to addresses 0x00/0x01.
HW_VERSION: 0x0003
Instructs the fuel gauge to return the hardware version to addresses 0x00/0x01.
10
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RESET_DATA: 0x0005
Instructs the fuel gauge to return the number of resets performed to addresses 0x00/0x01.
PREV_MACWRITE: 0x0007
Instructs the fuel gauge to return the previous command written to addresses 0x00/0x01. The value returned is
limited to less than 0x0020.
CHEM ID: 0x0008
Instructs the fuel gauge to return the chemical identifier for the Impedance Track configuration to addresses
0x00/0x01.
BOARD_OFFSET: 0x0009
Instructs the fuel gauge to calibrate board offset. During board offset calibration the [BCA] bit is set.
CC_OFFSET: 0x000A
Instructs the fuel gauge to calibrate the coulomb counter offset. During calibration the [CCA] bit is set.
CC_OFFSET_SAVE: 0x000B
Instructs the fuel gauge to save calibrate the coulomb counter offset after calibration.
DF_VERSION: 0x000C
Instructs the fuel gauge to return the data flash version to addresses 0x00/0x01.
SET_FULLSLEEP: 0x0010
Instructs the fuel gauge to set the FULLSLEEP bit in Control Status register to 1. This allows the gauge to enter
the FULLSLEEP power mode after the transition to SLEEP power state is detected. In FULLSLEEP mode less
power is consumed by disabling an oscillator circuit used by the communication engines. For HDQ
communication one host message will be dropped. For I2C communications, the first I2C message will incur a 6
ms–8 ms clock stretch while the oscillator is started and stabilized. A communication to the device in
FULLSLEEP will force the part back to the SLEEP mode.
STATIC_CHEM_DF_CHKSUM: 0x0017
Instructs the fuel gauge to calculate chemistry checksum as a 16-bit unsigned integer sum of all static chemistry
data. The most significant bit (MSB) of the checksum is masked yielding a 15-bit checksum. This checksum is
compared with the value stored in the data flash Static Chem DF Checksum. If the value matches, the MSB is
cleared to indicate pass. If it does not match, the MSB is set to indicate failure.
SEALED: 0x0020
Instructs the fuel gauge to transition from UNSEALED state to SEALED state. The fuel gauge should always be
set to SEALED state for use in customer’s end equipment.
IT ENABLE: 0x0021
Forces the fuel gauge to begin the Impedance Track algorithm, sets bit 2 of UpdateStatus and causes the [VOK]
and [QEN] flags to be set in the CONTROL STATUS register. [VOK] is cleared if the voltages are not suitable for
a Qmax update. Once set, [QEN] cannot be cleared. This command is only available when the fuel gauge is
UNSEALED and is typically enabled at the last step of production after system test is completed.
RESET: 0x0041
Instructs the fuel gauge to perform a full reset. This command is only available when the fuel gauge is
UNSEALED.
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EXIT_CAL: 0x0080
Instructs the fuel gauge to exit calibration mode.
ENTER_CAL: 0x0081
Instructs the fuel gauge to enter calibration mode.
OFFSET_CAL: 0x0082
Instructs the fuel gauge to perform offset calibration.
StateOfCharge(): 0x02 and 0x03
This read-only function returns an unsigned integer value of the predicted remaining battery capacity expressed
as a percentage of FullChargeCapacity(), with a range of 0 to 100%.
RemainingCapacity(): 0x04 and 0x05
This read-only command pair returns the compensated battery capacity remaining. Units are 1 mAh per bit.
FullChargeCapacity(): 0x06 and 07
This read-only command pair returns the compensated capacity of the battery when fully charged. Units are 1
mAh per bit except if X10 mode is selected. In X10 mode, units are 10 mAh per bit. FullChargeCapacity() is
updated at regular intervals, as specified by the Impedance Track algorithm.
Voltage(): 0x08 and 0x09
This read-word function returns an unsigned integer value of the measured cell-pack voltage in mV with a range
of 0 V to 65535 mV.
AverageCurrent(): 0x0a and 0x0b
This read-only command pair returns a signed integer value that is the average current flow through the sense
resistor. It is updated every 1 second. Units are 1 mA per bit except if X10 mode is selected. In X10 mode, units
are 10 mA per bit.
Temperature(): 0x0c and 0x0d
This read-word function returns an unsigned integer value of the temperature in units of 0.1ºK measured by the
gas gauge and has a range of 0 to 6553.5 ºK. The source of the measured temperature is configured by the
[TEMPS] bit in the Pack Configuration register (see EXTENDED DATA COMMANDS).
Table 5. Temperature Sensor Selection
TEMPS
Temperature() Source
0
Internal Temperature Sensor
1
TS Input (default)
Flags(): 0x0e/0x0f
This read-word function returns the contents of the gas-gauge status register, depicting current operation status.
Table 6. Flags Bit Definitions
12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High Byte
OTC
OTD
BATHIGH
BATLOW
CHG_INH
RSVD
FC
CHG
Low Byte
OCVTAKEN
ISD
TDD
RSVD
RSVD
SOC1
SOCF
DSG
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OTC: Over-Temperature in Charge condition is detected. True when set. OTD = Over-Temperature
in Discharge condition is detected. True when set.
BATHIGH: Battery High bit that indicates a high battery voltage condition. Refer to the data flash
BATTERY HIGH parameters for threshold settings.
BATLOW: Battery Low bit that indicates a low battery voltage condition. Refer to the data flash
BATTERY LOW parameters for threshold settings.
CHG_INH: Charge Inhibit: unable to begin charging [Charge Inhibit Temp Low, Charge Inhibit Temp
High]. True when set.
RSVD: Reserved.
FC: Full-charge is detected. FC is set when charge termination is reached and FC Set% = –1
(see CHARGING AND CHARGE TERMINATION INDICATION for details) or State of Charge
is larger than FC SET% and FC Set% is not –1. True when set.
CHG: (Fast) charging allowed. True when set.
OCVTAKEN: Cleared on entry to relax mode and set to 1 when OCV measurement is performed in relax
mode.
ISD: Internal Short is detected. True when set. TDD = Tab Disconnect is detected. True when set.
SOC1: State-of-Charge Threshold 1 reached. True when set.
SOCF: State-of-Charge Threshold Final reached. True when set.
DSG: Discharging detected. True when set.
DATA FLASH INTERFACE
ACCESSING DATA FLASH
The bq34z110 data flash is a non-volatile memory that contains bq34z110 initialization, default, cell status,
calibration, configuration, and user information. The data flash can be accessed in several different ways,
depending on what mode the bq34z110 is operating in and what data is being accessed.
Commonly accessed data flash memory locations, frequently read by a host, are conveniently accessed through
specific instructions (described in DATA COMMANDS). These commands are available when the bq34z110 is
either in UNSEALED or SEALED modes.
Most data flash locations, however, can only accessible in UNSEALED mode by use of the bq34z110 evaluation
software or by data flash block transfers. These locations should be optimized and/or fixed during the
development and manufacture processes. They become part of a Golden Image File and can then be written to
multiple battery packs. Once established, the values generally remain unchanged during end-equipment
operation.
To access data flash locations individually, the block containing the desired data flash location(s) must be
transferred to the command register locations, where they can be read to the host or changed directly. This is
accomplished by sending the set-up command BlockDataControl() (code 0x61) with data 0x00. Up to 32 bytes of
data can be read directly from the BlockData() command locations 0x40…0x5f, externally altered, then re-written
to the BlockData() command space. Alternatively, specific locations can be read, altered, and re-written if their
corresponding offsets are used to index into the BlockData() command space. Finally, the data residing in the
command space is transferred to data flash, once the correct checksum for the whole block is written to
BlockDataChecksum() (command number 0x60).
Occasionally, a data flash CLASS will be larger than the 32-byte block size. In this case, the DataFlashBlock()
command is used to designate which 32-byte block the desired locations reside in. The correct command
address is then given by 0x40 + offset modulo 32. For example, to access Terminate Voltage in the Gas
Gauging class, DataFlashClass() is issued 80 (0x50) to set the class. Because the offset is 48, it must reside in
the second 32-byte block. Hence, DataFlashBlock() is issued 0x01 to set the block offset, and the offset used to
index into the BlockData() memory area is 0x40 + 48 modulo 32 = 0x40 + 16 = 0x40 + 0X10 = 0x50.
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Reading and writing subclass data are block operations 32 bytes in length. Data can be written in shorter block
sizes, however. Blocks can be shorter than 32 bytes in length. Writing these blocks back to data flash does not
overwrite data that extend beyond the actual block length.
None of the data written to memory are bounded by the bq34z110—the values are not rejected by the gas
gauge. Writing an incorrect value may result in hardware failure due to firmware program interpretation of the
invalid data. The data written is persistent, so a Power-On Reset does resolve the fault.
MANUFACTURER INFORMATION BLOCK
The bq34z110 contains 32 bytes of user programmable data flash storage: Manufacturer Info Block. The
method for accessing these memory locations is slightly different, depending on whether the device is in
UNSEALED or SEALED modes.
When in UNSEALED mode and when and 0x00 has been written to BlockDataControl(), accessing the
Manufacturer Info Block is identical to accessing general data flash locations. First, a DataFlashClass() command
is used to set the subclass, then a DataFlashBlock() command sets the offset for the first data flash address
within the subclass. The BlockData() command codes contain the referenced data flash data. When writing the
data flash, a checksum is expected to be received by BlockDataChecksum(). Only when the checksum is
received and verified is the data actually written to data flash.
As an example, the data flash location for Manufacturer Info Block is defined as having a Subclass = 58 and an
Offset = 0 through 31 (32 byte block). The specification of Class = System Data is not needed to address
Manufacturer Info Block, but is used instead for grouping purposes when viewing data flash info in the bq34z110
evaluation software.
When in SEALED mode or when 0x01 BlockDataControl() does not contain 0x00, data flash is no longer
available in the manner used in UNSEALED mode. Rather than issuing subclass information, a designated
Manufacturer Information Block is selected with the DataFlashBlock() command. Issuing a 0x01, 0x02, or 0x03
with this command causes the corresponding information block (A, B, or C, respectively) to be transferred to the
command space 0x40…0x5f for editing or reading by the host. Upon successful writing of checksum information
to BlockDataChecksum(), the modified block is returned to data flash.
NOTE
Manufacturer Info Block A is “read only” when in SEALED mode.
ACCESS MODES
The bq34z110 provides three security modes which control data flash access permissions according to Table 7.
Public Access refers to those data flash locations, specified in Table 20 that are accessible to the user. Private
Access refers to reserved data flash locations used by the bq34z110 system. Care should be taken to avoid
writing to Private data flash locations when performing block writes in Full Access mode by following the method
outlined in ACCESSING DATA FLASH.
Table 7. Data Flash Access
14
Security Mode
DF: Public Access
BOOTROM
N/A
N/A
FULL ACCESS
R/W
R/W
UNSEALED
R/W
R/W
SEALED
R
N/A
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Although FULL ACCESS and UNSEALED modes appear identical, FULL ACCESS mode allows the bq34z110 to
directly transition to BOOTROM mode and also write access keys. The UNSEALED mode lacks these abilities.
SEALING AND UNSEALING DATA FLASH ACCESS
The bq34z110 implements a key-access scheme to transition between SEALED, UNSEALED, and FULLACCESS modes. Each transition requires that a unique set of two keys be sent to the bq34z110 via the Control()
command (these keys are unrelated to the keys used for SHA-1/HMAC authentication). The keys must be sent
consecutively, with no other data being written to the Control() register in between. Note that to avoid conflict, the
keys must be different from the codes presented in the CNTL DATA column of Table 3 subcommands.
When in SEALED mode the [SS] bit of Control Status() is set, but when the UNSEAL keys are correctly received
by the bq34z110, the [SS] bit is cleared. When the full access keys are correctly received then the Flags() [FAS]
bit is cleared.
Both the sets of keys for each level are 2 bytes each in length and are stored in data flash. The UNSEAL key
(stored at Unseal Key 0 and Unseal Key 1) and the FULL-ACCESS key (stored at Full Access Key 0 and Full
Access Key 1) can only be updated when in FULL-ACCESS mode. The order of the bytes entered through the
Control() command is the reverse of what is read from the part. For example, if the 1st and 2nd word of the
UnSeal Key 0 returns 0x1234 and 0x5678, then Control() should supply 0x3412 and 0x7856 to unseal the part.
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FUNCTIONAL DESCRIPTION
FUEL GAUGING
The bq34z110 measures the cell voltage, temperature, and current to determine the battery SOC based in the
Impedance Track algorithm (refer to the Theory and Implementation of Impedance Track Battery Fuel-Gauging
Algorithm application report [SLUA450] for more information). The bq34z110 monitors charge and discharge
activity by sensing the voltage across a small-value resistor (5 mΩ to 20 mΩ typ.) between the SRP and SRN
pins and in-series with the cell. By integrating charge passing through the battery, the cell’s SOC is adjusted
during battery charge or discharge.
The total battery capacity is found by comparing states of charge before and after applying the load with the
amount of charge passed. When an application load is applied, the impedance of the cell is measured by
comparing the OCV obtained from a predefined function for present SOC with the measured voltage under load.
Measurements of OCV and charge integration determine chemical state of charge and Chemical Capacity
(Qmax). The initial Qmax value is taken from a cell manufacturers' data sheet multiplied by the number of parallel
cells. The parallel value is also used for the value programmed in Design Capacity. The bq34z110 acquires and
updates the battery-impedance profile during normal battery usage. It uses this profile, along with SOC and the
Qmax value, to determine FullChargeCapacity() and StateOfCharge(), specifically for the present load and
temperature. FullChargeCapacity() is reported as capacity available from a fully charged battery under the
present load and temperature until Voltage() reaches the Terminate Voltage. NominalAvailableCapacity() and
FullAvailableCapacity() are the uncompensated (no or light load) versions of RemainingCapacity() and
FullChargeCapacity(), respectively.
The bq34z110 has two flags accessed by the Flags() function that warns when the battery’s SOC has fallen to
critical levels. When RemainingCapacity() falls below the first capacity threshold, specified in SOC1 Set
Threshold, the [SOC1] (State of Charge Initial) flag is set. The flag is cleared once RemainingCapacity() rises
above SOC1 Clear Threshold. All units are in mAh.
When RemainingCapacity() falls below the second capacity threshold, SOCF Set Threshold, the [SOCF] (State
of Charge Final) flag is set, serving as a final discharge warning. If SOCF Set Threshold = –1, the flag is
inoperative during discharge. Similarly, when RemainingCapacity() rises above SOCF Clear Threshold and the
[SOCF] flag has already been set, the [SOCF] flag is cleared. All units are in mAh.
The bq34z110 has two additional flags accessed by the Flags() function that warn of internal battery conditions.
The fuel gauge monitors the cell voltage during relaxed conditions to determine if an internal short has been
detected When this condition occurs, [ISD] will be set. The bq34z110 also has the capability of detecting when a
tab has been disconnected in a 2-cell parallel system by actively monitoring the state of health. When this
condition occurs, [TDD] is set.
Lead-Acid gauging in the charge direction makes use of four Charge Efficiency factors to correct for energy lost
due to heat. Lead-Acid charge efficiency is not linear throughout the charging process, as it drops with increasing
state of charge.
IMPEDANCE TRACK VARIABLES
The bq34z110 has several data flash variables that permit the user to customize the Impedance Track algorithm
for optimized performance. These variables are dependent upon the power characteristics of the application as
well as the cell itself.
Load Mode
Load Mode is used to select either the constant current or constant power model for the Impedance Track
algorithm as used in Load Select. See the Load Select section. When Load Mode is 0, the Constant Current
Model is used (default). When Load Mode is 1, the Constant Power Model is used. The [LDMD] bit of
CONTROL_STATUS reflects the status of Load Mode.
Load Select
Load Select defines the type of power or current model to be used to compute load-compensated capacity in the
Impedance Track algorithm. If Load Mode = 0 (Constant Current) then the options presented in Table 8 are
available.
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Table 8. Current Model Used when Load Mode = 0
Load Select Value
Current Model Used
Average discharge current from previous cycle: There is an internal register that records the average
discharge current through each entire discharge cycle. The previous average is stored in this register.
0
Present average discharge current: This is the average discharge current from the beginning of this
discharge cycle until present time.
1 (default)
2
Average Current: based on the AverageCurrent()
3
Current: based on a low-pass-filtered version of AverageCurrent() (τ=14s)
4
Design Capacity / 5: C Rate based off of Design Capacity /5 or a C / 5 rate in mA.
5
Use the value specified by AtRate()
6
Use the value in User_Rate-mA: This gives a completely user configurable method.
If Load Mode = 1 (Constant Power) then the following options are available:
Table 9. Constant-Power Model Used when Load Mode = 1
Load Select Value
Power Model Used
Average discharge power from previous cycle: There is an internal register that records the average
discharge power through each entire discharge cycle. The previous average is stored in this register.
0 (default)
1
Present average discharge power: This is the average discharge power from the beginning of this discharge
cycle until present time.
2
Average Current × Voltage: based off the AverageCurrent() and Voltage().
3
Current × Voltage: based on a low-pass-filtered version of AverageCurrent() (τ=14s) and Voltage()
4
Design Energy / 5: C Rate based off of Design Energy /5 or a C / 5 rate in mA .
5
Use whatever value specified by AtRate().
6
Use the value in User_Rate-mW/cW. This gives a completely user-configurable method.
Reserve Cap-mAh
Reserve Cap-mAh determines how much actual remaining capacity exists after reaching 0
RemainingCapacity(), before Terminate Voltage is reached. A loaded rate or no-load rate of compensation can
be selected for Reserve Cap by setting the [RESCAP] bit in the Pack Configuration register.
Reserve Cap-mWh/cWh
Reserve Cap-mWh determines how much actual remaining capacity exists after reaching 0 AvailableEnergy(),
before Terminate Voltage is reached. A loaded rate or no-load rate of compensation can be selected for
Reserve Cap by setting the [RESCAP] bit in the Pack Configuration register.
Design Energy Scale
Design Energy Scale is used to select the scale/unit of a set of data flash parameters. The value of Design
Energy Scale can be either 1 or 10 only.
When using Design Energy Scale = 10, the value for each of the parameters in Table 10 must be adjusted to
reflect the new units. See X10 MODE.
Table 10. Data Flash Parameter Scale/Unit-Based on Design Energy Scale
Data Flash Parameter
Design Energy Scale = 1 (default)
Design Energy Scale = 10
Design Energy
mWh
cWh
Reserve Energy-mWh/cWh
mWh
cWh
Avg Power Last Run
mW
cW
User Rate-mW/cW
mWh
cWh
T Rise
No Scale
Scaled by X10
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Dsg Current Threshold
This register is used as a threshold by many functions in the bq34z110 to determine if actual discharge current is
flowing into or out of the cell. The default for this register should be sufficient for most applications. This threshold
should be set low enough to be below any normal application load current but high enough to prevent noise or
drift from affecting the measurement.
Chg Current Threshold
This register is used as a threshold by many functions in the bq34z110 to determine if actual charge current is
flowing into or out of the cell. The default for this register should be sufficient for most applications. This threshold
should be set low enough to be below any normal charge current but high enough to prevent noise or drift from
affecting the measurement.
Quit Current, Dsg Relax Time, Chg Relax Time, and Quit Relax Time
The Quit Current is used as part of the Impedance Track algorithm to determine when the bq34z110 enters
relaxation mode from a current flowing mode in either the charge direction or the discharge direction. The value
of Quit Current is set to a default value that should be above the standby current of the host system.
Either of the following criteria must be met to enter relaxation mode:
1. |AverageCurrent()| < |Quit Current| for Dsg Relax Time.
2. |AverageCurrent()| > |Quit Current| for Chg Relax Time.
After about 6 minutes in relaxation mode, the bq34z110 attempts to take accurate OCV readings. An
additional requirement of dV/dt < 4 μV/s is required for the bq34z110 to perform Qmax updates. These
updates are used in the Impedance Track algorithms. It is critical that the battery voltage be relaxed during
OCV readings to and that the current is not higher than C/20 when attempting to go into relaxation mode.
Quit Relax Time specifies the minimum time required for AverageCurrent() to remain above the QuitCurrent
threshold before exiting relaxation mode.
Qmax
Qmax Cell 0 contains the maximum chemical capacity of the cell and is determined by comparing states of
charge before and after applying the load with the amount of charge passed. It also corresponds to capacity at
low rate of discharge such as C/20 rate. For high accuracy, this value is periodically updated by the bq34z110
during operation.
Based on the battery cell capacity information, the initial value of chemical capacity should be entered in the
Qmax Cell 0 data flash parameter. The Impedance Track algorithm will update this value and maintain it
internally in the gauge.
Update Status
The Update Status register indicates the status of the Impedance Track algorithm.
Table 11. Update Status Definitions
Update Status
18
Status
0x02
Qmax and Ra data are learned, but Impedance Track is not enabled. This should be the standard
setting for a Golden Image File.
0x04
Impedance Track is enabled but Qmax and Ra data are not yet learned.
0x05
Impedance Track is enabled and only Qmax has been updated during a learning cycle.
0x06
Impedance Track is enabled. Qmax and Ra data are learned after a successful learning cycle. This
should be the operation setting for end equipment.
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This register should only be updated by the bq34z110 during a learning cycle or when IT_ENABLE()
subcommand is received. Refer to STEP 8: Run an Optimization Cycle.
Avg I Last Run
The bq34z110 logs the current averaged from the beginning to the end of each discharge cycle. It stores this
average current from the previous discharge cycle in this register. This register should never need to be
modified. It is only updated by the bq34z110 when required.
Avg P Last Run
The bq34z110 logs the power averaged from the beginning to the end of each discharge cycle. It stores this
average power from the previous discharge cycle in this register. To get a correct average power reading the
bq34z110 continuously multiplies instantaneous current times Voltage() to get power. It then logs this data to
derive the average power. This register should never need to be modified. It is only updated by the bq34z110
when the required.
Delta Voltage
The bq34z110 stores the maximum difference of Voltage() during short load spikes and normal load, so the
Impedance Track algorithm can calculate remaining capacity for pulsed loads. It is not recommended to change
this value.
The Ra Tables
This data is automatically updated during device operation. No user changes should be made except for reading
the values from another pre-learned pack for creating Golden Image Files. Profiles have format Cell0 R_a M,
where M is the number that indicates the state of charge to which the value corresponds.
CHARGE EFFICIENCY
Tracking State of Charge during the charge phase is relatively easy with modern chemistries such as LithiumIon, where essentially none of the applied energy from the charger is lost to heat. However, lead-acid chemistries
may demonstrate significant losses to heat during charging. Therefore, to more accurately track state of charge
and Time-to-Full during the charge phase, the bq34z110 uses four charge-efficiency factors to compensate for
charge acceptance. These factors are Charge Efficiency, Charge Efficiency Reduction Rate, Charge
Efficiency Drop Off, and Charge Efficiency Temperature Compensation.
The bq34z110 applies the Charge Efficiency, when RelativeStateOfCharge() is less than the value coded in
Charge Efficiency Drop Off. When RelativeStateOfCharge() is greater than or equal to the value coded in
Charge Efficiency Drop Off, Charge Efficiency and Charge Efficiency Reduction Rate determine the charge
efficiency rate. Charge Efficiency Reduction Rate defines the percent efficiency reduction per percentage point
of RelativeStateOfCharge() over Charge Efficiency Drop Off. Note that the Charge Efficiency Reduction Rate
has units of 0.1%.
The bq34z110 also adjusts the efficiency factors for temperature. Charge Efficiency Temperature
Compensation defines the percent efficiency reduction per degree C over 25°C. Note that Charge Efficiency
Temperature Compensation has units of 0.01%.
Applying the four factors:
Effective Charge Efficiency % = Charge Efficiency – Charge Efficiency Reduction Rate [RSOC() – Charge
Efficiency Drop Off] - Charge Efficiency Temperature Compensation [Temperature – 25°C]
Where:
RSOC() ≥ Charge Efficiency and Temperature ≥ 25°C
PACK CONFIGURATION REGISTER
Some bq34z110 pins are configured via the Pack Configuration data flash register, as indicated in Table 12.
This register is programmed/read via the methods described in ACCESSING DATA FLASH. The register is
located at subclass = 64, offset = 0.
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Table 12. Pack Configuration Register Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High Byte
RESCAP
CALEN
RSVD
RSVD
VOLTSEL
IWAKE
RSNS1
RSNS0
Low Byte
X10
RESFACTSTEP
SLEEP
RMFCC
RSVD
RSVD
RSVD
TEMPS
RESCAP: No-load rate of compensation is applied to the reserve capacity calculation.
True when set. Default is 0.
CALEN: When enabled, entering calibration mode is permitted. For special use only.
Default = 0.
RSVD: Reserved. Default = 0.
VOLTSEL: This bit selects between use of internal or external battery voltage divider. The
internal divider is for single cell use only. 1 = external. 0 = internal. Default is 0.
IWAKE/RSNS1/RSNS0: These bits configure the current wake function (see Table 16). Default is 0/0/1.
X10: X10 Capacity and/or Current bit. The mA, mAh, and cWh settings and reports
will take on a value of ten times normal. This setting has no actual effect within
the gauge. It is the responsibility of the host to reinterpret the reported values.
X10 current measurement is achieved by calibrating the current measurement
to a value X10 lower than actual.
RESFACTSTEP: Enables Ra step up/down to Max/Min Res Factor before disabling Ra updates.
Default is 1.
SLEEP: The fuel gauge can enter sleep, if operating conditions allow. True when set.
Default is 1.
RMFCC: RM is updated with the value from FCC, on valid charge termination. True
when set. Default is 1.
RSVD: Reserved. Do not use.
TEMPS: Selects external thermistor for Temperature() measurements. True when set.
Uses internal temp when clear. Default is 1
TEMPERATURE MEASUREMENT
The bq34z110 can measure temperature via the on-chip temperature sensor or via the TS input depending on
the setting of the [TEMPS] bit PackConfiguration(). The bit is set by using the PackConfiguration() function,
described in EXTENDED DATA COMMANDS.
Temperature measurements are made by calling the Temperature() function (see STANDARD DATA
COMMANDS for specific information).
When an external thermistor is used, REG25 (pin 7) is used to bias the thermistor and TS (pin 11) is used to
measure the thermistor voltage (a pull-down circuit is implemented inside the bq34z110). The bq34z110 then
correlates the voltage to temperature, assuming the thermistor is a Semitec 103AT or similar device.
OVERTEMPERATURE INDICATION
Overtemperature: Charge
If during charging, Temperature() reaches the threshold of DF:OT Chg for a period of OT Chg Time and
AverageCurrent() > Chg Current Threshold, then the [OTC] bit of Flags() is set. Note: if OT Chg Time = 0 then
feature is completely disabled.
When Temperature() falls to OT Chg Recovery, the [OTC] of Flags() is reset.
Overtemperature: Discharge
If, during discharging, Temperature() reaches the threshold of OT Dsg for a period of OT Dsg Time, and
AverageCurrent() ≤ –Dsg Current Threshold, then the [OTD] bit of Flags() is set.
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NOTE
If OT Dsg Time = 0, then the feature is completely disabled.
When Temperature() falls to OT Dsg Recovery, the [OTD] bit of Flags() is reset.
CHARGING AND CHARGE TERMINATION INDICATION
For proper bq34z110 operation, the battery charging voltage must be specified by the user. The default value for
this variable is Charging Voltage = 4200 mV. This parameter should be set to the recommended charging
voltage for the entire battery stack.
The bq34z110 detects charge termination when (1) during two consecutive periods of Current Taper Window, the
AverageCurrent() is < Taper Current and (2) during the same periods, the accumulated change in capacity >
0.25 mAh /Taper Current Window and (3) Voltage() > Charging Voltage - Charging Taper Voltage. When this
occurs, the [CHG] bit of Flags() is cleared. Also, if the [RMFCC] bit of Pack Configuration is set, and
RemainingCapacity() is set equal to FullChargeCapacity().
X10 MODE
The bq34z110 supports high current and high capacity batteries above 32.76 Amperes and 32.76 Ampere-Hours
by switching to a times-ten mode where currents and capacities are internally handled correctly, but various
reported units and configuration quantities are rescaled to tens of milliamps and tens of milliamp-hours. The need
for this is due to the standardization of a two byte data command having a maximum representation of ±32767.
When the X10 bit (Bit 7) is set in the Pack Configuration register, all of the mAh, cWh, and mWh settings will take
on a value of ten times normal. When this bit is set, the actual units for all capacity and energy parameters will
be 10 mAh or Wh. This includes reporting of Remaining Capacity. This bit will also be used to rescale the current
reporting to 10 times normal, up to ±327 A. The actual resolution then becomes 10 mA.
It is important to know that setting the X10 flag does not actually change anything in the operation of the gauge.
It serves as a notice to the host that the various reported values should be reinterpreted ten times higher. X10
Current measurement is achieved by calibrating the current gain to a value X10 lower than actually applied.
Because the flag has no actual effect, it can be used to represent other scaling values. See Design Energy
Scale.
REMAINING STATE OF CHARGE LED INDICATION
The bq34z110 supports multiple options for using one to sixteen LEDs as an output device to display the
remaining state of charge. The LED/Comm Configuration register determines the behavior.
Table 13. LED/COMM Configuration Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XLED3
XLED2
XLED1
XLED0
LEDON
Mode2
Mode1
Mode0
Bits 0, 1, 2 are a code for one of five modes. 0 = No LED, 1 = Single LED, 2 = Four LEDs, 3 = External LEDs
with I2C comm, 4 = External LEDs with HDQ comm.
Setting Bit 3, LEDON, will cause the LED display to be always on, except in Single LED mode. When clear
(default), the LED pattern will only be displayed after holding an LED display button for one to two seconds. The
button applies 2.5 V from REG25 pin 7 to VEN pin 2 (refer to ). The LED Hold Time parameter may be used to
configure how long the LED display remains on if LEDON is clear. LED Hold Time configures the update interval
for the LED display if LEDON is set.
Bits 4, 5, 6, and 7 are a binary code for number of external LEDs. Code 0 is reserved. Codes 1 through 15
represents 2~16 external LEDs. So, number of External LEDs is 1 + Value of the 4-bit binary code. Display of
Remaining Capacity is evenly divided among the selected number of LEDs.
Upon detecting A/D value representing 2.5 V on VEN pin, Single LED mode toggles the LED as duty cycle on
within a period of one second. So, for example 10% RSOC will have the LED on for 100 ms and off for 900 ms.
90% RSOC has the LED on for 900 ms and off for 100 ms. Any value >90% displays as 90%.
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Upon detecting A/D value representing 2.5 V on VEN pin, Four-LED mode will display the RSOC by driving pins
RC2(LED1), RC0(LED2), RA1(LED3),RA2(LED4) in a proportional manner where each LED represents 25% of
the remaining state of charge. For example, if RSOC = 67%, three LEDs will be illuminated.
Upon detecting A/D value representing 2.5 V on the VEN pin, External LED mode will transmit the RSOC into an
SN74HC164 (for 2~8 LEDs) or two SN74HC164 devices (for 9 to approximately 16 LEDs) using a bit-banged
approach with RC2 as Clock and RC0 as Data (see Figure 9). LEDs are lit for number of seconds as defined in a
data flash parameter. See the SN54HC164, SN74HC164 8-Bit Parallel-Out Serial Shift Registers Data Sheet
(SCLS115E) for detail on these devices.
Extended commands are available to turn the LEDs on and off for test purposes.
ALERT SIGNAL
Based on the selected LED mode, various options are available for the hardware implementation of an Alert
signal. Software configuration of the Alert Configuration register determines which alert conditions will assert the
Alert pin.
Table 14. Alert Signal Pins
Mode
Description
Alert Pin
Alert Pin Name
Config Register
Hex Code
0
No LED
1
P2
0
1
Single LED
1
P2
1
2
4 LED
11
P6
2
3
5-LED Expander with I2C
Host Comm
12
P5
43
3
10-LED Expander with I2C
Host Comm
12
P5
93
4
5-LED Expander with HDQ
Host Comm
13
P4
44
4
10-LED Expander with HDQ
Host Comm
13
P4
94
Comment
Filter and FETs are required to
eliminate temperature sense pulses
(see Figure 9).
The port used for the Alert output depends on the mode setting in LED/Comm Configuration as defined in
Table 14. The default mode is 0. The Alert pin will be asserted by driving LOW. However, note that in LED/COM
mode 2, pin TS/P6, which has a dual purpose as temperature sense pin will be driven low except when
temperature measurements are made each second. Refer to the reference schematic for filter implementation
details if host alert sensing requires a continuous signal.
The Alert pin will be a logical OR of the selected bits in the new configuration register when asserted in the Flags
register. Default value for Alert Configuration register is 0.
Table 15. Alert Configuration Register Bit Definitions
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High Byte
OTC
OTD
BATHIGH
BATLOW
CHG_INH
Low Byte
RSVD
ISD
TDD
RSVD
RSVD
RSVD
FC
CHG
SOC1
SOCF
DSG
OTC: Overtemperature in Charge condition is detected. Alert enabled when set.
OTD: Overtemperature in Discharge condition is detected. Alert enabled when set.
BATHIGH: Battery High bit that indicates a high battery voltage condition. Refer to the data flash
BATTERY HIGH parameters for threshold settings. Alert enabled when set.
BATLOW: Battery Low bit that indicates a low battery voltage condition. Refer to the data flash
BATTERY LOW parameters for threshold settings. Alert enabled when set.
CHG_INH: Charge Inhibit: unable to begin charging [Charge Inhibit Temp Low, Charge Inhibit
Temp High]. Alert enabled when set.
RSVD: Reserved. Do not use.
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FC: Full-charge is detected. FC is set when charge termination is reached and FC Set% = –1
(see CHARGING AND CHARGE TERMINATION INDICATION for details) or State of
Charge is larger than FC Set% and FC Set% is not –1. Alert enabled when set.
CHG: (Fast) charging allowed. Alert enabled when set.
RSVD: Reserved. Do not use.
ISD: Internal Short is detected. Alert enabled when set.
TDD: Tab Disconnect is detected. Alert enabled when set.
SOC1: State-of-Charge Threshold 1 reached. Alert enabled when set.
SOCF: State-of-Charge Threshold Final reached. Alert enabled when set.
DSG: Discharging detected. Alert enabled when set.
POWER MODES
The bq34z110 has three power modes: NORMAL mode, SLEEP mode, and FULLSLEEP mode.
• In NORMAL mode, the bq34z110 is fully powered and can execute any allowable task.
• In SLEEP mode, the gas gauge exists in a reduced-power state, periodically taking measurements and
performing calculations.
• In FULLSLEEP mode, the high frequency oscillator is turned off, and power consumption is further reduced
compared to SLEEP mode.
NORMAL Mode
The gas gauge is in NORMAL mode when not in any other power mode. During this mode, AverageCurrent(),
Voltage() and Temperature() measurements are taken, and the interface data set is updated. Decisions to
change states are also made. This mode is exited by activating a different power mode.
SLEEP Mode
SLEEP mode is entered automatically if the feature is enabled (Pack Configuration [SLEEP] = 1) and Average
Current() is below the programmable level Sleep Current. Once entry to sleep has been qualified but prior to
entry to SLEEP mode, the bq34z110 performs an ADC autocalibration to minimize offset. Entry to SLEEP mode
can be disabled by the [SLEEP] bit of Pack Configuration(), where 0 = disabled and 1 = enabled. During SLEEP
mode, the bq34z110 periodically wakes to take data measurements and updates the data set, after which it then
returns directly to SLEEP. The bq34z110 exits SLEEP if any entry condition is broken, a change in protection
status occurs, or a current in excess of IWAKE through RSENSE is detected.
FULLSLEEP Mode
FULLSLEEP mode is entered automatically when the bq34z110 is in SLEEP mode and the timer counts down to
0 (Full Sleep Wait Time > 0). FULLSLEEP mode is disabled when Full Sleep Wait Time is set to 0.
During FULLSLEEP mode, the bq34z110 periodically takes data measurements and updates its data set.
However, a majority of its time is spent in an idle condition.
The gauge exits the FULLSLEEP mode when there is any communication activity. Therefore, the execution of
SET_FULLSLEEP sets [FULLSLEEP] bit, but the EVSW might still display the bit clear. The FULLSLEEP mode
can be verified by measuring the current consumption of the gauge. In this mode, the high frequency oscillator is
turned off. The power consumption is further reduced compared to the SLEEP mode.
While in FULLSLEEP mode, the fuel gauge can suspend serial communications as much as 4 ms by holding the
communication line(s) low. This delay is necessary to correctly process host communication since the fuel gauge
processor is mostly halted. For HDQ communication one host message will be dropped.
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POWER CONTROL
RESET FUNCTIONS
When the bq34z110 detects either a hardware or software reset (/MRST pin driven low or the [RESET] bit of
Control() initiated, respectively), it determines the type of reset and increments the corresponding counter. This
information is accessible by issuing the command Control() function with the RESET_DATA subcommand.
As shown in Figure 5, if a partial reset was detected, a RAM checksum is generated and compared against the
previously stored checksum. If the checksum values do not match, the RAM is reinitialized (a “Full Reset”). The
stored checksum is updated every time RAM is altered.
DEVICE RESET
Generate Active
RAM checksum
value
NO
Stored
checksum
Do the Checksum
Values Match?
Re-initialize all
RAM
YES
NORMAL
OPERATION
NO
Active RAM
changed ?
YES
Store
checksum
Generate new
checksum value
Figure 5. Partial Reset Flow Diagram
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WAKE-UP COMPARATOR
The wake up comparator is used to indicate a change in cell current while the bq34z110 is in SLEEP mode.
PackConfiguration() uses bits [RSNS1–RSNS0] to set the sense resistor selection. PackConfiguration() uses the
[IWAKE] bit to select one of two possible voltage threshold ranges for the given sense resistor selection. An
internal interrupt is generated when the threshold is breached in either charge or discharge directions. A setting
of 0x00 of RSNS1..0 disables this feature.
Table 16. IWAKE t = Threshold Settings (1)
(1)
RSNS1
RSNS0
IWAKE
Vth (SRP–SRN)
0
0
0
Disabled
0
0
1
Disabled
0
1
0
+1.25 mV or –1.25 mV
0
1
1
+2.5 mV or –2.5 mV
1
0
0
+2.5 mV or –2.5 mV
1
0
1
+5 mV or –5 mV
1
1
0
+5 mV or –5 mV
1
1
1
+10 mV or –10 mV
The actual resistance value vs. the setting of the sense resistor is not important just the actual voltage threshold when calculating the
configuration.
FLASH UPDATES
Data flash can only be updated if Voltage() ≥ Flash Update OK Voltage. Flash programming current can cause
an increase in LDO dropout. The value of Flash Update OK Voltage should be selected such that the bq34z110
Vcc voltage does not fall below its minimum of 2.4 V during Flash write operations. The default value of 2800 mV
is appropriate.
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VOLTAGE DIVISION AND CALIBRATION
The bq34z110 is shipped with factory configuration for the default case of 2-series lead-acid cell. This can be
changed by setting the number of series cells in the data flash configuration section.
Multi-cell applications, with voltages up to 65535 mV may be gauged by using the appropriate input scaling
resistors such that the maximum battery voltage, under all conditions, appears at the BAT input as approximately
900 mV. The actual gain function is determined by a calibration process and the resulting voltage calibration
factor is stored in the data flash location Voltage Divider.
For two-cell applications, an external divider network is not required. Inside the IC, behind the BAT pin is a
nominal 5:1 voltage divider with 88 KΩ in the top leg and 22 KΩ in the bottom leg. This internal divider network is
enabled by clearing the VOLTSEL bit in the Pack Configuration register. This ratio is optimum for directly
measuring a dual cell lead-acid cell where charge voltage is limited to 5 V max.
For higher voltage applications, an external resistor divider network should be implemented as per the reference
designs in this document. The quality of the divider resistors is very important to avoid gauging errors over time
and temperature. It is recommended to use 0.1% resistors with 25 ppm temperature coefficient. Alternately, a
matched network could be used that tracks its dividing ratio with temperature and age due to the similar
geometry of each element. Calculation of the series resistor can be made per the equation below. Note that
exceeding VIN max mV results in a measurement with degraded linearity.
The bottom leg of the divider resistor should be in the range of 15 KΩ to 25 KΩ. Assuming the use of 16.5 KΩ:
Rseries = 16500 Ω (VIN max mV – 900 mV) / 900 mV
For all applications, the Voltage Divider value in data flash is used by the firmware to calibrate the total divider
ratio. The nominal value for this parameter is the maximum expected value for the stack voltage. The calibration
routine adjusts the value to force the reported voltage to equal the actual applied voltage.
2S EXAMPLE
For stack voltages under 5 V max, it is not necessary to provide an external voltage divider network. The internal
5:1 divider should be selected by clearing the VOLTSEL bit in the Pack Configuration register. The default value
for Voltage Divider is 5000 (representing the internal 5000:1000 mV divider) when no external divider resistor is
used, and the default number of series cells = 2. In the 2S case, there is usually no requirement to calibrate the
voltage measurement, since the internal divider is calibrated during factory test to within 2 mV.
6S EXAMPLE
In the multi-cell case, the hardware configuration is different. An external voltage divider network is calculated
using the Rseries formula above. The bottom leg of the divider should be in the range of 15 KΩ to 25 KΩ. For
more details on configuration, see DESIGN STEPS.
AUTOCALIBRATION
The bq34z110 provides an autocalibration feature that will measure the voltage offset error across SRP and SRN
from time-to-time as operating conditions change. It subtracts the resulting offset error from normal sense
resistor voltage, VSR, for maximum measurement accuracy.
The gas gauge performs a single offset calibration when (1) the interface lines stay low for a minimum of Bus
Low Time and (2) Vsr > Deadband.
The gas gauge also performs a single offset when (1) the condition of AverageCurrent() ≤ Autocal Min Current
and (2) {voltage change since last offset calibration ≥ Delta Voltage} or {temperature change since last offset
calibration is greater than Delta Temperature for ≥ Autocal Time}.
Capacity and current measurements should continue at the last measured rate during the offset calibration when
these measurements cannot be performed. If the battery voltage drops more than Cal Abort during the offset
calibration, the load current has likely increased considerably; hence, the offset calibration is aborted.
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COMMUNICATIONS
AUTHENTICATION
The bq34z110 can act as a SHA-1 and HMAC authentication slave by using its internal engine. Sending a 160bit SHA-1 challenge message to the bq34z110 causes the IC to return a 160-bit digest, based upon the
challenge message and hidden plain-text authentication keys. When this digest matches an identical one,
generated by a host or dedicated authentication master (operating on the same challenge message and using
the same plain text keys), the authentication process is successful.
The bq34z110 contains a default plain-text authentication key of 0x0123456789ABCDEFFEDCBA987654321. If
using the bq34z110 device's internal authentication engine, the default key can be used for development
purposes, but should be changed to a secret key and the part immediately sealed, before putting a pack into
operation.
KEY PROGRAMMING
When the bq34z110 device's SHA-1 and HMAC internal engine is used, authentication keys are stored as plaintext in memory. A plain-text authentication key can only be written to the bq34z110 while the IC is in UNSEALED
mode. Once the IC is UNSEALED, a 0x00 is written to BlockDataControl() to enable the authentication data
commands. Next, subclass ID and offset are specified by writing 0x70 and 0x00 to DataFlashClass() and
DataFlashBlock(), respectively. The bq34z110 is now prepared to receive the 16-byte plain-text key, which must
begin at command location 0x4C. The key is accepted once a successful checksum has been written to
BlockDataChecksum(), for the entire 32-byte block (0x40 through 0x5f), not just the 16-byte key.
EXECUTING AN AUTHENTICATION QUERY
To execute an authentication query in UNSEALED mode, a host must first write 0x01 to the BlockDataControl()
command, to enable the authentication data commands. If in SEALED mode, 0x00 must be written to
DataFlashBlock(), instead.
Next, the host writes a 20-byte authentication challenge to the AuthenticateData() address locations (0x40
through 0x53). After a valid checksum for the challenge is written to AuthenticateChecksum(), the bq34z110 uses
the challenge to perform it own the SHA-1/HMAC computation, in conjunction with its programmed keys. The
resulting digest is written to AuthenticateData(), overwriting the pre-existing challenge. The host may then read
this response and compare it against the result created by its own parallel computation.
HDQ SINGLE-PIN SERIAL INTERFACE
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to
the bq34z110. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted
first. Note that the DATA signal on pin 12 is open-drain and requires an external pull-up resistor. The 8-bit
command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit
7). The R/W field directs the bq34z110 either to
• Store the next 8 or 16 bits of data to a specified register or
• Output 8 or 16 bits of data from the specified register
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
The return-to-one data bit frame of HDQ consists of three distinct sections. The first section is used to start the
transmission by either the host or by the bq34z110 taking the DATA pin to a logic-low state for a time tSTRH,B.
The next section is for data transmission, where the data are valid for a time tDSU, after the negative edge used
to start communication. The data are held until a time tDV, allowing the host or bq34z110 time to sample the data
bit. The final section is used to stop the transmission by returning the DATA pin to a logic-high state by at least a
time tSSU, after the negative edge used to start communication. The final logic-high state is held until the end of
tCYCH,B, allowing time to ensure the transmission was stopped correctly. The timing for data and break
communication is shown in HDQ COMMUNICATION TIMING CHARACTERISTICS.
HDQ serial communication is normally initiated by the host processor sending a break command to the
bq34z110. A break is detected when the DATA pin is driven to a logic-low state for a time tB or greater. The
DATA pin should then be returned to its normal ready high logic state for a time tBR. The bq34z110 is now ready
to receive information from the host processor.
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The bq34z110 is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral.
I2C INTERFACE
The gas gauge supports the standard I2C read, incremental read, one-byte write quick read, and functions. The
7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively.
Host Generated
S
0 A
ADDR[6:0]
Fuel Gauge Generated
A
CMD[7:0]
A P
DATA[7:0]
S
A
1
ADDR[6:0]
(a)
S
ADDR[6:0]
0 A
DATA[7:0]
N P
(b)
CMD[7:0]
A Sr
1
ADDR[6:0]
A
DATA[7:0]
N P
...
DATA[7:0]
(c)
S
ADDR[6:0]
0 A
CMD[7:0]
A Sr
ADDR[6:0]
1
A
DATA[7:0]
A
N P
(d)
Figure 6. Supported I2C formats: (a) 1-byte write, (b) quick read, ©) 1 byte-read, and (d) incremental read
(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, increments whenever data is acknowledged by the bq34z110 or the
I2C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data).
Attempt to write a read-only address (NACK after data sent by master):
S
ADDR[6:0]
0
A
A
CMD[7:0]
A
DATA[7:0]
P
Attempt to read an address above 0x7F (NACK command):
S
0
ADDR[6:0]
CMD[7:0]
A
N P
Attempt at incremental writes (NACK all extra data bytes sent):
S
ADDR[6:0]
0 A
CMD[7:0]
A
DATA[7:0]
A
DATA[7:0]
N
A
...
...
N P
Incremental read at the maximum allowed read address:
S
ADDR[6:0]
0 A
CMD[7:0]
A Sr
ADDR[6:0]
1
A
DATA[7:0]
Address
0x7F
Data From
addr 0x7F
DATA[7:0]
N P
Data From
addr 0x00
The I2C engine releases both SDA and SCL if the I2C bus is held low for tBUSERR. If the gas gauge was holding
the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines
low, the I2C engine enters the low-power SLEEP mode.
28
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bq34z110
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SLUSB55B – JUNE 2012 – REVISED MAY 2013
DESIGN STEPS
For additional design guidelines, see the bq34z110EVM Wide Range Impedance Track Enabled Battery Fuel
Gauge User's Guide (SLUU904).
STEP 1: Review and modify the Data Flash Configuration Data.
While many of the default parameters in the data flash will be suitable for most applications, the following should
first be reviewed and modified to match the intended application.
• Design Capacity: Enter the value in mAh for the battery, even if you plan to treat your application from the
“design energy” point of view.
• Design Energy: Enter the value in mWh.
• Cell Charge Voltage Tx-Ty: Enter the desired cell charge voltage for each JEITA temperature range.
STEP 2: Review and modify the Data Flash Configuration Registers.
•
•
•
•
LED_Comm Configuration: See Table 13 and Table 14 to aid in selection of an LED mode. Note that the pin
used for the optional Alert signal is dependent upon the LED mode selected.
Alert Configuration: See Table 15 to aid in selection of which faults will trigger the Alert pin.
Number of Series Cells
Pack Configuration: Ensure that the VOLSEL bit is set for multi-cell applications and cleared for single-cell
applications.
STEP 3: Design and Configure the Voltage Divider.
If the battery contains more than two series cells, a voltage divider network will be required. Design the divider
network, based on the formula below. The voltage division required is from the highest expected battery voltage,
down to approximately 900 mV. For example, using a lower leg resistor of 16.5 KΩ where the highest expected
voltage is 32000 mV:
Rseries = 16.5 KΩ (32000 mV – 900 mV) / 900 mV = 570.2 KΩ
Based on price and availability, a 600 K resistor or pair of 300 K resistors could be used in the top leg along with
a 16.5-K resistor in the bottom leg.
Set the Voltage Divider in the Data Flash Calibration section of the Evaluation Software to 32000 mV.
Use the Evaluation Software to calibrate to the applied nominal voltage, e.g.: 24000 mV. After calibration, a
slightly different value will appear in the Voltage Divider parameter, which can be used as a default value for the
project.
STEP 4: Determine the Sense Resistor Value.
To ensure accurate current measurement, the input voltage generated across the current sense resistor should
not exceed ±125 mV. For applications having high dynamic range, it is allowable to extend this range to absolute
maximum of ±300 mV for overload conditions where a protector device will be taking independent protective
action. In such an overloaded state, current reporting and gauging accuracy does not function correctly.
The value of the current sense resistor should be entered into both CC Gain and CC Delta parameters in the
Data Flash Calibration section of the Evaluation Software.
STEP 5: Review and Modify the Data Flash Gas Gauging Configuration, Data, and State.
• Load Select: See Table 8 and Table 9.
• Load Mode: See Table 8 and Table 9.
• Cell Terminate Voltage: This is the theoretical voltage where the system will begin to fail. It is defined as zero
state of charge. Generally a more conservative level is used in order to have some reserve capacity. Note the
value is for a single cell only.
• Quit Current: Generally should be set to a value slightly above the expected idle current of the system.
• Qmax Cell 0: Start with the C-rate value of your battery.
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SLUSB55B – JUNE 2012 – REVISED MAY 2013
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STEP 6: Determine and Program the Chemical ID.
Use the bqChem feature in the Evaluation Software to select and program the chemical ID matching your cell. If
no match is found, use the procedure defined in TI's Mathcad Chemistry Selection Tool (SLUC138).
STEP 7: Calibrate.
Follow the steps on the Calibration screen in the Evaluation Software. Achieving the best possible calibration is
important before moving on to STEP 8: Run an Optimization Cycle. For mass production, calibration is not
required for single-cell applications. For multi-cell applications, only voltage calibration is required. Current and
temperature may be calibrated to improve gauging accuracy if needed.
STEP 8: Run an Optimization Cycle.
1. Start with a fully charged and relaxed battery.
2. Temporarily Adjust the Cell BL Set Volt Threshold so as not to affect a full discharge.
3. Send the IT Enable command 0x21. The VOK and QEN flags should be set.
4. Discharge the battery at C/10 until the battery is empty.
CAUTION
It may be necessary to stop the load, check the rebound, then apply the load again to
ensure that the rebounded voltage will not be significantly higher than the Cell
Termination Voltage. For example, a Cell Termination Voltage of 1800 mV will be
10800 mV for a 12 V/six-cell battery. After stopping the load at 10500 mV, it can
bounce all the way up to 11500 mV, which is too high for this procedure. However, if
the load is continued until the battery voltage is 10000 mV, the resulting bounce back
will be close to the intended termination voltage.
5. Allow the battery to relax. Wait for The OCV reading to be taken and the VOK flag to clear. The update
status should now be set to 5.
6. Charge the battery until full. The VOK and QEN flags should be set during the charging operation.
7. Allow the battery to relax. The VOK flag will remain set.
8. Discharge the battery at C/10 until the battery is empty.
9. Allow the battery to relax. Wait for The OCV reading to be taken and the VOK flag to clear. The update
status should now be set to 6.
10. Restore the Cell BL Set Volt Threshold to the desired value.
30
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2
3
BAT -
PACK -
TB3
1
BAT +
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: bq34z110
GND
AGND
REGIN
AGND
R30
.010 75ppm
0.1uF
C2
AGND
R5
100
R6
100
SW1
1K
R1
C6
C5
LED Display
0.1uF
C8
REG25
REGIN
CE
BAT
P1
VEN
P2
0.1uF
7
6
5
4
3
P1
0.1uF
1
2
P2
C1
U2
1uF
C7
8
9
10
11
12
13
14
0.1uF
VSS
SRP
SRN
P6/TS
P5/HDQ
P4/SCL
P3/SDA
BQ34Z110PW
AGND
LED0
LED1
LED2
LED3
LED4
REGIN
GND
GND
D3
QTLP610C-4 GRN
R12
R11
R10
D11 QTLP610C-4 GRN
D12 QTLP610C-4 GRN
R9
R8
P1
AZ23C5V6-7
D2
R13
100
D10 QTLP610C-4 GRN
D9 QTLP610C-4 GRN
RT1
10K
R14
100
AZ23C5V6-7
R55
100
R56
100
D1
R53
100
R54
100
470
470
470
470
470
GND
GND
GND
J9
7
6
5
4
3
2
1
1
2
3
4
U3
GND
GND
QD
QC
QB
QA
B
A
CLK
~CLR
QE
QF
QG
QH
VCC
SN74HC164PW
J10
8
9
10
11
12
13
14
REGIN
HDQ or ALERT
GND
2
1
SDA
SCL or ALERT
3
4
P2
C3
0.1uF
GND
bq34z110
www.ti.com
SLUSB55B – JUNE 2012 – REVISED MAY 2013
APPLICATION SCHEMATICS
2-Cell Lead-Acid and 5-LED Display
Figure 7. 2-Cell Lead-Acid and 5-LED Display
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31
SH1 SH2
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3
PACK -
SH1
SH2
GND
AGND
R30
.010 75ppm *
* Optimize for required voltage and current
2
BAT -
TB3
1
BAT +
10k *
R3
R1
Q3
2N7002
0.1uF
C2
AGND
GND
BZT52C5V6T
R7
D
AGND
3
REGIN
16.5 K .1% 25PPM *
VOLTAGE DIVIDER .1% 25PPM *
D7
Q5
BSS84
R4
165K *
AGND
R6
R5
LED Display
SW1
3300 pF
C1
GND
Q4
2N7002
2 S
32
G
1
R2
100K *
100
100
1k
R15
P1
P2
C6
C5
REG25
U2
0.1uF
C8
REG25
REGIN
CE
BAT
P1
VEN
1uF
C7
8
9
10
11
12
13
14
0.1uF
VSS
SRP
SRN
P6/TS
P5/HDQ
P4/SCL
P3/SDA
BQ34Z110PW
P2
0.1uF
7
6
5
4
3
2
1
AGND
REG25
10K
RT1
LED0
LED1
LED2
LED3
LED4
REGIN
GND
GND
R11
R12
R10
D3
QTLP610C-4 GRN
D11 QTLP610C-4 GRN
D12 QTLP610C-4 GRN
R9
R8
P1
AZ23C5V6-7
D2
R13
100
D10 QTLP610C-4 GRN
D9 QTLP610C-4 GRN
R14
100
AZ23C5V6-7
R55
100
R56
100
D1
R53
100
R54
100
1k
1k
1k
1k
1k
GND
7
6
5
4
3
2
1
GND
QD
QC
QB
QA
B
A
CLK
~CLR
QE
QF
QG
QH
VCC
SN74HC164PW
U3
8
9
10
11
12
13
14
GND
GND
REGIN
1
2
3
4
P2
C3
J10
0.1uF
GND
GND
HDQ or ALERT
GND
SCL or ALERT
J9
SDA
2
1
3
4
bq34z110
SLUSB55B – JUNE 2012 – REVISED MAY 2013
www.ti.com
Multi-Cell and 5-LED Display
Figure 8. Multi-Cell and 5-LED Display
Copyright © 2012–2013, Texas Instruments Incorporated
PACK -
BAT -
BAT +
TB3
3
2
1
GND
R30
.010 75ppm
AGND
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: bq34z110
R18
R20
R22
R23
R24
D14 QTLP610C-3 YEL
D15 QTLP610C-4 GRN
D16 QTLP610C-4 GRN
D17 QTLP610C-4 GRN
D6
GND
6
TP4
U1
CLK
~CLR
QE
QF
QG
QH
VCC
GND
QD
QC
QB
QA
B
A
CLK
~CLR
QE
QF
QG
QH
VCC
SN74HC164PW
GND
QD
QC
QB
QA
B
A
TP5
8
9
10
3
4
TP7
TP8
0.1uF
TP6
C4
GND
C5
REGIN
0.1uF
C8
REG25
REGIN
CE
BAT
P1
VEN
1uF
8
9
10
11
12
13
14
0.1uF
C7
VSS
SRP
SRN
P6/TS
P5/HDQ
P4/SCL
P3/SDA
U2
BQ34Z1X0 PW
P2
0.1uF
7
6
5
4
3
2
1
Optimize for required LED power dissipation
AGND
QTLP610C-4 GRN
GND
R32
1M
Q1
2SK3019
LED A
Open for I2C
J1
2
I2C pullups normally implemented in the host. Duplicated here since EV2300 does not provide
C6
R38
1k
REG25
GND
P2
100
R6
0.1uF
100
C3
P1
P2
LED Display
R5
SW1
11
12
13
14
8
9
10
11
12
13
14
AGND
0.1uF
C2
Optional for additional power saving
7
5
TP3
4
3
2
1
7
6
U3
>5V
>5V
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