BQ4802LYPW

bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR AND EXTERNAL SRAM NONVOLATILE MEMORY BACKUP FEATURES D Real-Time Clock Counts Seconds Through D D D D D D D D D APPLICATIONS D D D D D D Centuries in BCD Format – bq4802Y: 5-V Operation – bq4802LY: 3.3-V Operation On-Chip Battery-Backup Switchover Circuit With Nonvolatile Control for External SRAM Less Than 500 nA of Clock Operation Current in Backup Mode Microprocessor Reset With Push-Button Override Independent Watchdog Timer With Programmable Time-Out Period Power-Fail Interrupt Warning Programmable Clock Alarm Interrupt Active in Battery-Backup Mode Programmable Periodic Interrupt Battery-Low Warning 28-pin SOIC, TSSOP, and SNAPHAT Package Options TYPICAL APPLICATION Telecommunications Base Stations Servers Handheld Data Collection Equipment Medical Equipment Handheld Instrumentation Test Equipment DESCRIPTION The bq4802Y/bq4802LY real-time clock is a low-power microprocessor peripheral that integrates a time-ofday clock, a century-based calendar, and a CPU supervisor, with package options including a 28-pin SOIC, TSSOP, or SNAPHAT that requires the bq48SH-28x6 to complete the two-piece module. The bq4802Y/ bq4802LY is ideal for fax machines, copiers, industrial control systems, point-of-sale terminals, data loggers, and computers. 5 kΩ VCC bq4802 ADDRESS BUS A0–A3 RST TO µP WDO DATA BUS FROM ADDRESS DECODE LOGIC DQ0–DQ7 CMOS SRAM INT CS 62256L ADDRESS BUS CEIN DATA BUS FROM µP I/O LINE A0–A3 VOUT WDI DQ0–DQ7 VCC CEOUT CE OE WR OE READ/ WRITE CONTROL FROM µP WE X1 BC 3V LITHIUM CELL 32.768 kHz CRYSTAL X2 VSS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The bq4802Y/bq4802LY provides direct connections for a 32.768-kHz quartz crystal and a 3-V backup battery. Through the use of the conditional chip enable output (CEOUT) and battery voltage output (VOUT) pins, the bq4802Y/bq4802LY can write-protect and make non- volatile external SRAMs. The backup cell powers the real-time clock and maintains SRAM information in the absence of system voltage. The crystal and battery are contained within the modules for a more integrated solution. The bq4802Y/bq4802LY contains a temperaturecompensated reference and comparator circuit that monitors the status of its voltage supply. When the bq4802Y/bq4802LY detects an out-of-tolerance condition, it generates an interrupt warning and subsequently a microprocessor reset. The reset stays active for 200 ms after VCC rises within tolerance, to allow for power supply and processor stabilization. The reset function also allows for an external push-button override. ORDERING INFORMATION TA OPERATION 0°C to +70°C 70°C SOIC(1) (DW) DEVICES TSSOP(1) (PW) SYMBOL SNAPHAT(1)(2)(3) (DSH) 5V bq4802YDW bq4802YPW bq4802YDSH bq4802Y 3.3 V bq4802LYDW bq4802LYPW bq4802LYDSH bq4802LY (1) The DW, PW and DSH packages are available taped and reeled. Add an R suffix to the device type (i.e., bq4802YDWR). (2) The DSH package is available taped only. (3) The bq48SH–28x6 should be ordered to complete the SNAPHAT module and is the same part number for both 3.3-V and 5-V modules. CAUTION: Wave soldering of DSH package may cause damage to SNAPHAT sockets. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) bq4802Y bq4802LY Input voltage range, VCC, VT (VT ≤ VCC +0.3) –0.3 V to 6.0 V Operating temperature range, TJ 0°C to 70°C Storage temperature range, Tstg – 55°C to 125°C Temperature under bias, TJbias – 40°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply voltage voltage, VCC MIN MAX bq4802Y 4.5 5.5 bq4802LY 2.7 3.6 UNIT V Input low voltage, VIL –0.3 0.8 V Input high voltage, VIH 2.2 V Backup cell voltage, VBC 2.4 VCC + 0.3 4.0 –0.3 0.4 V 2.2 VCC + 0.3 V Push button reset input low, VBC Push button reset input high, VPBRH 2 V bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC(min) ≤ VCC ≤ VCC(max) unless otherwise noted) INPUT SUPPLY PARAMETER TEST CONDITIONS ICC Supply current ISB1 Standby supply current ICCB Battery operation supply current ILI ILO TYP MAX 100% Minimum duty cycle, CS = VIL, II/O = 0 mA MIN 5 9 CS = VIH 3 CS = VCC – 0.2 V, 0 V ≤ VIN ≤ 0.2 V or VIN = VCC – 0.2 V Input leakage current VBC = 3 V, TA = 25°C, No load at VOUT or CEOUT, II/O = 0 mA VIN = VSS to VCC Output leakage current CS = VIH or OE = VIH or WE = VIL VOUT(1) VOUT(2) Output voltage IOUT = 80 mA,VCC > VBC IOUT = 100 µA, VCC < VBC VPFD Power fail detect voltage VSO Supply switch over voltage VBC > V(PFD) VBC < V(PFD) VRST VINT RST output voltage(1) INT output voltage(1) I(RST) = 4 mA I(INT) = 4 mA UNIT mA mA 1.5 0.5 µA –1 1 µA –1 1 µA 0.3 VCC-0.3 VBC-0.3 V bq4802Y 4.30 4.37 4.5 bq4802LY 2.4 2.53 2.65 VPFD VBC V V 0.4 V 0.4 V (1) RST and INT are open drain outputs. WATCHDOG PARAMETER I(WDIL) I(WDIH) Low-level watchdog input current V(WDO) WDO output voltage TEST CONDITIONS MIN TYP –50 –10 High-level watchdog input current 20 ISINK = 4 mA ISOURCE = 2 mA MAX 50 0.4 2.4 UNIT µA V CRYSTAL SPECIFICATIONS (DT-26) OR EQUIVALENT) PARAMETER TEST CONDITIONS MIN TYP MAX 32.768 UNIT fO CL Oscillation frequency TP k Temperature turnover point Q Quality factor R1 C0 Series resistance 45 kΩ Shunt capacitance 1.1 1.8 pF C0/C1 DL Capacitance ratio 430 600 ∆f/f0 Aging (first year at 25°C) Load capacitance kHz 6 20 25 Parabolic curvature constant pF 30 –0.042 40,000 °C ppm/°C 70,000 Drive level 1 1 µW – ppm MAX UNIT CAPACITANCE PARAMETER II/O CI Input/output capacitance Input capacitance TEST CONDITIONS VOut = 0 V V=0V MIN TYP 7 5 pF 3 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 AC TEST CONDITIONS, INPUT PULSE LEVELS VI = 0 V to 3.0 V, tR = tF = 5 NS, VREF = 1.5 V 3V 3V 962 Ω 962 Ω DOUT DOUT 510 Ω 100 pF 510 Ω 5 pF Figure 2. Output Load B Figure 1. Output Load A OPERATING CHARACTERISTICS READ CYCLE (TA = TOPR, VCC = 5 V) PARAMETER TEST CONDITIONS MIN MAX 200 UNIT tRC tAA Read cycle time ns Address access time Output load A 100 ns tACS tOE Chip select access time Output load A 100 ns Output enable to output valid Output load A 100 ns tCLZ tOLZ Chip select to output low Z Output load B 8 Output enable until output low Z Output load B 0 tCHZ tOHZ Output enable until output high Z Output load B 0 45 ns Output disable until output high Z Output load B 0 45 ns tOH Output hold from address change Output load A 10 ns ns ns READ CYCLE (TA = TOPR, VCC = 3.3 V) PARAMETER TEST CONDITIONS MIN MAX tRC tAA Read cycle time Address access time Output load A 150 ns tACS tOE Chip select access time Output load A 150 ns Output enable to output valid Output load A 150 ns tCLZ tOHL Chip select to output low Z Output load B 15 Output enable until output low Z Output load B 0 tCLH tOLZ Output enable until output high Z Output load B 0 60 ns Output disable until output high Z Output load B 0 60 ns tOH Output hold from address change Output load A 18 4 300 UNIT ns ns ns ns bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 PIN ASSIGNMENTS DW OR PW PACKAGE (TOP VIEW) VOUT X1 X2 WDO INT RST A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DSH PACKAGE (TOP VIEW) VCC WE CEIN CEOUT BC WDI OE CS VSS DQ7 DQ6 DQ5 DQ4 DQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VOUT NC NC WDO INT RST A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CEIN CEOUT NC WDI OE CS NC DQ7 DQ6 DQ5 DQ4 DQ3 NC – No internal connection Terminal Functions TERMINAL NAME NO. A0 10 A1 9 A2 8 A3 7 24(1) BC I/O DESCRIPTION A0 – A3 allow access to the 16 bytes y of real-time clock and control registers. g BC should be connected to a 3-V backup cell. A voltage within the VBC range on the BC pin should be present upon power up to provide proper oscillator start-up. Not accessible in module packages. CEIN CEOUT 26 Input to the chip-enable gating circuit 25 CEOUT goes low only when CEIN is low and VCC is above the power fail threshold. If CEIN is low, and power fail occurs, CEOUT stays low for 100 µs or until CEIN goes high, whichever occurs first. CS 21 I Chip-select input DQ0 11 I DQ0–DQ7 Q Q provide x8 data for real-time clock information. These pins connect to the memory y data bus. DQ1 12 I DQ2 13 I DQ3 15 I DQ4 16 I DQ5 17 I DQ6 18 I DQ7 19 I INT 5 INT goes low when a power fail, periodic, or alarm condition occurs. INT is an open-drain output. OE 22 OE provides the read control for the RTC memory locations. RST 6 RST goes low whenever VCC falls below the power fail threshold. RST remains low for 200 ms (typical) after VCC crosses the threshold on power-up. The bq4802Y/bq4802LY also enters the reset cycle when RST is released from being pulled low for more than 1 µs. VCC VOUT 28 I 5-V or 3.3-V input 1 O VOUT provides the higher of VCC or VBC, switched internally, to supply external RAM. Ground VSS 14 20(1) (1) This pin should be left unconnected (NC) when using the SNAPHAT (DSH) package. 5 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 Terminal Functions (Continued) TERMINAL NAME NO. WDI 23 WDO 4 WE I/O DESCRIPTION I WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-out period (1.5-s default), WDO goes low. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and VSS, which sets it to mid-supply when left unconnected. 27 2(1) 3(1) X1 X2 WDO goes low if WDI remains either high or low longer than the watchdog time-out period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. WE provides the write control for the RTC memory locations. Crystal y connection FUNCTIONAL BLOCK DIAGRAM Figure 3 is a block diagram of the bq4802Y/bq4802LY. The following sections describe the bq4802Y/bq4802LY functional operation including clock interface, data-retention modes, power-on reset timing, watchdog timer activation, and interrupt generation. X1 X2 TimeBase Oscillator ÷8 ÷64 ÷64 4 16:1 MUX Control/Status Registers Clock/Calendar Update Clock/Calendar and Alarm Registers User Buffer (16 Bytes) Interrupt Generator INT Watchdog Transition Detector WDO Power-Fail Control, Battery Switchover and Reset Circuits µP Bus Interface RST VOUT CEOUT A0 – A3 CS OE WE DQ0 – DQ7 WDI Figure 3. Block Diagram 6 CEIN VCC BC bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 READ CYCLE TIMING DIAGRAMS tRC Address tAA tOH DOUT Previous Data Valid Data Valid NOTES: A. WE is held high for a read cycle. B. Device is continuously selected: CS = OE = VIL. Figure 4. Read Cycle No. 1 – Address Access tRC CS tCHZ tACS tCLZ DOUT High-Z High-Z NOTES: A. WE is held high for a read cycle. B. Device is continuously selected: CS = OE = VIL. C. OE = VIL. Figure 5. Read Cycle No. 2 – CS Access tRC Address tAA OE tOE tOHZ tOLZ DOUT Data Valid High-Z High-Z NOTES: A. WE is held high for a read cycle. B. CS = VIL. Figure 6. Read Cycle No. 3 – OE Access 7 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 WRITE CYCLE TIMING DIAGRAMS tWC Address tAW tWR1 tCW CS tAS tWP WE tDW DIN tDH1 Data-In Valid tWZ DOUT tOW Data Undefined (see Note B) High-Z NOTES: A. WE or CS must be held high during address transition. B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied. C. If OE is high, the I/O pins remain in a state of high impedance. Figure 7. Write Cycle No. 1 – WE Controlled tWC Address tAW tAS tWR2 tCW CS tWP WE tDW DIN tDH2 Data-In Valid tWZ DOUT NOTES: A. B. C. D. E. Data Undefined (see Note B) WE or CS must be held high during address transition. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied. If OE is high, the I/O pins remain in a state of high impedance. Either tWR1 or tWR2 must be met. Either tDH1 or tDH2 must be met. Figure 8. Write Cycle No. 2 – CS Controlled 8 High-Z bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 WRITE CYCLE (TA = TOPR, VCC = 5 V) PARAMETER TEST CONDITIONS MIN MAX UNIT tWC tCW Write cycle time 200 ns Chip select to end of write See Note 1 195 ns tAW tAS Address valid to end of write See Note 1 195 ns Address setup time 30 ns tWP tWR1 Write pulse width Measured from address valid to beginning of write(2) Measured from beginning of write to end of write(1) 165 ns 5 ns tWR2 tDW Write recovery time (write cycle 2) tDH1 tDH2 Data hold time (write cycle 1) tWZ tOW Write recovery time (write cycle 1) Measured from WE going high to end of write cycle(3) Measured from CS going high to end of write cycle(3) 15 ns Measured to first low-to-high transition of either CS or WE Measured from WE going high to end of write cycle(4) 50 ns 0 ns 10 Write enable to output high Z Measured from CS going high to end of write cycle(4) I/O pins are in output state.(5) Output active from end of write I/O pins are in output state.(5) Data valid to end of write Data hold time (write cycle 2) 0 ns 45 0 ns ns (1) A write cycle ends at the earlier transition of CS going high and WE going high. (2) A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low. (3) Either tWR1 or tWR2 must be met. (4) Either tDH1 or tDH2 must be met. (5) If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state. WRITE CYCLE (TA = TOPR, VCC = 3.3 V) PARAMETER TEST CONDITIONS tWC tCW Write cycle time Chip select to end of write tAW tAS Address valid to end of write Address setup time tWP tWR1 Write pulse width Measured from address valid to beginning of write(2) Measured from beginning of write to end of write(1) tWR2 tDW Write recovery time (write cycle 2) tDH1 tDH2 Data hold time (write cycle 1) tWZ tOW Write recovery time (write cycle 1) MIN MAX UNIT 300 ns See Note 1 250 ns See Note 1 250 ns 56 ns 280 ns 8 ns Measured from WE going high to end of write cycle(3) Measured from CS going high to end of write cycle(3) 25 ns Measured to first low-to-high transition of either CS or WE Measured from WE going high to end of write cycle(4) 80 ns 0 ns 15 Write enable to output high Z Measured from CS going high to end of write cycle(4) I/O pins are in output state.(5) Output active from end of write I/O pins are in output state.(5) Data valid to end of write Data hold time (write cycle 2) 0 0 ns 60 ns ns (1) A write cycle ends at the earlier transition of CS going high and WE going high. (2) A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low. (3) Either tWR1 or tWR2 must be met. (4) Either tDH1 or tDH2 must be met. (5) If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state. 9 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 POWER-DOWN/POWER-UP TIMING (TA = TOPR) PARAMETER tF tR VCC slew rate fall time VCC slew rate rise time tPF Interrupt delay time from VPFD tWPT Write protect time for external SRAM Write-protect tCSR CS at VHI after power-up power up tRST tCER VPFD to RST active (reset active time-out period) Device enable recovery time TEST CONDITIONS MIN 3.0 V to 0 V 300 VSO to VPDF(max) 100 Device enable propagation delay time to external SRAM MAX bq4802Y 6 24 bq4802LY 10 40 bq4802Y See Note 1 90 100 125 bq4802LY See Note 1 150 170 210 bq4802Y See Note 2 100 200 300 bq4802LY See Note 2 170 330 See Note 3 tCSR tCSR bq4802Y tCED TYP bq4802LY Output load A tPBL Push-button low time (1) Delay after VCC slews down past VPFD before SRAM is write protected and RST activated. (2) Internal write-protection period after VCC passes VPFD on power up. (3) Time during which external SRAM is write protected after VCC passes VPFD on power up. UNIT µss 500 tCSR tCSR 9 15 15 25 ms ns µs 1 CAUTION:NEGATIVE UNDERSHOOTS BELOW THE ABSOLUTE MAXIMUM RATING OF –0.3 V IN BATTERYBACKUP MODE MAY AFFECT DATA INTEGRITY. tF tR tFS VCC VPFD(max) VPFD VCC VPFD 2.8 VSO VSO tCSR tPF CS tWPT tCER CEIN tCED tCED VOHB CEOUT tRST RST INT High-Z NOTES: A. PWRIE set to 1 to enable power fail interrupt. B. RST and INT are open drain and require and external pullup resistor. Figure 9. Power-Down/Power-Up Timing Diagram 10 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 tPBL tRST VPBRH RST VPBRL Figure 10. Push-Button Reset Timing 11 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 FUNCTIONAL DESCRIPTION The following sections describe the bq4802Y/bq4802LY functional operation including clock interface, data-retention modes, power-on reset timing, watchdog timer activation, and interrupt generation. Table 1. Operational Truth Table VCC < VCC(MAX) CS OE WE VIH VIL X X X CEIN VIL VIL VIL VIH VIL VIH VSO X X VIH X ≤ VSO X X X > VCC(MIN) CEOUT CEIN VOUT VOUT1 VOUT1 MODE DQ POWER Deselect High Z Standby Write Active Read CEIN VOUT1 VOUT1 DIN DOUT Read High-Z Active VOH VOHB VOUT1 VOUT2 Deselect High-Z CMOS standby Deselect High-Z Battery-backup mode CEIN Active ADDRESS MAP The bq4802Y/bq4802LY provides 16 bytes of clock and control status registers. Table 1 is a map of the bq4802Y/bq4802LY registers, and Table 2 describes the register bits. Table 2. Clock and Control Register Map Addr (h) D7 0 0 1 ALM1 2 0 3 ALM1 4 PM/AM 5 ALM1 PM/AM D6 D5 D4 10-second digit ALM0 10-second digit 10-minute digit ALM0 10-minute digit D2 D1 Range (h) Register 1-second digit 00–59 Seconds 1 second digit 1-second 00 59 00–59 Seconds alarm 1-minute digit 00–59 Minutes 1 minutedigit 1-minute digit 00 59 00–59 Minutes alarm 10-hour digit 1-hour digit 01–12AM 81–92PM Hours ALM0 10 hour digit 10-hour 1 hour digit 1-hour 01–12AM 81–92PM Hours alarm 10-day digit 1-day digit 01–31 Day 1-day digit 01–31 Day alarm 01–07 Day of Week 1-month digit 01–12 Month 1-year digit 00–99 Year 0 0 7 ALM1 ALM0 8 0 0 0 0 9 0 0 0 10 mo. 10-day digit 0 10-year digit day of week digit B (1) WD2 WD1 WD0 RS3 RS2 RS1 RS0 – Rates C (1) (1) (1) (1) AIE PIE PWRIE ABE – Enables D (1) (1) (1) (1) AF PF PWRF BVF – Flags E (1) (1) (1) (1) UTI STOP 24/12 DSE – Control 00–99 Century F 10-century digit 1-century digit (1) Unused bits; cannot be written to and read as 0. (2) Internal write-protection period after VCC passes VPFD on power up. (3) Clock calendar data in BCD. Automatic leap year adjustment up to year 2100. (4) PM/AM = 1 for PM and 0 for AM. (5) DSE = 1 to enable daylight savings adjustment. (6) 24/12 = 1 to enable 24–hour data representation and 0 for 12–hour data representation. (7) Day of week coded as Sunday = 1 through Saturday = 7 (8) BVF = 1 for valid BC input (9) STOP = 1 to turn the RTC on and 0 stops the RTC in battery-backup mode 12 D0 0 6 A D3 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 Table 3. Clock and Control Register Map BIT DESCRIPTION 24/12 24- or 12-hour data representation ABE Alarm interrupt enable in battery-backup mode AF Alarm interrupt flag AIE Alarm interrupt enable ALM0–ALM1 Alarm mask bits BVF Battery-valid flag DSE Daylight savings enable PF Periodic interrupt flag PIE Periodic interrupt enable PM/AM PM or AM indication PWRF Power-fail interrupt flag PWRIE Power-fail interrupt enable RS0–RS3 Periodic interrupt rate STOP Oscillator stop and start UTI Update transfer inhibit WD0–WD2 Watchdog time-out rate CLOCK MEMORY INTERFACE The bq4802Y/bq4802LY has the same interface for clock/calendar and control information as standard SRAM. To read and write to these locations, the user must put the bq4802Y/bq4802LY in the proper mode and meet the timing requirements. READ MODE The bq4802Y/bq4802LY is in read mode whenever OE (output enable) is low and CS (chip select) is low. The unique address, specified by the four address inputs, defines which one of the 16 clock/calendar bytes is to be accessed. The bq4802Y/bq4802LY makes valid data available at the data I/O pins within tAA (address access time). This occurs after the last address input signal is stable, and providing the CS and OE (output enable) access times are met. If the CS and OE access times are not met, valid data is available after the latter of chip select access time (tACS) or output enable access time (tOE). CS and OE control the state of the eight three-state data I/O signals. If the outputs are activated before tAA, the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CS and OE remain low, output data remains valid for tOH (output data hold time), but goes indeterminate until the next address access. WRITE MODE The bq4802Y/bq4802LY is in write mode whenever WE and CS are active. The start of a write is referenced from the latter-occurring falling edge of WE or CS. A write is terminated by the earlier rising edge of WE or CS. The addresses must be held valid throughout the cycle. CS or WE must return high for a minimum of tWR2 from CS or tWR1 from WE prior to the initiation of another read or write cycle. Data-in must be valid tDW prior to the end of write and remain valid for tDH1 or tDH2 afterward. OE should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on CS and OE, a low on WE disables the outputs tWZ after WE falls. READING THE CLOCK Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real-time counters. To prevent reading data in transition, updates to the bq4802Y/bq4802LY clock registers should be halted. Updating is halted by setting the update transfer inhibit (UTI) bit D3 of the control register E. As long as the UTI bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the UTI bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the UTI bit, reading the clock locations has no effect on clock accuracy. Once the UTI bit is reset to 0, the internal registers update within one second the user-accessible registers with the correct time. A halt command issued during a clock update allows the update to occur before freezing the data. SETTING THE CLOCK The UTI bit must also be used to set the bq4802Y/bq4802LY clock. Once set, the locations can be written with the desired information in BCD format. Resetting the UTI bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second. STOPPING AND STARTING THE CLOCK OSCILLATOR The bq4802Y/bq4802LY clock can be programmed to turn off when the part goes into battery back-up mode by setting STOP to 0 prior to power down. If the board using the bq4802Y/bq4802LY is to spend a significant period of time in storage, the STOP bit can be used to preserve some battery capacity. STOP set to 1 keeps the clock running when VCC drops below VSO. With VCC greater than VSO, the bq4802Y/bq4802LY clock runs regardless of the state of STOP. POWER-DOWN/POWER-UP CYCLE The bq4802Y/bq4802LY continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below VPFD, the bq4802Y/bq4802LY write-protects the clock and storage registers. The power source is switched to BC when VCC is less than VPFD and BC is greater than VPFD, or when VCC is less than VBC and VBC is less than 13 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 VPFD. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VPFD, the power source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD. An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq4802Y/ bq4802LY. As the voltage input VCC slews down during a power failure, the chip enable output, CEOUT, is forced inactive independent of the chip enable input CEIN. This activity unconditionally write-protects the external SRAM as VCC falls below VPFD. If a memory access is in progress to the external SRAM during power-fail detection, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time tWPT, the chip enable output is unconditionally driven high, write-protecting the controlled SRAM. As the supply continues to fall past VPFD, an internal switching device forces VOUT to the external backup energy source. CEOUT is held high by the VOUT energy source. During power up, VOUT is switched back to the main supply as VCC rises above the backup cell input voltage sourcing VOUT. If VPFD < VBC on the bq4802Y/bq4802LY the switch to the main supply occurs at VPFD. CEOUT is held inactive for time tCER (200-ms maximum) after the power supply has reached VPFD, independent of the CEIN input, to allow for processor stabilization. During power-valid operation, the CEIN input is passed through to the CEOUT output with a propagation delay of less than 12 ns. Figure 2 shows the hardware hookup for the external RAM, battery, and crystal. A primary backup energy source input is provided on the bq4802Y/bq4802LY. The BC input accepts a 3-V primary battery, typically some type of lithium chemistry. Since the bq4802Y/bq4802LY provides for reverse battery charging protection, no diode or current limiting resistor is needed in series with the cell. To prevent battery drain when there is no valid data to retain, VOUT and CEOUT are internally isolated from BC by the initial connection of a battery. Following the first application of VCC above VPFD, this isolation is broken, and the backup cell provides power to VOUT and CEOUT for the external SRAM. The crystal should be located as close to X1 and X2 as possible and meet the specifications in the crystal specifications section of the electrical characteristics tables. With the specified crystal, the bq4802Y/bq4802LY RTC is accurate to within one minute per month at room temperature. In the absence of a crystal, a 32.768-kHz waveform can be fed into X1 with X2 grounded. The power source and crystal are integrated into the SNAPHAT modules. 14 Power-On Reset The bq4802Y/bq4802LY provides a power-on reset, which pulls the RST pin low on power down and remains low on power up for tRST after VCC passes VPFD. With valid battery voltage on BC, RST remains valid for VCC = VSS. Push-Button Reset The bq4802Y/bq4802LY also provides a push-button override to the reset when the device is not already in a reset cycle. When the RST pin is released after being pulled low for 1 µs then the RST stays low for 200 ms (typical). WATCHDOG TIMER The watchdog monitors microprocessor activity through the watchdog input (WDI). To use the watchdog function, connect WDI to a bus line or a microprocessor I/O line. If WDI remains high or low for longer than the watchdog time-out period (1.5 seconds default), the bq4802Y/ bq4802LY asserts WDO and RST. Watchdog Input The bq4802Y/bq4802LY resets the watchdog timer if a change of state (high-to-low, low-to-high, or a minimum 100 ns pulse) occurs at the watchdog input (WDI) during the watchdog period. The watchdog time-out is set by WD0 – WD2 in register B. The bq4802Y/bq4802LY maintains the watchdog time-out programming through power cycles. The default state (no valid battery power) of WD0 – WD2 is 000 or 1.5 s on power up. Table 3 shows the programmable watchdog time-out rates. The watchdog time-out period immediately after a reset is equal to the programmed watchdog time-out. To disable the watchdog function, leave WDI floating. An internal resistor network (100-kΩ equivalent impedance at WDI) biases WDI to approximately 1.6 V. Internal comparators detect this level and disable the watchdog timer. When VCC is below the power-fail threshold, the bq4802Y/bq4802LY disables the watchdog function and disconnects WDI from its internal resistor network, thus making it high impedance. Watchdog Output The watchdog output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The bq4802Y/bq4802LY disables the watchdog function and WDO is a logic high when VCC is below the power fail threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog time-out period, the bq4802Y/bq4802LY asserts RST for the reset time-out period t1. WDO goes low and remains low until the next transition at WDI. If WDI is held high or low indefinitely, RST generates pulses (t1 seconds wide) every t3 seconds. Figure 11 shows the watchdog timing. bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 WDI WDO t2 RST t1 t1 t3 Figure 11. Watchdog Time-Out Period and Reset Active Time Table 5. Periodic Interrupt Rates Table 4. Watchdog and Reset Timeout Rates WATCHDOG TIMEOUT PERIOD RESET TIMEOUT PERIOD WD2 WD1 WD0 0 0 0 1.50 s 0.25 ms RS3 RS2 RS1 RS0 0 0 1 23.4375 ms 3.9063 ms 0 0 0 0 NONE 0 1 0 46.875 ms 7.8125 ms 0 0 0 1 30.5175 µs 0 1 1 93.750 ms 15.625 ms 0 0 1 0 61.035 µs 1 0 0 187.5 ms 31.25 ms 0 0 1 1 122.070 µs 1 0 1 375 ms 62.5 ms 0 1 0 0 244.141 µs 1 1 0 750 ms 125 ms 0 1 0 1 488.281 µs 0.5 s 0 1 1 0 976.5625 µs 0 1 1 1 1.95315 ms 1 0 0 0 3.90625 ms 1 0 0 1 7.8125 ms 1 0 1 0 15.625 ms 1 0 1 1 31.25 ms 1 1 0 0 62.5 ms 1 1 0 1 125 ms 1 1 1 0 250 ms 1 1 1 1 500 ms 1 1 1 3.0 s INTERRUPTS The bq4802Y/bq4802LY allows three individually selected interrupt events to generate an interrupt request on the INT pin. These three interrupt events are: D The periodic interrupt, programmable to occur once every 30.5 µs to 500 ms. D The alarm interrupt, programmable to occur once per second to once per month. D The power-fail interrupt, which can be enabled to be asserted when the bq4802Y/bq4802LY detects a power failure. An individual interrupt-enable bit in register C, the interrupts register, enables the periodic, alarm and power-fail interrupts. When an event occurs, its event flag bit in the flags register, register D, is set. If the corresponding event enable bit is also set, then an interrupt request is generated. Reading the flags register clears all flag bits and makes INT high impedance. To reset the flag register, the bq4802Y/bq4802LY addresses must be held stable at register D for at least 50 ns to avoid inadvertent resets. Periodic Interrupt Bits RS3 – RS0 in the interrupt register program the rate for the periodic interrupt. The user can interpret the interrupt in two ways, either by polling the flags register for PF assertion or by setting PIE so that INT goes active when the bq4802Y/bq4802LY sets the periodic flag. Reading the flags register resets the PF bit and returns INT to the high-impedance state. Table 5 shows the periodic rates. REGISTER BITS PERIODIC INTERRUPT PERIOD ALARM INTERRUPT Registers 1, 3, 5, and 7 program the real-time clock alarm. During each update cycle, the bq4802Y/bq4802LY compares the date, hours, minutes, and seconds in the clock registers with the corresponding alarm registers. If a match between all the corresponding bytes is found, the alarm flag AF in the flags register is set. If the alarm interrupt is enabled with AIE, an interrupt request is generated on INT. The alarm condition is cleared by a read to the flags register. ALM1 – ALM0 in the alarm registers, mask each alarm compare byte. Setting ALM1 (D7) and ALM0 (D6) to 1 masks an alarm byte. Alarm byte masking can be used to select the frequency of the alarm interrupt, according to Table 6. The alarm interrupt can be made active while the bq4802Y/bq4802LY is in the batterybackup mode by setting ABE in the interrupts register. Normally, the INT pin goes high-impedance during battery backup. With ABE set, INT is driven low if an alarm condition occurs and the AIE bit is set. 15 bq4802Y bq4802LY www.ti.com SLUS464C – AUGUST 2000 – REVISED JUNE 2002 Table 6. Alarm Frequency 1h 3h 5h 7h ALM1–ALM0 ALM1–ALM0 ALM1–ALM0 ALM1–ALM0 ALARM FREQUENCY 1 1 1 1 Once per second 0 1 1 1 Once per minute when seconds match 0 0 1 1 Once per hour, when minutes and seconds match 0 0 0 1 Once per day, when hours, minutes and seconds match 0 0 0 0 When date, hours minutes and seconds match POWER–FAIL INTERRUPT BATTERY–LOW WARNING When VCC falls to the power-fail-detect point, the power-fail flag PWRF is set. If the power-fail interrupt enable bit (PWRIE) is also set, then INT is asserted low. The power-fail interrupt occurs tWPT before the bq4802Y/bq4802LY generates a reset and deselects. The bq4802Y/bq4802LY checks the battery on power-up. When the battery voltage is approximately 2.1 V, the battery valid flag BVF in the flags register is set to a 0 indicating that clock and RAM data may be invalid. 16 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) BQ4802LYDW ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802LYDW Samples BQ4802LYDWR ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802LYDW Samples BQ4802LYPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802LYPW Samples BQ4802LYPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802LYPW Samples BQ4802YDW ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802YDW Samples BQ4802YDWR ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802YDW Samples BQ4802YPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4802YPW Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of