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bq51020, bq51021
SLUSBX1 – MAY 2014
bq5102x 5-W (WPC) Single-Chip Wireless Power Receiver
1 Features
3 Description
•
The bq5102x device is a fully contained wireless
power receiver capable of operating with the WPC
v1.1 protocol which allows a wireless power system
to deliver up to 5 W to the system when used with a
Qi inductive transmitter. The bq5102x device provides
a single device power conversion (rectification and
regulation) as well as the digital control and
communication for WPC specification. With marketleading efficiency and adjustable output voltage, the
bq5102x device allows for unparalleled efficiency and
system optimization. I2C also allows system
designers to implement interesting new features such
as aligning a receiver on the transmitter surface, or
detecting foreign objects on the receiver. The receiver
allows for synchronous rectification, regulation and
control and communication to all exist in a market
leading form factor, efficiency, and solution size.
1
•
•
•
Robust 5-W Solution With 50% Lower Losses for
Improved Thermals
– Inductorless Receiver for Lowest Height Profile
Solution
– Adjustable Output Voltage (4.5 to 8 V) for Coil
and Thermal Optimization
– Fully Synchronous Rectifier With 96%
Efficiency
– 97% Efficient Post Regulator
– 79% System Efficiency at 5 W
WPC v1.1 Compliant Communication
Patented Transmitter Pad Detect Function
Improves User Experience
Alignment Feature Through I2C Allows for User
Training to Find Best Position on Surface of TX
2 Applications
•
•
•
•
Device Information(1)
PART NUMBER
bq51020
Smart Phones, Tablets, and Headsets
Wi-Fi Hotspots
Power Banks
Other Handheld Devices
bq51021
PACKAGE
BODY SIZE (NOM)
DSBGA (42)
3.60 × 2.89 mm2
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
bq5102X
System
Load
AD-EN
AD
bq5102x System Efficiency 5-V Out
OUT
CCOMM1
90
C4
COMM1
CBOOT1
BOOT1
R7
RECT
C1
80
C3
AC1
R6
C2
VO_REG
70
VTSB
60
AC2
CBOOT2
BOOT2
TS/CTRL
COMM2
z
z
CCOMM2
CCLAMP2
CCLAMP1
TMEM
CLAMP2
C5
CLAMP1
WPG
NTC
HOST
Efficiency (%)
COIL
50
40
30
PD_DET
TERM
SCL
CM_ILIM
SDA
ILIM
FOD
PGND
20
10
WPC A1 TX
0
R1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
IOUT (A)
1
1.1 1.2
D001
RFOD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq51020, bq51021
SLUSBX1 – MAY 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 19
8.5 Register Maps ......................................................... 22
1
1
1
1
2
3
5
9
Applications and Implementation ...................... 26
9.1 Application Information............................................ 26
9.2 Typical Applications ................................................ 26
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
Absolute Maximum Ratings ...................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 13
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
5 Revision History
2
DATE
REVISION
NOTES
May 2014
*
Initial release
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Device Comparison Table
Device
Mode
More
bq51221
Dual (WPC v1.1, PMA)
Adjustable output voltage, highest system efficiency, I2C
bq51021
WPC v1.1
Adjustable output voltage, highest system efficiency, I2C
bq51020
WPC v1.1
Adjustable output voltage, highest system efficiency, standalone
6 Pin Configuration and Functions
YFP (42 PINS)
A1
PGND
A2
PGND
A3
PGND
A4
PGND
A5
PGND
A6
PGND
B1
AC1
B2
AC1
B3
AC1
B4
AC2
B5
AC2
B6
AC2
C1
BOOT1
C2
RECT
C3
RECT
C4
RECT
C5
RECT
C6
BOOT2
D1
OUT
D2
OUT
D3
OUT
D4
OUT
D5
OUT
D6
OUT
E1
CLAMP1
E2
AD
E3
AD_EN
E4
SCL
EN1
E5
VTSB
E6
CLAMP2
F1
COMM1
F2
FOD
F3
TERM
F4
SDA
EN2
F5
WPG
F6
COMM2
G1
VO_REG
G2
ILIM
G3
CM_ILIM
G4
TS/CTRL
G5
TMEM
G6
PD_DET
Pin Functions
PIN
NAME
NUMBER
TYPE
DESCRIPTION
AC1
B1, B2, B3
I
AC2
B4, B5, B6
I
AD
E2
I
Adapter sense pin
AD-EN
E3
O
Push-pull driver for dual PFET circuit that can pass AD input to the OUT pin; used for adapter mux
control
BOOT1
C1
O
BOOT2
C6
O
CLAMP1
E1
O
CLAMP2
E6
O
COMM1
F1
O
COMM2
F6
O
CM_ILIM
G3
I
EN1
E4
I
EN2
F4
I
EN1 and EN2 are used for I2C communication in bq5020. Ground if not needed. SCL and SDA are
used in bq51021.
Input that is used for scaling the received power message
AC input power from receiver resonant tank
Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier
Open-drain FETs used to clamp the secondary voltage by providing low impedance across
secondary
Open-drain FETs used to communicate with primary by varying reflected impedance
Enables or disables communication current limit; can be pulled high to disable or pull low enable
communication current limit
FOD
F2
I
ILIM
G2
I/O
Output current or overcurrent level programming pin
OUT
D1, D2, D3, D4,
D5, D6
O
Output pin, used to deliver power to the load
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Pin Functions (continued)
PIN
NAME
PD_DET
NUMBER
TYPE
DESCRIPTION
G6
O
Open drain output that allows user to sense when receiver is on transmitter surface
PGND
A1, A2, A3, A4,
A5, A6
–
Power and logic ground
RECT
C2, C3, C4, C5
O
Filter capacitor for the internal synchronous rectifier
SCL
E4
I
SDA
F4
I
SCL and SDA are used for I2C communication in bq5021. Ground if not needed. EN1 and EN2 are
used in bq51020.
TERM
F3
I
Unused. Float in all WPC receivers
TMEM
G5
O
TMEM allows capacitor to be connected to GND so energy from transmitter ping can be stored to
retain memory of state
TS/CTRL
G4
I
Temperature sense. Can be pulled high to send end power transfer (EPT – charge complete) to TX.
Can be pulled low to send EPT – Overtemperature
VO_REG
G1
I
Sets the regulation voltage for output. Default value is 0.5 V
VTSB
E5
I
Voltage bias for temperature sense
WPG
F5
O
Open-drain output that allows user to sense when power is transferred to load
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
(2)
PIN
MIN
MAX
AC1, AC2
–0.8
20
RECT, COMM1, COMM2, OUT, , CLAMP1, CLAMP2, WPG,
PD_DET
–0.3
20
AD, AD-EN
–0.3
30
BOOT1, BOOT2
–0.3
20
SCL, SDA, TERM, CM_ILIM, FOD, TS/CTRL, ILIM, TMEM, VTSB,
VO_REG, LPRBEN
–0.3
7
UNIT
V
Input current
AC1, AC2 (RMS)
2.5
Output current
OUT
1.5
A
Output sink current
WPG, PD_DET
15
mA
Output sink current
COMM1, COMM2
1.0
A
TJ, junction temperature
(1)
(2)
A
–40
150
°C
All voltages are with respect to the PGND pin, unless otherwise noted.
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
Tstg
Storage temperature range
VESD
(2)
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins , 100 pF, 1.5 kΩ
discharge
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3)
(1)
(2)
(3)
(1)
MIN
MAX
–65
150
UNIT
°C
–2
2
kV
–500
500
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VRECT
RECT voltage
IOUT
Output current
IAD-EN
Sink current
ICOMM
COMMx sink current
TJ
Junction temperature
MIN
MAX
UNIT
4.0
10.0
V
1.0
0
A
1
mA
500
mA
125
ºC
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7.4 Thermal Information
THERMAL METRIC (1)
bq5102x
YFP (42 PINS)
RθJA
Junction-to-ambient thermal resistance (2)
49.7
RθJC(top)
Junction-to-case (top) thermal resistance (3)
0.2
(4)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter (5)
1.4
ψJB
Junction-to-board characterization parameter (6)
6.0
(1)
(2)
(3)
(4)
(5)
(6)
6
6.1
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) , ILOAD = IOUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.9
VUVLO
Undervoltage lockout
VRECT: 0 to 3 V
2.8
VHYS-UVLO
Hysteresis on UVLO
VRECT: 3 to 2 V
393
VRECT-OVP
Input overvoltage
threshold
VRECT: 5 to 16 V
VHYS-OVP
Hysteresis on OVP
VRECT: 16 to 5 V
VRECT(REG)
Voltage at RECT pin set
by communication with
primary
VRECT(TRACK)
VRECT regulation above
VOUT
VILIM = 1.2 V
ILOAD-HYS
ILOAD hysteresis for
dynamic VRECT thresholds
as a % of IILIM
ILOAD falling
VRECT-DPM
Rectifier under voltage
protection, restricts IOUT at
VRECT-DPM
VRECT-REV
Rectifier reverse voltage
protection with a supply at
the output
14.6
15.1
UNIT
15.6
1.5
VOUT + 0.120
V
mV
V
V
VOUT + 2.0
140
V
mV
4
3
3.1
3.2
V
VRECT-REV = VOUT – VRECT,
VOUT = 10 V
8.8
9.2
V
VOUT ≤ 5 V, 0°C ≤ TJ ≤ 85°C
20
35
µA
209
235
Ω
QUIESCENT CURRENT
IOUT(standby)
Quiescent current at the
output when wireless
power is disabled
ILIM SHORT CIRCUIT
RILIM-SHORT
Highest value of RILIM
resistor considered a fault
(short). Monitored for IOUT
> 100 mA
tDGL-Short
Deglitch time transition
from ILIM short to IOUT
disable
ILIM_SC
ILIM-SHORT,OK enables the
ILIM short comparator
when IOUT is greater than
this value
ILOAD: 0 to 200 mA
Hysteresis for ILIMSHORT,OK comparator
ILOAD: 200 to 0 mA
20
mA
Maximum output current
limit
Maximum ILOAD that can be
delivered for 1 ms when ILIM
is shorted
3.7
A
ILIM-SHORT,OK
HYSTERESIS
IOUT-CL
RILIM: 200 to 50 Ω. IOUT
latches off, cycle power to
reset
1
110
125
ms
140
mA
OUTPUT
VO_REG
Feedback voltage set
point
ILOAD = 1000 mA
0.4950
0.5013
0.5075
ILOAD = 1 mA
0.4951
0.5014
0.5076
KILIM
Current programming
factor for hardware short
circuit protection
RILIM = KILIM / IILIM, where IILIM
is the hardware current limit
IOUT = 850 mA
IOUT_RANGE
Current limit programming
range
ICOMM
Output current limit during
communication
AΩ
1500
IOUT ≥ 320 mA
IOUT – 50
100 mA ≤ IOUT < 320 mA
IOUT + 50
IOUT < 100 mA
tHOLD-OFF
842
Hold off time for the
communication current
limit during startup
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mA
200
1
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) , ILOAD = IOUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TS/CTRL
VTS-Bias
TS bias voltage (internal)
ITS-Bias < 100 µA and
communication is active
(periodically driven, see
tTS/CTRL-Meas)
VCTRL-HI
CTRL pin threshold for a
high
VTS/CTRL: 50 to 150 mV
TTS/CTRL-Meas
Time period of TS/CTRL
measurements, when TS
is being driven
TS bias voltage is only driven
when power packets are sent
VTS-HOT
Voltage at TS pin when
device shuts down
1.8
90
105
V
120
mV
1700
ms
0.38
V
THERMAL PROTECTION
TJ(OFF)
Thermal shutdown
temperature
155
°C
TJ(OFF-HYS)
Thermal shutdown
hysteresis
20
°C
OUTPUT LOGIC LEVELS ON WPG
VOL
Open drain WPG pin
ISINK = 5 mA
550
mV
IOFF,STAT
WPG leakage current
when disabled
VWPG = 20 V
1
µA
RDS-ON(COMM)
COMM1 and COMM2
VRECT = 2.6 V
fCOMM
Signaling frequency on
COMMx pin for WPC
IOFF,COMM
COMMx pin leakage
current
COMM PIN
1.0
Ω
2.00
Kb/s
VCOMM1 = 20 V, VCOMM2 = 20
V
1
µA
CLAMP PIN
RDS-ON(CLAMP)
CLAMP1 and CLAMP2
Ω
0.5
ADAPTER ENABLE
VAD-EN
VAD rising threshold
voltage
VAD 0 V to 5 V
VAD-EN-HYS
VAD-EN hysteresis
VAD 5 V to 0 V
IAD
Input leakage current
VRECT = 0 V, VAD = 5 V
RAD_EN-OUT
Pullup resistance from ADEN to OUT when adapter
VAD = 0 V, VOUT = 5 V
mode is disabled and
VOUT > VAD
VAD_EN-ON
Voltage difference
between VAD and VAD-EN
when adapter mode is
enabled
3.5
3.6
3.8
450
V
mV
50
μA
230
350
Ω
VAD = 5 V, 0°C ≤ TJ ≤ 85°C
4
4.5
5
V
VAD = 9 V, 0°C ≤ TJ ≤ 85°C
3
6
7
V
SYNCHRONOUS RECTIFIER
ISYNC-EN
IOUT at which the
synchronous rectifier
enters half synchronous
mode
IOUT: 200 to 0 mA
100
mA
ISYNC-EN-HYST
Hysteresis for IOUT,RECT-EN
(full-synchronous mode
IOUT 0 to 200 mA
enabled)
40
mA
VHS-DIODE
High-side diode drop when
IAC-VRECT = 250 mA, and
the rectifier is in half
TJ = 25°C
synchronous mode
0.7
V
8
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) , ILOAD = IOUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
I C (ONLY FOR bq51021)
VIL
Input low threshold level
SDA
V(PULLUP) = 1.8 V, SDA
VIH
Input high threshold level
SDA
V(PULLUP) = 1.8 V, SDA
VIL
Input low threshold level
SCL
V(PULLUP) = 1.8 V, SCL
VIH
Input high threshold level
SCL
V(PULLUP) = 1.8 V, SCL
I2C speed
Typical
0.4
1.4
V
0.4
1.4
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V
100
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7.6 Typical Characteristics
60
0.5015
50
Quiescent Current (PA)
0.50155
VO_REG (V)
0.50145
0.5014
0.50135
0.5013
30
20
10
0.50125
0.5012
0.0001
0
0.001
Temp = 25°C
0.01
Load Current (A)
0.1
1
4
7
8
9
D002
TX = bq500212A
Figure 2. Quiescent Current as a Function of Output Voltage
850
2.88
845
2.865
840
2.85
2.835
VUVLO (V)
830
825
820
2.82
2.805
2.79
2.775
815
2.76
810
2.745
805
250
350
450
550
650
750
Load Current (mA)
850
2.73
-60
950
-40
-20
0
D001
20
40
60
Temperature (qC)
80
100
120
140
D004
Figure 4. UVLO as a Function of Junction Temperature
Figure 3. KILIM as a Function of Load Current
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
VO_REG (V)
VO_REG (V)
6
VOUT (V)
835
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
0
1
2
3
4
I2C Code
5
6
7
0
1
D001
Figure 5. VO_REG by Different I2C Codes, 1-mA Load
10
5
D001
Figure 1. Output Regulation as a Function of Load
KILIM
40
2
3
4
I2C Code
5
6
7
D001
Figure 6. VO_REG by Different I2C Codes, 1-A Load
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8 Detailed Description
8.1 Overview
WPC-based wireless power systems consist of a charging pad (primary, transmitter) and the secondary-side
equipment (receiver). There are coils placed in the charging pad and secondary equipment, which magnetically
couple to each other when the receiver is placed on the transmitter. Power is transferred from the primary to the
secondary by transformer action between the coils. The receiver can achieve control over the amount of power
transferred by requesting the transmitter to change the field strength by changing the frequency, or duty cycle, or
voltage rail energizing the primary coil.
The receiver equipment communicates with the primary by modulating the load seen by the primary. This load
modulation results in a change in the primary coil current or primary coil voltage, or both, which is measured and
demodulated by the transmitter.
A WPC system communication is digital — packets are transferred from the secondary to the primary. Differential
bi-phase encoding is used for the packets. The bit rate is 2 kb/s. Various types of communication packets are
defined. These include identification and authentication packets, error packets, control packets, power usage
packets, and end power transfer packets, among others.
Power
AC to DC
Drivers
bq5102x
Rectification
Voltage/
Current
Conditioning
System
Load
Communication
Controller
Transmitter
V/I
Sense
Battery
Charger
Controller
LI-Ion
Battery
Receiver
Figure 7. Dual Mode Wireless Power System Indicating the Functional Integration of the bq5102x Family
The bq5102x device integrates fully-compliant WPC v1.1 communication protocol in order to streamline the
wireless power receiver designs (no extra software development required). Other unique algorithms such as
Dynamic Rectifier Control are integrated to provide best-in-class system efficiency while keeping the smallest
solution size of the industry.
As a WPC system, when the receiver (shown in Figure 7) is placed on the charging pad, the secondary coil
couples to the magnetic flux generated by the coil in the transmitter, which consequently induces a voltage in the
secondary coil. The internal synchronous rectifier feeds this voltage to the RECT pin, which in turn feeds the
LDO which feeds the output.
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Overview (continued)
The bq5102x device identifies itself to the primary using the COMMx pins, switching on and off the COMM FETs,
and hence switching in and out COMM capacitors. If the authentication is successful, the primary remains
powered-up. The bq5102x device measures the voltage at the RECT pin, calculates the difference between the
actual voltage and the desired voltage VRECT(REG), and sends back error packets to the transmitter. This process
goes on until the input voltage settles at VRECT(REG) MAX. During a load change, the dynamic rectifier algorithm
sets the targets specified by targets between VRECT(REG) MAX and VRECT(REG) MIN shown in Table 1. This algorithm
enhances the transient response of the power supply while still allowing for very high efficiency at high loads.
After the voltage at the RECT pin is at the desired value, an internal pass FET (LDO) is enabled. The voltage
control loop ensures that the output voltage is maintained at VOUT(REG), powering the downstream charger. The
bq5102x device meanwhile continues to monitor the RECT voltage, and keeps sending control error packets
(CEP) to the primary on average every 250 ms. If a large transient occurs, the feedback to the primary speeds
up to 32-ms communication periods to converge on an operating point in less time.
12
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8.2 Functional Block Diagram
,
OUT
VREF,ILIM
VILIM
+
_
+
_
RECT
VOUT,FB
VOUT,REG
VOREG
VREF,IABS
VIABS,FB
+
_
VIN,FB
VIN,DPM
+
_
ILIM
AD
+
_
VREFAD,OVP
BOOT2
+
_
BOOT1
VREFAD,UVLO
AD-EN
AC1
AC2
Sync
Rectifier
Control
VIREG
TS
COMM1
COMM2
ADC
DATA_OUT
CLAMP1
VBG,REF
VIN,FB
VOUT,FB
VILIM
VIABS,FB
TS/CTRL
VIABS,REF
VIC,TEMP
VFOD1
CLAMP2
VFOD2
Digital Control
LPRB1 or
WPG
OVP
+
_
VFOD
VRECT
VOVP,REF
SCL
LPRB2 or
PD_DET
SDA
FOD
SCL
SDA
50uA
CM_ILIM
TERM
+
_
TMEM
ILIM
LPRBEN or
TERM
PGND
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8.3 Feature Description
8.3.1 Dynamic Rectifier Control
The Dynamic Rectifier Control algorithm offers the end-system designer optimal transient response for a given
maximum output current setting. This is achieved by providing enough voltage headroom across the internal
regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a
relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target.
Therefore, a transient response is dependent on the loosely coupled transformer's output impedance profile. The
Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed
at the output of the internal regulator (output of the bq5102x device). A 1-A application allows up to a 2-Ω output
impedance. The Dynamic Rectifier Control behavior is illustrated in Figure 12.
8.3.2 Dynamic Power Scaling
The Dynamic Power Scaling feature allows for the loss characteristics of the bq5102x device to be scaled based
on the maximum expected output power in the end application. This effectively optimizes the efficiency for each
application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the
maximum output current. Note that the maximum output current is set by the KILIM term and the RILIM resistance
(where RILIM = KILIM / IILIM). The flow diagram in Figure 12 shows how the rectifier is dynamically controlled
(Dynamic Rectifier Control) based on a fixed percentage of the IILIM setting. Table 1 summarizes how the rectifier
behavior is dynamically adjusted based on two different RILIM settings. Table 1 shows IMAX, which is typically
lower than IILIM (about 20% lower). See section RILIM Calculations about setting the ILIM resistor for more
details.
Table 1. Dynamic Rectifier Regulation
Output Current Percentage
RILIM = 1400 Ω
IMAX = 0.5 A
RILIM = 700 Ω
IMAX = 1.0 A
VRECT
0 to 10%
0 to 0.05 A
0 to 0.1 A
VOUT + 2.0
10 to 20%
0.05 to 0.1 A
0.1 to 0.2 A
VOUT + 1.68
20 to 40%
0.1 to 0.2 A
0.2 to 0.4 A
VOUT + 0.56
> 40%
> 0.2 A
> 0.4 A
VOUT + 0.12
Table 1 shows the shift in the Dynamic Rectifier Control behavior based on the two different RILIM settings. With
the rectifier voltage (VRECT) as the input to the internal LDO, this adjustment in the Dynamic Rectifier Control
thresholds dynamically adjusts the power dissipation across the LDO where,
PDIS VRECT VOUT IOUT
(1)
Figure 21 shows how the system efficiency is improved due to the Dynamic Power Scaling feature. Note that this
feature balances efficiency with optimal system transient response.
8.3.3 VO_REG Calculations
The bq5102x device allows the designer to set the output voltage by setting a feedback resistor divider network
from the OUT pin to the VO_REG pin, as seen in Figure 8. The resistor divider network should be chosen so that
the voltage at the VO_REG pin is 0.5 V at the desired output voltage. For the device bq51021 which has I2C
enabled, this applies to the default I2C code for VO_REG shown in I2C register in Figure 8.
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OUT
R7
VO_REG
R6
Figure 8. VO_REG Network
Choose the desired output voltage VOUT and R6:
0.5 V
K VO
VOUT
R6
(2)
K VO u R 7
1 K VO
(3)
8.3.4 RILIM Calculations
The bq5102x device includes a means of providing hardware overcurrent protection (IILIM) through an analog
current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum
allowable output current (for example, current compliance). The RILIM resistor size also sets the thresholds for the
dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The
calculation for the total RILIM resistance is as follows:
RILIM = KILIM / IILIM
R1 = RILIM – RFOD
(4)
(5)
RILIM allows for the ILIM pin to reach 1.2 V at an output current equal to IILIM. When choosing RILIM, two options
are possible.
If the user's application requires an output current equal to or greater than the external IILIM that the circuit is
designed for (input current limit on the charger where the receiver device is tied higher than the external IILIM),
ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver
device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output
does not drop to 0. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on
the charger, the charger will pull the output of the receiver device to ground when the receiver device enters
current regulation. If the user's applications are designed to extract less than the IILIM (1-A maximum), typical
designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10%
more than maximum current is drawn from the output. Such a design would have input current limit on the
charger lower than the external ILIM of the receiver device. In both cases, the charger must be capable of
regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same
behavior is also necessary during the WPC communication. The following calculations show how such a design
is achieved:
RILIM = KILIM / (1.1 × IILIM)
R1 = RILIM – RFOD
(6)
where ILIM is the hardware current limit
(7)
When referring to the application diagram shown in Typical Applications, RILIM is the sum of the R1 and RFOD
resistance (that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the application.
The tool for calculating RFOD can be obtained by contacting your TI representative. Use RFOD to allow the
receiver implementation to comply with WPC v1.1 requirements related to received power accuracy. For the
device bq51021 which has I2C enabled, this applies to the default I2C code for IO_REG (100%) shown in I2C
register in Figure 8.
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8.3.5 Adapter Enable Functionality
The bq5102x device can also help manage the multiplexing of adapter power to the output and can turn off the
TX when the adapter is plugged in and is above the VAD-EN. After the adapter is plugged in and the output turns
off, the RX device sends an EOC to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V
below AD, which allows the device turn on the back-to-back PMOS connected between AD and OUT (Figure 28).
Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. It must also be noted that it is
required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions.
Also, when AD mode is enabled, no load can be pulled from the RECT pin as this could cause an internal device
overvoltage in the bq5102x device.
For the device bq51021, the wired power will always take priority over wireless power, and thus when the
adapter is plugged in, the device will first send an EPT to the TX and then will send allow for up to 30 ms after
disabling the output allowing the WPG to go high impedance. It will then allow the wired power to be delivered to
the output by pulling the AD_EN below the AD pin to allow the adapter power to be passed on the output.
For the device bq51020, the EN1 and EN2 pins will determine the preference of wired or wireless power. Table 2
shows the EN1 and EN2 state and the corresponding device selection.
Table 2. Adapter Functionality EN1 and EN2
(1)
EN1
EN2
Adapter Insert
AD_EN
EPT Message
Preference
0
0
5V
VAD – 4 V
EPT 0x00
Wired preference
0
1
5V
VOUT / VAD
No EPT
Wireless preference
1
0
5V
VAD – 4 V
EPT 0x00
Wired preference (1)
1
1
5V
VOUT / VAD
EPT 0x00
Neither wired nor
wireless (1)
Only valid when wireless power is present.
8.3.6 Turning Off the Transmitter
WPC v1.1 specification allows the receiver to turn off the transmitter and put the system in a low-power standby
mode. There are two different ways to accomplish this with the bq5102x device. The first method is by using the
TS/CTRL pin. By pulling the pin high or low, EPT can be sent to the transmitter.
Pulling the TS/CTRL pin high will send EPT (code 0x01), which corresponds to charge complete. The transmitter
will then respond to this EPT code as per the transmitter's design. After this EPT code is sent, some transmitters
will then periodically check to make sure that the receiver is not looking for a refresh charge on the battery. The
period of how often the transmitter checks varies based on the transmitter design. The transmitter will use the
digital ping or a shortened version of it to check the receiver status. It is this energy on the digital ping that the
receiver uses to indicate whether it is still sitting on the transmitter surface by storing the energy from the digital
ping on the capacitor attached to the TMEM pin. The cap voltage (determined by the periodicity of the digital ping
and the bleed off resistor attached in parallel to the TMEM cap) determine when the receiver indicates that it is
no longer on the surface of the transmitter by allowing the PD_DET pin to go high impedance.
The TS/CTRL pin can also be pulled low. This will allow the receiver to determine that the host processor would
like to shut down the transmitter because of thermal reasons. Therefore, the receiver will send EPT (code 0x03)
indicating an overtemperature event.
8.3.6.1 End Power Transfer (EPT)
The WPC allows for a special command to terminate power transfer from the TX termed EPT packet. The v1.1
specifies the following reasons and their responding data field value in Table 3.
Table 3. End Power Transfer Codes in WPC
Reason
Unknown
0x00
AD > 3.6 V
Charge complete
0x01
TS/CTRL > 1.4V
(1)
16
Condition (1)
Value
The Condition column corresponds to the case where the bq5102x device will send the WPC EPT
command.
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Table 3. End Power Transfer Codes in WPC (continued)
Reason
Condition (1)
Value
Internal fault
0x02
TJ > 150°C or RILIM < 100 Ω
Over temperature
0x03
TS < VHOT, or TS/CTRL < 100 mV
Over voltage
0x04
VRECT target does not converge and stays higher or lower than target
Battery failure
0x06
Not sent
Reconfigure
0x07
Not sent
No response
0x08
Not sent
8.3.7 Communication Current Limit
Communication current limit is a feature that allows for error free communication to happen between the RX and
TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current
during communication with the TX. The communication current limit is set according to the Table 4. The
communication current limit can be disabled by pulling CM_ILIM pin high (> 1.4 V) or enabled by pulling the
CM_ILIM pin low. There is an internal pulldown that enables communication current limit when the CM_ILIM pin
is left floating.
Table 4. Communication Current Limit
IOUT
Communication Current Limit
0 mA < IOUT < 100 mA
None
100 mA < IOUT < 320 mA
IOUT + 50 mA
320 mA < IOUT < Max current
IOUT – 50 mA
When the communication current limit is enabled, the amount of current that the load can draw is limited. If the
charger in the system does not have a VIN-DPM feature, the output of the receiver will collapse if communication
current limit is enabled. To disable communication current limit, pull CM_ILIM pin high.
8.3.8
PD_DET and TMEM
PD_DET is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM
is higher than 1.6 V, PD_DET will be low. The voltage on the TMEM pin depends on capturing the energy from
the digital ping from the transmitter and storing it on the C5 capacitor in Figure 9. After the receiver sends an EPT
(charge complete), the transmitter shuts down and goes into a low-power mode. After this EPT code is sent,
some transmitters will then periodically check to make sure that the receiver is not looking for a refresh charge
on the battery. The period of how often the transmitter checks varies based on the transmitter design. The
transmitter will use the digital ping or a shortened version of it to check the receiver status. It is this energy on the
digital ping that the receiver uses to indicate whether it is still sitting on the transmitter surface by storing the
energy from the digital ping on the capacitor attached to the TMEM pin. The cap voltage (determined by the
periodicity of the digital ping and the bleed off resistor attached in parallel to the TMEM cap) determine when the
receiver indicates that it is no longer on the surface of the transmitter by allowing the PD_DET pin to go high
impedance. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes
the capacitor. A bleedoff resistor RMEMcan be chosen in parallel with C5 that sets the time constant so that the
TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is
indeterminate and depends on each transmitter manufacturer.
TMEM
C5
RMEM
Figure 9. TMEM Configuration
Set capacitor on C5 = TMEM to 2.2 µF. Resistor RMEM across C5 can be set by understanding the duration
between digital pings (tping). Set the resistor such that:
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tping
4 u C5
(8)
PD_DET typically requires a pullup resistor to an external source. The choice of the pullup resistor determines
load regulation; the suggested values for the pullup resistor are between 5.6 and 100 kΩ. The higher values offer
better load regulation.
8.3.9 TS/CTRL
The bq5102x device includes a ratio metric external temperature sense function. The temperature sense function
has a low ratio metric threshold which represents a hot condition. TI recommends an external temperature
sensor in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring
the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC)
resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to
adjust the NTC to match the trip point of the device. The implementation in Figure 10 shows the series-parallel
resistor implementation for setting the threshold at which VTS-HOT is reached. Once the VTS-HOT threshold is
reached, the device will send an EPT – overtemperature signal for a WPC transmitter.
VTSB
(1.8 V)
R2
20 k
TS/CTRL
R1
NTC
R3
Figure 10. NTC Resistor Setup
Figure 10 shows a parallel resistor setup that can be used to adjust the trip point of VTS-HOT. TS-HOT is VS. After
the NTC is chosen and RNTCHOT at VTS-HOT is determined from the data sheet of the NTC, Equation 9 can be
used to calculate R1 and R3. In many cases depending on the NTC resistor, R1 or R3 can be omitted. To omit R1,
set R1 to 0, and to omit R3, set R3 to 10 MΩ.
TS H O T
1 .8 V u
R NTCHOT
R1 u R 3 y
R NTCHOT R1 u R 3 y
R NTCHOT
R1 R 3
R NTCHOT R1 R 3
R2
(9)
8.3.10 I2C Communication
Only bq51021
The bq5102x device allows for I2C communication with the internal CPU. In case the I2C is not used, ground SCL
and SDA. See Register Maps for more information.
8.3.11 Input Overvoltage
If the input voltage suddenly increases in potential for some condition (for example, a change in position of the
equipment on the charging pad), the voltage-control loop inside the bq5102x device becomes active, and
prevents the output from going beyond VOUT(REG). The receiver then starts sending back error packets every 30
ms until the input voltage comes back to an acceptable level, and then maintains the error communication every
250 ms.
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If the input voltage increases in potential beyond VRECT-OVP, the device switches off the LDO and informs the
primary to bring the voltage back to VRECT(REG). In addition, a proprietary voltage protection circuit is activated by
means of CCLAMP1 and CCLAMP2 that protects the device from voltages beyond the maximum rating of the device.
8.4 Device Functional Modes
At startup operation, the bq5102x device must comply with proper handshaking to be granted a power contract
from the WPC transmitter. The transmitter initiates the handshake by providing an extended digital ping after
analog ping detects an object on the transmitter surface. If a receiver is present on the transmitter surface, the
receiver then provides the signal strength, configuration, and identification packets to the transmitter (see volume
1 of the WPC specification for details on each packet). These are the first three packets sent to the transmitter.
The only exception is if there is a true shutdown condition on the AD, or TS/CTRL pins where the receiver shuts
down the transmitter immediately. See Table 3 for details. After the transmitter has successfully received the
signal strength, configuration, and identification packets, the receiver is granted a power contract and is then
allowed to control the operating point of the power transfer. With the use of the bq5102x device Dynamic
Rectifier Control algorithm, the receiver will inform the transmitter to adjust the rectifier voltage approximately 8V
prior to enabling the output supply. This method enhances the transient performance during system startup. For
the startup flow diagram details, see Figure 11.
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Device Functional Modes (continued)
Tx Powered
without Rx
Active
Tx Extended Digital Ping
EN1/EN2/AD/TS-CTRL
EPT Condition?
Yes
Send EPT packet with
reason value
No
Identification,
Configuration, and SS,
Received by Tx?
No
Yes
Power Contract
Established. All
proceeding control is
dictated by the Rx.
Yes
Is VRECT < 8 V?
Send control error packet
to increase VRECT
No
Startup operating point
established. Enable the
Rx output.
Rx Active
Power Transfer
Stage
Figure 11. Wireless Power Startup Flow Diagram on WPC TX
After the startup procedure is established, the receiver will enter the active power transfer stage. This is
considered the main loop of operation. The Dynamic Rectifier Control algorithm determines the rectifier voltage
target based on a percentage of the maximum output current level setting (set by KILIM and the RILIM). The
receiver will send control error packets in order to converge on these targets. As the output current changes, the
rectifier voltage target dynamically changes. As a note, the feedback loop of the WPC system is relatively slow, it
can take up to 150 ms to converge on a new rectifier voltage target. It should be understood that the
instantaneous transient response of the system is open loop and dependent on the receiver coil output
impedance at that operating point. The main loop also determines if any conditions in Table 3 are true in order to
discontinue power transfer. Figure 12 shows the active power transfer loop.
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Device Functional Modes (continued)
RX Active Power
Transfer Stage
RX Shutdown
conditions per the
EPT Table?
Yes
Send EPT packet with reason
value
TX Powered
without RX
Active
No
Yes
VRECT target = VO + 2 V.
Send control error packets to
converge.
Yes
VRECT target = VO + 1.3 V.
Send control error packets to
converge.
Yes
VRECT target = VO + 0.6 V.
Send control error packets to
converge.
VILIM < 0.1 V?
No
VILIM < 0.2 V
No
VILIM < 0.4 V
No
VRECT target = VO + 0.12 V.
Send control error packets to
converge.
Measure Received Power
and Send Value to TX
Figure 12. Active Power Transfer Flow Diagram on WPC
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8.5 Register Maps
Locations 0x01 and 0x02 can be written to any time. Locations 0xE0 to 0xFF are only functional when VRECT >
VUVLO. When VRECT goes below VUVLO, locations 0xE0 to 0xFF are reset.
Table 5. Wireless Power Supply Current Register 1 (READ / WRITE)
Memory Location: 0x01, Default State: 00000001
BIT
NAME
READ / WRITE
FUNCTION
B7 (MSB)
Read / Write
Not used
B6
Read / Write
Not used
B5
Read / Write
Not used
B4
Read / Write
Not used
B3
Read / Write
Not used
B2
VOREG2
Read / Write
B1
VOREG1
Read / Write
B0
VOREG0
Read / Write
450, 500, 550, 600, 650, 700, 750, or 800 mV
Changes VO_REG target
Default value 001
SPACE
Table 6. Wireless Power Supply Current Register 2 (READ / WRITE)
Memory Location: 0x02, Default State: 00000111
BIT
NAME
READ / WRITE
B7 (MSB)
JEITA
Read / Write
Not used
Read / Write
Not used
B6
B5
ITERM2
Read / Write
B4
ITERM1
Read / Write
B3
ITERM0
Read / Write
B2
IOREG2
Read / Write
B1
IOREG1
Read / Write
B0
IOREG0
Read / Write
FUNCTION
Not used for bq5102x
10%, 20%, 30%, 40%, 50%, 60%, 90%, and 100% of IILIM current
based on configuration
000, 001, …111
SPACE
Table 7. I2C Mailbox Register (READ / WRITE)
Memory Location: 0xE0, Reset State: 10000000
BIT
NAME
READ / WRITE
B7
USER_PKT_DONE
Read
Set bit to 0 to send proprietary packet with header in 0xE2.
CPU checks header to pick relevant payload from 0xF1 to 0xF4
This bit will be set to 1 after the user packet with the header in register
0xE2 is sent.
B6
USER_PKT_ERR
Read
00
01
10
11
B4
FOD Mailer
Read / Write
Not used
B3
ALIGN Mailer
Read / Write
Setting this bit to 1 will enable alignment aid mode where the CEP = 0
will be sent until this bit is set to 0 (or CPU reset occurs) – see register
0xED
B2
FOD Scaler
Read / Write
Not used
B1
Reserved
Read / Write
B0
Reserved
Read / Write
B5
22
FUNCTION
= No error in sending packet
= Error: no transmitter present
= Illegal header found (packet will not be sent)
= Error: not defined yet
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Table 8. Wireless Power Supply FOD RAM (READ / WRITE)
Memory Location: 0xE1, Reset State: 00000000 (1)
(1)
BIT
NAME
READ / WRITE
FUNCTION
B7 (MSB)
ESR_ENABLE
Read / Write
Enables I2C based ESR in received power, Enable = 1, Disable = 0
B6
OFF_ENABLE
Read / Write
Enables I2C based offset power, Enable = 1, Disable = 0
B5
RoFOD5
Read / Write
B4
RoFOD4
Read / Write
B3
RoFOD3
Read / Write
000 – 0 mW
001 – +39 mW
010 – +78 mW
011 – +117 mW
100 – +156 mW
101 – +195 mW
110 – +234 mW
111 – +273 mW
The value is added to received power
message
B2
RsFOD2
Read / Write
B1
RsFOD1
Read / Write
101 – Not used
110 – Not used
111 – ESR/2
B0
RsFOD0
Read / Write
000 – ESR
001 – ESR
010 – ESR × 2
011 – ESR × 3
100 – ESR × 4
A non-zero value will change the I2R calculation resistor and offset in the received power calculation by a factor shown in the table.
SPACE
Table 9. Wireless Power User Header RAM (WRITE)
Memory Location: 0xE2, Reset State: 00000000 (1)
(1)
BIT
READ / WRITE
B7 (MSB)
Read / Write
B6
Read / Write
B5
Read / Write
B4
Read / Write
B3
Read / Write
B2
Read / Write
B1
Read / Write
B0
Read / Write
Must write a valid header to enable proprietary package. As soon as mailer (0xE0) is written, payload bytes are sent on the next
available communication slot as determined by CPU. After payload is sent, the mailer (USER_PKT_DONE) is set to 1.
SPACE
Table 10. Wireless Power USER VRECT Status RAM (READ) (1)
Memory Location: 0xE3, Reset State: 00000000
Range – 0 to 12 V
This register reads back the VRECT voltage with LSB = 46 mV
(1)
BIT
NAME
READ / WRITE
B7 (MSB)
VRECT7
Read
B6
VRECT6
Read
B5
VRECT5
Read
B4
VRECT4
Read
B3
VRECT3
Read
B2
VRECT2
Read
B1
VRECT1
Read
B0
VRECT0
Read
FUNCTION
LSB = 46 mV
VRECT is above UVLO.
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Table 11. Wireless Power VOUT Status RAM (READ) (1)
Memory Location: 0xE4, Reset State: 00000000
This register reads back the VOUT voltage with LSB = 46 mV
(1)
BIT
NAME
Read / Write
B7 (MSB)
VOUT7
Read / Write
B6
VOUT6
Read / Write
B5
VOUT5
Read / Write
B4
VOUT4
Read / Write
B3
VOUT3
Read / Write
B2
VOUT2
Read / Write
B1
VOUT1
Read / Write
B0
VOUT0
Read / Write
FUNCTION
LSB = 46 mV
Ouput is enabled.
SPACE
Table 12. Wireless Power REC PWR Most Significant Byte Status RAM (READ)
Memory Location: 0xE8, Reset State: 00000000
This register reads back the received power with LSB = 39 mW
BIT
Read / Write
B7 (MSB)
Read / Write
B6
Read / Write
B5
Read / Write
B4
Read / Write
B3
Read / Write
B2
Read / Write
B1
Read / Write
B0
Read / Write
SPACE
Table 13. Wireless Power Prop Packet Payload RAM Byte 0 (WRITE)
Memory Location: 0xF1, Reset State: 00000000
BIT
Read / Write
B7 (MSB)
Read / Write
B6
Read / Write
B5
Read / Write
B4
Read / Write
B3
Read / Write
B2
Read / Write
B1
Read / Write
B0
Read / Write
SPACE
Table 14. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE)
Memory Location: 0xF2, Reset State: 00000000
24
BIT
Read / Write
B7 (MSB)
Read / Write
B6
Read / Write
B5
Read / Write
B4
Read / Write
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Table 14. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE) (continued)
Memory Location: 0xF2, Reset State: 00000000
BIT
Read / Write
B3
Read / Write
B2
Read / Write
B1
Read / Write
B0
Read / Write
SPACE
Table 15. Wireless Power Prop Packet Payload RAM Byte 2 (WRITE)
Memory Location: 0xF3, Reset State: 00000000
BIT
Read / Write
B7 (MSB)
Read / Write
B6
Read / Write
B5
Read / Write
B4
Read / Write
B3
Read / Write
B2
Read / Write
B1
Read / Write
B0
Read / Write
SPACE
Table 16. Wireless Power Prop Packet Payload RAM Byte 3 (WRITE)
Memory Location: 0xF4, Reset State: 00000000
BIT
Read / Write
B7 (MSB)
Read / Write
B6
Read / Write
B5
Read / Write
B4
Read / Write
B3
Read / Write
B2
Read / Write
B1
Read / Write
B0
Read / Write
SPACE
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9 Applications and Implementation
9.1 Application Information
The bq5102x device complies with the WPC v1.1 standard. There are several tools available for the design of
the system. These tools may be obtained by checking the product page at www.ti.com. The following sections
detail how to design a WPC v1.1 mode RX system.
9.2 Typical Applications
9.2.1 WPC Power Supply 5-V Output With 1-A Maximum Current and I2C
System
Load
Q1
bq51021
AD-EN
AD
OUT
CCOMM1
C4
COMM1
CBOOT1
BOOT1
R7
RECT
C1
C3
AC1
R6
COIL
VO_REG
C2
VTSB
AC2
CBOOT2
R9
BOOT2
TS/CTRL
COMM2
z
z
CCOMM2
CCLAMP2
CCLAMP1
TMEM
CLAMP2
NTC
HOST
C5
CLAMP1
WPG
PD_DET
GPIO
TERM
SCL
SCL
CM_ILIM
SDA
SDA
ILIM
FOD
R1
ROS
PGND
RECT
RFOD
Figure 13. WPC 5-W Schematic Using bq5102x
26
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Typical Applications (continued)
9.2.1.1 Design Requirements
Table 17. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VOUT
5V
IOUT MAXIMUM
1A
MODE
WPC v1.1
9.2.1.2 Detailed Design Procedure
To
•
•
•
begin the design procedure, start by determining the following:
Mode of operation – in this case WPC v1.1
Output voltage
Maximum output current
9.2.1.2.1 Output Voltage Set Point
The output voltage of the bq5102x device can be set by adjusting a feedback resistor divider network. The
resistor divider network is used to set the voltage gain at the VO_REG pin. The device is intended to operate
where the voltage at the VO_REG pin is set to 0.5 V. This value is the default setting and can be changed
through I2C (for the device bq51021). In Figure 14, R6 and R7 are the feedback network for the output voltage
sense.
OUT
C4
R7
R6
VO_REG
Figure 14. Voltage Gain for Feedback
K VO
R6
0.5 V
VOUT
(10)
K VO u R 7
1 K VO
(11)
Choose R7 to be a standard value. In this case, take care to choose R6 and R7 to be large values in order to
avoid dissipating excessive power in the resistors, and thereby lowering efficiency.
KVO is set to be 0.5 / 5 = 0.1, choose R7 to be 102 kΩ, and thus R6 to be 11.3 kΩ.
9.2.1.2.2 Output and Rectifier Capacitors
Set C4 between 1 and 4.7 µF. This example uses 1 µF.
Set C3 between 4.7 and 22 µF. This example uses 20 µF.
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9.2.1.2.2.1 TMEM
Set C5 to 2.2 µF. In order to determine the bleed off resistor, the WPC transmitters for which the PD_DET is
being set for needs to be determined. After the ping timing (time between two consecutive digital pings after EPT
charge complete is sent) is determined, the bleedoff resistor can be determined. This example uses TI
transmitter EVMs for the use case. In this case, the time between pings is 5 s. To set the time constant using the
Equation 8, it is set to 5600 kΩ.
9.2.1.2.3 Maximum Output Current Set Point
ILIM
FOD1
R1
ROS
RECT
RFOD
Figure 15. Current Limit Setting for bq5102x
The bq5102x device includes a means of providing hardware overcurrent protection by means of an analog
current regulation loop. The hardware current limit provides a level of safety by clamping the maximum allowable
output current (for example, a current compliance). The RILIM resistor size also sets the thresholds for the
dynamic rectifier levels and thus providing efficiency tuning per each application’s maximum system current. The
calculation for the total RILIM resistance is as follows:
R IL IM
R1
K IL IM
I IL IM
(12)
R IL IM R F O D
(13)
The RILIM will allow for the ILIM pin to reach 1.2 V at an output current equal to IILIM. When choosing RILIM, two
options are possible.
If the application requires an output current equal to or greater than external ILIM that the circuit is designed for
(input current limit on the charger where the RX is delivering power to is higher than the external ILIM), ensure
that the downstream charger is capable of regulating the voltage of the input into which the RX device output is
tied to by lowering the amount of current being drawn. This will ensure that the RX output does not collapse.
Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the
charger will pull the output of the RX device to ground when the RX device enters current regulation.
If the applications are designed to extract less than the ILIM (1-A maximum), typical designs should leave a
design margin of at least 20% so that the voltage at ILIM pin reaches 1.2 V when 20% more than maximum
current of the system is drawn from the output of the RX. Such a design would have input current limit on the
charger lower than the external ILIM of the RX device.
In both cases, the charger must be capable of regulating the current drawn from the device to allow the output
voltage to stay at a reasonable value. This same behavior is also necessary during the WPC V1.1
Communication. See Communication Current Limit for more details. The following calculations show how such a
design is achieved:
R IL IM
R1
28
K IL IM
1 .2 u I IL IM
(14)
R IL IM R F O D
(15)
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When referring to the application diagram shown in Figure 15, RILIM is the sum of the R1 and RFOD resistance
(that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the FOD application note that
can be obtained by contacting your TI representative. This is used to allow the RX implementation to comply with
WPC v1.1 requirements related to received power accuracy.
In many applications, the resistor ROS is needed in order to comply with WPC V1.1 requirements. In such a case,
the offset on the FOD pin from the voltage on RFOD can cause a shift in the calculation that can reduce the
expected current limit. Therefore, it is always a good idea to check the output current limit after FOD calibration is
performed according to the FOD application note. Because the RECT voltage is not deterministic, and depends
on transmitter operation to a certain degree, it is not possible to determine R1 with ROS present in a deterministic
manner.
In this example, set maximum current for the example to be 1000 mA. Set IILIM = 1.2 A to allow for the 20%
margin.
840
R IL IM
700 :
1 .2
(16)
9.2.1.2.4 TERM Pin
The term pin is not used for bq5102x. Leave the pin floating.
9.2.1.2.5 I2C
The I2C lines are used to communicate with the device. To enable the I2C, they can be pulled up to an internal
host bus. The device address is 0x6C. I2C is enabled only for the device bq51021.
9.2.1.2.6 Communication Current Limit
Communication current limit allows the device to communicate with the transmitter in an error free manner by
decoupling the coil from load transients on the OUT pin during WPC communication. This is done by setting the
current limit in a manner that is consistent with Table 4. However, this will require the downstream charger to
have a function such as VIN_DPM. In some cases this communication current limit feature is not desirable if the
charger does not have this feature. In this design, the user enables the communication current limit by tying the
CM_ILIM pin to GND. In the case that this is not needed, the CM_ILIM pin can be tied to OUT pin to disable the
communication current limit. In this case, take care that the voltage on the CM_ILIM pin does not exceed the
maximum rating of the pin which is 7 V.
9.2.1.2.7 Receiver Coil
The receiver coil design is the most open part of the system design. The choice of the receiver inductance,
shape, and materials all intimately influence the parameters themselves in an intertwined manner. This design
can be complicated and involves optimizing many different aspects; refer to the user's guide for the EVM
(SLUUAX6).
The typical choice of the inductance of the receiver coil for a WPC only 5-V solution is between 8 to 11 µH
depending on the mutual inductance between the transmitter coil and the receiver coil.
9.2.1.2.8 Series and Parallel Resonant Capacitors
Resonant capacitors C1 and C2 are set according to WPC specification.
The equations for calculating the values of the resonant capacitors are shown:
-1
é
ù
2
C = ê f × 2p × L' ú
1 ê S
Sú
ë
(
)
û
é
ù
2
C = ê f × 2p × L - 1 ú
2 ê D
S C ú
1û
ë
(
)
-1
(17)
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9.2.1.2.9 Communication, Boot, and Clamp Capacitors
Set CCOMMx to a value ranging from C1 / 8 to C1 / 3. Note that higher capacitors lower the overall efficiency of the
system. Make sure these are X7R ceramic material and have at least a minimum voltage rating of 25 V; TI
recommends a minimum voltage rating of 50 V.
Set CBOOTx to be 15 nF. Make sure these are X7R ceramic material and have at least a minimum voltage rating
of 25 V; TI recommends a minimum voltage rating of 50 V.
Set CCLAMPx to be 470 nF. Make sure these are X7R ceramic material and have at least a minimum voltage
rating of 25 V; TI recommends a minimum voltage rating of 50 V.
30
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9.2.1.3 Application Performance Plots
Figure 16. bq5102x No Load Start-up on a WPC TX
5000
5
4500
0
4000
-5
3500
-10
3000
-15
2500
-20
2000
-25
1500
-30
1000
-35
Min
Max
Difference
500
-40
0
0
600
IOUT (mA)
800
1000
-45
1200
D001
7.5
7.25
7
6.75
6.5
6.25
6
5.75
5.5
5.25
5
4.75
4.5
4.25
4
700 :
1400 :
0
Figure 20. TS Voltage Bias Without TS Resistor
400
Figure 19. Received Power Variation (mW) vs IOUT (mA) on
a WPC TX
VRECT (V)
Figure 18. 1000 to 0 mA Load Dump on a WPC TX
200
Differene in Max and Min Messages
Received Power (mW)
Figure 17. 0- to 1000-mA Step on a WPC TX
200
400
600
IOUT (mA)
800
1000
1200
D001
Figure 21. Rectifier Regulation as a Function or RILIM on a
WPC TX
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90
200
80
190
70
180
Frequency (kHz)
Efficiency (%)
SLUSBX1 – MAY 2014
60
50
40
30
170
160
150
140
130
20
120
10
110
0
100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
IOUT (A)
1
1.1 1.2
0
200
400
D001
Figure 22. bq5102x WPC Efficiency 5 V, 1 A on a WPC TX
600
IOUT (mA)
800
1000
1200
D001
Figure 23. Frequency Range of 5-V, 1-A RX on a WPC TX
8
5.115
VRECT ASC
VRECT DEC
7.5
5.1125
6.5
VOUT (V)
VRECT (V)
7
6
5.5
5.11
5.1075
5
5.105
4.5
4
5.1025
0
200
400
600
IOUT (mA)
800
1000
1200
0
200
D013
Figure 24. Dynamic Regulation, RILIM = 700 Ω on a
WPC TX
400
600
IOUT (mA)
800
1000
1200
D001
Figure 25. Output Regulation on a WPC TX
555
VO_REG
VRECT
554
553
IOUT (mA)
552
551
550
549
548
547
546
545
2.5
3
3.5
4
Voltage (V)
4.5
5
D015
Figure 26. Rect Foldback in Current Limit on a WPC TX
32
Figure 27. Start-Up WPC TX 7-V Out
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9.2.2 bq5102x Standalone in System Board or Back Cover
When the bq5102x device is implemented as an embedded device on the system board, the EN1 and EN2 pins
are the only differences from the previous design using I2C.
System
Load
Q1
bq51020
AD-EN
AD
OUT
CCOMM1
C4
COMM1
CBOOT1
BOOT1
R7
RECT
C1
C3
AC1
R6
COIL
VO_REG
C2
VTSB
AC2
CBOOT2
R9
BOOT2
TS/CTRL
COMM2
z
z
CCOMM2
CCLAMP2
CCLAMP1
TMEM
CLAMP2
HOST
NTC
C5
CLAMP1
WPG
PD_DET
GPIO
TERM
EN1
GPIO
CM_ILIM
EN2
GPIO
ILIM
FOD
R1
ROS
PGND
RECT
RFOD
Figure 28. bq5102x Embedded in a System Board
Refer to WPC Power Supply 5-V Output With 1-A Maximum Current and I2C for all design and application
details.
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10 Power Supply Recommendations
These devices are intended to be operated within the ranges shown in the Recommended Operating Conditions.
Because the system involves a loosely coupled inductor setup, the voltages produced on the receiver are a
function of the inductances and the available magnetic field. Ensure that the design in the worst case keeps the
voltages within the Absolute Maximum Ratings.
34
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
Keep the trace resistance as low as possible on AC1, AC2, and OUT.
Detection and resonant capacitors need to be as close to the device as possible.
COMM, CLAMP, and BOOT capacitors need to be placed as close to the device as possible.
Via interconnect on GND net is critical for appropriate signal integrity and proper thermal performance.
High frequency bypass capacitors need to be placed close to RECT and OUT pins.
ILIM and FOD resistors are important signal paths and the loops in those paths to GND must be minimized.
Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually
measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being
interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main
source of noise in the board. These traces should be shielded from other components in the board. It is
usually preferred to have a ground copper area placed underneath these traces to provide additional
shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB should have a
ground plane (return) connected directly to the return of all components through vias (two vias per capacitor
for power-stage capacitors, one via per capacitor for small-signal components.
For a 1-A fast charge current application, the current rating for each net is as follows:
• AC1 = AC2 = 1.2 A
• OUT = 1 A
• RECT = 100 mA (RMS)
• COMMx = 300 mA
• CLAMPx = 500 mA
• All others can be rated for 10 mA or less
11.2 Layout Example
AD is also a
power trace.
Keep the trace
resistance as
low as possible
on AC1, AC2,
and OUT.
Isolate noisy
traces using
GND trace.
Place signal and
sensing
components as
close as possible
to the IC.
Place detection
and resonant
capacitors Cd
and Cs here.
It is always a good
practice to place high
frequency bypass
capacitors next to RECT
and OUT.
The via interconnect is important and
must be optimized near the power pad
of the IC and the GND for good thermal
dissipation.
Place COMM,
CLAMP, and
BOOT capacitors
as close as
possible to the IC
terminals.
Figure 29. Layout Example for bq5102x
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 18. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq51020
Click here
Click here
Click here
Click here
Click here
bq51021
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
36
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ51020YFPR
ACTIVE
DSBGA
YFP
42
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BQ51020
BQ51020YFPT
ACTIVE
DSBGA
YFP
42
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BQ51020
BQ51021YFPR
ACTIVE
DSBGA
YFP
42
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BQ51021
BQ51021YFPT
ACTIVE
DSBGA
YFP
42
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
BQ51021
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
BQ51020YFPR
DSBGA
YFP
42
3000
330.0
12.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.99
3.71
0.81
8.0
12.0
Q1
BQ51020YFPT
DSBGA
YFP
42
250
330.0
12.4
2.99
3.71
0.81
8.0
12.0
Q1
BQ51021YFPR
DSBGA
YFP
42
3000
330.0
12.4
2.99
3.71
0.81
8.0
12.0
Q1
BQ51021YFPT
DSBGA
YFP
42
250
330.0
12.4
2.99
3.71
0.81
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ51020YFPR
DSBGA
YFP
42
3000
367.0
367.0
35.0
BQ51020YFPT
DSBGA
YFP
42
250
367.0
367.0
35.0
BQ51021YFPR
DSBGA
YFP
42
3000
367.0
367.0
35.0
BQ51021YFPT
DSBGA
YFP
42
250
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFP0042
DSBGA - 0.5 mm max height
SCALE 4.700
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.5 MAX
SEATING PLANE
BALL TYP
0.19
0.13
0.05 C
2 TYP
SYMM
G
F
D: Max = 3.586 mm, Min =3.526 mm
E
SYMM
2.4
TYP
E: Max = 2.874 mm, Min =2.814 mm
D
C
0.3
0.2
0.015
42X
B
C A
B
A
0.4 TYP
1
2
3
4
5
6
0.4 TYP
4221555/B 04/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFP0042
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
42X ( 0.23)
1
2
3
4
6
5
A
(0.4) TYP
B
C
SYMM
D
E
F
G
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
( 0.23)
METAL
0.05 MAX
METAL
UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221555/B 04/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0042
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
42X ( 0.25)
1
2
4
3
5
6
A
(0.4)
TYP
METAL
TYP
B
C
SYMM
D
E
F
G
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4221555/B 04/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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