BQ7694000DBTR

BQ76920, BQ76930, BQ76940 SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 BQ769x0 3-Series to 15-Series Cell Battery Monitor Family for Li-Ion and Phosphate Applications 1 Features 3 Description • The BQ769x0 family of robust analog front-end (AFE) devices serves as part of a complete pack monitoring and protection solution for next-generation, high-power systems, such as light electric vehicles, power tools, and uninterruptible power supplies. The BQ769x0 is designed with low power in mind: Subblocks within the IC may be enabled or disabled to control the overall chip current consumption, and a SHIP mode provides a simple way to put the pack into an ultra-low power state. • • AFE monitoring features – Pure digital interface – Internal ADC measures cell voltage, die temperature, and external thermistor – A separate, internal ADC measures pack current (coulomb counter) – Directly supports up to three thermistors (103AT) Hardware protection features – Overcurrent in Discharge (OCD) – Short Circuit in Discharge (SCD) – Overvoltage (OV) – Undervoltage (UV) – Secondary protector fault detection Additional features – Integrated cell balancing FETs – Charge, discharge low-side NCH FET drivers – Alert interrupt to host microcontroller – 2.5-V or 3.3-V output voltage regulator – No EEPROM programming necessary – High supply voltage absolute maximum (up to 108 V) – Simple I2C compatible interface (CRC option) – Random cell connection tolerant The BQ76920 device supports up to 5-series cells or typical 18-V packs, the BQ76930 handles up to 10-series cells or typical 36-V packs, and the BQ76940 works for up to 15-series cells or typical 48-V packs. A variety of battery chemistries may be managed with these AFEs, including Li-ion, Li-iron phosphate, and more. Through I2C, a host controller can use the BQ769x0 to implement many battery pack management functions, such as monitoring (cell voltages, pack current, pack temperatures), protection (controlling charge/discharge FETs), and balancing. Integrated A/D converters enable a purely digital readout of critical system parameters, with calibration handled in TI’s manufacturing process. 2 Applications • • • • Device Information PART NUMBER1 Light electric vehicles (LEV): eBikes, eScooters, pedelec, and pedal-assist bicycles Power tools and garden tools Battery backup units (BBUS), energy storage systems (ESS), and uninterruptible power supply (UPS) systems Other industrial battery packs (≥10S) PACKAGE BODY SIZE (NOM) BQ76920 TSSOP (20) 6.50 mm × 4.40 mm BQ76930 TSSOP (30) 7.80 mm × 4.40 mm BQ76940 TSSOP (44) 11.00 mm × 4.40 mm PACK + Rf BAT Rc Cc Rc Cc Rc VC 5 REGSRC VC 4 REGOUT VC 3 CAP 1 VC 2 TS 1 VC 1 SCL VC 0 10 kΩ 1 µF 1 µF Cf 4.7 µF 10 k SDA Cc Rc SRP VSS SRN CHG ALERT DSG PUSH - BUTTON FOR BOOT Cc VCC Rc Cc SCL SDA Cc Companion Controller GPIO 1M Rc VSS 0 .1 µF 0 .1 µF 100 0 .1 µF 100 1M 1M Rsns PACK – Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................3 6.1 Versions...................................................................... 3 6.2 BQ76920 Pin Diagram................................................ 4 6.3 BQ76930 Pin Diagram................................................ 5 6.4 BQ76940 Pin Diagram................................................ 6 7 Specifications.................................................................. 8 7.1 Absolute Maximum Ratings........................................ 8 7.2 ESD Ratings............................................................... 8 7.3 Recommended Operating Conditions.........................9 7.4 Thermal Information..................................................10 7.5 Electrical Characteristics...........................................10 7.6 Timing Requirements................................................ 14 7.7 Typical Characteristics.............................................. 15 8 Detailed Description......................................................16 8.1 Overview................................................................... 16 8.2 Functional Block Diagram......................................... 16 8.3 Feature Description...................................................17 8.4 Device Functional Modes..........................................27 8.5 Register Maps...........................................................29 9 Application and Implementation.................................. 38 9.1 Application Information............................................. 38 9.2 Typical Applications ................................................. 41 10 Power Supply Recommendations..............................46 11 Layout........................................................................... 47 11.1 Layout Guidelines................................................... 47 11.2 Layout Example...................................................... 47 12 Device and Documentation Support..........................49 12.1 Third-Party Products Disclaimer............................. 49 12.2 Documentation Support.......................................... 49 12.3 Related Links.......................................................... 49 12.4 Receiving Notification of Documentation Updates..49 12.5 Trademarks............................................................. 49 13 Mechanical, Packaging, and Orderable Information.................................................................... 49 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (March 2019) to Revision I (March 2022) Page • Changed the formatting throughout ................................................................................................................... 1 • Added VCn rows in Absolute Maximum Ratings table....................................................................................... 8 • Changed tablenote for POR and referenced entries........................................................................................ 10 • Changed the scale in the VCx and OV Protection plots .................................................................................. 15 • Updated 16-Bit Pack Voltage ...........................................................................................................................21 • Changed "OV Trip" to "UV Trip" in the description of undervoltage protection................................................. 21 • Changed the LSB bit count from 2 to 4 for the OV_TRIP register.................................................................... 30 • Updated Application Information ......................................................................................................................38 • Added Device Timing .......................................................................................................................................38 • Added Random Cell Connection ..................................................................................................................... 38 • Added Power Pin Diodes .................................................................................................................................38 • Added Alert Pin ................................................................................................................................................38 • Added Sense Inputs ........................................................................................................................................ 38 • Added TSn Pins ...............................................................................................................................................38 • Updated Unused Pins ......................................................................................................................................39 • Updated Step-by-Step Design Procedure ....................................................................................................... 45 Changes from Revision G (April 2016) to Revision H (March 2019) Page • Changed Applications ........................................................................................................................................1 • Changed the Description ................................................................................................................................... 1 • Added High-Side FET Driving ..........................................................................................................................23 • Added the link to the BQ769x0 Boot Switch Alternatives Application Report ..................................................27 • Added the link to the BQ769x0 Family Top Design Considerations Application Report .................................. 38 • Added Figure 9-4 to provide an example of a high-side FET configuration......................................................41 • Added BQ769x0 Family Top Design Considerations Application Report link................................................... 46 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 5 Device Comparison Table TUBE (1) TAPE & REEL CELLS BQ7692000PW BQ7692000PWR BQ7692001PW(1) BQ7692001PWR(1) BQ7692002PW(1) BQ7692002PWR(1) BQ7692003PW BQ7692003PWR BQ7692006PW BQ7692006PWR BQ7693000DBT BQ7693000DBTR BQ7693001DBT BQ7693001DBTR BQ7693002DBT BQ7693002DBTR BQ7693003DBT BQ7693003DBTR BQ7693006DBT BQ7693006DBTR BQ7693007DBT BQ7693007DBTR BQ7694000DBT BQ7694000DBTR BQ7694001DBT BQ7694001DBTR BQ7694002DBT BQ7694002DBTR BQ7694003DBT BQ7694003DBTR BQ7694006DBT BQ7694006DBTR I2C ADDRESS (7Bit) LDO (V) CRC No 2.5 3–5 Yes 0x08 No 3.3 20-TSSOP (PW) Yes 0x18 No No 2.5 Yes 0x08 No 6–10 Yes 3.3 30-TSSOP (DBT) No 0x18 Yes No 2.5 9–15 PACKAGE Yes 0x08 No 3.3 44-TSSOP (DBT) Yes 0x18 No Product Preview only Texas Instruments preconfigures the BQ769x0 devices for a specific I2C address, LDO voltage, and more. These settings are permanently stored in EEPROM and cannot be further modified. Contact Texas Instruments for other options not listed above, as well as any options noted as “Product Preview only.” 6 Pin Configuration and Functions 6.1 Versions DSG 1 20 ALERT DSG 1 30 ALERT DSG 1 44 ALERT CHG 2 19 SRN CHG 2 29 SRN CHG 2 43 SRN VSS 3 18 SRP VSS 3 28 SRP VSS 3 42 SRP SDA 4 17 VC0 SDA 4 27 VC0 SDA 4 41 VC0 16 VC1 SCL 5 26 VC1 SCL 5 40 VC1 15 VC2 TS1 6 25 VC2 TS1 6 39 VC2 24 VC3 CAP1 7 38 VC3 23 VC4 REGOUT 8 37 VC4 REGSRC 9 36 VC5 VC5x 10 35 VC5B 34 VC6 33 VC7 SCL 5 TS1 6 CAP 1 7 14 VC3 CAP1 7 REGOUT 8 13 VC4 REGOUT 8 REGSRC 9 12 VC5 REGSRC 9 22 VC5 BAT 10 11 NC VC5x 10 21 VC5B NC 11 20 VC6 NC 11 NC 12 20-TSSOP 30-TSSOP 44-TSSOP NC 12 19 VC7 TS2 13 18 VC8 TS2 13 32 VC8 CAP2 14 17 VC9 CAP2 14 31 VC9 BAT 15 16 VC10 VC10x 15 30 VC10 NC 16 29 VC10B NC 17 28 VC11 TS3 18 27 VC12 CAP3 19 26 VC13 BAT 20 25 VC14 NC 21 24 VC15 NC 22 23 NC BQ76920: 3–5 Series Cells (20-TSSOP) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 3 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 • 6.5 mm x 4.4 mm x 1.2 mm BQ76930: 6–10 Series Cells (30-TSSOP) • 7.8 mm x 4.4 mm x 1.2 mm BQ76940: 9–15 Series Cells (44-TSSOP) • 11.3 mm x 4.4 mm x 1.2 mm 6.2 BQ76920 Pin Diagram DSG 1 20 ALERT CHG 2 19 SRN VSS 3 18 SRP SDA 4 17 VC0 SCL 5 16 VC1 TS1 6 15 VC2 CAP 1 7 14 VC3 REGOUT 8 13 VC4 REGSRC 9 12 VC5 11 NC BAT 20-TSSOP 10 Table 6-1. BQ76920 Pin Functions (1) 4 PIN NAME TYPE 1 DSG O Discharge FET driver 2 CHG O Charge FET driver 3 VSS — Chip VSS 4 SDA I/O I2C communication to the host controller 5 SCL I I2C communication to the host controller 6 TS1 I Thermistor #1 positive terminal(1) 7 CAP1 O Capacitor to VSS 8 REGOUT P Output LDO 9 REGSRC I Input source for output LDO 10 BAT P Battery (top-most) terminal 11 NC — No connect 12 VC5 I Sense voltage for 5th cell positive terminal 13 VC4 I Sense voltage for 4th cell positive terminal 14 VC3 I Sense voltage for 3rd cell positive terminal 15 VC2 I Sense voltage for 2nd cell positive terminal 16 VC1 I Sense voltage for 1st cell positive terminal 17 VC0 I Sense voltage for 1st cell negative terminal 18 SRP I Negative current sense (nearest VSS) Positive current sense 19 SRN I 20 ALERT I/O DESCRIPTION Alert output and override input If not used, pull down to VSS with a 10-kΩ nominal resistor. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 6.3 BQ76930 Pin Diagram DSG 1 30 ALERT CHG 2 29 SRN VSS 3 28 SRP SDA 4 27 VC0 SCL 5 26 VC1 TS1 6 25 VC2 CAP1 7 24 VC3 30-TSSOP REGOUT 8 23 VC4 REGSRC 9 22 VC5 VC5x 10 21 VC5B NC 11 20 VC6 NC 12 19 VC7 TS2 13 18 VC8 CAP2 14 17 VC9 BAT 15 16 VC10 Table 6-2. BQ76930 Pin Functions PIN NAME TYPE 1 DSG O Discharge FET driver DESCRIPTION 2 CHG O Charge FET driver 3 VSS — Chip VSS 4 SDA I/O I2C communication to the host controller 5 SCL I I2C communication to the host controller 6 TS1 I Thermistor #1 positive terminal(1) 7 CAP1 O Capacitor to VSS 8 REGOUT P Output LDO 9 REGSRC I Input source for output LDO 10 VC5X P Thermistor #2 negative terminal 11 NC — No connect (short to CAP2) 12 NC — No connect (short to CAP2) 13 TS2 I Thermistor #2 positive terminal(1) 14 CAP2 O Capacitor to VC5X 15 BAT P Battery (top-most) terminal 16 VC10 I Sense voltage for 10th cell positive terminal 17 VC9 I Sense voltage for 9th cell positive terminal 18 VC8 I Sense voltage for 8th cell positive terminal 19 VC7 I Sense voltage for 7th cell positive terminal 20 VC6 I Sense voltage for 6th cell positive terminal 21 VC5B I Sense voltage for 6th cell negative terminal 22 VC5 I Sense voltage for 5th cell positive terminal 23 VC4 I Sense voltage for 4th cell positive terminal 24 VC3 I Sense voltage for 3rd cell positive terminal 25 VC2 I Sense voltage for 2nd cell positive terminal 26 VC1 I Sense voltage for 1st cell positive terminal 27 VC0 I Sense voltage for 1st cell negative terminal Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 5 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table 6-2. BQ76930 Pin Functions (continued) (1) PIN NAME TYPE 28 SRP I Negative current sense (nearest VSS) Positive current sense 29 SRN I 30 ALERT I/O DESCRIPTION Alert output and override input If not used, pull down to group ground reference (VSS for TS1 and VC5X for TS2) with a 10-kΩ nominal resistor. 6.4 BQ76940 Pin Diagram DSG 1 44 ALERT CHG 2 43 SRN VSS 3 42 SRP SDA 4 41 VC0 SCL 5 40 VC1 TS1 6 39 VC2 CAP1 7 38 VC3 REGOUT 8 37 VC4 REGSRC 9 36 VC5 VC5x 10 35 VC5B NC 11 34 VC6 NC 12 33 VC7 TS2 13 32 VC8 CAP2 14 31 VC9 VC10x 15 30 VC10 NC 16 29 VC10B NC 17 28 VC11 44-TSSOP TS3 18 27 VC12 CAP3 19 26 VC13 BAT 20 25 VC14 NC 21 24 VC15 NC 22 23 NC BQ76940 Pin Functions 6 PIN NAME TYPE 1 DSG O Discharge FET driver DESCRIPTION 2 CHG O Charge FET driver 3 VSS — Chip VSS 4 SDA I/O I2C communication to the host controller 5 SCL I I2C communication to the host controller 6 TS1 I Thermistor #1 positive terminal(1) 7 CAP1 O Capacitor to VSS 8 REGOUT P Output LDO 9 REGSRC I Input source for output LDO 10 VC5X P Thermistor #2 negative terminal 11 NC — No connect (short to CAP2) 12 NC — No connect (short to CAP2) 13 TS2 I Thermistor #2 positive terminal(1) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 BQ76940 Pin Functions (continued) (1) PIN NAME TYPE 14 CAP2 O Capacitor to VC5X DESCRIPTION 15 VC10X P Thermistor #3 negative terminal 16 NC — No connect (short to CAP3) 17 NC — No connect (short to CAP3) 18 TS3 I Thermistor #3 positive terminal(1) 19 CAP3 O Capacitor to VC10X 20 BAT P Battery (top-most) terminal 21 NC — No connect 22 NC — No connect 23 NC — No connect 24 VC15 I Sense voltage for 15th cell positive terminal 25 VC14 I Sense voltage for 14th cell positive terminal 26 VC13 I Sense voltage for 13th cell positive terminal 27 VC12 I Sense voltage for 12th cell positive terminal 28 VC11 I Sense voltage for 11th cell positive terminal 29 VC10B I Sense voltage for 11th cell negative terminal 30 VC10 I Sense voltage for 10th cell positive terminal 31 VC9 I Sense voltage for 9th cell positive terminal 32 VC8 I Sense voltage for 8th cell positive terminal 33 VC7 I Sense voltage for 7th cell positive terminal 34 VC6 I Sense voltage for 6th cell positive terminal 35 VC5B I Sense voltage for 6th cell negative terminal 36 VC5 I Sense voltage for 5th cell positive terminal 37 VC4 I Sense voltage for 4th cell positive terminal 38 VC3 I Sense voltage for 3rd cell positive terminal 39 VC2 I Sense voltage for 2nd cell positive terminal 40 VC1 I Sense voltage for 1st cell positive terminal 41 VC0 I Sense voltage for 1st cell negative terminal 42 SRP I Negative current sense (nearest VSS) 43 SRN I Positive current sense 44 ALERT I/O Alert output and override input If not used, pull down to group ground reference (VSS for TS1, VC5X for TS2, and VC10X for TS3) with a 10-kΩ nominal resistor. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 7 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7 Specifications 7.1 Absolute Maximum Ratings Over-operating free-air temperature range (unless otherwise noted) (1) VBAT Supply voltage VI Input voltage (BAT–VSS) BQ76920 (BAT–VC5x), (VC5x–VSS) BQ76930 (BAT–VC10x), (VC10x–VC5x), (VC5x–VSS) BQ76940 (VCn–VSS) where n = 1..5 BQ76920, BQ76930, BQ76940 (VCn-VC5x) where n = 6..10 BQ76930, BQ76940 (VCn–VC10x) where n = 11..15 BQ76940 Cell input pins, differential (VCn–VCn–1) where n = 1..15/10/5 (BQ76940/BQ76930/BQ76920, respectively) Output voltage (VC0–VSS), (CAP1–VSS), (TS1–VSS)(2) BQ76920 (VC0–VSS), (VC5b–VC5x), (CAP2–VC5x), (CAP1– VSS), (TS2–VC5x), (TS1–VSS)(2) BQ76930 (VC0–VSS), (VC5b–VC5x), (VC10b–VC10x), (CAP3– VC10x), (CAP2–VC5x), (CAP1–VSS), (TS3–VC10x), (TS2–VC5x), (TS1–VSS)(2) BQ76940 –0.3 36 UNIT V (n × 7.2) –0.3 (n–5) × 7.2 V (n–10) × 7.2 –0.3 9 –0.3 3.6 REGSRC –0.3 36 REGOUT, ALERT –0.3 3.6 DSG –0.3 20 CHG –0.3 VCHGCLAMP ICB Cell balancing current (per cell) IDSG Discharge pin input current when disabled (measured into terminal) V V V BQ76920 70 mA BQ76930, BQ76940 5 mA Storage temperature TSTG (2) MAX SRN, SRP, SCL, SDA VO (1) MIN 7 mA –65 150 Lead temperature (soldering, 10 s) 300 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The Absolute Maximum Ratings for (TS1–VSS) apply after the device completes POR and should be observed after tBOOTREADY (10 ms), following the application of the boot signal on TS1. Prior to completion of POR, TS1 should not exceed 5 V. 7.2 ESD Ratings VALUE V(ESD) (1) (2) 8 Electrostatic discharge Human body model (HBM) ESD stress voltage(1) Charged device model (CDM) ESD stress voltage(2) UNIT ±2 kV ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.3 Recommended Operating Conditions Over-operating free-air temperature range (unless otherwise noted). See Section 9.1.8 for more information on cell configurations. All voltages are relative to VSS, except "Cell input differential." MIN VBAT Supply voltage (BAT–VSS) BQ76920 (BAT–VC5x), (VC5x–VSS) BQ76930 (BAT–VC10x), (VC10x–VC5x), (VC5x–VSS) BQ76940 TYP MAX UNIT 6 25 V 2 5 V 0 5×n V –10 10 mV –200 200 mV 0 3.6 REGSRC 6 25 CHG, DSG 0 16 V 0 3.6 V Cell input pins, differential (VCn–VCn–1) where n = 1..15/10/5 (BQ76940/BQ76930/BQ76920, respectively), in-use cells only (VCn–VSS) where n = 1..5 BQ76920 (VCn–VSS) where n = 1..5, (VCn– VC5x) where n = 6..10 BQ76930 (VCn–VSS) where n = 1..5, (VCn– VC5x) where n = 6..10, (VCn– VC10x) where n = 11..15 BQ76940 SRP VIN Input voltage (VC0–VSS) BQ76920 (VC0–VSS), (VC5b–VC5x) BQ76930 (VC0–VSS), (VC5b–VC5x), (VC10b–VC10x) BQ76940 SRN SCL, SDA (TS1–VSS) BQ76920 (TS1–VSS), (TS2–VC5x) BQ76930 (TS1–VSS), (TS2–VC5x), (TS3– VC10x) BQ76940 V REGOUT, ALERT VOUT Output voltage (CAP1–VSS) BQ76920 (CAP1–VSS), (CAP2–VC5x) BQ76930 (CAP1–VSS), (CAP2–VC5x), (CAP3–VC10x) BQ76940 Cell balancing current (internal, per cell) BQ76920 0 50 mA ICB BQ76930, BQ76940 0 5 mA RC External cell input resistance BQ76920 40 100 1K Ω BQ76930, BQ76940 500 1K 1K Ω CC External cell input capacitance 0.1 1 10 µF Rf External supply filter resistance 40 100 1K Ω Cf External supply filter capacitance 40 µF RFILT Sense resistor filter resistance RALERT ALERT pin to VSS resistor CL REGOUT loading capacitance CCAP REGSRC, CAP1, CAP2, and CAP3 output capacitance 1 µF RTS External thermistor nominal resistance (103AT) at 25°C 10K Ω TOPR Operating free-air temperature –40 1 10 100 1K 1M Ω 1 4.7 µF Ω 85 °C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 9 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.4 Thermal Information Over-operating free-air temperature range (unless otherwise noted) TSSOP THERMAL METRIC(1) BQ76920xy 20 PINS (PW) BQ76930xy 30 PINS (DBT) BQ76940xy 44 PINS (DBT) UNIT RθJA, High K Junction-to-ambient thermal resistance 93.7 86.5 70.1 °C/W RθJC(top) Junction-to-case(top) thermal resistance 28.7 19.4 17.5 °C/W RθJB Junction-to-board thermal resistance 44.6 41.3 33.9 °C/W ψJT Junction-to-top characterization parameter 1.3 0.5 0.5 °C/W ψJB Junction-to-board characterization parameter 44.1 40.6 33.4 °C/W n/a n/a n/a °C/W RθJC(bottom) Junction-to-case(bottom) thermal resistance (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application Report (SPRA953). 7.5 Electrical Characteristics Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP MAX 40 60 60 90 110 165 NORMAL mode: ADC on, CC on 130 195 NORMAL mode: ADC off 30 45 50 75 10 15 80 120 0.6 1.8 –5 ±2.5 5 –1.0 ±0.1 1.0 15 25 ±0.1 0.3 UNIT SUPPLY CURRENTS NORMAL mode: ADC off, CC off NORMAL mode: ADC on, CC off IDD Sum of ICC_BAT and ICC_REGSRC currents NORMAL mode: ADC off, CC on ICC_BAT ICC_REGSRC ISHIP Into BAT pin NORMAL mode: ADC on NORMAL mode: CC off Into REGSRC pin NORMAL mode: CC on Device in full shutdown, only VSTUP/BG and BOOT detector on SHIP/SHUTDOWN mode µA LEAKAGE AND OFFSET CURRENTS dINOM NORMAL mode supply current offset dISHIP SHIP mode supply current offset dIALERT Supply current when ALERT active dICELL Cell measurement input current ILKG Measured into VC5x (BQ76930, BQ76940) and VC10x (BQ76940) Measured into VC5x (BQ76930, BQ76940) or added to BAT (BQ76920) Measured into VC0–VC15 except VC5, VC10, VC15 –0.3 Measured into VC5, VC10, VC15 µA 0.5 Terminal input leakage 1 INTERNAL POWER CONTROL (STARTUP and SHUTDOWN) VPORA Analog POR threshold VBAT rising. See (4). VSHUT Shutdown voltage VBAT falling. See (4). tI2CSTARTUP Time delay after boot signal on TS1 before I2C communications allowed Delay after boot sequence when I2C communication is allowed 10 Submit Document Feedback 4 1 5 V 3.6 V ms Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.5 Electrical Characteristics (continued) Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP Delay after boot signal when device has completed full boot-up sequence tBOOTREADY Device boot startup delay TSHUTD Thermal shutdown voltage 100 MAX UNIT 10 ms 150 °C MEASUREMENT SCHEDULE tVCELL Cell voltage measurement interval tINDCELL Individual cell measurement time tCB_RELAX Cell balancing relaxation time before cell voltage measured 12.5 tTEMP_DEC Temperature measurement Measurement duration for temperature decimation time reading 12.5 tBAT Pack voltage calculation interval 250 tTEMP Temperature measurement Period of measurement of either interval TS1/TS2/TS3 or internal die temp BQ76920, BQ76930, BQ76940 250 Per cell, balancing off 50 Per cell, balancing on 12.5 ms 2 s 14-BIT ADC FOR CELL VOLTAGE AND TEMPERATURE MEASUREMENT ADCRANGE ADC measurement recommend operation range ADCLSB ADC LSB value VCELL measurements TS/Temp measurements 5 V 0.3 3 V 382 ADC cell voltage accuracy at 25°C ADC 2 ADC cell voltage accuracy 0°C to 60°C ADC cell voltage accuracy –40°C to 85°C VCELL = 3.6 V – 4.3 V ±10 VCELL = 3.2 V – 4.6 V ±15 VCELL = 2.0 V – 5.0 V ±25 VCELL = 3.6 V – 4.3 V ±20 VCELL = 3.2 V – 4.6 V ±25 VCELL = 2.0 V – 5.0 V ±35 µV mV VCELL = 3.6 V – 4.3 V –40 40 VCELL = 3.2 V – 4.6 V –40 40 VCELL = 2.0 V – 5.0 V –50 50 16-BIT CC FOR PACK CURRENT MEASUREMENT CCRANGE CC input voltage range –200 200 mV CCFSR CC full scale range –270 270 mV CCLSB CC LSB value CC running constantly 8.44 µV tCCREAD Conversion time Single conversion 250 ms CCINL Integral nonlinearity 16-bit, best fit over input voltage range ± 200 mV ±2 ± 40 LSB CCOFFSET Offset error ±1 ±3 LSB CCGAIN Gain error Over input voltage range ± 0.5% ± 1.5% FSR CCGAINDRIFT Gain error drift Over input voltage range CCRIN Effective input resistance 150 PPM / °C 2.5 MΩ THERMISTOR BIAS RTS Pull-up resistance TA = 25°C RTSDRIFT Pull-up resistance across temp TA = –40°C to 85°C 9.85 9.7 10 10.15 kΩ 10.3 kΩ Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 11 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.5 Electrical Characteristics (continued) Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP MAX UNIT DIETEMP VDIETEMP25 Die temperature voltage VDIETEMPDRIFT Die temperature voltage drift TA = 25°C 1.20 V –4.2 mV/°C INTEGRATED HARDWARE PROTECTIONS OVRANGE OV threshold range 0x2008 0x2FF8 ADC UVRANGE UV threshold range 0x1000 0x1FF0 ADC OVUVSTEP OV and UV threshold step size UVMINQUAL UV minimum value to qualify OVDELAY UVDELAY OCDRANGE OV delay timer options UV delay timer options OCD threshold options OCDSTEP OCD threshold step size OCDDELAY OCD delay options SCDRANGE SCDSTEP SCD threshold options SCD threshold step size SCDDELAY SCD delay options tPROTACC Delay accuracy for OCD OCOFFSET OCD and SCD voltage offset OCSCALEERR OCD and SCD scale accuracy Below UVMINQUAL, the cell is shorted (unused) 16 LSB 0x0518 ADC OV delay = 1 s 0.7 1 1.75 OV delay = 2 s 1.6 2 2.75 OV delay = 4 s 3.5 4 5 OV delay = 8 s 7 8 10 UV delay = 1 s 0.7 1 1.75 UV delay = 4 s 3.5 4 5 UV delay = 8 s 7 8 10 UV delay = 16 s 14 16 20 Measured across (SRP–SRN)(2) 8 RSNS = 0 RSNS = 1 8 (SRP–SRN)(2) 22 RSNS = 0 mV 1280 ms 200 mV 11.1 RSNS = 1 mV mV 5.56 See Note(3) Measured across 100 2.78 s mV 22.2 mV 35 70 105 µs 50 100 150 µs 140 200 260 µs 280 400 520 µs –20% 20% –2.5 2.5 –10% 10% mV CHARGE AND DISCHARGE DRIVERS VFETON CHG and DSG on REGSRC ≥ 12 V with load resistance of 10 MΩ 10 12 14 V REGSRC < 12 V with load resistance of 10 MΩ REGSRC – 2 REGSRC – 1 REGSRC V tFET_ON CHG and DSG ON rise time CHG/DSG driving an equivalent load capacitance of 10 nF, measured from 10% to 90% of VFETON 200 250 µs tDSG_OFF DSG pull-down OFF fall time DSG driving an equivalent load capacitance of 10 nF, measured from 90% to 10% 60 90 µs 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.5 Electrical Characteristics (continued) Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP MAX UNIT RCHG_OFF CHG pull-down OFF resistance to VSS When CHG disabled, CHG held at 12 V 750 1000 1250 kΩ RDSG_OFF DSG pull-down OFF resistance to VSS When DSG disabled, DSG held at 12 V 1.75 2.50 4.25 kΩ VLOAD_DETECT Load detection threshold 0.4 0.7 1.0 V 18 20 22 V VCHG_CLAMP If the CHG pin externally pulled high (through PACK–, if load applied), 500µA max sink current into CHG pin. With CHG_ON bit cleared. CHG clamp voltage ALERT PIN VALERT_OH ALERT output voltage high IOL = 1 mA VALERT_OL ALERT output voltage low Unloaded VALERT_IH ALERT input high ALERT externally forced high when internally driven low. See note (1). RALERT_PD ALERT pin weak pulldown Measured into ALERT pin with ALERT = resistance when driven low REGOUT REGOUT x 0.75 V 1 REGOUT x 0.25 V 1.5 V 0.8 2.5 8 MΩ 1 5 10 Ω CELL BALANCING DRIVER RDSFET Internal cell balancing driver resistance VCELL = 3.6 V XBAL Cell balancing duty cycle when enabled Every 250 ms 70% EXTERNAL REGULATOR External LDO voltage options Nominal values, TI factory programmed, unloaded, across temp VEXTLDO_LN Line regulation REGSRC pin stepped from 6 to 25 V, with 10-mA load, in 100 µs VEXTLDO_LD Load regulation IREGOUT = 0 mA to 10 mA VEXTLDO VEXTLDO_DC IEXTLDO_LIMIT External LDO minimum voltage under DC load External LDO current limit 2.45 2.50 2.55 V 3.20 3.30 3.40 V 100 mV –4% 4% REGOUT = 10-mA DC, 2.5-V version 2.4 V REGOUT = 20-mA DC, 2.5-V version 2.3 V REGOUT = 10-mA DC, 3.3-V version 3.15 V REGOUT = 20-mA DC, 3.3-V version 3.05 V REGOUT = 0 V 30 38 45 mA 300 1000 mV 10 2000 µs BOOT DETECTOR VBOOT Boot threshold voltage Measured at TS1 pin with device in SHIP mode. Below MIN, the device does not boot up. Above MAX, the device boots up. tBOOT_max Boot threshold application time Measured at TS1 pin. Below MIN, the device does not boot up. Above MAX, the device boots up. (1) (2) (3) (4) MIN specifies the threshold below which the device will never register that an external alert has occurred. MAX specifies the minimum threshold above which the device will always register that an external alert has occurred. Values indicate nominal thresholds only. For min and max variation, apply OCOFFSET and OCSCALERR. Values indicate nominal thresholds only. For min and max variation, apply tPROTACC. Measured at each VBAT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 13 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.6 Timing Requirements I2C COMPATIBLE INTERFACE MIN TYP MAX REGOUT x 0.25 UNIT VIL Input low logic threshold VIH Input high logic threshold VOL Output low logic drive 0.20 tf SCL, SDA fall time 0.40 VOH Output high logic drive (not applicable due to open-drain outputs) N/A tHIGH SCL pulse width high 4.0 µs tLOW SCL pulse width low 4.7 µs tSU;STA Setup time for START condition 4.7 µs tHD;STA START condition hold time after which first clock pulse is generated 4.0 µs tSU;DAT Data setup time 250 ns tHD;DAT Data hold time 0 µs tSU;STO Setup time for STOP condition 4.0 µs tBUF Time the bus must be free before new transmission can start 4.7 tVD;DAT Clock low to data out valid tHD;DAT Data out hold time after clock low 0 fSCL Clock frequency 0 REGOUT x 0.75 V V N/A V V µs 900 ns 100 kHz ns SCL SDA SCL SDA SCL SDA Figure 7-1. I2C Timing 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.7 Typical Characteristics 0.020 0.016 VC2 Error 0.014 VC3 Error 0.012 VC4 Error 0.010 VC5 Error 25 Gain Error (PPM) VCx Error (V) 30 VC1 Error 0.018 0.008 0.006 0.004 0.002 0.000 20 15 10 5 0 ±0.002 ±5 ±0.004 2.00 2.30 2.60 2.90 3.20 3.50 3.80 4.10 4.40 4.70 5.00 VCx Input (V) ±40 35 60 Temperature (ƒC) 85 C005 Figure 7-3. Coulomb Counter Gain Error Temperature Drift (from –0.2 V to 0.2 V) Figure 7-2. BQ76930 VCx Error Across Input Range at 25°C with VIN at 3.6 V 0.0 0.0 ±0.1 ±0.2 ±0.4 ±0.2 Offset (uV) Gain Error (%FSR) 10 ±15 C001 ±0.3 ±0.4 ±0.5 ±0.6 ±0.8 ±1.0 ±1.2 ±0.6 ±1.4 ±0.7 ±1.6 ±40 ±15 10 35 60 85 Temperature (ƒC) ±40 10 ±15 35 60 Temperature (ƒC) C003 Figure 7-4. Coulomb Counter Gain Error (from –0.2 V to 0.2 V) 85 C002 Figure 7-5. Coulomb Counter Offset 0.01 OV Detection Error (V) 0.005 0 -0.005 -0.01 -0.015 -0.02 -40 -15 10 35 Temperature (°C) 60 85 Figure 7-6. OV Protection Detection Error (0xFF Setting) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 15 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8 Detailed Description 8.1 Overview In the BQ769x0 family of analog front-end (AFE) devices, the BQ76920 device supports up to 5-series cells, the BQ76930 device supports up to 10-series cells, and the BQ76940 device supports up to 15-series cells. Through I2C, a host controller can use the BQ769x0 to implement battery pack management functions, such as monitoring (cell voltages, pack current, pack temperatures), protection (controlling charge/discharge FETs), and balancing. Integrated A/D converters enable a purely digital readout of critical system parameters including cell voltages and internal or external temperature, with calibration handled in TI’s manufacturing process. For an additional degree of pack reliability, the BQ769x0 includes hardware protections for voltage (OV, UV) and current (OCD, SCD). The BQ769x0 provides two low-side FET drivers, charge (CHG) and discharge (DSG), which may be used to directly manipulate low-side power NCH FETs, or as signals that control an external circuit that enables high-side PCH or NCH FETs. A dedicated ALERT input/output pin serves as an interrupt signal to the host microcontroller, quickly informing the microcontroller of an updated status in the AFE. This may include a fault event or that a coulomb counter sample is available for reading. An available ALERT pin may also be driven externally by a secondary protector to provide a redundant means of disabling the CHG and DSG signals and higher system visibility. 8.2 Functional Block Diagram REG SRC CAP Bandgap IBIAS VSTUP/POR BAT Cell Balance Drivers/FETs BOOT Internal 3.3-V LDO ALERT 256 kHz Digital core Die temp REG OUT 14-bit ADC Modulator V2I VCx Inputs External 2.5/3.3-V LDO CC VREF FET DRIVER and LOAD DETECT CHG DSG TS SCL 16-bit ACC Modulator I2C SDA TS BOOT SCD comp To POR OCD comp VSS EEPROM SRP SRN Copyright © 2016, Texas Instruments Incorporated 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.3 Feature Description 8.3.1 Subsystems BQ769x0 consists of three major subsystems: Measurement, Protection, and Control. These work together to ensure that the fundamental battery pack parameters—voltage, current and temperature—are accurately captured and easily available to a host controller, while ensuring a baseline or secondary level of hardware protection in the event that a host controller is unable or unavailable to manage certain fault conditions. Note The BQ769x0 is intended to serve as an analog front-end (AFE) as part of a chipset system solution: A companion microcontroller is required to oversee and control this AFE. • • • The Measurement subsystem’s core responsibility is to digitize the cell voltages, pack current (integrated into a passed charge calculation), external thermistor temperature, and internal die temperature. It also performs an automatic calculation of the total battery stack voltage, by simply adding up all measured cell voltages. The Protection subsystem provides a baseline or secondary level of hardware protections to better support a battery pack’s FMEA requirements in the event of a loss of host control or simply if a host is unable to respond to a certain fault event in time. Integrated protections include pack-level faults such as OV, UV, OCD, SCD, detection of an external secondary protector fault, and internal logic “watchdog”-style device fault (XREADY). Protection events will trigger toggling of the ALERT pin, as well as automatic disabling of the DSG or CHG FET driver (depending on the fault). Recovery from a fault event must be handled by the host microcontroller. The Control subsystem implements a suite of useful pack features, including direct low-side NCH FET drivers, cell balancing drivers, the ALERT digital output, an external LDO and more. The following sections describe each subsystem in greater detail, as well as explaining the various power states that are available. 8.3.1.1 Measurement Subsystem Overview The monitoring subsystem ensures that all cell voltages, temperatures, and pack current may be easily measured by the host. All ADCs are trimmed by TI. ADC and CC data are always returned as atomic values if both high and low registers are read in the same transaction (using address auto-increment). 8.3.1.1.1 Data Transfer to the Host Controller The BQ769x0 has a fully digital interface: All information is transferred through I2C, simply by reading and/or writing to the appropriate register(s) storing the relevant data. Block reads and writes, buffered by an 8-bit CRC code per byte, ensure a fast and robust transmission of data. 8.3.1.1.2 14-Bit ADC Each BQ769x0 device measures cell voltages and temperatures using a 14-bit ADC. This ADC measures all differential cell voltages, thermistors and/or die temperature with a nominal full-scale unsigned range of 0–6.275 V and LSB of 382 µV. To enable the ADC, the [ADC_EN] bit in the SYS_CTRL1 register must be set. This bit is set automatically whenever the device enters NORMAL mode. When enabled, the ADC ensures that the integrated OV and UV protections are functional. For each contiguous set of five cells (VC1 to VC5, VC6 to VC10), when no cells in that particular set are being balanced, each cell is measured over a 50-ms decimation window and a complete update is available every 250 ms. In the BQ76930 and BQ76940, every set of five cells above the primary five cells is measured in parallel. The 50-ms decimation greatly assists with removing the aliasing effects present in a noisy motor environment. When any cells in a contiguous set of 5 cells are being balanced, those affected cells are measured in a reduced 12.5-ms decimation period, to allow the cell balancing to function properly without affecting the integrated OV and UV protections. Since cell balancing is typically only performed during pack charge or idle periods, the Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 17 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 shortened decimation periods should not impact accuracy as the system noise during these times is greatly reduced. This reduced decimation period is only applied to sets where one of the cells is being balanced. The following summarizes this for the BQ76920–BQ76940 devices: • • • • VC1 to VC5 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL1 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL1 register are 1. VC6 to VC10 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL2 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL2 register are 1. VC11 to VC15 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL3 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL3 register are 1. Total update interval is 250 ms. Each differential cell input is factory-trimmed for gain or offset, such that the resulting reading through I2C is always consistent from part-to-part and requires no additional calibration or correction factor application. The ADC is required to be enabled in order for the integrated OV and UV protections to be operating. The following shows how to convert the 14-bit ADC reading into an analog voltage. Each device is factory calibrated, with a GAIN and OFFSET stored into EEPROM. The ADC transfer function is a linear equation defined as follows: V(cell) = GAIN x ADC(cell) + OFFSET (1) GAIN is stored in units of µV/LSB, while OFFSET is stored in mV units. Some example cell voltage calculations are provided in the table below. For illustration purposes, the example uses a hypothetical GAIN of 380 µV/LSB (ADCGAIN = 0x0F) and OFFSET of 30 mV (ADCOFFSET = 0x1E). 14-Bit ADC Result ADC Result in Decimal GAIN (µV/LSB) OFFSET (mV) Cell Voltage (mV) 0x1800 6144 380 30 2365 0x1F10 7952 380 30 3052 Note When entering NORMAL mode from SHIP mode, please allow for the following times before reading out initial cell voltage data: BQ76920: 250 ms BQ76930: 400 ms BQ76940: 800 ms 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller The performance of the cell voltage values measured by the 14-bit ADC has a factory-calibrated accuracy, as follows: • • • +/– 10 mV TYP, +/– 40 mV MIN and MAX from 3.6 to 4.3 V, +/– 15 mV TYP, +/– 40 mV MIN and MAX from 3.2 to 4.6 V, and +/– 50 mV MIN and MAX from 2.0 to 5.0 V While this is suitable for the majority of pack protection and basic monitoring applications the BQ769x0 AFE family is intended to support, certain systems may require a higher accuracy performance. To achieve this, use an available ADC channel and general purpose output terminal on the host microcontroller paired with the BQ769x0. A simple external circuit consisting of two precision resistors and a small-signal FET is activated by the host microcontroller to determine the total stack voltage, VSTACK. This is then compared against the sum of the individual cell voltages as measured by the internal ADC of the BQ769x0. The resulting transfer function coefficient, GAIN2, is simply applied to each cell voltage ADC value for improved accuracy. Battery cell stack Host microcontroller A/D input Gen. purpose output Figure 8-1. External Real-Time Calibration Circuit to Host Microcontroller The process is as follows: 1. Periodically measure VSTACK. a. VSTACK = VAD × (R1 + R2) / R1 2. Read out all VCELL ADC readings from the BQ769x0 and apply the standard GAIN and OFFSET values stored in the BQ769x0. a. V(1) = GAIN x ADC1 + OFFSET, V(2) = GAIN x ADC2 + OFFSET, and so on 3. Sum up all VCELL values, VSUM. a. VSUM = V(1) + V(2) + V(3) … 4. Calculate GAIN2. a. GAIN2 = VSTACK / VSUM As a general recommendation, a new GAIN2 function should be generated when the cell voltages increase or decrease by more than 100 mV. With GAIN2, each cell voltage calculation becomes: V(cell) = GAIN2 × (GAIN x ADC(cell) + OFFSET) (2) For systems that do not require this additional in-use calibration function, GAIN2 is simply “1”. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 19 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.3.1.1.3 16-Bit CC A 16-bit integrating ADC, commonly referred to as the coulomb counter (CC), provides measurements of accumulated charge across the current sense resistor. The integration period for this reading is 250 ms. The CC may be operated in one of two modes: ALWAYS ON and 1-SHOT. • • In ALWAYS ON mode, the CC runs at 100%, gathering a fresh reading every 250 ms. The conclusion of each reading sets the CC_READY bit, which toggles the ALERT pin high to inform the microcontroller that a new reading is available. To enable Always On mode, set [CC_EN] = 1. In 1-SHOT mode, the CC performs a single 250-ms reading, and similarly sets the CC_READY bit when completed. This mode is intended for non-gauging usages, where the host simply desires to check the pack current. To enable a 1-SHOT reading, ensure [CC_EN] = 0 and set [CC_ONESHOT] = 1. The fullscale range of the CC is ± 270 mV, with a max recommended input range of ± 200 mV, thus yielding an LSB of approximately 8.44 µV. The following equation shows how to convert the 16-bit CC reading into an analog voltage if no board-level calibration is performed: CC Reading (in µV) = [16-bit 2’s Complement Value] × (8.44 µV/LSB) (3) 16-Bit CC Result ADC Result in Decimal CC Reading (in µV) 0x0001 1 8.44 0x2710 10000 84,400 0x7D00 32000 270,080 0x8300 –32000 –270,080 0xC350 –15536 –131,123.84 0xFFFF –1 –8.44 8.3.1.1.4 External Thermistor One (BQ76920), two (BQ76930), or three (BQ76940) 10-kΩ NTC 103AT thermistors may be measured by the device. These are measured by applying a factory-trimmed internal 10-k pull-up resistance to an internal regulator value of nominally 3.3 V, the result of which can be read out from the TSx (TS1, TS2, TS3) registers. To select thermistor measurement mode, set [TEMP_SEL] = 1. Thermistor TS1 is connected between TS1 and VSS; TS2 is connected between TS2 and VC5x (BQ76930 and BQ76940 only); and TS3 is connected between TS3 and VC10x (BQ76940 only). These thermistors may be placed in various areas in the battery pack to measure such things as localized cell temperature, FET heating, and so forth. The thermistor impedance may be calculated using the 14-bit ADC reading in the TS1, TS2, and TS3 registers and 10-k internal pull-up resistance as follows: The following equations show how to use the 14-bit ADC readings in TS1, TS2, and TS3 to determine the resistance of the external 103AT thermistor: VTSX = (ADC in Decimal) x 382 µV/LSB (4) RTS = (10,000 × VTSX) ÷ (3.3 – VTSX) (5) To convert the thermistor resistance into temperature, please refer to the thermistor component manufacturer’s data sheet. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.3.1.1.5 Die Temperature Monitor Note When switching between external and internal temperature monitoring, a 2-s latency may be incurred due to the natural scheduler update interval. A die temperature block generates a voltage that is proportional to the die temperature, and provides a way of reducing component count if pack thermistors are not used or ensuring that the die power dissipation requirements are observed. The die is measured using the same on-board 14-bit ADC as the cell voltages. To select internal die temperature measurement mode, set [TEMP_SEL] = 0. For BQ76930 and BQ76940, multiple die temperature measurements are available. These are stored in TS2 and TS3. To convert a DIETEMP reading into temperature, refer to the following equation box. If more accurate temperature readings are needed from DIETEMP, the DIETEMP at room temperature value should be stored during production calibration. The following equation shows how to use the 14-bit ADC readings in TS1, TS2, and TS3 when [TEMPSEL] = 0 to determine the internal die temperature: V25 = 1.200 V (nominal) (6) VTSX = (ADC in Decimal) x 382 µV/LSB (7) TEMPDIE = 25° – ((VTSX – V25) ÷ 0.0042) (8) 8.3.1.1.6 16-Bit Pack Voltage Once converted to digital form, each cell voltage is added up and the summation result stored in the BAT registers. The sum is divided by 4 so that the result of summing 15 cells fits in the 16-bit value. This 16-bit value has a nominal LSB of 1.532 mV. The following shows how to convert the 16-bit pack voltage ADC reading into an analog voltage. This value also uses the GAIN and OFFSET stored into EEPROM. The ADC transfer function is a linear equation defined as follows: V(BAT) = 4 × GAIN × ADC(cell) + (#Cells x OFFSET) (9) GAIN is stored in units of µV/LSB, while OFFSET is stored in mV units. 8.3.1.1.7 System Scheduler A master scheduler oversees the monitoring intervals, creating a full update every 250 ms. Temperature measurements are taken every 2 seconds. Pack voltage is calculated every 250 ms. More information on the System Scheduler can be found in the Embedded Scheduler in Cell Battery Monitor of the BQ769x0 application report. 8.3.1.2 Protection Subsystem 8.3.1.2.1 Integrated Hardware Protections Integrated hardware protections are provided as an extra degree of safety and are meant to supplement the standard protection feature set that would be incorporated into the host controller firmware. They should not be used as the sole means of protecting a battery pack, but are useful for FMEA purposes; for example, in the event that a host microcontroller is unable to react to any of the below protection situations. All hardware protection thresholds and delays should be loaded into the AFE by the host microcontroller during system startup. The AFE will also default to predefined threshold and delay settings, in case the host microcontroller is unable to or does not wish to program the protection settings. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 21 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) are implemented using sampled analog comparators that run at 32 kHz, and that continuously monitor the voltage across (SRP–SRN) while the device is in NORMAL mode. Upon detection of a voltage that exceeds the programmed OCD or SCD threshold, a counter begins to count up to a programmed delay setting. If the counter reaches its target value, the SYS_STAT register is updated to indicate the fault condition, the FET state(s) are updated as shown in Table 8-1, and the ALERT pin is driven high to interrupt the host. The protection fault threshold and delay settings for OCD and SCD protections are configured through the PROTECT1 and PROTECT2 registers. See Section 8.5 for details about supported values. Overvoltage (OV) and undervoltage (UV) protections are handled digitally, by comparing the cell voltage readings against the 8-bit programmed thresholds in the OV and UV registers. The OV threshold is stored in the OV_TRIP register and is a direct mapping of 8 bits of the 14-bit ADC reading, with the upper 2 MSB preset to “10” and the lower 4 LSB preset to “1000”. In other words, the corresponding OV trip level is mapped to “10-XXXX-XXXX–1000”. The programmable range of OV thresholds is approximately 3.15 to 4.7 V, but this is subject to variation due to the (GAIN, OFFSET) linear equation used to map the ADC values. The UV threshold is stored in the UV_TRIP register and is a direct mapping of 8 bits of the 14-bit ADC reading, with the upper 2 MSB preset to “01” and lower 4 LSB preset to “0000”. In other words, the corresponding UV trip level is mapped to “01-XXXX-XXXX–0000”. The programmable range of UV thresholds is approximately 1.58 to 3.1 V, but this is subject to variation due to the (GAIN, OFFSET) linear equation used to map the ADC values. Protection Upper 2 MSB Middle 8 Bits Lower 4 LSB OV 10 Set in OV_TRIP Register 1000 UV 01 Set in UV_TRIP Register 0000 Note To support flexible cell configurations within BQ76920, BQ76930, and BQ76940, UV is ignored on any cells that have a reading under UVMINQUAL. This allows cell pins to be shorted in implementations where not all cells are needed (for example, 6-series cells using the BQ76930). Default protection thresholds and delays are shown in the register description at the end of this data These are loaded into the digital register (RAM) of the device when the device enters NORMAL mode. RAM values may then be overwritten by the host controller to any other values, which they will retain POR event. It is recommended that the host controller reload these values during its standard power-up reinitialization sequence. sheet. These until a and/or To calculate the correct OV_TRIP and UV_TRIP register values for a device, use the following procedure: 1. Determine desired OV. 2. Read out [ADCGAIN] and [ADCOFFSET] from their corresponding registers. Note that ADCGAIN is stored in units of µV/LSB, while ADCOFFSET is stored in mV. 3. Calculate the full 14-bit ADC value needed to meet the desired OV and UV trip thresholds as follows: a. OV_TRIP_FULL = (OV – ADCOFFSET) ÷ ADCGAIN b. UV_TRIP_FULL = (UV – ADCOFFSET) ÷ ADCGAIN 4. Remove the upper 2 MSB and lower 4 LSB from the full 14-bit value, retaining only the remaining middle 8 bits. This can be done by shifting the OV_TRIP_FULL and UV_TRIP_FULL binary values 4 bits to the right and removing the upper 2 MSB. 5. Write OV_TRIP and UV_TRIP to their corresponding registers. Both OV and UV protections require the ADC to be enabled. Ensure that the [ADC_EN] bit is set to 1 if OV and UV protections are needed. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.3.1.2.2 Reduced Test Time A special debug and test configuration bit is provided in the SYS_CTRL2 register, called [DELAY_DIS]. Setting [DELAY_DIS] bypasses the OV/UV protection fault timers and allows a fault condition to be registered within 200 ms after application of such a fault condition. 8.3.1.3 Control Subsystem 8.3.1.3.1 FET Driving (CHG AND DSG) Each BQ769x0 device provides two low-side FET drivers, CHG and DSG, which control NCH power FETs or may be used as a signal to enable various other circuits such as a high-side NCH charge pump circuit. Both DSG and CHG drivers have a fast pull-up to nominally 12 V when enabled. DSG uses a fast pull-down to VSS when disabled, while CHG utilizes a high impedance (nominally 1 MΩ) pull-down path when disabled. An additional internal clamp circuit ensures that the CHG pin does not exceed a maximum of 20 V. DSG CHG Q3 This diode allows CHG to pull the Q1 gate high. Q3 is a low-cost PCH FET and is used to keep CHG away from any voltages below VSS. When CHG is not being pulled high, PACK± being pulled below VSS will not be seen by CHG as Q2 does not turn on. Q3 also allows R2 to keep Q1 OFF, since all voltages below this FET can "follow" PACK± as it goes below VSS. R1 drops the voltage when PACK± is pulled high and R1 limits the current going into the CHG pin. Since CHG (1M) clamps at ~ 18 V, R1 will limit current to approximately (V(PACK±) - 18) / R1. R2 (1M) R2 Q2 BAT± Q1 This zener clamp may be needed to prevent Q1 from turning on too quickly (optional). PACK t R2 clamps Q1 when CHG is turned off. Rsns Figure 8-2. CHG and DSG FET Circuit The power path for the CHG and DSG pull-up circuit originates from the REGSRC pin, instead of BAT. To enable the CHG fet, set the [CHG_ON] register bit to 1; to disable, set [CHG_ON] = 0. The discharge FET may be similarly controlled through the [DSG_ON] register bit. Certain fault conditions or power state transitions will clear the state of the CHG/DSG FET controls. Table 8-1 shows what action, if any, to take to [CHG_ON] and [DSG_ON] in response to various system events: 8.3.1.3.1.1 High-Side FET Driving The BQ769x0 battery monitors provide low-side FET drivers that work well for many systems. For some systems, high-side FETs may also be beneficial. High-side FETs enable continuous communication between a host controller and the monitor, regardless of whether the FETs are on or off. This allows the controller to read critical pack parameters despite safety faults, enabling the system to access pack conditions before allowing normal operations to resume. The BQ769200 high-side N-channel FET driver can be used with the BQ769x0 monitor in systems where high-side FETs are needed. See Figure 9-4. Table 8-1. CHG, DSG Response Under Various System Events EVENT [CHG_ON] [DSG_ON] OV Fault Set to 0 — UV Fault — Set to 0 OCD Fault — Set to 0 SCD Fault — Set to 0 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 23 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table 8-1. CHG, DSG Response Under Various System Events (continued) EVENT [CHG_ON] [DSG_ON] ALERT Override Set to 0 Set to 0 DEVICE_XREADY is set Set to 0 Set to 0 Enter SHIP mode from NORMAL Set to 0 Set to 0 Note The host microcontroller must initiate all protection recovery. To resume FET operation after a fault condition, the host microcontroller must first clear the corresponding status bit in the SYS_STAT register, which will clear the ALERT pin, and then manually reenable the CHG and/or DSG bit. Certain faults, such as OV or UV, may immediately retoggle if such a condition still persists. Refer to Table 8-3 for details on clearing status bits. There are no conditions under which the BQ769x0 automatically sets either [CHG_ON] or [DSG_ON] to 1. 8.3.1.3.2 Load Detection A load detection circuit is present on the CHG pin and activated whenever the CHG FET is disabled ([CHG_ON] = 0). This circuit detects if the CHG pin is externally pulled high when the high impedance (approximately 1 MΩ) pull-down path should actually be holding the CHG pin to VSS, and is useful for determining if the PACK– pin (outside of the AFE) is being held at a high voltage—for example, if the load is present while the power FETs are off. The state of the load detection circuit is read from the [LOAD_PRESENT] bit of the SYS_CTRL1 register. After an OCD or SCD fault has occurred, the DSG FET will be disabled ([DSG_ON] cleared), and the CHG FET must similarly be explicitly disabled to activate the load detection circuit. The host microcontroller may periodically poll the [LOAD_PRESENT] bit to determine the state of the PACK– pin and determine when the load is removed ([LOAD_PRESENT] = 0). 8.3.1.3.3 Cell Balancing Both internal and external passive cell balancing options are fully supported by the BQ76920, while external cell balancing is recommended for BQ76930 and BQ76940. It is left to the host controller to determine the exact balancing algorithm to be used in any given system. Each BQ769x0 device provides the cell voltages and balancing drivers to enable this. If using the internal cell balance drivers, up to 50 mA may be balanced per cell. If using external cell balancing, much higher balancing currents may be employed. To activate a particular cell balancing channel, simply set the corresponding bit for that cell in the CELLBAL1, CELLBAL2, or CELLBAL3 register. For example, VC1–VC0 is enabled by setting [CB1], while VC12–VC11 is set through [CB12]. Multiple cells may be simultaneously balanced. It is left to the user’s discretion to determine the ideal number of cells to concurrently balance. Adjacent cells should not be balanced simultaneously. This may cause cell pins to exceed their absolute maximum conditions and is also not recommended for external balancing implementations. Additionally, if internal balancing is used, care should be taken to avoid exceeding package power dissipation ratings. Note The host controller must ensure that no two adjacent cells are balanced simultaneously within each set of the following: • VC1–VC5 • VC6–VC10 • VC11–VC15 The total duty cycle devoted to balancing is approximately 70% per 250 ms. This is because a portion of the 250 ms is allotted for normal cell voltage measurements through the ADC. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 If [ADC_EN] =1, OV and UV protections are not affected by cell balancing, since the cell balancing is temporarily suspended for a small slice of time every 250 ms during which the cell voltage readings are taken. This ensures that the OV and UV protections do not accidentally trigger, or miss an actual OV/UV condition on the cells while balancing is enabled. Note All cell balancing control bits in CELLBAL1, CELLBAL2, and CELLBAL3 are automatically cleared under the following events, and must be explicitly rewritten by the host microcontroller following clearing of the event: • DEVICE_XREADY is set • Enters NORMAL mode from SHIP mode 8.3.1.3.4 Alert The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of the host microcontroller. This signal is an OR of all bits in the SYS_STAT register. In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by writing a “1” to that bit. This will cause an automatic clear of the ALERT pin once all bits are cleared. The ALERT pin may also be driven by an external source; for example, the pack may include a secondary overvoltage protector IC. When the ALERT pin is forced high externally while low, the device will recognize this as an OVRD_ALERT fault and set the [OVRD_ALERT] bit. This triggers automatic disabling of both CHG and DSG FET drivers. The device cannot recognize the ALERT signal input high when it is already forcing the ALERT signal high from another condition. The ALERT pin has no internal debounce support so care should be taken to protect the pin from noise or other parasitic transients. Note It is highly recommended to place an external 500 kΩ–1 MΩ pull-down resistor from ALERT to VSS as close to the IC as possible. Additional recommendations are: a) To keep all traces between the IC and components connected to the ALERT pin very short. b) To include a guard ring around the components connected to the ALERT pin and the pin itself. 8.3.1.3.5 Output LDO An adjustable output voltage regulator LDO is provided as a simple way to provide power to additional components in the battery pack, such as the host microcontroller or LEDs. The LDO is configured in EEPROM by TI during the production test process, and can support 2.5-V or 3.3-V options. A cascode small-signal FET must be added in the external path between BAT and REGSRC with the BQ76930 and BQ76940. This helps drop most of the power dissipation outside of the package and cuts down on package power dissipation. 8.3.1.4 Communications Subsystem The AFE implements a standard 100-kHz I2C interface and acts as a slave device. The I2C device address is 7-bits and is factory programmed. Consult the Device Comparison Table (Section 5) of this data sheet for more information. A write transaction is shown in Figure 8-3. Block writes are allowed by sending additional data bytes before the Stop. The I2C block will auto-increment the register address after each data byte. When enabled, the CRC is calculated as follows: • In a single-byte write transaction, the CRC is calculated over the slave address, register address, and data. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 25 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 • In a block write transaction, the CRC for the first data byte is calculated over the slave address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only. The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0. When the slave detects a bad CRC, the I2C slave will NACK the CRC, which causes the I2C slave to go to an idle state. SCL A6 A5 SDA Start ... A0 R/W ACK Slave Address R7 R6 ... R0 ACK D7 D6 Register Address ... D0 C7 C6 ACK ... C0 ACK CRC (optional) Data Stop Figure 8-3. I2C Write Figure 8-4 shows a read transaction using a Repeated Start. SCL A6 A5 SDA Start ... A0 R/W ACK Slave Address R7 R6 ... R0 A6 A5 ACK Register Address ... A0 R/W ACK Slave Address Repeated Start D7 D6 ... D0 ACK Slave Drives Data C7 C6 ... C0 NACK Slave Stop Drives CRC (optional) Master Drives NACK Figure 8-4. I2C Read with Repeated Start Figure 8-5 shows a read transaction where a Repeated Start is not used, for example if not available in hardware. For a block read, the master ACK’s each data byte except the last and continues to clock the interface. The I2C block will auto-increment the register address after each data byte. When enabled, the CRC for a read transaction is calculated as follows: • • In a single-byte read transaction, the CRC is calculated after the second start and uses the slave address and data byte. In a block read transaction, the CRC for the first data byte is calculated after the second start and uses the slave address and data byte. The CRC for subsequent data bytes is calculated over the data byte only. The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0. When the master detects a bad CRC, the I2C master will NACK the CRC, which causes the I2C slave to go to an idle state. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 SCL A6 A5 SDA Start ... A0 R/W ACK R7 R6 ... R0 Register Address Slave Address A6 A5 ACK Stop Start D7 D6 ... A0 R/W ACK Slave Address ... D0 ACK C7 C6 Slave Drives Data ... C0 NACK Slave Stop Drives CRC (optional) Master Drives NACK Figure 8-5. I2C Read Without Repeated Start 8.4 Device Functional Modes Each BQ769x0 device supports the following modes of operation. Table 8-2. Supported Power Modes Mode Description NORMAL Fully operational state. Both ADC and CC may be on, or disabled by host microcontroller. OV and UV protection enabled if ADC is on. OCD and SCD enabled. ADC and CC may be disabled to reduce power consumption, and CC may be operated in a “1-SHOT” mode for flexible power savings. SHIP Lowest possible power state, intended for pack assembly and/or longterm pack storage. Must see a BOOT signal (> 1 VBOOT) on TS1 pin to boot from SHIP → NORMAL. Note that the device always enters SHIP mode upon POR. 8.4.1 NORMAL Mode NORMAL mode represents the fully operational mode where all blocks are enabled and the device sees its highest current consumption. In this mode, certain blocks/functions may be disabled to save power—these include the ADC and CC. OV and UV are running continuously as long as the ADC is enabled. The OCD and SCD comparators may not be disabled in this mode. Transitioning from NORMAL to SHIP mode is also initiated by the host, and requires consecutive writes to two bits in the SYS_CTRL1 register. 8.4.2 SHIP Mode SHIP mode is the basic and lowest power mode that BQ769x0 supports. SHIP mode is automatically entered during initial pack assembly and after every POR event. When the device is in NORMAL mode, it may enter SHIP by the host controller through a specific sequence of I2C commands. In SHIP mode, only a minimum of blocks is turned on, including the VSTUP power supply and primal boot detector. Waking from SHIP mode to NORMAL mode requires pulling the TS1 pin greater than VBOOT, which triggers the device boot-up sequence. To enter SHIP mode from NORMAL mode, the [SHUT_A] and [SHUT_B] bits in the SYS_CTRL1 register must be written with specific patterns across two consecutive writes: • • Write #1: [SHUT_A] = 0, [SHUT_B] = 1 Write #2: [SHUT_A] = 1, [SHUT_B] = 0 Note that [SHUT_A] and [SHUT_B] should each be in a 0 state prior to executing the shutdown command above. If this specific sequence is entered into the device, the device transitions into SHIP mode. If any other sequence is written to the [SHUT_A] and [SHUT_B] bits or if either of the two patterns is not correctly entered, the device will not enter SHIP mode. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 27 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 CAUTION DO NOT OPERATE THE DEVICE BELOW POR. When designing with the BQ76940, the intermediate voltages (BAT–VC10x), (VC10x–VC5x), and (VC5x–VSS) must each never fall below VSHUT. When this occurs, a full device reset must be initiated by powering down all three intermediate voltages (BAT–VC10x), (VC10x–VC5x), and (VC5x–VSS) below VSHUT and rebooting by applying the appropriate VBOOT signal to the TS1 pin. When designing with the BQ76930, the intermediate voltages (BAT–VC5x) and (VC5x–VSS) must each never fall below VSHUT. If this occurs, a full device reset must be initiated by powering down both intermediate voltages (BAT– VC5x) and (VC5x–VSS) below VSHUT and rebooting by applying the appropriate VBOOT signal to the TS1 pin. The device will also enter SHIP mode during a POR event; however, this is not a recommended method of SHIP mode entry. If any of the supply-side voltages fall below VSHUT and then back up above VPORA, the device defaults into the SHIP mode state. This is similar to an initial pack assembly condition. In order to exit SHIP mode into NORMAL mode, the device must follow the standard boot sequence by applying a voltage greater than the VBOOT threshold on the TS1 pin. The BQ769x0 Boot Switch Alternatives Application Report details multiple methods for generating the needed signal on the TS1 pin. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.5 Register Maps Name Addr D7 D6 D5 D4 D3 D2 D1 D0 SYS_STAT 0x00 CC_READY RSVD DEVICE_ XREADY OVRD_ ALERT UV OV SCD OCD SHUT_A SHUT_B DSG_ON CHG_ON CELLBAL1 0x01 RSVD RSVD RSVD CB CELLBAL2(1) 0x02 RSVD RSVD RSVD CB CELLBAL3(2) 0x03 RSVD RSVD RSVD SYS_CTRL1 0x04 LOAD_ PRESENT RSVD RSVD SYS_CTRL2 0x05 DELAY_DIS CC_EN CC_ ONESHOT PROTECT1 0x06 RSNS RSVD PROTECT2 0x07 RSVD PROTECT3 0x08 OV_TRIP 0x09 UV_TRIP 0x0A CC_CFG 0x0B RSVD RSVD VC1_HI 0x0C RSVD RSVD VC1_LO 0x0D VC2_HI 0x0E VC2_LO 0x0F VC3_HI 0x10 VC3_LO 0x11 VC4_HI 0x12 VC4_LO 0x13 VC5_HI 0x14 VC5_LO 0x15 VC6_HI(1) 0x16 VC6_LO(1) 0x17 VC7_HI(1) 0x18 VC7_LO(1) 0x19 VC8_HI(1) 0x1A VC8_LO(1) 0x1B VC9_HI(1) 0x1C VC9_LO(1) 0x1D VC10_HI(1) 0x1E VC10_LO(1) 0x1F VC11_HI(2) 0x20 VC11_LO(2) 0x21 VC12_HI(2) 0x22 VC12_LO(2) 0x23 VC13_HI(2) 0x24 VC13_LO(2) 0x25 VC14_HI(2) 0x26 VC14_LO(2) 0x27 CB ADC_EN RSVD TEMP_SEL RSVD SCD_DELAY OCD_THRESH OV_DELAY RSVD OV_THRESH UV_THRESH Must be programmed to 0x19 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VC15_HI(2) 0x28 VC15_LO(2) 0x29 BAT_HI 0x2A BAT_LO 0x2B TS1_HI 0x2C TS1_LO 0x2D TS2_HI(1) 0x2E SCD_THRESH OCD_DELAY UV_DELAY RSVD RSVD RSVD RSVD RSVD RSVD RSVD Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 29 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Name Addr TS2_LO(1) 0x2F TS3_HI(2) 0x30 TS3_LO(2) 0x31 CC_HI 0x32 CC_LO 0x33 ADCGAIN1 0x50 ADCOFFSET 0x51 ADCGAIN2 0x59 (1) (2) D7 D6 D5 D4 D3 D2 D1 D0 RSVD RSVD RSVD ADCGAIN RSVD ADCOFFSET ADCGAIN RSVD These registers are only valid for BQ76930 and BQ76940. These registers are only valid for BQ76940. 8.5.1 Register Details Table 8-3. SYS_STAT (0x00) BIT 7 6 5 4 3 2 1 0 NAME CC_READY RSVD DEVICE_ XREADY OVRD_ ALERT UV OV SCD OCD RESET 0 0 0 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW Note Bits in SYS_STAT may be cleared by writing a "1" to the corresponding bit. Writing a "0" does not change the state of the corresponding bit. CC_READY (Bit 7): Indicates that a fresh coulomb counter reading is available. Note that if this bit is not cleared between two adjacent CC readings becoming available, the bit remains latched to 1. This bit may only be cleared (and not set) by the host. 0 = Fresh CC reading not yet available or bit is cleared by host microcontroller. 1 = Fresh CC reading is available. Remains latched high until cleared by host. RSVD (Bit 6): Reserved. Do not use. DEVICE_XREADY (Bit 5): Internal chip fault indicator. When this bit is set to 1, it should be cleared by the host. May be set due to excessive system transients. This bit may only be cleared (and not set) by the host. 0 = Device is OK. 1= Internal chip fault detected, recommend that host microcontroller clear this bit after waiting a few seconds. Remains latched high until cleared by the host. OVRD_ALERT (Bit 4): External pull-up on the ALERT pin indicator. Only active when ALERT pin is not already being driven high by the AFE itself. 0 = No external override detected 1 = External override detected. Remains latched high until cleared by the host. UV (Bit 3): Undervoltage fault event indicator. 0 = No UV fault is detected. 1 = UV fault is detected. Remains latched high until cleared by the host. OV (Bit 2): Overvoltage fault event indicator. 0 = No OV fault is detected. 1 = OV fault is detected. Remains latched high until cleared by the host. SCD (Bit 1): Short circuit in discharge fault event indicator. 0 = No SCD fault is detected. 1 = SCD fault is detected. Remains latched high until cleared by the host. OCD (Bit 0): Over current in discharge fault event indicator. 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 0 = No OCD fault is detected. 1 = OCD fault is detected. Remains latched high until cleared by the host. Table 8-4. CELLBAL1 (0x01) for BQ76920, BQ76930, and BQ76940 BIT 7 6 5 4 3 2 1 0 NAME — — — CB5 CB4 CB3 CB2 CB1 RESET 0 0 0 0 0 0 0 0 ACCESS R R R RW RW RW RW RW CBx (Bits 4–0): 0 = Cell balancing on Cell “x” is disabled. 1 = Cell balancing on Cell “x” is enabled. Table 8-5. CELLBAL2 (0x02) for BQ76930 and BQ76940 BIT 7 6 5 4 3 2 1 0 NAME — — — CB10 CB9 CB8 CB7 CB6 RESET 0 0 0 0 0 0 0 0 ACCESS R R R RW RW RW RW RW CBx (Bits 4–0): 0 = Cell balancing on Cell “x” is disabled. 1 = Cell balancing on Cell “x” is enabled. Table 8-6. CELLBAL3 (0x03) for BQ76940 BIT 7 6 5 4 3 2 1 0 NAME — — — CB15 CB14 CB13 CB12 CB11 RESET 0 0 0 0 0 0 0 0 ACCESS R R R RW RW RW RW RW CBx (Bits 4–0): 0 = Cell balancing on Cell “x” is disabled. 1 = Cell balancing on Cell “x” is enabled. Table 8-7. SYS_CTRL1 (0x04) BIT 7 6 5 4 3 2 1 0 NAME LOAD_ PRESENT — — ADC_EN TEMP_SEL RSVD SHUT_A SHUT_B RESET 0 0 0 0 0 0 0 0 ACCESS R R R RW RW RW RW RW LOAD_PRESENT (Bit 7): Valid only when [CHG_ON] = 0. Is high if CHG pin is detected to exceed VLOAD_DETECT while CHG_ON = 0, which suggests that external load is present. Note this bit is read-only and automatically clears when load is removed. 0 = CHG pin < VLOAD_DETECT or [CHG_ON] = 1. 1 = CHG pin >VLOAD_DETECT, while [CHG_ON] = 0. ADC_EN (Bit 4): ADC enable command 0 = Disable voltage and temperature ADC readings (also disables OV protection) 1 = Enable voltage and temperature ADC readings (also enables OV protection) TEMP_SEL (Bit 3): TSx_HI and TSx_LO temperature source 0 = Store internal die temperature voltage reading in TSx_HI and TSx_LO Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 31 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 1 = Store thermistor reading in TSx_HI and TSx_LO (all thermistor ports) RSVD (Bit 2): Reserved, do not set to 1. SHUT_A, SHUT_B (Bits 1–0): Shutdown command from host microcontroller. Must be written in a specific sequence, shown below: Starting from: [SHUT_A] = 0, [SHUT_B] = 0 Write #1: [SHUT_A] = 0, [SHUT_B] = 1 Write #2: [SHUT_A] = 1, [SHUT_B] = 0 Other writes cause the command to be ignored. Table 8-8. SYS_CTRL2 (0x05) BIT 7 6 5 4 3 2 1 0 RSVD RSVD RSVD DSG_ON CHG_ON NAME DELAY_DIS CC_EN CC_ ONESHOT RESET 0 0 0 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW DELAY_DIS (Bit 7): Disable OV, UV, OCD, and SCD delays for faster customer production testing. 0 = Normal delay settings 1 = OV, UV, OCD, and SCD delay circuit is bypassed, creating zero delay (approximately 250 ms). CC_EN (Bit 6): Coulomb counter continuous operation enable command. If set high, [CC_ONESHOT] bit is ignored. 0 = Disable CC continuous readings 1 = Enable CC continuous readings and ignore [CC_ONESHOT] state CC_ONESHOT (Bit 5): Coulomb counter single 250-ms reading trigger command. If set to 1, the coulomb counter will be activated for a single 250-ms reading, and then turned back off. [CC_ONESHOT] will also be cleared at the conclusion of this reading, while [CC_READY] bit will be set to 1. 0 = No action 1 = Enable single CC reading (only valid if [CC_EN] = 0), and [CC_READY] = 0) RSVD (Bits 4–2): Reserved. Do not use. DSG_ON (Bit 1): Discharge FET driver (low side NCH) or discharge signal control 0 = DSG is off. 1 = DSG is on. CHG_ON (Bit 0): Discharge FET driver (low side NCH) or discharge signal control 0= CHG is off. 1= CHG is on. Table 8-9. PROTECT1 (0x06) BIT 7 6 5 4 3 2 1 0 NAME RSNS — RSVD SCD_D1 SCD_D0 SCD_T2 SCD_T1 SCD_T0 RESET 0 0 0 0 0 0 0 0 ACCESS RW R RW RW RW RW RW RW RSNS (Bit 7): Allows for doubling the OCD and SCD thresholds simultaneously 0 = OCD and SCD thresholds at lower input range 1 = OCD and SCD thresholds at upper input range RSVD (Bit 5): Reserved, do not set to 1. SCD_D1:0 (Bits 4–3): Short circuit in discharge delay setting. A 400-µs setting is recommended only in systems using maximum cell measurement input resistance, Rc, of 1 kΩ (which corresponds to minimum internal cell balancing current or external cell balancing configuration). 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Code (in µs) 0x0 70 0x1 100 0x2 200 0x3 400 SCD_T2:0 (Bits 2–0): Short circuit in discharge threshold setting Code RSNS = 1 (in mV) RSNS = 0 (in mV) 0x0 44 22 0x1 67 33 0x2 89 44 0x3 111 56 0x4 133 67 0x5 155 78 0x6 178 89 0x7 200 100 Table 8-10. PROTECT2 (0x07) BIT 7 6 5 4 3 2 1 0 NAME — OCD_D2 OCD_D1 OCD_D0 OCD_T3 OCD_T2 OCD_T1 OCD_T0 RESET 0 0 0 0 0 0 0 0 ACCESS R RW RW RW RW RW RW RW OCD_D2:0 (Bits 6–4): Overcurrent in discharge delay setting Code (in ms) 0x0 8 0x1 20 0x2 40 0x3 80 0x4 160 0x5 320 0x6 640 0x7 1280 OCD_T3:0 (Bits 3–0): Overcurrent in discharge threshold setting Code RSNS = 1 (in mV) (RSNS = 0 (in mV) 0x0 17 8 0x1 22 11 0x2 28 14 0x3 33 17 0x4 39 19 0x5 44 22 0x6 50 25 0x7 56 28 0x8 61 31 0x9 67 33 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 33 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Code RSNS = 1 (in mV) (RSNS = 0 (in mV) 0xA 72 36 0xB 78 39 0xC 83 42 0xD 89 44 0xE 94 47 0xF 100 50 Table 8-11. PROTECT3 (0x08) BIT 7 6 5 4 3 2 1 0 NAME UV_D1 UV_D0 OV_D1 OV_D0 RSVD RSVD RSVD RSVD RESET 0 0 0 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW UV_D1:0 (Bits 7–6): Undervoltage delay setting Code (in s) 0x0 1 0x1 4 0x2 8 0x3 16 Code (in s) 0x0 1 0x1 2 0x2 4 0x3 8 OV_D1:0 (Bits 5–4): Overvoltage delay setting RSVD (Bits 3–0): These bits are for TI internal debug use only and must be configured to the default settings indicated. Table 8-12. OV_TRIP (0x09) BIT 7 6 5 4 3 2 1 0 NAME OV_T7 OV_T6 OV_T5 OV_T4 OV_T3 OV_T2 OV_T1 OV_T0 RESET 1 0 1 0 1 1 0 0 ACCESS RW RW RW RW RW RW RW RW OV_T7:0 (Bits 7–0): Middle 8 bits of the direct ADC mapping of the desired OV protection threshold, with upper 2 MSB set to 10 and lower 4 LSB set to 1000. The equivalent OV threshold is mapped to: 10-OV_T1000. By default, OV_TRIP is configured to a 0xAC setting. Note that OV_TRIP is based on the ADC voltage, which requires back-calculation using the GAIN and OFFSET values stored in ADCGAINand ADCOFFSET. Table 8-13. UV_TRIP (0x0A) 34 BIT 7 6 5 4 3 2 1 0 NAME UV_T7 UV_T6 UV_T5 UV_T4 UV_T3 UV_T2 UV_T1 UV_T0 RESET 1 0 0 1 0 1 1 1 ACCESS RW RW RW RW RW RW RW RW Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 UV_T7:0 (Bits 7–0): Middle 8 bits of the direct ADC mapping of the desired UV protection threshold, with upper 2 MSB set to 01 and lower 4 LSB set to 0000. In other words, the equivalent OV threshold is mapped to: 01-UV_T–0000. By default, UV_TRIP is configured to a 0x97 setting. Note that UV_TRIP is based on the ADC voltage, which requires back-calculation using the GAIN and OFFSET values stored in ADCGAINand ADCOFFSET. Table 8-14. CC_CFG REGISTER (0x0B) BIT 7 6 5 4 3 2 1 0 NAME — — CC_CFG5 CC_CFG4 CC_CFG3 CC_CFG2 CC_CFG1 CC_CFG0 RESET 0 0 0 0 0 0 0 0 ACCESS R R RW RW RW RW RW RW CC_CFG5:0 (Bits 5–0): For optimal performance, these bits should be programmed to 0x19 upon device startup. 8.5.2 Read-Only Registers Table 8-15. CELL VOLTAGE REGISTERS VC1_HI, _LO (0x0C–0x0D), VC2_HI, _LO (0x0E–0x0F), VC3_HI, _LO (0x10–0x11), VC4_HI, _LO (0x12–0x13), VC5_HI, _LO (0x14– 0x15) / BQ76930, BQ76940: VC6_HI, _LO (0x16–0x17), VC7_HI, _LO (0x18–0x19), VC8_HI, _LO (0x1A–0x1B), VC9_HI, _LO (0x1C– 0x1D), VC10_HI, _LO (0x1E–0x1F) / BQ76940: VC11_HI, _LO (0x20–0x21), VC12_HI, _LO (0x22–0x23), VC13_HI, _LO (0x24–0x25), VC14_HI, _LO (0x26–0x27), VC15_HI, _LO (0x28–0x29) BIT 7 6 5 4 3 2 1 0 NAME — — D13 D12 D11 D10 D9 D8 RESET 0 0 0 0 0 0 0 0 NAME D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 D11:8 (Bits 3–0): Cell “x” ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). D7:0 (Bits 7–0): Cell ”x” ADC reading, lower 8 LSB. Table 8-16. BAT_HI (0x2A) and BAT_LO (0x2B) BIT 7 6 5 4 3 2 1 0 NAME D15 D14 D13 D12 D11 D10 D9 D8 RESET 0 0 0 0 0 0 0 0 NAME D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 D15:8 (Bits 7–0): BAT calculation based on adding up Cells 1–15, upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). D7:0 (Bits 7–0): BAT calculation based on adding up Cells 1–15, lower 8 LSB Table 8-17. TS1_HI (0x2C) and TS1_LO (0x2D) BIT 7 6 5 4 3 2 1 0 NAME — — D13 D12 D11 D10 D9 D8 RESET 0 0 0 0 0 0 0 0 NAME D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 D11:8 (Bits 3–0): TS1 or DIETEMP ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 35 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 D7:0 (Bits 7–0): TS1 or DIETEMP ADC reading, lower 8 LSB Table 8-18. TS2_HI (0x2E) and TS2_LO (0x2F) BIT 7 6 5 4 3 2 1 0 NAME — — D13 D12 D11 D10 D9 D8 RESET 0 0 0 0 0 0 0 0 NAME D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 D11:8 (Bits 3–0): TS2 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). D7:0 (Bits 7–0): TS2 ADC reading, lower 8 LSB Table 8-19. TS3_HI (0x30) and TS3_LO (0x31) BIT 7 6 5 4 3 2 1 0 NAME — — D13 D12 D11 D10 D9 D8 RESET 0 0 0 0 0 0 0 0 NAME D7 D6 D5 D4 D3 D2 D1 D0 RESET 0 0 0 0 0 0 0 0 D11:8 (Bits 3–0): TS3 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). D7:0 (Bits 7–0): TS3 ADC reading, lower 8 LSB Table 8-20. CC_HI (0x32) and CC_LO (0x33) BIT 7 6 5 4 3 2 1 0 NAME CC15 CC14 CC13 CC12 CC11 CC10 CC9 CC8 RESET 0 0 0 0 0 0 0 0 NAME CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 RESET 0 0 0 0 0 0 0 0 CC15:8 (Bits 7–0): Coulomb counter upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same transaction (using address auto-increment). CC7:0 (Bits 7–0): Coulomb counter lower 8 LSB Table 8-21. ADCGAIN1 (0x50) BIT 7 6 5 4 3 2 1 0 NAME — — — — ADCGAIN4 ADCGAIN3 — — RESET — — — — — — — — ACCESS R R R R R R R R BIT 7 6 5 4 3 2 1 0 NAME ADCGAIN2 ADCGAIN1 ADCGAIN0 — — — — — RESET — — — — — — — — ACCESS R R R R R R R R Table 8-22. ADCGAIN2 (0x59) ADCGAIN4:3 (Bits 3–2, address 0x50): ADC GAIN offset upper 2 MSB ADCGAIN2:0 (Bits 7–5, address 0x59): 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 ADC GAIN offset lower 3 LSB ADCGAIN is a production-trimmed value for the ADC transfer function, in units of µV/LSB. The range is 365 µV/LSB to 396 µV/LSB, in steps of 1 µV/LSB, and may be calculated as follows: GAIN = 365 µV/LSB + (ADCGAINin decimal) × (1 µV/LSB) Alternately, a conversion table is provided below: ADC GAIN Gain (µV/LSB) ADC GAIN Gain (µV/LSB) 0x00 365 0x10 381 0x01 366 0x11 382 0x02 367 0x12 383 0x03 368 0x13 384 0x04 369 0x14 385 0x05 370 0x15 386 0x06 371 0x16 387 0x07 372 0x17 388 0x08 373 0x18 389 0x09 374 0x19 390 0x0A 375 0x1A 391 0x0B 376 0x1B 392 0x0C 377 0x1C 393 0x0D 378 0x1D 394 0x0E 379 0x1E 395 0x0F 380 0x1F 396 Table 8-23. ADCOFFSET (0x51) BIT 7 6 5 4 3 2 1 0 NAME ADC OFFSET7 ADC OFFSET6 ADC OFFSET5 ADC OFFSET4 ADC OFFSET3 ADC OFFSET2 ADC OFFSET1 ADC OFFSET0 RESET — — — — — — — — ACCESS R R R R R R R R ADCOFFSET7:0 (Bits 7–0): ADC offset, stored in 2’s complement format in mV units. Positive full-scale range corresponds to 0x7F and negative full-scale corresponds to 0x80. The full-scale input range is –128 mV to 127 mV, with an LSB of 1 mV. The table below shows example offsets. ADCOFFSET Offset (mV) 0x00 0 0x01 1 0x7F 127 0x80 –128 0x81 –127 0xFF –1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 37 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The BQ769x0 family of battery monitoring AFEs enabling cell parametric measurement and protection is a variety of 3-series to 15-series Li-ion/li-polymer battery packs. To evaluate the performance and configurations of the device users need the , BQ76940, BQ76930, and BQ76920 Evaluation Software tool to configure the internal registers for a specific battery pack and application. The Evaluation Software tool is a graphical user-interface tool installed on a PC during development. This can be used in conjunction with the BQ76920EVM, BQ76930EVM or BQ76940EVM. The BQ769x0 devices are expected to be implemented in a system with a microcontroller that can perform additional functions based on the data made collected. The BQ78350-R1 is one example of a companion to the BQ769x0 family. Additional application information is available in the BQ769x0 Family Top Design Considerations Application Report. 9.1.1 Device Timing The device timeline accuracy is typically 3.5%. Each five-cell group in the BQ76930 and BQ76940 devices uses an independent 250-ms timeline, so voltage and temperature measurements of different groups drift with respect to one another. 9.1.2 Random Cell Connection The device design anticipated transient conditions during cell connection, but that design did not result in unique specifications. The large component value ranges used in the application circuits may require special considerations for random cell connection. See additional information in the BQ769x0 Family Top Design Considerations Application Report. 9.1.3 Power Pin Diodes The VC5X, VC10X, and BAT pins must have a diode from the top group input to the associated power pin, as shown in Figure 9-2 and Figure 9-3. These diodes limit the excursion of the input voltage above the supply. The diodes should be conventional diodes rather than Schottky type to allow some variation of the supply voltage without loading the cell input. When needed, two diodes may be used in series. 9.1.4 Alert Pin The ALERT pin is an input and output. The input is sensitive to noise and may benefit from a RC filter at the pin to reduce noise at the pin. A maximum 250-μs time constant is suggested to allow the pin to fall when it is cleared as an output before it is sampled as an input. 500-kΩ and 470-pF values are commonly recommended. Guard traces around the traces may be helpful to avoid crosstalk to the ALERT trace. 9.1.5 Sense Inputs The SRP input should operate near VSS, so VSS references the battery negative on the battery side of the sense resistor near the filter connection for SRP. The SRP and SRN have a common mode range to their supply from REGOUT and the VSS rail. When moving away from the recommended level due to high current or a buffer amplifier, the OCD and SCD may still trip, but accuracy could be compromised. 9.1.6 TSn Pins The TSn pins must connect with a thermistor or resistor to the reference power pin for the associated cell group, as shown in the applications diagram. A resistor must be connected for normal operation even if external 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 temperature measurement is not used. When thermistors are removable, they should be substituted with a test resistance at board test to prevent XREADY faults during test. The TSn pins should not be pulled below their reference power pin or the device may not start properly or the ADC may not operate properly. A capacitor across the thermistor is not required but may filter noise picked up by thermistor leads. The thermistor is biased 37.5 ms before measurement begins, so a 4.7-nF capacitor, such as is used on the evaluation module or smaller, allows many time constants for settling before measurement. Note The capacitor across the thermistor does not filter noise that may be picked up by the thermistor leads between different thermistors on the BQ76930 or BQ76940 devices. TS1 is also used to boot the part. A rising edge is required for boot. A high level maintained on TS1 does not prevent shutdown or waking the part. A voltage level maintained on the TS1 pin after boot affects the voltage on the thermistor and the temperature determined by the MCU if external temperature sensing is used in normal operation. 9.1.7 Unused Pins Pins should be connected to the appropriate circuits, as shown in the simplified diagrams in Typical Applications and as described in the Pin Configuration and Functions section. See Pin Usage for additional comments. Table 9-1. Pin Usage PIN NAME RECOMMENDATION DSG, CHG DSG and CHG are outputs and may be left unconnected if not used. VSS Must be used SDA, SCL Must be used TSn Must have a thermistor or pull down resistor to the group reference. TS1 must have a rising edge to boot the part. CAPn A capacitor must be installed. REGOUT REGOUT also supplies internal circuits. A capacitor must be installed even if REGOUT is not used for external circuitry. REGSRC Must be supplied BAT Primary power pin for the part, must be connected to the top cell through the power filter VC5x, VC10x Must connect to the appropriate cell through the power filter NC Some pins named NC must be connected to the appropriate CAPn pin. See Pin Configuration and Functions . VCn Cell voltage sense input pins. Must be connected through the input filter to the cells. When not all cells are needed, connect as described in Configuring Alternative Cell Counts. SRP, SRN Current sense inputs. When not used, connect to VSS. ALERT When not used, a pulldown is recommended. See Alert Pin. 9.1.8 Configuring Alternative Cell Counts Each BQ769x0 family of IC's support a variety of cell counts. The following tables provide guidance on which device and which input pins to use, depending on the number of cells in the pack. Table 9-2. Cell Connections for BQ76920 Cell Input 3 Cells 4 Cells 5 Cells VC5–VC4 CELL 3 CELL 4 CELL 5 VC4–VC3 short short CELL 4 VC3–VC2 short CELL 3 CELL 3 VC2–VC1 CELL 2 CELL 2 CELL 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 39 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table 9-2. Cell Connections for BQ76920 (continued) Cell Input 3 Cells 4 Cells 5 Cells VC1–VC0 CELL 1 CELL 1 CELL 1 Table 9-3. Cell Connections for BQ76930 Cell Input 6 Cells 7 Cells 8 Cells 9 Cells 10 Cells VC10–VC9 CELL 6 CELL 7 CELL 8 CELL 9 CELL 10 VC9–VC8 short short short short CELL 9 VC8–VC7 short short CELL 7 CELL 8 CELL 8 VC7–VC6 CELL 5 CELL 6 CELL 6 CELL 7 CELL 7 VC6–VC5b CELL 4 CELL 5 CELL 5 CELL 6 CELL 6 VC5–VC4 CELL 3 CELL 4 CELL 4 CELL 5 CELL 5 VC4–VC3 short short short CELL 4 CELL 4 VC3–VC2 short CELL 3 CELL 3 CELL 3 CELL 3 VC2–VC1 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 VC1–VC0 CELL 1 CELL 1 CELL 1 CELL 1 CELL 1 Table 9-4. Cell Connections for BQ76940 40 Cell Input 9 Cells 10 Cells 11 Cells 12 Cells 13 Cells 14 Cells 15 Cells VC15–VC14 CELL 9 CELL 10 CELL 11 CELL 12 CELL 13 CELL 14 CELL 15 VC14–VC13 short short short short short short CELL 14 VC13–VC12 short short short CELL 11 CELL 12 CELL 13 CELL 13 VC12–VC11 CELL 8 CELL 9 CELL 10 CELL 10 CELL 11 CELL 12 CELL 12 VC11–VC10b CELL 7 CELL 8 CELL 9 CELL 9 CELL 10 CELL 11 CELL 11 VC10–VC9 CELL 6 CELL 7 CELL 8 CELL 8 CELL 9 CELL 10 CELL 10 VC9–VC8 short short short short short CELL 9 CELL 9 VC8–VC7 short short CELL 7 CELL 7 CELL 8 CELL 8 CELL 8 VC7–VC6 CELL 5 CELL 6 CELL 6 CELL 6 CELL 7 CELL 7 CELL 7 VC6–VC5b CELL 4 CELL 5 CELL 5 CELL 5 CELL 6 CELL 6 CELL 6 VC5–VC4 CELL 3 CELL 4 CELL 4 CELL 4 CELL 5 CELL 5 CELL 5 VC4–VC3 short short short short CELL 4 CELL 4 CELL 4 VC3–VC2 short CELL 3 CELL 3 CELL 3 CELL 3 CELL 3 CELL 3 VC2–VC1 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 VC1–VC0 CELL 1 CELL 1 CELL 1 CELL 1 CELL 1 CELL 1 CELL 1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 9.2 Typical Applications CAUTION The external circuitries in the following schematics show minimum requirements to ensure device robustness during cell connection to the PCB and normal operation. PACK + Rf BAT Rc Cc Rc Cc Rc VC 5 REGSRC VC 4 REGOUT VC 3 CAP 1 VC 2 TS 1 VC 1 SCL VC 0 10 kΩ 1 µF 1 µF Cf 4.7 µF 10 k SDA Cc Rc SRP VSS SRN CHG ALERT DSG PUSH - BUTTON FOR BOOT Cc VCC Rc Cc SCL SDA Cc Companion Controller GPIO 1M Rc VSS 0 .1 µF 0 .1 µF 100 0 .1 µF 100 1M 1M Rsns PACK – Figure 9-1. BQ76920 with BQ78350 Companion Controller IC Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 41 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 PACK + Rc Cc Rc Cc Rc Cc Rc Rf VC10 Cc Rc Cc VC5x Rc VC9 CAP2 VC8 TS2 VC7 NC VC6 Cc VC5b A Rc Cc Rc Cc Rc Cc Rc Cc Rc Rc BAT Cf 10k 1 µF NC A VC5x VC5 REGSRC VC4 REGOUT VC3 CAP1 VC2 TS1 VC1 SCL VC0 SDA SRP VSS SRN CHG ALERT DSG Rf 10 kΩ 1µF 1µF Cf 4.7 µF 10k PUSH-BUTTON FOR BOOT VCC Cc SCL SDA Cc 1M 0.1 µF 0.1 µF 100 Companion Controller GPIO VSS 0.1 µF 100 1M 1M Rsns PACK Copyright © 2016, Texas Instruments Incorporated Figure 9-2. BQ76930 With BQ78350 Companion Controller IC 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 PACK + Rc Cc Rc Cc Rc Cc Rc Cc Rc Cc VC10x Rc Cc Rf B Rc Cc Rc VC15 Cc Rc Cc VC14 BAT VC13 CAP3 VC12 TS3 VC11 NC VC10b Rc Cc Rc Cc VC5x Rc VC10x VC9 CAP2 VC8 TS2 VC7 NC VC5b Rc Cc Rc Cc Rc Cc Rc Cc B Rf Cf 10k 1 µF NC VC5x VC5 REGSRC VC4 REGOUT VC3 CAP1 VC2 TS1 VC1 SCL VC0 SDA SRP VSS SRN CHG ALERT DSG A Rf 10 kΩ 1 µF 1 µF Cf 4.7 µF 10k PUSH-BUTTON FOR BOOT VCC Rc Rc 1 µF NC VC10 VC6 Cc A Cf 10k Cc SCL SDA Cc 1M 0.1 µF 0.1 µF 100 Companion Controller GPIO VSS 0.1 µF 100 1M 1M Rsns PACK – Copyright © 2016, Texas Instruments Incorporated Figure 9-3. BQ76940 with BQ78350 Companion Controller IC Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 43 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 1M Rpchg 10 M Rgs Rc Cc Rc 10 M Rgs Cc Rc PACK+ 10 M Rgs Cc Rc Cc Rc Cc VC10x Rc Cc B Analog Front End Rf Cc Rc Cc Rc VC14 BAT VC13 CAP3 VC12 TS3 VC11 Cc 470 nF CVDDCP 100 Rfilter VC15 B Rc 1 µF 0.01 µF Cfilter Rf VC10b Rc Cc Rc Cc VC10 VC10x VC9 CAP2 VC8 TS2 VC5b A Cc Rc Cc Rc Cc Rc Cc Rc Rc DSG Cf 10k PACK PCHG_EN Rf VSS 1 µF Ra VC5x VC5 REGSRC VC4 REGOUT VC3 CAP1 VC2 TS1 VC1 SCL VC0 SDA SRP VSS SRN CHG ALERT DSG 10 NŸ 1 µF Cf 4.7 µF 1 µF 10 k PUSH-BUTTON FOR BOOT Cc GPIO GPIO VCC GPIO SCL SDA Cc µC ADC_IN GPIO 0.1 µF 0.1 µF 100 0.01 µF Cfilter PMON_EN PACKDIV VC6 Cc Rc NC CHG_EN DSG_EN A 100 Rfilter PCHG NC CP_EN VC7 bq76940 VC5x Rc NC BAT Cf 10k bq76200 CHG VDDCP 0.1 µF Rb VSS 100 Rsns PACK- Figure 9-4. BQ76940 with BQ78350 Companion Controller IC and BQ76200 High-Side N-Channel FET Driver 9.2.1 Design Requirements Table 9-5. BQ769x0 Design Requirements DESIGN PARAMETER 44 EXAMPLE VALUE at TA = 25°C Minimum system operating voltage 24 V Cell minimum operating voltage 3.0 V Series Cell Count 8 Charge Voltage 33.6 V Maximum Charge Current 3.0 A Peak Discharge Current 10.0 A OV Protection Threshold 4.30 V OV Protection Delay 2s UV Protection Threshold 2.5 V UV Protection Delay 4s OCD Protection Threshold Max 15 A OCD Protection Delay Time 320 ms SCD Protection Threshold Max 25 A Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table 9-5. BQ769x0 Design Requirements (continued) DESIGN PARAMETER EXAMPLE VALUE at TA = 25°C SCD Protection Delay Time 100 µs 9.2.2 Detailed Design Procedure To begin the design process, there are some key steps required for component selection and protection configuration. 9.2.2.1 Step-by-Step Design Procedure • • • • • • Determine the number of series cells. – This value depends on the cell chemistry and the load requirements of the system. For example, to support a minimum battery voltage of 24 V using Li-CO2 type cells with a cell minimum voltage of 3.0 V, there needs to be at least 8-series cells. Select the correct BQ769x0 device. – For 8-series cells, the BQ76930 is needed. – For the correct cell connections, see Table 9-3. Select the correct protection FETs. – The BQ76930 uses a low-side drive suitable for N-CH FETs. – These FETs should be rated for the maximum: • Voltage, which should be approximately 5 V (DC) 10 V (peak) per series cell: for example, 40 V. • Current, which should be calculated based on both the maximum DC current and the maximum transient current with some margin: for example, 30 A. • Power Dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the PCB design: for example, 5 W, assuming 5 mΩ RDS(ON). Select the correct sense resistor. – The resistance value should be selected to maximize the input bandwidth use of the coulomb counter range, CCRANGE, as well as keeping the SCD and OCD thresholds in the available selections, and not exceed the absolute maximum ratings. The sense resistance RSNS is the threshold or input voltage divided by the current. • Using the normal max discharge current, RSNS = 200 mV / 10.0 A = 20 mΩ maximum. • However, considering the maximum SCD threshold of 200 mV and ISCD of 25 A , RSNS = 200 mV / 25 A = 8 mΩ maximum. • The maximum OCD threshold available is 100 mV, with the maximum current of 15 A, RSNS = 100 mV / 15.0 A = 6.7 mΩ maximum. – Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin should also be considered, so RSNS of 5 mΩ would be suitable with a 75-ppm temperature coefficient and power rating of 5 W. – With VSS referenced at the SRP terminal charge current creates a negative voltage on SRN. The 5 mΩ with 3 A charge current is within the absolute maximum range. The BQ76930 is chosen, and so the REGSRC pin needs to be powered through a source follower circuit where the FET is used to provide current for REGSRC from the battery positive terminal while reducing the voltage to a suitable value for the IC. – The FET also dissipates the power resulting from the load current and dropped voltage external to the IC and care should be taken to ensure the correct dissipation ratings are specified by the chosen FET. Configure the Current-based protection settings through PROTECT1 and PROTECT2: – Ideal SCD Threshold = 25 A × 5 mΩ = 125 mV. • However, the closest options are 111 mV (0x03) and 133 mV (0x04) providing 22.2 A and 26.6 A, respectively. Both options have the RSNS bit = 1. • 0x03 (22.2 A) will be used in this example. – The SCD delay threshold setting for a 100 µs delay is 0x01. – Therefore, PROTECT1 should be programmed with 0x8B. – Ideal OCD Threshold = 15 A × 5 mΩ = 75 mV. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 45 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 • However, the closest options are 72 mV (0x0A) and 78 mV (0x0B), providing 14.4 A and 15.6 A, respectively. Both options have the RSNS bit = 1. • 0x0A (14.4A) will be used in this example. – The OCD delay threshold setting for a 320-ms delay is 0x05. – Therefore, PROTECT2 should be programmed with 0x5B. Note Care should be taken when determining the setting of OV_TRIP and UV_TRIP as these are ADC value outputs and correlation to cell voltage also requires consideration of the ADC GAIN and ADC OFFSET registers. More specific details can be found in Section 8.3.1.2. • Configure the Voltage-based protection settings through OV_TRIP, UV_TRIP and PROTECT3: – The selected OV Threshold is 4.30 V. If ADCOFFSET is 0 and GAIN is 382, the desired threshold is 11257 or 0x2BF9. • Therefore, OV_TRIP should be programmed with 0xBF. – The selected UV Threshold is 2.5 V. If ADCOFFSET is 0 and GAIN is 382, the desired threshold is 6545 or 0x1991. • Therefore, UV_TRIP should be programmed with 0x99. – The selected OV Delay is 2 s and the selected UV Delay is 4 s. • Therefore, PROTECT3 should be programmed with 0x50. 9.2.3 Application Curves 0.020 0.016 VC2 Error ±0.2 0.014 VC3 Error ±0.4 0.012 VC4 Error 0.010 VC5 Error Offset (uV) VCx Error (V) 0.0 VC1 Error 0.018 0.008 0.006 0.004 ±0.6 ±0.8 ±1.0 ±1.2 0.002 0.000 ±1.4 ±0.002 ±0.004 2.00 2.30 2.60 2.90 3.20 3.50 3.80 4.10 4.40 4.70 5.00 VCx Input (V) ±1.6 ±40 ±15 Figure 9-5. BQ76930 VCx Error Across Input Range at 25°C 10 35 60 Temperature (ƒC) C001 85 C002 Figure 9-6. Coulomb Counter Offset 10 Power Supply Recommendations The BQ769x0 devices are powered through the BAT and REGSRC pins but the BQ76930 and BQ76940 have additional ‘Power’ pins to provide the power to the entire device in the higher cell configurations. The use of Rf and Cf connected to the BAT pin, noted in the typical application diagrams, are required to filter system transients from disturbing the device power supply. These components should be placed as close as to the IC as possible. Additionally, for the BQ76930 and BQ76940 there are additional requirements to ensure a stable power supply to the device. The REGSRC pin is powered through a source follower circuit where the FET is used to provide current for REGSRC from the battery positive terminal while reducing the voltage to a suitable value for the IC. The FET also dissipates the power resulting from the load current and dropped voltage external to the IC and care should be taken to ensure the correct dissipation ratings are specified by the chosen FET. The BQ76920 does not use a FET because the battery voltage is within the REGSRC range. More information on this topic is available in the BQ769x0 Family Top Design Considerations Application Report. 46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 11 Layout 11.1 Layout Guidelines It is strongly recommended for best measurement performance to keep high current signals from interfering with the measurement system inputs and ground. A second key recommendation is to ensure that the BQ769x0 input filtering capacitors and power capacitors are connected to a common ground with as little parasitic resistance between the connections as possible. 11.2 Layout Example Figure 11-1 shows a guideline of how to place key components compared to respective ground zones, based on the BQ76920, BQ76930, and BQ76940 EVMs. bq769x0 bq78350 Low Current Ground Plane Available Area Key components placed here bq78350 bq76920/30/40 Measurement Filter Resistors and Capacitors Ground interconnect BAT- RSNS DSG CHG Key components placed here Protection FETs Sense Resistor BAT+ PACK- PACK+ High Current Ground Plane Available Area Figure 11-1. System Component Placement Layout vs. Ground Zone Guide CAUTION Care should be taken when placing key power pin capacitors to minimize PCB trace impedances. These impedances could result in device resets or other unexpected operations when the device is at peak power consumption. Although not shown in the diagrams, this caution also applies to the resistor and capacitor network surrounding the current sense resistor. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 47 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 BATTERY– bq76920 REGSRC REGOUT VC1 VC0 PCB Trace impedance VSS SENSE RESISTOR Figure 11-2. Good Layout: Input Capacitor Grounding With Low Parasitic PCB Impedance BATTERY– bq76920 REGSRC REGOUT VC1 VC0 PCB Trace impedance VSS SENSE RESISTOR Figure 11-3. Weak Layout: Input Capacitor Grounding with High Parasitic PCB Impedance 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 12 Device and Documentation Support 12.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support For related documentation, see the following: • BQ76200 High Voltage Battery Pack Front-End Charge/Discharge High-Side NFET Driver Data Sheet (SLUSC16) • BQ769x0 Family Top Design Considerations Application Report (SLUA749) • BQ769x0 Boot Switch Alternatives Application Report (SLUA769) • BQ769x0 Pin Equivalent Diagrams (SLVA682) • BQ769x0 BMS Configurations for Cordless Appliances (SLUA810) • Fault Monitoring for High-Availability Systems Using the BQ769x0 (SLUA805) 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY BQ76920 Click here Click here Click here Click here Click here BQ76930 Click here Click here Click here Click here Click here BQ76940 Click here Click here Click here Click here Click here 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.5 Trademarks All trademarks are the property of their respective owners. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 49 PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ7692000PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7692000 BQ7692000PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7692000 BQ7692003PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7692003 BQ7692003PWR ACTIVE TSSOP PW 20 2000 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7692003 BQ7692006PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7692006 BQ7692006PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7692006 BQ7693000DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693000 BQ7693000DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693000 BQ7693001DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693001 BQ7693001DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693001 BQ7693002DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693002 BQ7693002DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693002 BQ7693003DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693003 BQ7693003DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693003 BQ7693006DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693006 BQ7693006DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693006 BQ7693007DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693007 BQ7693007DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7693007 BQ7694000DBT ACTIVE TSSOP DBT 44 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694000 BQ7694000DBTR ACTIVE TSSOP DBT 44 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694000 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 15-Jan-2021 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ7694001DBT ACTIVE TSSOP DBT 44 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694001 BQ7694001DBTR ACTIVE TSSOP DBT 44 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694001 BQ7694002DBT ACTIVE TSSOP DBT 44 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694002 BQ7694002DBTR ACTIVE TSSOP DBT 44 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694002 BQ7694003DBT ACTIVE TSSOP DBT 44 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694003 BQ7694003DBTR ACTIVE TSSOP DBT 44 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694003 BQ7694006DBT ACTIVE TSSOP DBT 44 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694006 BQ7694006DBTR ACTIVE TSSOP DBT 44 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7694006 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of