BQ7695201PFBR

BQ76952 SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 BQ76952 3-Series to 16-Series High Accuracy Battery Monitor and Protector for Li-Ion, Li-Polymer, and LiFePO4 Battery Packs 1 Features 2 Applications • • • • • • FUSE 5V BREG LD PDSG PCHG NC DSG PACK DSG + VC15 REGIN + VC14 REG1 + VC13 REG2 + VC12 RST_SHUT + VC11 DDSG + VC10 + VC9 DFETOFF + VC8 CFETOFF + VC7 HDQ + VC6 SDA + VC5 SCL + VC4 ALERT COMMUNICATIONS TRANSCEIVER COMM TO SYSTEM COMM VDD 3.3V MCU REG18 TS3 TS2 DCHG TS1 • + SRN • CHG NC • PACK+ SRP • BODY SIZE (NOM) 7 mm × 7 mm See the Device Comparison Table for information on the device family. For all available devices, see the orderable addendum at the end of the data sheet. CP1 • (1) PACKAGE PFB (48-pin) VSS • PART BQ76952xx BAT • Device Information NUMBER(1) CHG • • VC0 • The Texas Instruments BQ76952 device is a highly integrated, high-accuracy battery monitor and protector for 3-series to 16-series Li-ion, Lipolymer, and LiFePO4 battery packs. The device includes a high-accuracy monitoring system, a highly configurable protection subsystem, and support for autonomous or host controlled cell balancing. Integration includes high-side charge-pump NFET drivers, dual programmable LDOs for external system use, and a host communication peripheral supporting 400-kHz I2C, SPI, and HDQ one-wire standards. The BQ76952 device is available in a 48-pin TQFP package. VC1 • 3 Description VC16 • VC2 • Battery backup unit (BBU) E-bike, e-scooter, and LEV Cordless power tools and garden tools Non-military drones Other industrial battery pack (≥10S) VC3 • Battery monitoring capability for 3-series to 16series cells Integrated charge pump for high-side NFET protection with optional autonomous recovery Extensive protection suite including voltage, temperature, current, and internal diagnostics Two independent ADCs – Support for simultaneous current and voltage sampling – High-accuracy coulomb counter with input offset error < 1 µV (typical) – High accuracy cell voltage measurement < 10 mV (typical) Wide-range current applications (±200-mV measurement range across sense resistor) Integrated secondary chemical fuse drive protection Autonomous or host-controlled cell balancing Multiple power modes (typical battery pack operating range conditions) – NORMAL mode: 286 µA – Multiple SLEEP mode options: 24 µA to 41 µA – Multiple DEEPSLEEP mode options: 9 µA to 10 µA – SHUTDOWN mode: 1 µA High-voltage tolerance of 85 V on cell connect and select additional pins Tolerant of random cell attach sequence on production line Support for temperature sensing using internal sensor and up to nine external thermistors Integrated one-time-programmable (OTP) memory programmable by customers on production line Communication options include 400-kHz I2C, SPI, and HDQ one-wire interface Dual-programmable LDOs for external system usage 48-pin TQFP package (PFB) GND + + + PACK- Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 3 5 Device Comparison Table...............................................4 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 7 7.1 Absolute Maximum Ratings ....................................... 7 7.2 ESD Ratings .............................................................. 8 7.3 Recommended Operating Conditions ........................9 7.4 Thermal Information BQ76952 .................................10 7.5 Supply Current ......................................................... 10 7.6 Digital I/O ................................................................. 11 7.7 LD Pin ...................................................................... 12 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive ................................................................... 12 7.9 FUSE Pin Functionality ............................................ 12 7.10 REG18 LDO ...........................................................12 7.11 REG0 Pre-regulator ............................................... 13 7.12 REG1 LDO .............................................................13 7.13 REG2 LDO .............................................................14 7.14 Voltage References ................................................14 7.15 Coulomb Counter ...................................................15 7.16 Coulomb Counter Digital Filter (CC1) .................... 15 7.17 Current Measurement Digital Filter (CC2) ............. 16 7.18 Current Wake Detector .......................................... 16 7.19 Analog-to-Digital Converter ....................................16 7.20 Cell Balancing ........................................................ 18 7.21 Cell Open Wire Detector ........................................ 18 7.22 Internal Temperature Sensor ................................. 18 7.23 Thermistor Measurement .......................................18 7.24 Internal Oscillators ................................................. 19 7.25 High-side NFET Drivers ......................................... 20 7.26 Comparator-Based Protection Subsystem .............21 7.27 Timing Requirements - I2C Interface, 100kHz Mode .......................................................................... 23 7.28 Timing Requirements - I2C Interface, 400kHz Mode .......................................................................... 23 7.29 Timing Requirements - HDQ Interface ...................24 7.30 Timing Requirements - SPI Interface ..................... 24 7.31 Interface Timing Diagrams...................................... 25 7.32 Typical Characteristics............................................ 27 8 Device Description........................................................ 32 8.1 Overview................................................................... 32 8.2 Functional Block Diagram......................................... 33 8.3 BQ76952 Device Versions........................................ 33 8.4 Diagnostics............................................................... 33 9 Device Configuration.................................................... 34 9.1 Commands and Subcommands................................34 9.2 Configuration Using OTP or Registers......................34 9.3 Device Security......................................................... 34 9.4 Scratchpad Memory..................................................34 10 Measurement Subsystem........................................... 35 10.1 Voltage Measurement............................................. 35 10.2 General Purpose ADCIN Functionality................... 37 10.3 Coulomb Counter and Digital Filters....................... 37 10.4 Synchronized Voltage and Current Measurement.. 38 10.5 Internal Temperature Measurement........................38 2 10.6 Thermistor Temperature Measurement...................38 10.7 Factory Trim of Voltage ADC.................................. 39 10.8 Voltage Calibration (ADC Measurements).............. 39 10.9 Voltage Calibration (COV and CUV Protections).... 40 10.10 Current Calibration................................................41 10.11 Temperature Calibration........................................41 11 Primary and Secondary Protection Subsystems......42 11.1 Protections Overview.............................................. 42 11.2 Primary Protections.................................................42 11.3 Secondary Protections............................................ 43 11.4 High-Side NFET Drivers..........................................44 11.5 Protection FETs Configuration and Control.............45 11.6 Load Detect Functionality........................................45 12 Device Hardware Features..........................................46 12.1 Voltage References.................................................46 12.2 ADC Multiplexer...................................................... 46 12.3 LDOs.......................................................................46 12.4 Standalone Versus Host Interface.......................... 47 12.5 Multifunction Pin Controls....................................... 47 12.6 RST_SHUT Pin Operation...................................... 48 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality................................................................ 48 12.8 ALERT Pin Operation............................................. 48 12.9 DDSG and DCHG Pin Operation............................ 49 12.10 Fuse Drive.............................................................49 12.11 Cell Open Wire......................................................50 12.12 Low Frequency Oscillator..................................... 50 12.13 High Frequency Oscillator.....................................50 13 Device Functional Modes........................................... 51 13.1 Overview................................................................. 51 13.2 NORMAL Mode.......................................................51 13.3 SLEEP Mode.......................................................... 52 13.4 DEEPSLEEP Mode.................................................52 13.5 SHUTDOWN Mode.................................................53 13.6 CONFIG_UPDATE Mode........................................54 14 Serial Communications Interface...............................54 14.1 Serial Communications Overview........................... 54 14.2 I2C Communications............................................... 54 14.3 SPI Communications.............................................. 56 14.4 HDQ Communications............................................ 62 15 Cell Balancing..............................................................63 15.1 Cell Balancing Overview......................................... 63 16 Application and Implementation................................ 64 16.1 Application Information........................................... 64 16.2 Typical Applications................................................ 64 16.3 Random Cell Connection Support.......................... 70 16.4 Startup Timing.........................................................71 16.5 FET Driver Turn-Off................................................ 72 16.6 Unused Pins............................................................74 17 Power Supply Requirements......................................75 18 Layout...........................................................................75 18.1 Layout Guidelines................................................... 75 18.2 Layout Example...................................................... 76 19 Device and Documentation Support..........................79 19.1 Documentation Support.......................................... 79 19.2 Support Resources................................................. 79 19.3 Trademarks............................................................. 79 19.4 Electrostatic Discharge Caution..............................79 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 19.5 Glossary..................................................................79 20 Mechanical, Packaging, Orderable Information....... 79 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2021) to Revision B (November 2021) Page • Updated the simplified schematic....................................................................................................................... 1 • Updated the Absolute Maximum Ratings, Recommended Operating Conditions, ESD Ratings, and Analog-toDigital Converter tables...................................................................................................................................... 7 • Added Cell 1 Voltage Validation During SLEEP Mode .................................................................................... 36 • Updated the voltage..........................................................................................................................................37 • Updated the nominal value of VREF1 and the ADC counts calculations based on that value......................... 39 • Updated the simplified schematic. Denoted capacitors on sense resistor inputs to VSS as optional.............. 64 • Updated Documentation Support .................................................................................................................... 79 Changes from Revision * (November 2020) to Revision A (February 2021) Page • Updated devices from PRODUCT PREVIEW to Production Data......................................................................4 • Updated the SPI Interface table and SCD threshold detection accuracy in the Comparator-Based Protection Subsystem table in Specifications ..................................................................................................................... 7 • Updated the REG18 voltage plot to show data over temperature and with different BAT levels...................... 27 • Updated approximate ADC saturation level when measuring cell voltages..................................................... 35 • Updated I2C Communications ......................................................................................................................... 54 • Updated SPI Communications .........................................................................................................................56 • Updated SPI Protocol ...................................................................................................................................... 57 • Updated HDQ Communications ...................................................................................................................... 62 • Updated Application and Implementation ........................................................................................................ 64 • Updated Documentation Support .................................................................................................................... 79 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 3 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 5 Device Comparison Table BQ76952 Device Family PART NUMBER Communications Interface CRC Enabled REG1 LDO Default BQ76952 I2C N Disabled BQ7695201 SPI Y Disabled BQ7695202 I2C Y Enabled, set to 3.3 V BQ7695203 SPI Y Enabled, set to 5 V BQ7695204 SPI Y Enabled, set to 3.3 V VC16 BAT CP1 CHG NC DSG PACK LD PCHG PDSG FUSE BREG 48 47 46 45 44 43 42 41 40 39 38 37 6 Pin Configuration and Functions VC12 4 33 RST_SHUT VC11 5 32 DDSG VC10 6 31 DCHG VC9 7 30 DFETOFF VC8 8 29 CFETOFF VC7 9 28 HDQ VC6 10 27 SDA VC5 11 26 SCL VC4 12 25 ALERT Not to scale REG18 TS3 TS2 TS1 SRN NC SRP VSS VC0 VC1 VC2 VC3 24 REG2 23 34 22 3 21 VC13 20 REG1 19 35 18 2 17 VC14 16 REGIN 15 36 14 1 13 VC15 Table 6-1. BQ76952 TQFP Package (PFB) Pin Functions PIN 4 I/O TYPE DESCRIPTION VC15 I IA Sense voltage input pin for the fifteenth cell from the bottom of the stack, balance current input for the fifteenth cell from the bottom of the stack, and return balance current for the sixteenth cell from the bottom of stack 2 VC14 I IA Sense voltage input pin for the fourteenth cell from the bottom of the stack, balance current input for the fourteenth cell from the bottom of the stack, and return balance current for the fifteenth cell from the bottom of the stack 3 VC13 I IA Sense voltage input pin for the thirteenth cell from the bottom of the stack, balance current input for the thirteenth cell from the bottom of the stack, and return balance current for the fourteenth cell from the bottom of the stack NO. NAME 1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table 6-1. BQ76952 TQFP Package (PFB) Pin Functions (continued) PIN I/O TYPE VC12 I IA Sense voltage input pin for the twelfth cell from the bottom of the stack, balance current input for the twelfth cell from the bottom of the stack, and return balance current for the thirteenth cell from the bottom of the stack 5 VC11 I IA Sense voltage input pin for the eleventh cell from the bottom of the stack, balance current input for the eleventh cell from the bottom of the stack, and return balance current for the twelfth cell from the bottom of the stack 6 VC10 I IA Sense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and return balance current for the eleventh cell from the bottom of the stack 7 VC9 I IA Sense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack 8 VC8 I IA Sense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack 9 VC7 I IA Sense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack, and return balance current for the eighth cell from the bottom of the stack 10 VC6 I IA Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack 11 VC5 I IA Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack 12 VC4 I IA Sense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack 13 VC3 I IA Sense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack 14 VC2 I IA Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack 15 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack 16 VC0 I IA Sense voltage input pin for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell from the bottom of the stack 17 VSS — P Device ground 18 SRP I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN. 19 NC — — This pin is not connected to silicon. 20 SRN I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN. 21 TS1 I/O OD, I/OA Thermistor input, or general purpose ADC input 22 TS2 I/O OD, I/OA Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input 23 TS3 I/O OD, I/OA Thermistor input, or general purpose ADC input 24 REG18 O P Internal 1.8-V LDO output (only for internal use) 25 ALERT I/O I/OD, I/OA 26 SCL I/O I/OD NO. NAME 4 DESCRIPTION Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output Multifunction pin, can be SCL or SPI_SCLK Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 5 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table 6-1. BQ76952 TQFP Package (PFB) Pin Functions (continued) PIN NO. 6 NAME I/O TYPE DESCRIPTION 27 SDA I/O I/OD Multifunction pin, can be SDA or SPI_MISO 28 HDQ I/O I/OD, I/OA Multifunction pin, can be HDQ I/O, SPI_MOSI, thermistor input, general purpose ADC input, or general purpose digital output 29 CFETOFF I/O I/OD, I/OA Multifunction pin, can be CFETOFF, SPI_CS, thermistor input, general purpose ADC input, or general purpose digital output 30 DFETOFF I/O I/OD, I/OA Multifunction pin, can be DFETOFF, BOTHOFF, thermistor input, general purpose ADC input, or general purpose digital output 31 DCHG I/O OD, I/OA Multifunction pin, can be DCHG, thermistor input, general purpose ADC input, or general purpose digital output 32 DDSG I/O OD, I/OA Multifunction pin, can be DDSG, thermistor input, general purpose ADC input, or general purpose digital output 33 RST_SHUT I ID Digital input pin for reset or shutdown 34 REG2 O P Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V. 35 REG1 O P First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V. 36 REGIN I IA Input pin for REG1 and REG2 LDOs 37 BREG O OA Base control signal for external preregulator transistor 38 FUSE I/O I/OA Fuse sense and drive 39 PDSG O OA Predischarge PFET control 40 PCHG O OA Precharge PFET control 41 LD I/O I/OA Load detect pin 42 PACK I IA Pack sense input pin 43 DSG O OA NMOS Discharge FET drive output pin 44 NC — — This pin is not connected to silicon. 45 CHG O OA NMOS Charge FET drive output pin 46 CP1 I/O I/OA Charge pump capacitor 47 BAT I P Primary power supply input pin 48 VC16 I IA Sense voltage input pin for the sixteenth cell from the bottom of the stack, balance current input for the sixteenth cell from the bottom of the stack, and top-of-stack measurement point Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) DESCRIPTION Supply voltage range PINS MIN MAX UNIT BAT VSS–0.3 VSS+85 V Input voltage range, VIN PACK, LD VSS–0.3 VSS+85 V Input voltage range, VIN PCHG, PDSG the maximum of VBAT-10 or VLD-10 VSS+85 V Input voltage range, VIN REGIN the maximum of VSS–0.3 or VBREG-5.5 the minimum of VSS+6 or VBAT+0.3 or VBREG+0.3 V Input voltage range, VIN FUSE(2) the minimum VSS–0.3 of VSS+20 or VBAT+0.3 V Input voltage range, VIN BREG Input voltage range, VIN the maximum of VSS–0.3 or VREGIN-0.3 VREGIN+5.5 V REG1, REG2 VSS–0.3 minimum of VSS+6 or VREGIN+0.3 V Input voltage range, VIN ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, RST_SHUT (3) VSS–0.3 VSS+6 V Input voltage range, VIN TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG (when used as thermistor or general purpose ADC input) VSS–0.3 VREG18 + 0.3 V Input voltage range, VIN SRP, SRN VSS–0.3 VREG18 + 0.3 V VSS+85 V Input voltage range, VIN VC16 maximum of VSS-0.3 and VC15–0.3 Input voltage range, VIN VC15 maximum of VSS-0.3 and VC14–0.3 VSS+85 V Input voltage range, VIN VC14 maximum of VSS-0.3 and VC13–0.3 VSS+85 V Input voltage range, VIN VC13 maximum of VSS-0.3 and VC12–0.3 VSS+85 V Input voltage range, VIN VC12 maximum of VSS-0.3 and VC11–0.3 VSS+85 V Input voltage range, VIN VC11 maximum of VSS-0.3 and VC10–0.3 VSS+85 V Input voltage range, VIN VC10 maximum of VSS-0.3 and VC9–0.3 VSS+85 V Input voltage range, VIN VC9 maximum of VSS-0.3 and VC8–0.3 VSS+85 V Input voltage range, VIN VC8 maximum of VSS-0.3 and VC7–0.3 VSS+85 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 7 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.1 Absolute Maximum Ratings (continued) over operating free-air temperature range (unless otherwise noted)(1) DESCRIPTION PINS MIN MAX Input voltage range, VIN VC7 maximum of VSS-0.3 and VC6–0.3 VSS+85 V Input voltage range, VIN VC6 maximum of VSS-0.3 and VC5–0.3 VSS+85 V Input voltage range, VIN VC5 maximum of VSS-0.3 and VC4–0.3 VSS+85 V Input voltage range, VIN VC4 maximum of VSS-0.3 and VC3–0.3 VSS+85 V Input voltage range, VIN VC3 maximum of VSS-0.3 and VC2–0.3 VSS+85 V Input voltage range, VIN VC2 maximum of VSS-0.3 and VC1–0.3 VSS+85 V Input voltage range, VIN VC1 maximum of VSS-0.3 and VC0–0.3 VSS+85 V Input voltage range, VIN VC0 VSS–0.3 VSS+6 V Output voltage range, VO CP1 the minimum VBAT–0.3 of VSS+85 or VBAT+15 V Output voltage range, VO CHG VSS–0.3 VSS+85 V Output voltage range, VO DSG VSS–0.3 VSS+85 V Output voltage range, VO REG1, REG2, TS2 (for wakeup function), ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG, when configured to drive a digital output VSS–0.3 VSS+6 V Output voltage range, VO REG18 VSS–0.3 VSS+2 V Maximum cell balancing current through a single cell VC0 – VC16 Maximum VSS current, ISS UNIT 100 mA 75 mA Functional temperature, TFUNC –40 85 °C Junction temperature, TJ –55 150 °C Storage temperature, TSTG –55 150 °C (1) (2) (3) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The current allowed to flow into the FUSE pin must be limited (such as by using external series resistance) to 2 mA or less. When the ALERT, HDQ, CFETOFF, DFETOFF, DCHG, or DDSG pins are selected for thermistor input or general purpose ADC–input, their voltage is limited to VREG18 + 0.3 V. These pins can accept up to 6 V when configured for other uses, such as a digital input. 7.2 ESD Ratings UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±1000 V V(ESD) Electrostatic discharge Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002, all pins(2) ±250 V (1) 8 VALUE JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com (2) SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBAT Supply voltage Voltage on BAT pin (normal operation) 4.7 80 V VBAT Supply voltage(4) Voltage on BAT pin (OTP programming) 10 12 V TOTP OTP programming temperature(4) -40 45 °C VPORA Power-on reset Rising threshold on BAT 3 4 V VPORA_HYS Power-on reset hysteresis Device shuts down when BAT < VPORA - VPORA_HYS VWAKEONLD Wake on LD voltage Rising edge on LD, with BAT already in valid range 0.8 VWAKEONTS2 Wake on TS2 voltage Falling edge on TS2, with BAT already in valid range. TS2 will be weakly driven with a ≈ 5 V level during shutdown. VIN Input voltage range(4) PACK, LD VIN range(4) 180 2.25 V 0.7 1.1 V 0 80 V the maximum of VBAT-9 or VLD-19 80 V Input voltage range(4) REG1, REG2, RST_SHUT, ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, except when the pin is being used for general purpose ADC input or thermistor measurement. 0 5.5 V VIN Input voltage range(4) TS1, TS2, TS3, CFETOFF, DFETOFF, DCHG, DDSG, ALERT, HDQ, when the pin is configured for general purpose ADC input or thermistor measurement. 0 VREG18 V VIN Input voltage range(4) SRP, SRN, SRP-SRN (while measuring current) –0.2 0.2 V VIN Input voltage range(4) SRP, SRN (without measuring current) –0.2 0.75 V VIN Input voltage range(4) (5) VVC(0) VIN Input voltage VIN Input voltage range(4) VIN range(4) RC Input voltage PCHG, PDSG 1.45 mV –0.2 0.5 V VVC(x), 1 ≤ x ≤ 4 maximum of VVC(x–1) – 0.2 or VSS–0.2 minimum of VVC(x– 1)+5.5 or VSS+80 V VVC(x), x ≥ 5 maximum of VVC(x–1) – 0.2 or VSS + 2.0 minimum of VVC(x–1) + 5.5 or VSS + 80 V 20 100 Ω 1 µF External cell input resistance(4) (7) CC External cell input capacitance(4) (7) VO Output voltage range LD 80 V VO Output voltage range(6) CHG, DSG, CP1 85 V 85 °C TOPR Operating 0.1 temperature(6) –40 0.22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 9 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.3 Recommended Operating Conditions (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCELL(ACC) Cell voltage measurement accuracy 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 16(2) (3) VCELL(ACC) Cell voltage measurement accuracy(6) VCELL(ACC) MIN TYP MAX UNIT –5 5 mV 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 16(2) (3) –10 10 mV Cell voltage measurement accuracy(6) –0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 16(2) (3) –15 15 mV VSTACK(ACC) Stack voltage (VC16 - VSS) measurement accuracy(6) 0 V < VVC16 - VVSS < 80 V, TA = -40°C to 85°C(2) –0.5 0.5 V VPACK(ACC) PACK pin voltage measurement 0 V < VPACK < 80 V, TA = -40°C to accuracy(6) 85°C(2) –0.5 0.5 V VLD(ACC) LD pin voltage measurement accuracy(6) –0.5 0.5 V (1) (2) (3) (4) (5) (6) (7) 0 V < VLD < 80 V, TA = -40°C to 85°C(2) Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Cell voltage accuracy is specified after completion of board offset calibration While in SLEEP mode, it is important that the cell 1 voltage measurement be validated before being considered valid. For further information and details, see Cell 1 Voltage Validation during SLEEP Mode. Specified by design Voltage on VC0 can extend higher (limited by absolute maximum specification) during cell balancing. Specified by characterization Values may need to be optimized during system design and evaluation for best performance 7.4 Thermal Information BQ76952 BQ76952 THERMAL METRIC(1) PFB (TQFP) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 66.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 19.6 °C/W RθJB Junction-to-board thermal resistance 29.3 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 29.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Supply Current Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER INORMAL ISLEEP_1 10 TEST CONDITIONS MIN TYP MAX UNIT Normal Mode Regular measurements and protections active, REG1 = 3.3 V with no load, REG2 = OFF, CHG = ON in 11V overdrive mode, DSG = ON in 11V overdrive mode, Settings:Configuration:Power Config[FASTADC] = 0, no communication 286 µA SLEEP Mode Periodic protections and monitoring, no pack current, REG1 = OFF, REG2 = OFF, CHG = OFF, DSG = ON in 11V overdrive mode, no communication, Power:Sleep:Voltage Time = 5 s 41 µA Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.5 Supply Current (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS ISLEEP_2 SLEEP Mode Periodic protections and monitoring, no pack current, REG1 = OFF, REG2 = OFF, CHG = OFF, DSG = source follower mode, no communication, Power:Sleep:Voltage Time = 5 s IDEEPSLEEP_1 DEEPSLEEP Mode IDEEPSLEEP_2 ISHUTDOWN (1) MIN TYP MAX UNIT 24 µA No monitoring or protections, REG1 = 3.3 V with no load, REG2 = OFF, LFO = ON, no communication 10.7 µA DEEPSLEEP Mode No monitoring or protections, REG1 = 3.3 V with no load, REG2 = OFF, LFO = OFF, no communication 9.2 µA SHUTDOWN Mode All blocks powered down, with the exception of the TS2 wakeup circuit, no monitoring or protections, no communication 1 3.1 µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.6 Digital I/O Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VIH High-level input ALERT (configured as HDQ), SCL, SDA, HDQ, CFETOFF, DFETOFF, RST_SHUT VIL Low-level input ALERT (configured as HDQ), SCL, SDA, HDQ, CFETOFF, DFETOFF, RST_SHUT VOH Output voltage high, TS2 TS2 during SHUTDOWN mode, VBAT > 6 V VOH Output voltage high, TS2 low voltage TS2 during SHUTDOWN mode, 4.7 V ≤ VBAT ≤ 6 V Output voltage high, 5 V case ALERT, SDA (configured as SPI_MISO), SCL (configured as SPI_SCLK), CFETOFF (configured as GPO), DFETOFF (configured as GPO), DCHG, DDSG, pins driving from REG1, VREG1 set to 5 V nominal setting, VBAT > 8 V, IOH = -5.0 mA, 10 pF load VOL Output voltage low, 5 V case ALERT, SCL, SDA, HDQ, DCHG, DDSG, CFETOFF (configured as GPO), DFETOFF (configured as GPO), pins driving from REG1, VREG1 set to 5 V nominal setting, VBAT > 8 V, IOL = 5 mA, 10 pF load ROH Output weak high resistance TS2 during SHUTDOWN mode CIN Input capacitance(2) ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, REGIN, TS1, TS2, TS3 ILKG Input leakage current ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, REGIN, device in SHUTDOWN mode VOH (1) MIN TYP 0.66 x VREG18 MAX UNIT 5.5 V 0.33 x VREG18 V 4.5 6 V 3 6 V 0.9 x VREG1 VREG1 V 0.77 V 4600 kΩ 2 pF 1 µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 11 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 (2) Specified by design 7.7 LD Pin Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS I(PULLUP) Internal pullup current from BAT pin to LD VBAT ≥ 4.7 V, VLD = VSS pin, used for load detect functionality RPD Internal pulldown resistance on LD pin in SHUTDOWN mode (1) MIN TYP MAX UNIT 35 100 172 µA VBAT ≥ 4.7 V 80 kΩ Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS V(PCHG_ON) Output voltage, PCHG on max(VPACK, VBAT) - VPCHG, VPACK ≥ 8 V, VBAT ≥ 4.7 V V(PCHG_ON) Output voltage, PCHG on VPACK - VPCHG, 4.7 V ≤ VPACK < 8 V, VBAT ≥ 4.7 V, VPACK > VBAT V(PDSG_ON) Output voltage, PDSG on max(VLD, VBAT) - VPDSG, VBAT ≥ 8 V V(PDSG_ON) Output voltage, PDSG on VBAT - VPDSG, 4.7 V ≤ VBAT < 8 V, VBAT ≥ VLD I(PULLDOWN) Current sink capability, PCHG and PDSG PCHG and PDSG enabled, VBAT = 59.2 V (1) MIN TYP MAX 7.5 8.4 9.7 V VPACK V 9.7 V VBAT V VPACK – 0.5 V 7.47 8.4 VBAT – 0.5 V 30 UNIT µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.9 FUSE Pin Functionality Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER V(OH) TEST CONDITIONS Output voltage high (when driving fuse) VBAT ≥ 8 V, CL = 1 nF, 5 kΩ load. MIN TYP MAX 6 7 9 V(OH) Output voltage high (when driving fuse) 4.7 V ≤ VBAT < 8 V, CL = 1 nF, 5 kΩ load. VBAT – 1.75 V(IH) High-level input (for fuse detection) Current into device pin must be limited to maximum 2 mA 2 V(IL) Low-level input (for fuse detection) t(RISE) Output rise time (when driving fuse) (1) VBAT ≥ 8 V, CL = 1 nF, RLOAD = 5 kΩ, V(OH) = 10% to 90% of final settled voltage UNIT V V 12 V 0.7 V 0.5 µs Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.10 REG18 LDO Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER CREG18 12 External capacitor, REG18 to TEST CONDITIONS VSS(2) Submit Document Feedback MIN TYP MAX 1.8 2.2 22 UNIT µF Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.10 REG18 LDO (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX 1.6 1.8 2 UNIT VREG18 Regulator voltage ΔVO(TEMP) Regulator output over temperature ΔVREG18 vs (VREG18 at 25°C), IREG18 = 1 mA, VBAT = 55 V ΔVO(LINE) Line regulation ΔVREG18 vs (VREG18 at 25°C, VBAT = 55 V), IREG18 = 1 mA, as VBAT varies across specified range –0.6 0.5 % ΔVO(LOAD) Load regulation ΔVREG18 vs (VREG18, VBAT = 55 V), IREG18 = 0 mA to 1 mA, at 25°C –1.5 1.5 % ISC Regulator short-circuit current limit VREG18 = 0 V 3 14 mA (1) (2) ±0.15 V % Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design 7.11 REG0 Pre-regulator Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VBREG_HDRM Pre-regulator control voltage headroom ( min(VBAT - VBREG) )(4) VBAT ≥ 4.7 V VREGIN_INT Pre-regulator voltage, when generated using BREG VBAT > 8 V, although specific requirement depends on external device selected VREGIN_EXT Pre-regulator voltage when using externally supplied REGIN(4) See requirements based on settings of REG1 and REG2 ΔVO(TEMP) Regulator output over temperature ΔVREGIN vs VREGIN at 25°C, IREGIN = 50 mA, VBAT > 8 V IMax Maximum current driven out from BREG(4) Under short circuit conditions (VREGIN = 0 V) External capacitor REGIN to VSS(3) CEXT (4) CBREG (1) (2) (3) (4) MIN 5 TYP MAX UNIT 1.5 1.91 V 5.5 5.8 V 5.5 V ±0.05 % 2.5 3.33 mA 15 22 External capacitor BREG to VSS(4) 27 nF 150 pF Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Supported output current is limited for VSTACK < 5.5 V. VREGIN limited to ~2.5 V below VBAT. Capacitance should be above 7 nF after consideration for aging and derating. Specified by design 7.12 REG1 LDO Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREG1_1.8 Regulator voltage (nominal 1.8V setting) VREGIN ≥ 3.0 V, IREG1 = 0 mA to 45 mA 1.6 1.84 2 V VREG1_2.5 Regulator voltage (nominal 2.5V setting) VREGIN ≥ 3.5 V, IREG1 = 0 mA to 45 mA 2.25 2.55 2.75 V VREG1_3.0 Regulator voltage (nominal 3.0V setting) VREGIN ≥ 3.8 V, IREG1 = 0 mA to 45 mA 2.7 3.05 3.3 V VREG1_3.3 Regulator voltage (nominal 3.3V setting) VREGIN ≥ 4.1 V, IREG1 = 0 mA to 45 mA 3 3.36 3.6 V VREG1_5.0 Regulator voltage (nominal 5.0V setting) VREGIN ≥ 5.0 V, IREG1 = 0 mA to 45 mA 4.5 5.19 5.5 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 13 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.12 REG1 LDO (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Regulator output over temperature ΔVREG1 vs (VREG1 at 25°C, IREG1 = 20 mA, VREGIN = 5.5 V, VREG1 set to nominal 3.3 V setting) ΔVO(LINE) Line regulation ΔVREG1 vs (VREG1 at 25°C, VREGIN = 5.5 V, IREG1 = 20 mA), as VREGIN varies from 5 V to 6 V, VREG1 set to nominal 3.3 V setting –1 1 % ISC Regulator short-circuit current limit VREG1 = 0 V 47 80 mA ΔVO(TEMP) CEXT (1) (2) External capacitor REG1 to VSS(2) ±0.25 % 1 µF Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design 7.13 REG2 LDO Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) MIN TYP MAX VREG2_1.8 Regulator voltage (nominal 1.8V setting) PARAMETER VREGIN ≥ 3.0 V, IREG2 = 0 mA to 45 mA 1.6 1.84 2 V VREG2_2.5 Regulator voltage (nominal 2.5V setting) VREGIN ≥ 3.5 V, IREG2 = 0 mA to 45 mA 2.25 2.55 2.75 V VREG2_3.0 Regulator voltage (nominal 3.0V setting) VREGIN ≥ 3.8 V, IREG2 = 0 mA to 45 mA 2.7 3.06 3.3 V VREG2_3.3 Regulator voltage (nominal 3.3V setting) VREGIN ≥ 4.1 V, IREG2 = 0 mA to 45 mA 3.0 3.38 3.6 V VREG2_5.0 Regulator voltage (nominal 5.0V setting) VREGIN ≥ 5.0 V, IREG2 = 0 mA to 45 mA 4.5 5.23 5.5 V Δ Regulator output over temperature VO(TEMP) ΔVREG2 vs (VREG2 at 25°C, IREG2 = 20 mA, VREGIN = 5.5 V, VREG2 set to nominal 3.3 V setting) ΔVO(LINE) Line regulation ΔVREG2 vs (VREG2 at 25°C, VREGIN = 5.5 V, IREG2 = 20 mA), as VREGIN varies from 5 V to 6 V, VREG2 set to nominal 3.3 V setting –1 1 % VREG2 = 0 V 47 80 mA ISC Regulator short-circuit current limit CEXT (1) (2) TEST CONDITIONS External capacitor REG2 to VSS(2) ±0.25 UNIT % 1 µF Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design 7.14 Voltage References Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.210 1.212 1.214 V VOLTAGE REFERENCE 1 V(REF1) Internal reference voltage (2) TA = 25°C V(REF1DRIFT) Internal reference voltage drift (2) (4) TA = -10°C to 60°C ±10 PPM/°C V(REF1DRIFT) Internal reference voltage drift (2) (4) TA = -40°C to 85°C ±10 PPM/°C VOLTAGE REFERENCE 2 V(REF2) Internal reference voltage (3) TA = 25°C V(REF2DRIFT) Internal reference voltage drift(3) (4) TA = -10°C to 60°C 14 Submit Document Feedback 1.23 1.24 ±20 1.25 V PPM/°C Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.14 Voltage References (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER V(REF2DRIFT) (1) (2) (3) (4) TEST CONDITIONS Internal reference voltage drift(3) (4) MIN TA = -40°C to 85°C TYP MAX ±50 UNIT PPM/°C Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. V(REF1) is used for the ADC reference. Its effective value is determined through indirect measurement using the ADC and measuring the differential voltage on VC1 - VC0. V(REF2) is used for the LDO, coulomb counter, and current measurement Specified by characterization 7.15 Coulomb Counter Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(CC_IN) Input voltage range for measurements(4) VSRP - VSRN –0.2 0.2 V V(CC_IN) Input voltage range for measurements(4) VSRP, VSRN –0.2 0.2 V B(CC_INL) Integral nonlinearity(3) 16-bit, best fit over input voltage range, using 0 V common mode voltage. ±5.2 B(CC_DNL) Differential nonlinearity 16-bit, no missing codes ±0.1 V(CC_OFF) Offset error(3) drift(3) V(CC_OFF_DRIFT) Offset error B(CC_GAIN) Gain(3) R(CC_IN) Effective input resistance(4) (1) (2) (3) (4) 16-bit, uncalibrated 16-bit, post-calibration 16-bit, over ideal input voltage range ±22.3 LSB(2) LSB(2) -1 1 LSB(2) 0.03 LSB/°C(2) –0.03 130845 132335 LSB/V(2) 131454 2 MΩ Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 1 LSB (16-bit mode, using CC1 filter) = VREF2 / (5 x 2N-1) ≈ 1.24 / (5 x 215) = 7.6µV Specified by characterization Specified by design 7.16 Coulomb Counter Digital Filter (CC1) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER t(CC1_CONV_FA ST) t(CC1_CONV_SL OW) B(CC1_RSL) (1) (2) (3) TEST CONDITIONS MIN TYP Conversion-time Single conversion (when operating from LFO in 262.144kHz mode) 250 Conversion-time Single conversion (when operating from LFO in 32.768kHz mode) 4 Code stability(2) (3) Single conversion 14.3 MAX UNIT ms s bits Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB. Specified by a combination of design and production test Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 15 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.17 Current Measurement Digital Filter (CC2) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS t(CC2_CONV) Conversion-time Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 t(CC2_CONV_FA Conversion-time in fast mode Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 B(CC2_RES) Code stability(2) (3) Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 B(CC2_RES_FA Code stability in fast mode(2) Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 ST) ST) (1) (2) (3) MIN 14 TYP MAX UNIT 2.93 ms 1.46 ms 15 bits 13.5 bits Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB. Specified by characterization 7.18 Current Wake Detector Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT µV VWAKE_THR Wakeup voltage threshold error(2) TA = 25°C, VWAKE = VSRP – VSRN, setting between ±0.5 mV and ±5 mV. Measured using averaged data to remove effects of noise. -200 200 VWAKE_THR Wakeup voltage threshold error(2) TA = 25°C, VWAKE = VSRP – VSRN, setting beyond ±5 mV. Measured using averaged data to remove effects of noise. -5 5 tWAKE Measurement interval(2) (1) (2) 12 % of setting ms Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design 7.19 Analog-to-Digital Converter Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS V(ADC_IN_CELLS) Input voltage range (differential cell input mode)(5) V(ADC_IN) Internal reference (Vref = VREF1), applicable Input voltage range to ADCIN measurements using the TS1, TS2, (ADCIN measurement TS3, ALERT, CFETOFF, DFETOFF, HDQ, (6) mode) DCHG, and DDSG pins V(ADC_IN_TS) Input voltage range (external thermistor measurement mode) (7) 16 Internal reference (Vref = VREF1) Regulator reference (Vref = VREG18), applicable to external thermistor measurements using the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins Submit Document Feedback MIN TYP MAX UNIT –0.2 5.5 V –0.2 VREG18 V –0.2 VREG18 V Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.19 Analog-to-Digital Converter (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(ADC_IN_DIV) Input voltage range Internal reference (Vref = VREF1), applicable (divider measurement to divider measurements using the VC16, mode)(8) PACK, and LD pins relative to VSS. B(ADC_INL) Integral nonlinearity 16-bit, best fit over -0.1 V to 5.5 V (when using VREF1 and differential cell voltage measurement 16-bit, best fit over -0.2 V to 0.2 V mode at VC16 VC15)(4) B(ADC_DNL) Differential nonlinearity 16-bit, no missing codes, using differential cell voltage measurement at VC16-VC15 B(ADC_OFF_CELL) Differential cell offset error 16-bit, uncalibrated, using VC16 - VC15 B(ADC_OFF) ADCIN offset error 16-bit, uncalibrated, using ADCIN mode on TS1 pin 0.53 LSB(6) B(ADC_OFF_DIV) Divider offset error 16-bit, uncalibrated, using divider mode on PACK pin 0.17 LSB(8) B(ADC_OFF_DRIFT_CELL) Differential cell offset error drift(4) Offset error measured 16-bit, post calibration, using VC16 - VC15. Drift measured as change in offset over operating temperature range as compared to offset at 30°C. B(ADC_GAIN) Gain Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC16-VC15, uncalibrated. B(ADC_GAIN_DRIFT) Gain drift(4) Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC16-VC15, uncalibrated. Drift value measured as change in gain over operating temperature range, compared to gain at 30°C. R(ADC_IN_CELL) Effective input resistance(3) Differential cell input mode on VC16-VC15(9) R(ADC_IN_LD) Effective input resistance Divider measurement on LD pin (only active while the LD pin is being measured) R(ADC_IN_DIV) Effective input resistance Divider measurement on VC16 and PACK pins (only active while the pin is being measured) B(ADC_RES) Code stability(2) (4) Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 B(ADC_RES_FAST) Code stability in fast mode(2) t(ADC_CONV) t(ADC_CONV_FAST) (1) (2) (3) (4) –0.2 80 V –6.6 6.6 LSB(5) –4 4 LSB(5) LSB(5) ±0.12 –2.75 3.5 LSB(5) 0.004 0.07 LSB/°C(5) 5385 5406 5427 LSB/V(5) -0.25 0.025 0.25 2.1 LSB/V/ °C(5) MΩ 2 MΩ 600 kΩ 15 bits Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 14 bits Conversion-time Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0 2.93 ms Conversion-time in fast mode Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1 1.46 ms 13.5 Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB. Specified by design Specified by characterization Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 17 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 (5) (6) (7) (8) (9) The 16-bit LSB size of the differential cell voltage measurement is given by 1 LSB = 5 x VREF1 / 2N-1 ≈ 5 x 1.212 V / 215 = 185 µV The 16-bit LSB size of the ADCIN voltage measurement is given by 1 LSB = 5 / 3 x VREF1 / 2N-1 ≈ 5 / 3 x 1.212 V / 215 = 62 µV The LSB size of the external thermistor voltage measurement when reported in 32-bit format is given by 1 LSB = 5 / 3 x VREG18 / 2N-1 ≈ 5 / 3 x 1.8 V / 223 = 358 nV The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 425 / 3 x VREF1 / 2N-1 ≈ 425 / 3 x 1.212 / 215 = 5.24 mV Average effective differential input resistance with device operating in NORMAL mode, cell balancing disabled, three or more thermistors in use, and a 5 V differential voltage applied. 7.20 Cell Balancing Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER Internal cell balancing resistance(2) R(CB) (1) (2) TEST CONDITIONS MIN TYP MAX 15 28 46 RDS(ON) for internal FET switch at VVC(n) VVC(n-1) = 1.5V, 1 ≤ n ≤ 16, VBAT ≥ 4.7 V UNIT Ω Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Cell balancing must be controlled to limit the current based on the absolute maximum allowed current, and to avoid exceeding the recommended device operating temperature. This can be accomplished by appropriate sizing of the offchip cell input resistors and limiting the number of cells that can be balanced simultaneously. 7.21 Cell Open Wire Detector Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER I(OW) (1) TEST CONDITIONS MIN TYP MAX 22 54 95 Internal cell open wire check current from VCx > VSS + 0.8 V, 1 ≤ x ≤ 4; VCx > VSS VCx pin to VSS, 1 ≤ x ≤ 16 + 2.8 V, 5 ≤ x ≤ 16 UNIT µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.22 Internal Temperature Sensor Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER V(TEMP) (1) TEST CONDITIONS Internal temperature sensor voltage drift MIN ΔVBE measurement TYP MAX 0.410 UNIT mV/°C Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.23 Thermistor Measurement Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER R(TS_PU) Internal pullup resistance(2) R(TS_PAD) Internal pad resistance(3) 18 TEST CONDITIONS MIN TYP MAX UNIT Setting for nominal 18-kΩ 14.4 18.3 21.6 kΩ Setting for nominal 180-kΩ 140 178 216 kΩ 526 Submit Document Feedback Ω Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.23 Thermistor Measurement (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER Internal pullup resistance change over temperature R(TS_PU_DRIFT) (1) (2) (3) TEST CONDITIONS MIN TYP MAX UNIT Change over -40°C/+85°C vs value at 25°C for nominal 18-kΩ ±200 Ω Change over -40°C/+85°C vs value at 25°C for nominal 180-kΩ ±2000 Ω Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. The internal pullup resistance includes only the resistance between the REG18 pin and the point where the voltage is sensed by the ADC. The internal pad resistance includes the resistance between the point where the voltage is sensed by the ADC and the pin where an external thermistor is attached (which includes the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins) 7.24 Internal Oscillators Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-frequency Oscillator fHFO Operating frequency fHFO(ERR) Frequency error(3) fHFO(SU) Start-up time(2) 16.78 TA = -40°C to +85°C, includes frequency drift –4.0 ±0.25 MHz 4.0 % TA = -40°C to +85°C, at power-up from SHUTDOWN or exiting DEEPSLEEP mode, oscillator frequency within ±3% of nominal 4.3 ms TA = -40°C to +85°C, cases other than power-up from SHUTDOWN or exiting DEEPSLEEP mode, oscillator frequency within ±3% of nominal 135 µs Low-frequency Oscillator fLFO Operating frequency fLFO(ERR) Frequency fLFO(FAIL) (1) (2) (3) error(3) Failure detection frequency Full-speed setting 262.144 kHz Low speed setting 32.768 kHz Full-speed setting, TA = -10°C to +60°C, includes frequency drift –1.5 ±0.25 1.5 % Full-speed setting, TA = -40°C to +85°C, includes frequency drift –2.5 ±0.25 2.5 % 8.5 12 18 kHz Detects oscillator failure if the LFO frequency falls below this level. Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design Specified by a combination of design and production test Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 19 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.25 High-side NFET Drivers Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER MIN TYP MAX CHG/DSG CL = 20 nF, charge pump high overdrive setting 10 11 13 V V(FETON_HI_LOBAT) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ VBAT < 8 V, VLD ≤ VDSG (2) CHG/DSG CL = 20 nF, charge pump high overdrive setting 8 11 13 V V(FETON_LO) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ VBAT ≤ 80 V, VLD ≤ VDSG (2) CHG/DSG CL = 20 nF, charge pump low overdrive setting 4.5 5.7 7 V V(FETON_LO_LOBAT) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ VBAT < 8 V, VLD ≤ VDSG (2) CHG/DSG CL = 20 nF, charge pump low overdrive setting 3.5 5 7 V V(SRCFOL_FETON) DSG on voltage with respect to BAT CHG/DSG CL = 20 nF, source follower mode V(CHGFETOFF) CHG off voltage with respect to BAT CHG/DSG CL = 20 nF, steady state value 0.4 V V(DSGFETOFF) DSG off voltage with respect to LD CHG/DSG CL = 20 nF, steady state value 0.7 V t(FET_ON) CHG and DSG rise time CHG/DSG CL = 20 nF, RGATE = 100 Ω, 0.5 V to 4 V gate-source overdrive, charge pump high overdrive setting(4) (5) 21 40 µs t(CHGFETOFF) CHG fall time to BAT CHG CL = 20 nF, RGATE = 100 Ω, 90% to 10% of V(FETON) (5) 46 65 µs t(DSGFETOFF) DSG fall time to LD DSG CL = 20 nF, RGATE = 100 Ω, 90% to 10% of V(FETON) (5) 2 20 µs t(CP_START) Charge pump start up CL = 20 nF, C(CP1) = 470 nF, 10% to 90% of time V(FETON) 100 ms C(CP1) Charge pump capacitor(3) 2200 nF V(FETON_HI) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ VBAT ≤ 80 V, VLD ≤ VDSG (2) (1) (2) (3) (4) (5) 20 TEST CONDITIONS 0 100 470 UNIT V Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that VLD > VDSG, the voltage at DSG will rise to ≈ VLD - 0.7 V Specified by design Specified by characterization RGATE can be optimized during design and system evaluation for best performance. A larger value may be desired to avoid an overly fast FET turn off, which can result in a large voltage transient due to cell and harness inductance. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.26 Comparator-Based Protection Subsystem Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER V(OVP) TEST CONDITIONS Overvoltage detection range MIN Nominal setting (50.6 mV steps) TA = +25°C, nominal setting between 1.012 V and 5.566 V(2) TA = +25°C, nominal setting between 3.036 V and 5.06 V(2) V(OVP_ACC) Overvoltage detection voltage threshold accuracy(4) –10 delay(3) V(OVP_DLY) Overvoltage detection V(UVP) Undervoltage detection range 25 mV ms Nominal setting (50.6 mV steps) 1.012 V to 4.048 V in 50.6 mV steps V ±1.3 –10 TA = -10°C to +60°C, nominal setting between 1.012 V and 4.048 V(2) TA = -10°C to +60°C, nominal setting between 1.518 V and 3.542 V(2) TA = -40°C to +85°C, nominal setting between 1.518 V and 3.542 V(2) Undervoltage detection delay(3) mV Nominal setting (3.3 ms steps) Nominal setting (3.3 ms steps) mV 10 ±1.4 –15 TA = -40°C to +85°C, nominal setting between 1.012 V and 4.048 V(2) V(UVP_DLY) mV 10 ms to 6753 ms in 3.3 ms steps TA = +25°C, nominal setting between 1.518 V and 3.542 V(2) V(UVP_ACC) 15 –25 mV mV ±5 TA = +25°C, nominal setting between 1.012 V and 4.048 V(2) Undervoltage detection voltage threshold accuracy(4) mV 10 –15 UNIT V ±3 TA = -40°C to +85°C, nominal setting between 1.012 V and 5.566 V(2) TA = -40°C to +85°C, nominal setting between 3.036 V and 5.06 V(2) MAX ±2 TA = -10°C to +60°C, nominal setting between 1.012 V and 5.566 V(2) TA = -10°C to +60°C, nominal setting between 3.036 V and 5.06 V(2) TYP 1.012 V to 5.566 V in 50.6 mV steps mV 15 ±1.6 –25 mV mV 25 10 ms to 6753 ms in 3.3 ms steps mV mV ms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 21 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.26 Comparator-Based Protection Subsystem (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER V(SCD) V(SCD_ACC) Short circuit in discharge voltage threshold range Short circuit in discharge voltage threshold detection accuracy(4) TEST CONDITIONS MIN Nominal settings, threshold based on VSRP - VSRN V(SCD_DLY) TA = -40°C to +85°C, V(SCD) settings > -20 mV –35 % of 35 nominal threshold Fastest setting (with 25 mV on VSRN VSRP) Overcurrent in charge (OCC) voltage Nominal settings, threshold based on threshold range VSRP - VSRN V(OCD) Overcurrent in discharge (OCD1, OCD2) voltage threshold ranges V(OC_ACC) Overcurrent (OCC, OCD1, OCD2) detection voltage threshold accuracy(4) (1) (2) (3) (4) 22 mV % of 15 nominal threshold V(OCC) V(OC_DLY) UNIT –15 Nominal setting (15 µs steps) Overcurrent (OCC, OCD1, OCD2) detection delay (independent delay setting for each protection) MAX TA = -40°C to +85°C, V(SCD) settings ≤ -20 mV Fastest setting (with 3 mV on VSRN VSRP) Short circuit in discharge detection delay TYP –10, –20, –40, –60, –80, –100, –125, –150, –175, –200, –250, –300, –350, –400, –450, –500 Nominal settings, thresholds based on VSRP - VSRN 8 µs 600 ns 15 µs to 450 µs in 15 µs steps µs 4 mV to 124 mV in 2 mV steps mV –4 mV to –200 mV in 2 mV steps mV |Setting| < 20 mV –2 2.65 mV |Setting| = 20 mV ~ 56 mV –4 4 mV |Setting| = 56 mV ~ 100 mV –5 5 mV |Setting| > 100 mV –7 5 mV Nominal setting (3.3 ms steps) 10 ms to 425 ms in 3.3 ms steps ms Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Measured by fault triggered using 100 ms detection delay. Cell balancing not active. Timing of overvoltage and undervoltage protection checks is modified when cell balancing is in progress. Specified by a combination of characterization and production test Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.27 Timing Requirements - I2C Interface, 100kHz Mode Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS Clock operating frequency(2) fSCL MIN TYP SCL duty cycle = 50% time(2) MAX UNIT 100 kHz tHD:STA START condition hold 4.0 µs tLOW Low period of the SCL clock(2) 4.7 µs tHIGH High period of the SCL clock(2) 4.0 µs tSU:STA Setup repeated START(2) 4.7 µs tHD:DAT Data hold time (SDA input)(2) 0 ns tSU:DAT Data setup time (SDA tr Clock rise time(2) input)(2) 250 time(2) tf Clock fall tSU:STO Setup time STOP condition(2) tBUF Bus free time STOP to START(2) tRST I2C bus reset(2) RPULLUP Pullup resistor(3) Pullup voltage rail ≤ 5 V (2) (3) 1000 90% to 10% Bus interface is reset if SCL is detected low for this duration (1) ns 10% to 90% 300 ns ns 4.0 µs 4.7 µs 1.9 1.5 2.1 s kΩ Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design Specified by characterization 7.28 Timing Requirements - I2C Interface, 400kHz Mode Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS Clock operating frequency(2) fSCL MIN SCL duty cycle = 50% time(2) TYP MAX UNIT 400 kHz tHD:STA START condition hold 0.6 µs tLOW Low period of the SCL clock(2) 1.3 µs tHIGH High period of the SCL clock(2) 600 ns tSU:STA Setup repeated START(2) 600 ns 0 ns 100 ns input)(2) tHD:DAT Data hold time (SDA tSU:DAT Data setup time (SDA input)(2) time(2) tr Clock rise tf Clock fall time(2) 10% to 90% 300 ns 90% to 10% 300 ns condition(2) tSU:STO Setup time STOP tBUF Bus free time STOP to START(2) tRST I2C bus reset(2) Bus interface is reset if SCL is detected low for this duration 1.9 RPULLUP Pullup resistor(3) Pullup voltage rail ≤ 5 V 1.5 (1) (2) (3) 0.6 µs 1.3 µs 2.1 s kΩ Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design Specified by characterization Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 23 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.29 Timing Requirements - HDQ Interface Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS Break Time(2) tB MIN TYP MAX 190 Time(2) UNIT µs tBR Break Recovery tHW1 Host Write 1 Time(2) Host drives HDQ tHW0 Host Write 0 Time(2) Host drives HDQ tCYCH Cycle Time, Host to device(2) Device drives HDQ 190 tCYCD Cycle Time, device to Host(2) Device drives HDQ 190 tDW1 Device Write 1 Time(2) Device drives HDQ tDW0 Device Write 0 Time(2) Device drives HDQ Device drives HDQ 190 µs Host drives HDQ after device drives HDQ 210 µs Time(2) (4) tRSPS Device Response tTRND Host Turn Around Time(2) tRISE 40 HDQ Line Rising Time to Logic tRST HDQ Bus Reset(2) RPULLUP Pullup Resistor(3) Pullup voltage rail ≤ 5 V (2) (3) (4) 50 µs 86 145 µs µs 205 250 µs 32 50 µs 80 145 µs 1(2) Host holds bus low to initiate device interface reset (1) µs 0.5 1.9 1.5 1.8 µs 2.1 s kΩ Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design Specified by characterization Response time will vary depending on the internal device processing 7.30 Timing Requirements - SPI Interface Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted). All values specified with SPI pin filtering enabled.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSCK SPI clock period(2) 500(5) ns tLEAD Enable lead-time(2) 625 ns time(2) tLAG Enable lag tTD Sequential transfer delay(3) 50 tSU Data setup time(2) (6) 50 ns tHI Data hold time (inputs)(2) (6) 50 ns (outputs)(2) tHO Data hold time tA Responder access time(2) time(2) Responder DOUT disable tV Data valid(2) tR Rise time(2) tF Fall time(2) SPI bus reset(2) Bus interface is reset if SPI_CS is low and SPI_SCLK is detected unchanged for this duration (1) (2) (3) 24 µs 0 tDIS tRST ns 50 ns 500 ns 450 ns 235(5) ns Up to 25pF load 30 ns Up to 25pF load 30 ns 2.1 s 1.9 Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Specified by design See later discussion in datasheet for more details Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com (4) (5) SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Specified by characterization This assumes 15 ns setup time on the SPI controller for MISO. If additional setup time is required, the clock period should be extended accordingly. When SPI pin filtering is enabled, pulses on input pins of duration below 200 ns may be filtered out. (6) 7.31 Interface Timing Diagrams SDA tLOW tf tBUF tHD;STA tr tf tr tSP SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 7-1. I2C Communications Interface Timing SPI_CS t TD S t t LEAD t LAG SCK tR t sckl SPI_SCLK t sckh t HO SPI_MISO tF BITN-2« %,71 MSB OUT t tV t DIS LS B O U T A t SU t HI SPI_MOSI BITN-2« %,71 M S B IN L S B IN Figure 7-2. SPI Communications Interface Timing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 25 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 1.2 V t(B) t(RISE) t(BR) (a) Break and Break Recovery (b) HDQ Line Rise Time T(DW1) T(HW1) T(HW0) T(DW0) T(CYCH) T(CYCD) (c) HDQ Host Transmitted Bit Break 7-bit address (d) Device Transmitted Bit 1-bit R/W 7-bit address t(RSPS) (e) Device to HDQ Host Response t(RST) (f) HDQ Reset a. HDQ Breaking b. Rise time of HDQ line c. HDQ Host to Device communication d. Device to HDQ Host communication e. Device to HDQ Host response format f. HDQ Host to Device Figure 7-3. HDQ Communications Interface Timing 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.32 Typical Characteristics Figure 7-4. Cell Voltage Measurement Error at 25°C Across Input Range Figure 7-5. Cell Voltage Measurement Error vs. Temperature with Cell Voltage = 1.5 V Figure 7-6. Cell Voltage Measurement Error vs. Temperature with Cell Voltage = 2.5 V Figure 7-7. Cell Voltage Measurement Error vs. Temperature with Cell Voltage = 3.5 V Figure 7-8. Cell Voltage Measurement Error vs. Temperature with Cell Voltage = 4.5 V Figure 7-9. Cell Voltage Measurement Error vs. Temperature with Cell Voltage = 5.5 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 27 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Error in measurement of differential voltage between SRP and SRN pins Figure 7-10. Current Measurement Error vs. Temperature Figure 7-12. Internal Temperature Sensor (Delta VBE) Voltage vs. Temperature 28 Error in measurement of differential voltage between SRP and SRN pins Figure 7-11. Internal Voltage References vs. Temperature (VREF1 and VREF2) LFO measured in FULL SPEED mode (262 kHz) Figure 7-13. Low Frequency Oscillator (LFO) Accuracy vs. Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 7-14. High Frequency Oscillator (HFO) Accuracy vs. Temperature Figure 7-15. Overcurrent in Discharge Protection 1 (OCD1) Threshold vs. Temperature Figure 7-16. Overcurrent in Charge Protection (OCC) Threshold vs. Temperature Figure 7-17. Cell Balancing Resistance vs. Temperature Figure 7-18. Cell Balancing Resistance vs. Cell Common-Mode Voltage at 25°C Figure 7-19. REG1 Voltage vs. Load at 25°C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 29 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 7-20. REG2 Voltage vs. Load at 25°C Figure 7-22. Thermistor Pullup Resistance vs. Temperature (180-kΩ Setting) Figure 7-21. Thermistor Pullup Resistance vs. Temperature (18-kΩ Setting) Error calculated as percentage of nominal gain across ±200mV input range Figure 7-23. Coulomb Counter Gain Error vs. Temperature Figure 7-24. LD Wake Voltage vs. Temperature 30 Figure 7-25. REG18 Voltage vs. Temperature, with No Load Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 1.835 BAT=4.7V, 0mA BAT=8V, 0mA BAT=10V, 0mA BAT=20V, 0mA BAT=25.9V, 0mA BAT=40V, 0mA BAT=60V, 0mA BAT=80V, 0mA 1.83 1.825 Voltage (V) 1.82 1.815 1.81 BAT=4.7V, 1mA BAT=8V, 1mA BAT=10V, 1mA BAT=20V, 1mA BAT=25.9V, 1mA BAT=40V, 1mA BAT=60V, 1mA BAT=80V, 1mA 1.805 1.8 1.795 1.79 1.785 1.78 -40 -20 0 20 40 Temp (°C) 60 80 100 Figure 7-26. REG18 Voltage vs. Temperature, Across BAT Levels Measurements taken using external BJT Figure 7-27. REGIN Voltage vs. BAT Voltage Figure 7-28. BAT Current in NORMAL Mode vs. Temperature Figure 7-29. BAT Current in SHUTDOWN Mode vs. Temperature Figure 7-30. BAT Current in SLEEP2 (SRC Follower) Mode vs. Temperature Figure 7-31. BAT Current in DEEPSLEEP2 (No LFO) Mode vs. Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 31 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 8 Device Description 8.1 Overview The BQ76952 device is a highly integrated, accurate battery monitor and protector for 3-series to 16-series Li-ion, Li-polymer, and LiFePO4 battery packs. A high-accuracy voltage, current, and temperature measurement provides data for host-based algorithms and control. A feature-rich and highly configurable protection subsystem provides a wide set of protections that can be triggered and recovered completely autonomously by the device or under full control of a host processor. The integrated charge pump with high-side protection NFET drivers enables host communication with the device even when FETs are off by preserving the ground connection to the pack. Dual programmable LDOs are included for external system use, with each independently programmable to voltages of 1.8 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V, capable of providing up to 45 mA each. The BQ76952 device includes one-time-programmable (OTP) memory for customers to set up device operation on their own production line. Multiple communications interfaces are supported, including 400-kHz I2C, SPI, and HDQ one-wire standards. Multiple digital control and status data are available through several multifunction pins on the device, including an interrupt to the host processor, and independent controls for host override of each high-side protection NFET. Three dedicated pins enable temperature measurements using external thermistors, and multifunction pins can be programmed to use for additional thermistors, supporting a total of up to nine thermistors, in addition to an internal die temperature measurement. 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 8.2 Functional Block Diagram PACK Internal LDO BAT /'2¶V 1.8V / 2.5V / 3.0V / 3.3V / 5V CHG/DSG drivers To Digital REG2 Load Detect Charge Pump REG1 BAT To Digital REGIN Charger Detect BREG BAT BAT REG18 CP1 PACK FUSE Driver LD FUSE CFETOFF/SPI_CS/TS/ ADCIN/GPO VC16 VC15 VC14 DFETOFF/BOTHOFF/TS/ ADCIN/GPO VC13 VC12 CHG/ DSG Drivers VC11 VC10 OSCs CHG DSG VC9 VC8 VC7 PCHG Driver PCHG PDSG Driver PDSG VREF1 MUXs MUX1 & MUX2 VC6 VC5 VC4 û- ADC VC3 HDQ VC2 HDQ/SPI_MOSI/TS/ ADCIN/GPO VC1 DCHG/TS/ ADCIN/GPO VC0 OV, UV, OW Pullup source & switching control DDSG/TS/ ADCIN/GPO Digital Core TS1 TS2/WAKE TS3 ALERT/HDQ/TS/ADCIN/ GPO VREF2 SDA/SPI_MISO I2C/SPI VC16 VC7 VC15 VC6 VC5 VC4 VC3 VC2 CELL BALANCING VC8 SCL/SPI_SCLK Fuse, Load Detect Reset/ shutdown VC14 VC13 VC12 VREF2 VC11 û- ADC Coulomb Counter & Wakeup RST_SHUT Registers VC10 VC1 VC9 VC0 VC8 OTP Customer Settings SCD, OCD1, OCD2, OCC SRN SRP VSS 8.3 BQ76952 Device Versions The BQ76952 device family includes several versions with differing default settings programmed during factory test. These different settings, which may include having a different default communications interface or a different setting for the REG1 LDO, are described in the Device Comparison Table. 8.4 Diagnostics The BQ76952 device includes a suite of diagnostic tests that the system can use to improve operation robustness. These include comparisons between the two voltage references integrated within the device, a hardware monitor of the LFO frequency, memory checks at power-up or reset, an internal watchdog on the embedded processor, and more. The BQ76952 Technical Reference Manual describes these in detail. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 33 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 9 Device Configuration 9.1 Commands and Subcommands The BQ76952 device includes support for direct commands and subcommands. The direct commands are accessed using a 7-bit command address that is sent from a host through the device serial communications interface and either triggers an action, provides a data value to be written to the device, or instructs the device to report data back to the host. Subcommands are additional commands that are accessed indirectly using the 7-bit command address space and provide the capability for block data transfers. For more information on the commands and subcommands supported by the device, refer to the BQ76952 Technical Reference Manual. 9.2 Configuration Using OTP or Registers The BQ76952 device includes registers, with values that are stored in the RAM and can be loaded automatically from one-time programmable (OTP) memory. At initial power-up, the device loads OTP settings into registers, which are used by the device firmware during operation. The recommended procedure is for the customer to write settings into OTP on the manufacturing line, in which case the device will use these settings whenever it is powered up. Alternatively, the host processor can initialize registers after power-up, without using the OTP memory, but the registers will need to be reinitialized after each power cycle of the device. Register values are preserved while the device is in NORMAL, SLEEP, or DEEPSLEEP modes. If the device enters SHUTDOWN mode, all register memory is cleared, and the device returns to the default parameters (or the OTP configuration if that has been programmed) when powered again. See the BQ76952 Technical Reference Manual for more details. 9.3 Device Security The BQ76952 device includes three security modes: SEALED, UNSEALED, and FULLACCESS, which can be used to limit the ability to view or change settings. • • • In SEALED mode, most data and status can be read using commands and subcommands, but only selected settings can be changed. Data memory settings cannot be changed directly. UNSEALED mode includes SEALED functionality, and also adds the ability to execute additional subcommands, and read and write data memory. FULLACCESS mode allows capability to read and modify all device settings, including writing OTP memory. Selected settings in the device can be modified while the device is in operation through supported commands and subcommands, but in order to modify all settings, the device must enter CONFIG_UPDATE mode (see Section 13.6), which stops device operation while settings are being updated. After the update is completed, the operation is restarted using the new settings. CONFIG_UPDATE mode is only available in FULLACCESS mode. The BQ76952 device implements a key-access scheme to transition among SEALED, UNSEALED, and FULLACCESS modes. Each transition requires that a unique set of keys be sent to the device through subcommands. Refer to the BQ76952 Technical Reference Manual for more details. The device provides additional checks which can be used to optimize system robustness, including subcommands which calculate the digital signature of the integrated instruction ROM and data ROM. These signatures should never change for a particular product. If these were to change, it would indicate an error, either that the ROM had been corrupted, or the readback of the ROM or calculation of the signature experienced an error. An additional subcommand calculates a digital signature for the static configuration data (which excludes calibration values) and compares it to a stored value, returning a flag if the result does not match. 9.4 Scratchpad Memory The BQ76952 device integrates a 32-byte scratchpad memory which can be used by the customer for storing manufacturing data, such as serial numbers, production or test dates, and so forth. The scratchpad data can be written into OTP memory on the customer production line. This data can only be written while in FULLACCESS mode, although it can be read in all modes. 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 10 Measurement Subsystem 10.1 Voltage Measurement The BQ76952 device integrates a voltage ADC that is multiplexed between measurements of cell voltages, an internal temperature sensor, and up to nine external thermistors, as well as performs measurements of the voltage at the VC16 pin, the PACK pin, the LD pin, the internal REG18 LDO voltage, and the VSS rail (for diagnostic purposes). The BQ76952 device supports measurement of individual differential cell voltages in a series configuration, ranging from 3-series cells to 16-series cells. Each cell voltage measurement is a differential measurement of the voltage between two adjacent cell input pins, such as VC1-VC0, VC2-VC1, and so forth. The cell voltage measurements are processed based on trim and calibration corrections, and then reported in 16-bit resolution using units of 1 mV. The raw 24-bit digital output of the ADC is also available for readout using 32-bit subcommands. The cell voltage measurements can support a recommended voltage range from –0.2 V to 5.5 V. The voltage ADC saturates at a level of 5 × VREF1 (approximately 6.06 V) when measuring cell voltages, although for best performance it is recommended to stay at a maximum input of 5.5 V. 10.1.1 Voltage Measurement Schedule The BQ76952 voltage measurements are taken in a measurement loop that consists of multiple measurement slots. All 16 cell voltages are measured on each loop, then one slot is used for one of the VC16 or PACK or LD pin voltages, one slot is used for internal temperature or Vref or VSS measurement, then up to three slots are used to measure thermistors or multifunction pin voltages (ADCIN functionality). Over the course of three loops, a full set of measurements is completed. One measurement loop consists of either 18 (if no thermistors or ADCIN are enabled), 19 (if one thermistor or ADCIN is enabled), 20 (if two thermistors or ADCIN are enabled), or 21 (if three or more thermistors or ADCIN are enabled) measurement slots. The speed of a measurement loop can be controlled by settings. Each voltage measurement (slot) takes 3 ms (or 1.5 ms depending on setting), so a typical measurement loop with 21 slots per loop takes 63 ms (or 31.5 ms depending on setting). If measurement data is not required as quickly, the timing for the measurement loop can be programmed to slower speeds, which injects idle slots in each loop after the measurement slots. Using slower loop cycle time will reduce the power dissipation of the device when in NORMAL mode. 10.1.2 Usage of VC Pins for Cells Versus Interconnect If the BQ76952 device is used in a system with fewer than 16-series cells, the additional cell inputs can be utilized to improve measurement performance. For example, a long connection may exist between two cells in a pack, such that there may be significant interconnect resistance between the cells, such as shown in Figure 10-1 between CELL-A and CELL-B. By connecting VC12 close to the positive terminal of CELL-B, and connecting VC13 close to the negative terminal of CELL-A, more accurate cell voltage measurements are obtained for CELL-A and CELL-B, since the I·R voltage across the interconnect resistance between the cells is not included in either cell voltage measurement. Since the device reports the voltage across the interconnect resistance and the synchronized current, the resistance of the interconnect between CELL-A and CELL-B can also be calculated and monitored during operation. It is recommended to include the series resistance and bypass capacitor on cell inputs connected in this manner, as shown below. Note It is important that the differential input for each cell input not fall below –0.3 V (the Absolute Maximum data sheet limit), with the recommended minimum voltage of –0.2 V. Therefore, it is important that the I·R voltage drop across the interconnect resistance does not cause a violation of this requirement. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 35 BQ76952 + VC15 CELL-A + VC14 CELL-B + + VC12 + VC10 BREG FUSE PDSG LD PACK DSG NC CHG CP1 BAT VC16 + PCHG www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 VC13 VC11 VC9 Figure 10-1. Using Cell Input Pins for Interconnect Measurement VC8 If this connection across an interconnect is not needed (or it VC7 is preferred to avoid the extra resistor and capacitor), then the unused cell input pins should be shorted to adjacent cell input pins, as shown in Figure 10-2 VC6 for VC13. VC5 + VC15 CELL-A + VC14 CELL-B + + VC12 + VC10 VC13 VC11 VC9 Figure 10-2. Terminating an Unused VC8Cell Input Pin A configuration register is used to specify which cell inputs areVC7 used for actual cells. The device uses this information to disable cell voltage protections associated with inputs VC6which are used to measure interconnect or are not used at all. Voltage measurements for all inputs are reported in 16-bit format (in units of mV) as well as 32-bit format (in units of raw ADC counts), irrespective of whether VC5 they are used for cells or not. 10.1.3 Cell 1 Voltage Validation During SLEEP Mode VC4 In rare cases, an invalid Cell 1 Voltage() reading has been observed to occur in some devices taken during SLEEP mode. 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BREG FUSE PDSG PCHG LD PACK DSG NC CP1 CHG + BAT VC16 VC4 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 While the device is in SLEEP mode, each result obtained from reading the Cell 1 Voltage() must be validated before it can be considered valid. During SLEEP mode, current is below programmable thresholds, so the pack is typically not being charged or discharged with any significant level of current. Thus, the cell voltages will generally not be changing significantly. In order to determine if a measurement of Cell 1 Voltage() taken during SLEEP mode is valid, it is necessary to compare each measurement to measurements taken before and after the particular measurement. It is important that these three readings represent three separate measurements for the Cell 1 Voltage(). If the reading is significantly different from the separate readings taken before and after, then that reading is considered invalid and should be discarded. In order to ensure the three measurements read from the device are truly separate measurements, the host can read the measurements at intervals exceeding Power:Sleep:Voltage Time while the device is in SLEEP mode. This is necessary to avoid the host reading an existing measurement multiple times, before a new measurement has been taken and is available for readout. An invalid Cell 1 Voltage() reading may result in an SUV PF Alert being set but does not result in an SUV PF status fault if the SUV Delay is set to 1 second or longer. It also does not trigger a Cell Undervoltage (CUV) Protection alert or status fault, since this protection uses a comparator for its detection. If a reading reported by Cell 1 Voltage() is below the Protections:CUV:Threshold level and the CUV protection is enabled, but the CUV Alert is not triggered, this also can be used as an indication the reading is invalid. This validation process is necessary to ensure that valid Cell 1 Voltage() results are measured. 10.2 General Purpose ADCIN Functionality Several multifunction pins on the BQ76952 device can be used for general purpose ADC input (ADCIN) measurement, if not being used for other purposes. This includes the TS1, TS2, TS3, CFETOFF, DFETOFF, HDQ, DCHG, DDSG, and ALERT pins. When used for ADCIN functionality, the internal bandgap reference is used by the ADC, and the input range of the ADC is limited to the REG18 pin voltage. The digital fullscale range of the ADC is effectively 1.6667 × VREF1, which is approximately 2.02 V during normal operation. The BQ76952 device also reports the raw ADC counts when a measurement is taken using the TS1 pin. This data can be used during manufacturing to better calibrate the ADCIN functionality. 10.3 Coulomb Counter and Digital Filters The BQ76952 device monitors pack current using a low-side sense resistor, which connects to the SRP and SRN pins through an external RC filter, which should be connected such that a charging current will create a positive voltage on SRP relative to SRN. The differential voltage between SRP and SRN is digitized by an integrated coulomb counter ADC, which can digitize voltages over a ±200 mV range and uses multiple digital filters to provide optimized measurement of the instantaneous, averaged, and integrated current. The device supports a wide range of sense resistor value, with a larger value providing better resolution for the digitized result. The maximum value of sense resistor should be limited to ensure the differential voltage remains within the ±200 mV range for system operation when current measurement is desired. For example, a system with maximum discharge current of 200 A during normal operation (not a fault condition) should limit the sense resistor to 1 mΩ or below. The SRP and SRN pins can also support higher positive voltages relative to VSS, such as may occur during overcurrent or short circuit in discharge conditions, without damage to the device, although the current is not accurately digitized in this case. For example, a system with a 1 mΩ sense resistor and the Short Circuit in Discharge protection threshold programmed to a 500 mV level would trigger an SCD protection fault when a discharge current of 500 A was detected. Multiple digitized current values are available for readout over the serial communications interface, including two using separate hardware digital filters, CC1 and CC2, as well as a firmware filter CC3. The CC1 filter generates a 16-bit current measurement that is used for charge integration and other decision purposes, with one output generated every 250 ms when the device is operating in NORMAL mode. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 37 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 The CC2 filter generates a 24-bit current measurement that is used for current reporting, with one output every 3 ms when the device is operating in NORMAL mode (which can be reduced to one output every 1.5 ms based on setting, with reduced measurement resolution). It is reported in 16-bit format, and the 24-bit CC2 data is also available as raw coulomb counter ADC counts, provided in a 32-bit format (with the data contained in the lower 24-bits and the upper 8-bits sign-extended). The CC3 filter output is an average of a programmable number of CC2 current samples (up to 255), based on the configuration setting. The CC3 output is reported in 32-bit format. The integrated passed charge is available as a 64-bit value, which includes the upper 32-bits of accumulated charge as the integer portion, the lower 32-bits of accumulated charge as the fractional portion, and a 32-bit accumulated time over which the charge has been integrated in units of seconds. The accumulated charge integration and timer can be reset by a command from the host over the digital communications interface. 10.4 Synchronized Voltage and Current Measurement While the cell voltages are digitized sequentially using a single muxed ADC during normal operation, the current is digitized continuously by the dedicated coulomb counter ADC. The current is measured synchronously with each cell voltage measurement, and can be used for individual cell impedance analysis. The ongoing periodic current measurements can be read out through the digital communication interface, while the measurements taken that were synchronized with particular cell voltage measurements are stored paired with the associated cell voltage measurement for separate readout. These values can be read using a block subcommand, which ensures the synchronously aligned voltage and current data are read out together. 10.5 Internal Temperature Measurement The BQ76952 device integrates the capability to measure its internal die temperature by digitizing the difference in internal transistor base-emitter voltages (delta-VBE). This voltage is measured periodically as part of the measurement loop and is processed to provide a reported temperature value available through the digital communications interface. This internal temperature measurement can be used for cell or FET temperature protections and logic based on configuration settings. 10.6 Thermistor Temperature Measurement The BQ76952 device includes an on-chip temperature measurement and can also support up to nine external thermistors on multifunction pins (TS1, TS2, TS3, CFETOFF, DFETOFF, ALERT, HDQ, DCHG, and DDSG). The device includes an internal pullup resistor to bias a thermistor during measurement. The internal pullup resistor has two options which can set the pullup resistor to either 18-kΩ or 180-kΩ (or none at all). The 18-kΩ option is intended for use with thermistors such as the Semitec 103-AT, which has 10-kΩ resistance at room temperature. The 180-kΩ is intended for use with higher resistance thermistors such as the Semitec 204AP-2, which has 200-kΩ resistance at room temperature. The resistor values are measured during factory production and stored within the device for use during temperature calculation. The individual pin configuration registers determine which pin is used for a thermistor measurement, what value of pullup resistor is used, as well as whether the thermistor measurement is used for a cell or FET temperature reading. 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 REG18 (§1.8V) VREF1 §162 NŸ §18 NŸ reference Voltage ADC T S DDSG Pin §500 Ÿ §500 Ÿ T S DCHG Pin T S HDQ Pin §500 Ÿ §500 Ÿ T S TS3 Pin T S TS2 Pin §500 Ÿ §500 Ÿ T S TS1 Pin T S ALERT Pin §500 Ÿ §500 Ÿ T S DFETOFF Pin CFETOFF Pin §500 Ÿ input T S Figure 10-3. External Thermistor Biasing To provide a high precision temperature result, the device uses the same 1.8 V LDO voltage for the ADC reference as is used for biasing the thermistor pullup resistor, thereby implementing a ratiometric measurement that removes the error contribution from the LDO voltage level. The device processes the digitized thermistor voltage to calculate the temperature based on multiorder polynomials, which can be programmed by the user based on the specific thermistor selected. 10.7 Factory Trim of Voltage ADC The BQ76952 device includes factory trim for the cell voltage ADC measurements in order to optimize the voltage measurement performance even if no further calibration is performed by the customer. Calibration can be performed by the customer on the production line to further optimize the performance in the system. The trim information is used to correct the raw ADC readings before they are reported as 16-bit voltage values. The 32-bit ADC voltage data, which is generated in units of ADC counts, is modified before reporting by subtracting a stored offset trim value. The resulting reported data does not include any further correction (such as for gain), therefore the customer will need to process them before use. The device includes a factory gain trim for the voltage measurements performed using the general purpose ADC input capability on the multifunction pins as well as the TS1, TS2, and TS3 pins. It also includes factory gain trim on the voltage measurements of the PACK pin, the LD pin, and the top-of-stack (VC16) pin. 10.8 Voltage Calibration (ADC Measurements) The BQ76952 device includes optional capability for the customer to calibrate each cell voltage gain and the gain for the stack voltage, the PACK pin voltage, and the LD pin voltage individually, and multifunction pin general ADC measurements. An offset calibration value Calibration:Vcell Offset:Vcell Offset is included for use with the cell voltage measurements, and Calibration:Vdiv Offset:Vdiv Offset is used with the TOS (stack), PACK, and LD voltage measurements. The cell voltage gains determined during calibration are written in Calibration:Voltage:Cell 1 Gain – Cell 16 Gain, where Cell 1 Gain is used for the measurement of VC1– VC0, Cell 2 Gain is used for the measurement of VC2–VC1, and so forth. Similarly, the calibration voltage gain for the TOS voltage should be written in Calibration:Voltage:TOS Gain, the PACK pin voltage gain in Calibration:Voltage:Pack Gain, the LD pin voltage gain in Calibration:Voltage:LD Gain, and multifunction pin general purpose ADCIN measurement gain in Calibration:Voltage:ADC Gain. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 39 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 If values for the calibration gain configuration are not written, the BQ76952 device will use factory trim or default values for the respective gain values. When a calibration gain configuration value is written, the device will use that in place of any factory trim or default gain. The raw ADC measurement data (in units of counts) is corrected by first subtracting a stored offset trim value, then the gain is applied, then the Calibration:Vcell Offset:Vcell Offset (for cell voltage measurements) or the Calibration:Vdiv Offset:Vdiv Offset (for TOS, PACK, or LD voltage measurements) is subtracted, before the final voltage value is reported. The factory trim values for the Cell Gain parameters can be read from the Cell Gain data memory registers while in FULLACCESS mode but not in CONFIG_UPDATE mode, if the data memory values have not been overwritten. While in CONFIG_UPDATE mode, the Cell Gain values will read back either with all zeros, if they have not been overwritten, or whatever values have been written to these registers. Upon exiting CONFIG_UPDATE mode, readback of the Cell Gain parameters will provide the values presently used in operation. Further detail on calibration procedures can be found in the BQ76952 Technical Reference Manual. The effective fullscale digital range of the cell measurement is 5 × VREF1, and the effective fullscale digital range of the ADCIN measurement is 1.667 × VREF1, although the voltages applied for these measurement should be limited based on the specifications in Section 7. Using a value for VREF1 of 1.212 V, the nominal gain for the cell measurements is 12120, while the nominal gain for the ADCIN measurements is 4040. The reported voltages are calculated as: Cell # Voltage() = Calibration:Voltage:Cell # Gain × (16-bit ADC counts) / 65536 – Calibration:Vcell Offset:Vcell Offset Stack Voltage() = Calibration:Voltage:TOS Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset PACK Pin Voltage() = Calibration:Voltage:Pack Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset LD Pin Voltage() = Calibration:Voltage:LD Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset ADCIN Voltage = Calibration:Voltage:ADC Gain × (16-bit ADC counts) / 65536 Note Cell # Voltage() and Calibration:Vcell Offset:Vcell Offset both have units of mV. The divider voltages (Stack Voltage(), PACK Pin Voltage(), and LD Pin Voltage()) and Calibration:Vdiv Offset:Vdiv Offset all have units of userV. 10.9 Voltage Calibration (COV and CUV Protections) The BQ76952 device includes optional capability for the customer to calibrate the COV (cell overvoltage) and CUV (cell undervoltage) protection thresholds on the production line, in order to improve threshold accuracy in system or to realize a threshold between the preset thresholds available from the device. This calibration is performed while the device is in CONFIG_UPDATE mode. To calibrate the COV threshold, an external voltage is first applied between VC16 and VC15 that is equal to the desired COV threshold. Next, the CAL_COV() subcommand is sent by the host, which causes the BQ76952 device to perform a search for the appropriate calibration coefficients to realize a COV threshold at or close to the applied voltage level. When this search is completed, the resulting calibration coefficient is returned by the subcommand and automatically written into the Protections:COV:COV Threshold Override configuration parameter. If this parameter is nonzero, the device will not use its factory trim settings but will instead use this value. The CUV threshold is calibrated similarly, an external voltage is applied between VC16 and VC15 equal to the desired CUV threshold. Next, while in CONFIG_UPDATE mode, the CAL_CUV() subcommand is sent by the host, which causes the BQ76952 device to perform a search for the appropriate calibration coefficients to realize a CUV threshold at or close to the applied voltage level. When this search is completed, the resulting calibration coefficient is returned by the subcommand and automatically written into the Protections:CUV:CUV Threshold Override configuration parameter. 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 10.10 Current Calibration The BQ76952 device coulomb counter ADC measures the differential voltage between the SRP and SRN pins to calculate the system current. The device includes the optional capability for the customer to calibrate the coulomb counter offset and current gain on the production line. The Calibration:Current Offset:CC Offset configuration register contains an offset value in units of 32-bit coulomb counter ADC counts / Calibration:Current Offset:Coulomb Counter Offset Samples. The value of Calibration:Current Offset:CC Offset / Calibration:Current Offset:Coulomb Counter Offset Samples is subtracted from the raw coulomb counter ADC counts, then the result is multiplied by Calibration:Current:CC Gain and scaled to provide the final result in units of userA. The BQ76952 device uses the Calibration:Current:CC Gain and Calibration:Current:Capacity Gain configuration values to convert from the ADC value to current. The CC Gain reflects the value of the sense resistor used in the system, while the Capacity Gain is simply the CC Gain multiplied by 298261.6178. Both the CC Gain and Capacity Gain are encoded using a 32-bit IEEE-754 floating point format. The effective value of the sense resistor is given by: CC Gain = 7.4768 / (Rsense in mΩ) 10.11 Temperature Calibration The BQ76952 device enables the customer to calibrate the internal as well as external temperature measurements on the production line, by storing an offset value that is added to the calculated measurement before reporting. A separate offset for each temperature measurement can be stored in the configuration registers shown below. Table 10-1. Temperature Calibration Settings Section Subsection Register Description Comment Units Calibration Temperature Internal Temp Offset Calibration Temperature CFETOFF Temp Offset CFETOFF pin thermistor 0.1 K Calibration Temperature DFETOFF Temp Offset DFETOFF pin thermistor 0.1 K Calibration Temperature ALERT Temp Offset ALERT pin thermistor 0.1 K Calibration Temperature TS1 Temp Offset TS1 pin thermistor 0.1 K Calibration Temperature TS2 Temp Offset TS2 pin thermistor 0.1 K Calibration Temperature TS3 Temp Offset TS3 pin thermistor 0.1 K Calibration Temperature HDQ Temp Offset HDQ pin thermistor 0.1 K Calibration Temperature DCHG Temp Offset DCHG pin thermistor 0.1 K Calibration Temperature DDSG Temp Offset DDSG pin thermistor 0.1 K 0.1 K Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 41 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 11 Primary and Secondary Protection Subsystems 11.1 Protections Overview An extensive protection subsystem is integrated within BQ76952, which can monitor a variety of parameters, initiate protective actions, and autonomously recover based on conditions. The device also includes a wide range of flexibility, such that the device can be configured to monitor and initiate protective action, but with recovery controlled by the host processor, or such that the device only monitors and alerts the host processor whenever conditions warrant protective action, but with action and recovery fully controlled by the host processor. The primary protection subsystem includes a suite of individual protections which can be individually enabled and configured, including cell undervoltage and overvoltage, overcurrent in charge, three separate overcurrent in discharge protections, short circuit current in discharge, cell overtemperature and undertemperature in charge and discharge, FET overtemperature, a host processor communication watchdog timeout, and PRECHARGE mode timeout. The cell undervoltage and overvoltage, overcurrent in charge, overcurrent in discharge 1 and 2, and short circuit in discharge protections are based on comparator thresholds, while the remaining protections (such as those involving temperature, host watchdog, and precharging) are based on firmware on the internal controller. The device integrates NFET drivers for high-side CHG and DSG protection FETs, which can be configured in a series or parallel configuration. An integrated charge pump generates a voltage which is driven onto the NFET gates based on host command or the on-chip protection subsystem settings. Support is also included for high-side PFETs used to implement a precharge and predischarge functionality. The secondary protection suite within the BQ76952 device can react to more serious faults and take action to permanently disable the pack, by initiating a Permanent Fail (PF). The secondary safety provides protection against safety cell undervoltage and overvoltage, safety overcurrent in charge and discharge, safety overtemperature for cells and FETs, excessive cell voltage imbalance, internal memory faults, and internal diagnostic failures. When a Permanent Fail has occurred, the BQ76952 device can be configured to either simply provide a flag, or to indefinitely disable the protection FETs, or to assert the FUSE pin to permanently disable the pack. The FUSE pin can be used to blow an in-line fuse and also can monitor if a separate secondary protector IC has attempted to blow the fuse. 11.2 Primary Protections The BQ76952 device integrates a broad suite of protections for battery management and provides the capability to enable individual protections, as well as to select which protections will result in autonomous control of the FETs. See the BQ76952 Technical Reference Manual for detailed descriptions of each protection function. The primary protection features include: • • • • • • • • • • • • • • • • 42 Cell Undervoltage Protection Cell Overvoltage Protection Cell Overvoltage Latch Protection Overcurrent in Charge Protection Overcurrent in Discharge Protection (three tiers) Overcurrent in Discharge Latch Protection Short Circuit in Discharge Protection Short Circuit in Discharge Latch Protection Undertemperature in Charge Protection Undertemperature in Discharge Protection Internal Undertemperature Protection Overtemperature in Charge Protection Overtemperature in Discharge Protection Internal Overtemperature Protection FET Overtemperature Protection Precharge Timeout Protection Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com • SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Host Watchdog Fault Protection 11.3 Secondary Protections The BQ76952 device integrates a suite of secondary protection checks on battery operation and status that can trigger a Permanent Fail (PF) if conditions are considered so serious that the pack should be permanently disabled. The various PF checks can be enabled individually based on configuration settings, along with associated thresholds and delays for most checks. When a Permanent Fail has occurred, the BQ76952 device can be configured to either simply provide a flag, to indefinitely disable the protection FETs, or to assert the FUSE pin to permanently disable the pack. The FUSE pin can be used to blow an in-line fuse and also can monitor if a separate secondary protector IC has attempted to blow the fuse. Because the device stores Permanent Fail status in RAM, that status would be lost when the device resets. To mitigate this, the device can write Permanent Fail status to OTP based on configuration setting. OTP programming may be delayed in low-voltage and high-temperature conditions until OTP programming can reliably be accomplished. Normally, a Permanent Fail causes the FETs to remain off indefinitely and the fuse may be blown. In that situation, no further action would be taken on further monitoring operations, and charging would no longer be possible. To avoid rapidly draining the battery, the device may be configured to enter DEEPSLEEP mode when a Permanent Fail occurs. Entrance to DEEPSLEEP mode will still be delayed until after fuse blow and OTP programming are completed, if those options are enabled. When a Permanent Fail occurs, the device may be configured to either turn the REG1 and REG2 LDOs off, or to leave them in their present state. Once disabled, they may still be reenabled through command. The Permanent Fail checks incorporate a programmable delay to avoid triggering a PF fault on an intermittent condition or measurement. When the threshold is first detected as being met or exceeded by an enabled PF check, the device will set a PF Alert signal, which can be monitored using commands and can also trigger an interrupt on the ALERT pin. Note The device only evaluates the conditions for Permanent Fail at one second intervals while in NORMAL and SLEEP modes, it does not continuously compare measurements to the Permanent Fail fault thresholds between intervals. Thus, it is possible for a condition to trigger a PF alert if detected over threshold, but even if the condition drops back below threshold briefly between the one second interval checks, the PF alert would not be cleared until it was detected below threshold at a periodic check. For more details on the Permanent Fail checks implemented in the BQ76952, refer to the BQ76952 Technical Reference Manual. The secondary protection checks include: • • • • • • • • • • • • • • Safety Cell Undervoltage Permanent Fail Safety Cell Overvoltage Permanent Fail Safety Overcurrent in Charge Permanent Fail Safety Overcurrent in Discharge Permanent Fail Safety Overtemperature Permanent Fail Safety Overtemperature FET Permanent Fail Copper Deposition Permanent Fail Short Circuit in Discharge Latch Permanent Fail Voltage Imbalance Active Permanent Fail Voltage Imbalance at Rest Permanent Fail Second Level Protector Permanent Fail Discharge FET Permanent Fail Charge FET Permanent Fail OTP Memory Permanent Fail Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 43 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 • • • • • • • • Data ROM Permanent Fail Instruction ROM Permanent Fail Internal LFO Permanent Fail Internal Voltage Reference Permanent Fail Internal VSS Measurement Permanent Fail Internal Stuck Hardware Mux Permanent Fail Commanded Permanent Fail Top of Stack Versus Cell Sum Permanent Fail 11.4 High-Side NFET Drivers The BQ76952 device includes an integrated charge pump and high-side NFET drivers for driving CHG and DSG protection FETs. The charge pump uses an external capacitor connected between the BAT and CP1 pins that is charged to an overdrive voltage when the charge pump is enabled. Due to the time required for the charge pump to bring the overdrive voltage on the external CP1 pin to full voltage, it is recommended to leave the charge pump powered whenever it may be needed quickly to drive the CHG or DSG FETs. The DSG FET driver includes a special option (denoted source follower mode) to drive the DSG FET with the BAT pin voltage during SLEEP mode. This capability is included to provide low power in SLEEP mode, when there is no significant charge or discharge current flowing. It is recommended to keep the charge pump enabled even when the source follower mode is enabled, so whenever a discharge current is detected, the device can quickly transition to driving the DSG FET using the charge pump voltage. The source follower mode is enabled using a configuration setting and is not intended to be used when significant charging or discharging current is flowing, since the FET will exhibit a large drain-source voltage and may undergo excessive heating. The overdrive level of the charge pump voltage can be set to 5.5 V or 11 V, based on the configuration setting. In general, the 5.5-V setting results in lower power dissipation when a FET is being driven, while the higher 11-V overdrive reduces the on-resistance of the FET. If a FET exhibits significant gate leakage current when driven at the higher overdrive level, this can result in a higher device current for the charge pump to support this. In this case, using the lower overdrive level can reduce the leakage current and thus the device current. The BQ76952 device supports a system with FETs in a series or parallel configuration, where the parallel configuration includes a separate path for the charger connection versus the discharge (load) connection. The control logic for the device operates slightly differently in these two cases, which is set based on the configuration setting. The FET drivers in the BQ76952 device can be controlled in several different manner, depending on customer requirements: Fully autonomous The BQ76952 device can detect protection faults and autonomously disable the FETs, monitor for a recovery condition, and autonomously reenable the FETs, without requiring any host processor involvement. Partially autonomous The BQ76952 device can detect protection faults and autonomously disable the FETs. When the host receives an interrupt and recognizes the fault, the host can send commands across the digital communications interface to keep the FETs off until the host decides to release them. Alternatively, the host can assert the CFETOFF or DFETOFF pins to keep the FETs off. As long as these pins are asserted, the FETs are blocked from being reenabled. When these pins are deasserted, the BQ76952 will reenable the FETs if nothing is blocking them being reenabled (such as fault conditions still present, or the CFETOFF or DFETOFF pins are asserted). Manual control 44 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 The BQ76952 device can detect protection faults and provide an interrupt to a host processor over the ALERT pin. The host processor can read the status information of the fault over the communication bus (if desired) and can quickly force the CHG or DSG FETs off by driving the CFETOFF or DFETOFF pins from the host processor, or commands over the digital communications interface. When the host decides to allow the FETs to turn on again, it writes the appropriate command or deasserts the CFETOFF and DFETOFF pins, and the BQ76952 device will reenable the FETs if nothing is blocking them being reenabled. 11.5 Protection FETs Configuration and Control 11.5.1 FET Configuration The BQ76952 device supports both a series configuration and a parallel configuration for the protection FETs in the system, as well as a system that does not use one or both FETs. When a series FET configuration is used, the BQ76952 device provides body diode protection for the case when one FET is off and one FET is on. If the CHG FET is off, the DSG or PDSG FET is on, and a discharge current greater in magnitude than a programmable threshold (that is, a significant discharging current) is detected, the device will turn on the CHG FET, to avoid current flowing through the CHG FET body diode and damaging the FET. When the current rises above the threshold (that is, less discharge current flowing), the CHG FET will be turned off again if the reasons for its turn-off are still present. If the DSG FET is off, the CHG or PCHG FET is on, and a current in excess of a programmable threshold (that is, a significant charging current) is detected, the device will turn on the DSG FET, to avoid current flowing through the DSG FET body diode and damaging the FET. When the current falls below the threshold (that is, less charging current flowing), the DSG FET will be turned off again if the reasons for its turn-off are still present. When a parallel configuration is used, the body diode protection is disabled. 11.5.2 PRECHARGE and PREDISCHARGE Modes The BQ76952 device includes precharge functionality, which can be used to reduce the charging current for an undervoltage battery by charging using a high-side PCHG PFET (driven from the PCHG pin) with series resistor until the battery reaches a programmable voltage level. When the minimum cell voltage is less than a programmable threshold, the PCHG FET will be used for charging. The device also supports predischarge functionality, which can be used to reduce inrush current when the load is initially powered, by first enabling a high-side PDSG PFET (driven from the PDSG pin) with series resistor, which enables the load to slowly charge. If PREDISCHARGE mode is enabled, whenever the DSG FET is turned on to power the load, the device will first enable the PDSG FET, then transition to turn on the DSG FET and turn off the PDSG FET. The PCHG and PDSG drivers are limited in the current they can sink while enabled. As such, it is recommended to use 1 MΩ or larger resistance across the FET gate-source. 11.6 Load Detect Functionality When a Short Circuit in Discharge Latch or Overcurrent in Discharge Latch protection fault has occurred and the DSG FET is off, the device can be configured to recover when load removal is detected. This feature is useful if the system has a removable pack, such that the user can remove the pack from the system when a fault occurs, or if the effective system load that remains on the battery pack is higher than ~20-kΩ when the DSG FET is disabled. The device will periodically enable a current source out the LD pin and will recover the fault if a voltage is detected at the LD pin above a 4-V level. If a low-impedance load is still present on the pack, the voltage the device measures on the LD pin will generally be below 4-V, preventing recovery based on Load Detect. If the pack has been removed from the system and the effective load is high, such that the current source generates a voltage on the LD pin above a 4-V level, then the device can recover from the fault. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 45 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Note Typically, a 10-kΩ resistor is connected between the PACK+ terminal and the LD pin, this resistance should be comprehended when considering the load impedance. The Load Detect current is enabled for a programmable time duration, then is disabled for another programmable time duration, with this sequence repeating until the load has been detected as removed or it times out. 12 Device Hardware Features 12.1 Voltage References The BQ76952 device includes two voltage references, VREF1 and VREF2, with VREF1 used by the voltage ADC for most measurements except external thermistors. VREF2 is used by the integrated 1.8 V LDO, internal oscillators, and integrated coulomb counter ADC. The value of VREF2 can be measured indirectly by the voltage ADC's measurement of the REG18 LDO voltage while using VREF1 for diagnostic purposes. 12.2 ADC Multiplexer The ADC multiplexer connects various signals to the voltage ADC, including the individual differential cell voltage pins, the on-chip temperature sensor, the biased thermistor pins, the REG18 LDO voltage, the VSS pin voltage, and internal dividers connected to the VC16, PACK, and LD pins. 12.3 LDOs The BQ76952 device contains an integrated 1.8-V LDO (REG18) that provides a regulated 1.8 V supply voltage for the device's internal circuitry and digital logic. This regulator uses an external capacitor connected to the REG18 pin, and it should only be used for internal circuitry. The device also integrates two separately programmable LDOs (REG1 and REG2) for external circuitry, such as a host processor or external transceiver circuitry, which can be programmed to independent output voltages. The REG1 and REG2 LDOs take their input from the REGIN pin, with this voltage either provided externally or generated by an on-chip preregulator (referred to as REG0). The REG1 and REG2 LDOs can provide an output current of up to 45 mA each. 12.3.1 Preregulator Control The REG1 and REG2 LDOs take their input from the REGIN pin, which should be approximately 5.5 V. This REGIN pin voltage can be supplied externally (such as by a separate DC/DC converter) or using the integrated voltage preregulator (referring to as REG0), which drives the base of an external NPN BJT (using the BREG pin) to provide the 5.5-V REGIN pin voltage. When the preregulator is being used, special care should be taken to ensure the device retains sufficient voltage on its BAT pin, per the specifications in Specifications. Note The system designer should ensure the external BJT can tolerate the peak power that may be dissipated in it under maximum load expected on REG1 and REG2. If the maximum stack voltage is 80 V, then the BJT will experience a collector-emitter voltage of approximately 75 V, thereby dissipating 6.75 W if REG1 and REG2 are both used to support a 45-mA load. Note There is a diode connection between the REGIN pin (anode) and the BAT pin (cathode), so the voltage on REGIN should not exceed the voltage on BAT. 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 12.3.2 REG1 and REG2 LDO Controls The REG1 and REG2 LDOs in the BQ76952 device are for customer use, and their output voltages can be programmed independently to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V. The REG1 and REG2 LDOs and the REG0 preregulator are disabled by default in the BQ76952 device. While in SHUTDOWN mode, the REG1 and REG2 pins have ≈10-MΩ resistances to VSS, to discharge any output capacitance. While in other power modes, when REG1 and REG2 are powered down, they are pulled to VSS with an internal resistance of ≈2.5-kΩ. If pullup resistors for serial communications are connected to the REG1 voltage output, the REG1 voltage can be overdriven from an external voltage supply on the manufacturing line, to allow communications with the device. The BQ76952 device can then be programmed to enable REG0 and REG1 with the desired configuration, and this setting can be programmed into OTP memory. Thus, at each later power-up, the device will autonomously load the OTP settings and enable the LDO as configured, without requiring communications first. 12.4 Standalone Versus Host Interface The BQ76952 device can be configured to operate in a completely standalone mode, without any host processor in the system, or together with a host processor. If in standalone mode, the device can monitor conditions, control FETs and an in-line fuse based on threshold settings, and recover FETs when conditions allow, all without requiring any interaction with an external processor. If a host processor is present, the device can still be configured to operate fully autonomously, while the host processor can read measurements and exercise control as desired. In addition, the device can be configured for manual host control, such that the device can monitor and provide a flag when a protection alert or fault has occurred, but will rely on the host to disable FETs. The host processor can interface with the BQ76952 device through a serial bus as well as selected pin controls. Serial bus communication through I2C (supporting speeds up to 400 kHz), SPI or HDQ is available, with the serial bus configured for I2C by default in the BQ76952, while the default communications mode may differ for other versions of the device. The pin controls available include RST_SHUT, ALERT, CFETOFF, DFETOFF, DDSG, and DCHG, which are described in detail below. 12.5 Multifunction Pin Controls The BQ76952 device provides flexibility regarding the multifunction pins on the device, which includes the TS1, TS2, TS3, CFETOFF, DFETOFF, ALERT, HDQ, DCHG, and DDSG pins. Several of the pins can be used as active-high outputs with configurable output level. The digital output driver for these pins can be configured to drive an output powered from the REG1 LDO or from the internal REG18 LDO, and thus when asserted active-high will drive out the voltage of the selected LDO. Note The REG18 LDO is not capable of driving high current levels, so it is recommended to only use this LDO to provide a digital output if it will be driving a very high resistance (such as > 1 MΩ) or light capacitive load. Otherwise, the REG1 should be powered and used to drive the output signal. The options supported on each pin include: ALERT Alarm interrupt output HDQ communications CFETOFF Input to control the CHG FET (that is, CFETOFF functionality) DFETOFF Input to control the DSG FET (that is, DFETOFF functionality) Input to control both the DSG and CHG FETs (that is, BOTHOFF functionality) HDQ HDQ communications Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 47 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 SPI MOSI pin DCHG DCHG functionality—a logic-level output corresponding to a fault that would normally cause the CHG driver to be disabled DDSG DDSG functionality—a logic-level output corresponding to a fault that would normally cause the DSG driver to be disabled ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG General purpose digital output Can be driven high or low by command Can be configured for an active-high output to be driven from the REG1 LDO or the REG18 LDO Can be configured to have a weak pulldown to VSS or weak pullup to REG1 enabled continuously ALERT, CFETOFF, DFETOFF, TS1, TS2, TS3, HDQ, DCHG, and DDSG Thermistor temperature measurement A thermistor can be attached between the pin and VSS ADCIN Pin can be used for general purpose ADC measurement 12.6 RST_SHUT Pin Operation The RST_SHUT pin provides a simple way to reset or shutdown the BQ76952 device without needing to use serial bus communication. During normal operation, the RST_SHUT pin should be driven low. When the pin is driven high, the device will immediately reset most of the digital logic, including that associated with the serial communications bus. However, it does not reset the logic that holds the state of the protection FETs and FUSE, these remain as they were before the pin was driven high. If the pin continues to be driven high for 1 second, the device will then transition into SHUTDOWN mode, which involves disabling external protection FETs, and powering off the internal oscillators, the REG18 LDO, the on-chip preregulator, and the REG1 and REG2 LDOs. 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality The BQ76952 device includes two pins (CFETOFF and DFETOFF) which can be used to disable the protection FET drivers quickly, without going through the host serial communications interface. When the selected pin is asserted, the device disables the respective protection FET. Note: when the selected pin is deasserted, the respective FET will only be enabled if there are no other items blocking them being reenabled, such as if the host also sent a command to disable the FETs using the serial communications interface after setting the selected pin. Both the CFETOFF and DFETOFF pins can be used for other functions if the FET turnoff feature is not required. The CFETOFF pin can optionally be used to disable the CHG and PCHG FETs, and the DFETOFF pin can optionally be used to disable the DSG and PDSG FETs. The device also includes the option to configure the DFETOFF pin as BOTHOFF functionality, such that if that pin is asserted, the CHG, PCHG, DSG, and PDSG FETs will be disabled. This allows the CFETOFF pin to be used for an additional thermistor in the system, while still providing pin control to disable the FETs. The CFETOFF or BOTHOFF functionality disables both the CHG FET and the PCHG FET when asserted. The DFETOFF or BOTHOFF functionality disables both the DSG FET and the PDSG FET when asserted. 12.8 ALERT Pin Operation The ALERT pin is a multifunction pin that can be configured either as ALERT (to provide an interrupt to a host processor), a thermistor input, a general purpose ADC input, a general purpose digital output, or an HDQ serial communication interface. The pin can be configured as active-high, active-low, or open-drain, to 48 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 accommodate different system design preferences. When configured as the HDQ interface pin, the pin will operate in open-drain mode. When the pin is configured to drive an active high output, the output voltage is driven from either the REG18 1.8 V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V). Note: if a DC or significant transient current may be driven by this pin, then the output should be configured to drive using the REG1 LDO, not the REG18 LDO. The BQ76952 device includes functionality to generate an alarm signal at the ALERT pin, which can be used as an interrupt to a host processor. When used for the alarm function, the pin can be programmed to drive the signal as an active-low or hi-Z signal, an active-high or low signal, or an active-low or high signal (that is, inverted polarity). The alarm function within the BQ76952 device includes a programmable mask, to allow the customer to decide which of many flags or events can trigger an alarm. 12.9 DDSG and DCHG Pin Operation The BQ76952 device includes two multifunction pins, DDSG and DCHG, which can be configured as logic-level outputs to provide a fault-related signal to a host processor or external circuitry (that is, DDSG and DCHG functionality), as a thermistor input, a general purpose ADC input, or a general purpose digital output. When used as a digital output, the pins can be configured to drive an active high output, with the output voltage driven from either the REG18 1.8-V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V). Note If a DC or significant transient current may be driven by a pin, then the output should be configured to drive using the REG1 LDO, not the REG18 LDO. When the pins are configured for DDSG and DCHG functionality, they provide signals related to protection faults that (on the DCHG pin) would normally cause the CHG driver to be disabled, or (on the DDSG pin) would normally cause the DSG driver to be disabled. These signals can be used to control external protection circuitry, if the integrated high-side NFET drivers will not be used in the system. They can also be used as interrupts in manual FET control mode for the host processor to decide whether to disable the FETs through commands or using the CFETOFF and DFETOFF pins. 12.10 Fuse Drive The FUSE pin on the BQ76952 device can be used to blow a chemical fuse in the presence of a Permanent Fail (PF), as well as to determine if an external secondary protector in the system has detected a fault and is attempting to blow the fuse itself. The pin can drive the gate of an NFET, which can be combined with the drive from an external secondary protector, as shown in Figure 12-1. When the FUSE pin is not asserted by the BQ76952 device, it remains in a high-impedance state and detects a voltage applied at the pin by a secondary protector. The device can be configured to generate a PF if it detects a high signal at the FUSE pin. The device can be configured to blow the fuse when a PF occurs. In this case, the device will only attempt to blow the fuse if the stack voltage is above a programmed threshold, based on a system configuration with the fuse placed between the top of stack and the high-side protection FETs. If instead the fuse is placed between the FETs and the PACK+ connector, then the device bases its decision on the PACK pin voltage (based on configuration setting). This voltage threshold check may be disregarded under certain special cases, as described in the BQ76952 Technical Reference Manual . Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 49 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 12-1. FUSE Pin Operation 12.11 Cell Open Wire The BQ76952 device supports detection of a broken connection between a cell in the pack and the cell attachment to the PCB containing BQ76952. Without this check, the voltage at the cell input pin of the BQ76952 device may persist for some time on the board-level capacitor, leading to incorrect voltage readings. The Cell Open Wire detection in the BQ76952 device operates by enabling a small current source from each cell to VSS at programmable intervals. If a cell input pin is floating due to an open wire condition, this current discharges the capacitance, causing the voltage at the pin to slowly drop. This drop in voltage eventually triggers a protection fault on that particular cell and the cell above it. Eventually, the voltage drops low enough to trigger a Permanent Fail on the particular cell and the cell above it. The Cell Open Wire current is enabled at a periodic interval set by configuration register. The current source is enabled once every interval for a duration of the ADC measurement time (which is 3 ms by default). This provides programmability in the average current drawn from ≈0.65 nA to ≈165 nA, based on the typical current level of 55 µA. Note The Cell Open Wire check can create a cell imbalance, so the settings should be selected appropriately. 12.12 Low Frequency Oscillator The low frequency oscillator (LFO) in the BQ76952 device operates continuously while in NORMAL and SLEEP modes, and can be configured to remain powered or shutdown (except when needed) during DEEPSLEEP mode. The LFO runs at ≈262.144 kHz during NORMAL mode, and reduces to ≈32.768 kHz in SLEEP or DEEPSLEEP modes. The LFO is trimmed during manufacturing to meet the specified accuracy across temperature. 12.13 High Frequency Oscillator The high frequency oscillator (HFO) in the BQ76952 device operates at 16.78 MHz and is frequency locked to the LFO. The HFO powers up as needed for internal logic functions. 50 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 13 Device Functional Modes 13.1 Overview This device supports four functional modes to support optimized features and power dissipation, with the device able to transition between modes either autonomously or controlled by a host processor. • • • • NORMAL mode: In this mode, the device performs frequent measurements of system current, cell voltages, internal and thermistor temperature, and various other voltages, operates protections as configured, and provides data and status updates. SLEEP mode: In this mode, the DSG FET is enabled, the CHG FET can optionally be disabled, and the device performs measurements, calculations, and data updates in adjustable time intervals. Battery protections are still enabled. Between the measurement intervals, the device is operating in a reduced power stage to minimize total average current consumption. DEEPSLEEP mode: In this mode, the CHG, PCHG, DSG, and PDSG FETs are disabled, all battery protections are disabled, and no current or voltage measurements are taken. The REG1 and REG2 LDOs can be kept powered, in order to maintain power to external circuitry, such as a host processor. SHUTDOWN mode: The device is completely disabled (including the internal, REG1, and REG2 LDOs), the CHG, PCHG, DSG, and PDSG FETs are all disabled, all battery protections are disabled, and no measurements are taken. This is the lowest power state of the device, which may be used for shipment or long-term storage. All register settings are lost when in SHUTDOWN mode. The device also includes a CONFIG_UPDATE mode, which is used for parameter updates. Transitioning between functional modes is shown below. SHUTDOWN MODE Charger detect on TS2 pulldown detect on Very low VBAT Charger detection or TS2 pulldown detection Shutdown signal by RST_SHUT pin or low VBAT or high temp Shutdown signal by RST_SHUT pin or command or low VBAT or high temp SLEEP MODE REG18, REG1, REG2 on Comparator protections on Periodic ADC protections on Current wake detector on DEEPSLEEP MODE REG18, REG1, REG2 on LFO on DEEPSLEEP() command twice EXIT_DEEPSLEEP() command or reset signal by RST_SHUT pin or charger detected NORMAL MODE Monitoring on Protection on REG18, REG1, REG2 on DEEPSLEEP() command twice, or Permanent Fail Blue = programmable Low current SLEEP_DISABLE() command or fault or fault recovery or current detected or charger detected or reset signal by RST_SHUT pin Reset signal by RST_SHUT pin Figure 13-1. Device Functional Modes 13.2 NORMAL Mode NORMAL mode is the highest performance mode of the device, in which the device is making regular measurement of voltage, current, and temperature, the LFO (low frequency oscillator) is operating, and the internal processor powers up (as needed) for data processing and control. Full battery protections are operating, based on device configuration settings. System current is measured at intervals of 3 ms, with cell voltages measured at intervals of 63 ms or slower, depending on configuration. The device also provides a configuration Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 51 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 bit which causes the conversion speed for both voltages and CC2 Current to be doubled, with a reduction in measurement resolution. The device will generally be in NORMAL mode whenever any active charging or discharging is underway. When the CC1 Current measurement falls below a programmable current threshold, the system is considered in relax mode, and the BQ76952 device can autonomously transition into SLEEP mode, depending on the configuration. 13.3 SLEEP Mode SLEEP mode is a reduced functionality state that can be optionally used to reduce power dissipation when there is little or no system load current or charging in progress, but still provides voltage at the battery pack terminals to keep the system alive. At initial power up, a configuration bit determines whether the device can enter SLEEP mode. After initialization, SLEEP mode can be allowed or disallowed using subcommands. Status bits are provided to indicate whether the device is presently allowed to enter SLEEP mode or not, and whether it is presently in SLEEP mode or not. When the magnitude of the CC1 Current measurement falls below a programmable current threshold, the system is considered in relax mode, and the BQ76952 device will autonomously transition into SLEEP mode, if settings permit. During SLEEP mode, comparator-based protections operate the same as during NORMAL mode. ADC-based current, voltage, and temperature measurements are taken at programmable intervals. All temperature protections use the ADC measurements taken at these intervals, so they will update at a reduced rate during SLEEP mode. The BQ76952 device will exit SLEEP mode if a protection fault occurs, or current begins flowing, or a charger is attached, or if forced by subcommand, or if the RST_SHUT pin is asserted for < 1 s. When exiting based on current flow, the device will quickly enable the FETs (if the CHG FET was off, or the DSG FET was in source follower mode), but the standard measurement loop is not restarted until the next 1-s boundary occurs within the device timing. Therefore, new data may not be available for up to ≈1-s after the device exits SLEEP mode. The coulomb counter ADC operates in a reduced power and speed mode to monitor current during SLEEP mode. The current is measured every 12 ms and, if it exceeds a programmable threshold in magnitude, the device quickly transitions back to NORMAL mode. In addition to this check, if the CC1 Current measurement taken at each programmed interval exceeds this threshold, the device will exit SLEEP mode. The device monitors the PACK pin voltage and the top-of-stack voltage at each programmed measurement interval. If the PACK pin voltage is higher than the top-of-stack voltage by more than a programmable delta and the top-of-stack voltage is less than a programmed threshold, the device will exit SLEEP mode. The BQ76952 device also includes a hysteresis on the SLEEP mode entrance, in order to avoid the device quickly entering and exiting SLEEP mode based on a dynamic load. After transitioning to NORMAL mode, the device will not enter SLEEP mode again for a number of seconds given by the hysteresis setting. During SLEEP mode, the DSG FET can be driven either using the charge pump or in source-follower mode, as described in Section 11.4. The CHG FET can be disabled or driven using the charge pump, based on the configuration setting. 13.4 DEEPSLEEP Mode The BQ76952 device integrates a DEEPSLEEP mode, which is a low power mode that allows the REG1 and REG2 LDOs to remain powered, but disables other subsystems. In this mode, the protection FETs are all disabled, so no voltage is provided at the battery pack terminals. All protections are disabled, and all voltage, current, and temperature measurements are disabled. DEEPSLEEP mode can be entered by sending a subcommand over the serial communications interface. The device will exit DEEPSLEEP mode and return to NORMAL mode if directed by a subcommand, or if the RST_SHUT pin is asserted for < 1 second, or if a charger is attached (which is detected by the voltage on the LD pin rising from below VWAKEONLD to exceed it). In addition, if the BAT pin voltage falls below VPORA – VPORA_HYS, the device transitions to SHUTDOWN mode. When the device exits DEEPSLEEP mode, it first completes a full measurement loop and evaluates conditions relative to enabled protections, to ensure that conditions are acceptable to proceed to NORMAL mode. This may take ≈250 ms plus the time for the measurement loop to complete. 52 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 The REG1 and REG2 LDOs will maintain their power state when entering DEEPSLEEP mode based on the configuration setting. The device also provides the ability to keep the LFO running while in DEEPSLEEP mode, which allows for a faster responsiveness to communications and transition back to NORMAL mode, but will consume additional power. Other than sending a subcommand to exit DEEPSLEEP mode, communications with the device over the serial interface will not cause it to exit DEEPSLEEP mode. However, since no measurements are taken while in DEEPSLEEP mode, there is no new information available for readout. 13.5 SHUTDOWN Mode SHUTDOWN mode is the lowest power mode of the BQ76952, which can be used for shipping or long-term storage. In this mode, the device loses all register state information, the internal logic is powered down, the protection FETs are all disabled, so no voltage is provided at the battery pack terminals. All protections are disabled, all voltage, current, and temperature measurements are disabled, and no communications are supported. When the device exits SHUTDOWN, it will boot and read parameters stored in OTP (if that has been written). If the OTP has not been written, the device will power up with default settings, and then settings can be changed by the host writing device registers. Entering SHUTDOWN mode involves a sequence of steps. The sequence can be initiated manually through the serial communications interface. The device can also be configured to enter SHUTDOWN mode automatically based on the top of stack voltage or the minimum cell voltage. If the top-of-stack voltage falls below a programmed stack voltage threshold, or if the minimum cell voltage falls below a programmed cell voltage threshold, the SHUTDOWN mode sequence is automatically initiated. The shutdown based on cell voltage does not apply to cell input pins being used to measure interconnect. While the BQ76952 device is in NORMAL mode or SLEEP mode, the device can also be configured to enter SHUTDOWN mode if the internal temperature measurement exceeds a programmed temperature threshold for a programmed delay. When the SHUTDOWN mode sequence has been initiated by subcommand or the RST_SHUT pin driven high for 1-sec, the device will wait for a delay then disable the protection FETs. After the delay from when the sequence begins, the device will enter SHUTDOWN mode. However, if the voltage on the LD pin is still above the VWAKEONLD level, shutdown will be delayed until the voltage on LD falls below that level. While the device is in SHUTDOWN mode, a ≈5 V voltage is provided at the TS2 pin with high source impedance. If the TS2 pin is pulled low, such as by a switch to VSS, or if a voltage is applied at the LD pin above VWAKEONLD (such as when a charger is attached in series FET configuration), the device will exit SHUTDOWN mode. Note: if a thermistor is attached from the TS2 pin to VSS, this may prevent the device from ever fully entering SHUTDOWN mode. As a countermeasure to avoid an unintentional wake from SHUTDOWN mode when putting the BQ76952 device into long-term storage, the device can be configured to automatically reenter SHUTDOWN mode after a programmed number of minutes. The BQ76952 device performs periodic memory integrity checks and will force a watchdog reset if any corruption is detected. To avoid a cycle of resets in the case of a memory fault, the device will enter SHUTDOWN mode rather than resetting if a memory error is detected within a programmed number of seconds after a watchdog reset has occurred. When the device is wakened from SHUTDOWN, it generally requires approximately 200-300 ms for the internal circuitry to power up, load settings from OTP memory, perform initial measurements, evaluate those relative to enabled protections, then to enable FETs if conditions allow. This can be much longer depending on settings. The BQ76952 device integrates a hardware overtemperature detection circuit, which determines when the die temperature passes an excessive temperature of approximately 120°C. If this detector triggers, the device will automatically begin the sequence to enter SHUTDOWN if this functionality is enabled through configuration. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 53 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 13.6 CONFIG_UPDATE Mode The BQ76952 device uses a special CONFIG_UPDATE mode to make changes to the data memory settings. If changes were made to the data memory settings while the firmware was in normal operation, it could result in an unexpected operation or consequences if settings used by the firmware changed in the midst of operation. When changes to the data memory settings are needed (which generally should only be done on the customer manufacturing line or in an offline condition), the host should put the device into CONFIG_UPDATE mode, modify settings as required, then exit CONFIG_UPDATE mode. See the BQ76952 Technical Reference Manual for more details. When in CONFIG_UPDATE mode, the device stops normal firmware operation and stops all measurements and protection monitoring. The host can then make changes to data memory settings (either writing registers directly into RAM, or instructing the device to program the RAM data into OTP). After changes are complete, the host then exits CONFIG_UPDATE mode, at which point the device restarts normal firmware operation using the new data memory settings. 14 Serial Communications Interface 14.1 Serial Communications Overview The BQ76952 device integrates three serial communication interfaces - an I2C bus, which supports 100 kHz and 400 kHz modes with an optional CRC check, an SPI bus with an optional CRC check, and a single-wire HDQ interface. The BQ76952 device is configured default in I2C mode, while other versions of the device may have a different default configuration (such as the BQ7695201 device, which by default is configured in SPI mode with CRC enabled). The communication mode can be changed by programming either the register or OTP configuration. The customer can program the device's integrated OTP on the manufacturing line to set the desired communications speed and protocol to be used at power up in operation. 14.2 I2C Communications The I2C serial communications interface in the BQ76952 device acts as a responder device and supports rates up to 400 kHz with an optional CRC check. If the OTP is not programmed, the BQ76952 device will initially power up by default in 400 kHz I2C mode, although other versions of the device may initially power up in a different mode (as described in the Device Comparison Table. The OTP setting can be programmed on the manufacturing line, then when the device powers up, it automatically enters the selected mode per OTP setting. The host can also change the I2C speed setting while in CONFIG_UPDATE mode, then the new speed setting takes effect upon exit of CONFIG_UPDATE mode. Alternatively, the host can use the SWAP_TO_I2C() subcommand to change the communications interface to I2C immediately. The I2C device address (as an 8-bit value including responder address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can be changed by configuration setting. The communications interface includes programmable timeout capability. This should only be used if the bus will be operating at 100 kHz or 400 kHz. If this is enabled with the device set to 100-kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than a tTIMEOUT of 25 ms to 35 ms, or if the cumulative clock low responder extend time exceeds ≈25 ms, or if the cumulative clock low controller extend time exceeds 10 ms. If the timeouts are enabled with the device set to 400-kHz mode, then the device will reset the communications interface logic if a clock is detected low longer than tTIMEOUT of 5 ms to 20 ms. The bus also includes a long-term timeout if the SCL pin is detected low for more than 2 seconds, which applies whether or not the timeouts above are enabled. Figure 14-1 shows an I2C write transaction. Block writes are allowed by sending additional data bytes before the Stop. The I2C logic will auto-increment the register address after each data byte. When enabled, the CRC is calculated as follows: • • 54 In a single-byte write transaction, the CRC is calculated over the responder address, register address, and data. In a block write transaction, the CRC for the first data byte is calculated over the responder address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0. When the responder detects an invalid CRC, the I2C responder NACKs the CRC, which causes the I2C responder to go to an idle state. SCL A7 A6 SDA ... A1 R/W ACK Responder Address Start R7 R6 ... R0 ACK D7 D6 Register Address ... D0 C7 C6 ACK ... C0 ACK CRC (optional) Data Stop Figure 14-1. I2C Write Figure 14-2 shows a read transaction using a Repeated Start. SCL A7 A6 SDA Start ... A1 R/W ACK Responder Address R7 R6 ... R0 A7 A6 ACK Register Address ... A1 R/W ACK Responder Address Repeated Start D7 D6 ... D0 ACK Responder Drives Data C7 C6 ... C0 NACK Respsonder Stop Drives CRC (optional) Controller Drives NACK Figure 14-2. I2C Read with Repeated Start Figure 14-3 shows a read transaction where a Repeated Start is not used; for example, if not available in hardware. For a block read, the controller ACKs each data byte except the last and continues to clock the interface. The I2C block auto-increments the register address after each data byte. When enabled, the CRC for a read transaction is calculated as follows: • • In a single-byte read transaction, the CRC is calculated beginning at the first start, so includes the responder address, the register address, then the responder address with a read bit set, then the data byte. In a block read transaction, the CRC for the first data byte is calculated beginning at the first start and will include the responder address, the register address, then the responder address with a read bit set, then the data byte. The CRC resets after each data byte and after each stop. The CRC for subsequent data bytes is calculated over the data byte only. The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0. When the controller detects an invalid CRC, the I2C controller will NACK the CRC, which causes the I2C responder to go to an idle state. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 55 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 SCL ... A1 A7 A6 SDA Start R/W ACK R7 R6 ... R0 Register Address Responder Address A7 A6 ACK R/W ACK Responder Address Stop Start D7 D6 ... A1 ... D0 ACK C7 C6 Responder Drives Data ... C0 NACK Responder Stop Drives CRC (optional) Controller Drives NACK Figure 14-3. I2C Read Without Repeated Start 14.3 SPI Communications The SPI interface in the BQ76952 device operates as a responder-only interface with an optional CRC check. If the OTP has not been programmed, the BQ76952 device initially powers up by default in 400 kHz I2C mode, while other device versions will initially powerup by default in SPI mode with CRC enabled, as described in the Device Comparison Table. The OTP setting to select SPI mode can be programmed into the BQ76952 on the manufacturing line, then when the device powers up, it automatically enters SPI mode. The host can also change the serial communication setting while in CONFIG_UPDATE mode, although the device will not immediately change communication mode upon exit of CONFIG_UPDATE mode to avoid losing communications during evaluation or production. The host can reset the device or write the SWAP_TO_SPI() subcommand to change the communications interface to SPI immediately. The SPI interface logic operates with clock polarity (CPOL) = 0 and clock phase (CPHA) = 0, as shown in the figure below. SPI_CS SPI_SCLK CYCLE # 1 2 3 4 5 6 7 8 SPI_MISO 1 2 3 4 5 6 7 8 SPI_MOSI 1 2 3 4 5 6 7 8 Figure 14-4. SPI with CPOL = 0 and CPHA = 0 The device also includes an optional 8-bit CRC using polynomial x8+x2+x+1. The interface must use 16-bit transactions if CRC is not enabled, and must use 24-bit transactions when CRC is enabled. CRC mode is enabled or disabled based on the setting of Settings:Configuration:Comm Type. Based on configuration settings, the logic will: (a) Only work with CRC, will not accept data without valid CRC, or (b) Only accept transactions without CRC (so the host must only clock 16-bits per transaction, the device will detect an error if more or less clocks are sent). If the host performs a write with CRC and the CRC is not correct, then the incoming data is not transferred to the incoming buffer, and the outgoing buffer (used for the next transaction) is also reset to 0xFFFF. This transaction 56 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 is considered invalid. On the next transaction, the CRC (if clocked out) will be 0xAA, so the 0xFFFFAA will indicate to the controller that a CRC error was detected. The internal oscillator in the BQ76952 device may not be running when the host initiates a transaction (for example, this can occur if the device is in SLEEP mode). If this occurs, the interface will drive out 0xFFFF on SPI_MISO for the first 16-bits clocked out. It will also drive out 0xFF for the third (CRC) byte as well, if CRC is enabled. So the 0xFFFF or 0xFFFFFF will indicate to the controller that the internal oscillator is not ready yet. The device will automatically wake the internal oscillator at a falling edge of SPI_CS, but it may take up to 50 µs to stabilize and be available for use to the SPI interface logic. The address 0x7F used in the device is defined in such a manner that there should be no valid transaction to write 0xFF into this address. Thus the two-byte pattern 0xFFFF should never occur as a valid sequence in the first two bytes of a transaction (that is, it is only used as a flag that something is wrong, similar to an I2C NACK). Due to the delay in the HFO powering up if initially off, the device includes a programmable hysteresis to cause the HFO to stay powered for a programmable number of seconds after it is wakened by a falling edge on SPI_CS. This hysteresis is controlled by the Settings:Configuration:Comm Idle Time configuration setting, which can be set from 0 to 255 seconds (while in SPI mode, the device will use a minimum hysteresis of 1 second even if the value is set to 0). The host can set this to a longer time (up to 255 seconds) and maintain regular communications within this time window, causing the HFO to stay powered, so the device can respond quickly to SPI transactions. However, keeping the HFO running continuously will cause the device to consume additional supply current beyond what it would consume if the HFO were only powered when needed (the HFO draws ≈30 µA when powered). To avoid this extra supply current, the host can send an initial, unnecessary SPI transaction to cause the HFO to waken, and retry this until a valid response is returned on SPI_MISO. At this point, the host can begin sending the intended SPI transactions. If an excessive number of SPI transactions occur over a long period of time, the device may experience a watchdog fault. It is recommended to limit the frequency of SPI transactions by providing 50 μs or more from the end of one transaction to the start of a new transaction. The device includes ability to detect a frozen or disconnected SPI bus condition, and it will then reset the bus logic. This condition is recognized when the SPI_CS is low and the SPI_SCLK is static and not changing for a two second timeout. Depending on the version of the device being used, the SPI_MISO pin may be configured by default to use the REG18 LDO for its output drive, which will result in a 1.8-V signal level. This may cause communications errors if the host processor operates with a higher voltage, such as 3.3 V or 5 V. The SPI_MISO pin can be programmed to instead use the REG1 LDO for its output drive by setting the Settings:Configuration:SPI Configuration[MISO_REG1] data memory configuration bit. This bit should only be set if the REG1 LDO is powered. After this bit has been modified, it is necessary to send the SWAP_TO_SPI() or SWAP_COMM_MODE() subcommands for the device to use the new value. The device includes optional pin filtering on the SPI input pins, which implements a filter with approximately 200 ns delay on each input pin. This filtering is enabled by default but can be disabled by clearing the Settings:Configuration:SPI Configuration[FILT] data memory configuration bit. 14.3.1 SPI Protocol The first byte of a SPI transaction consists of an R/W bit (R = 0, W = 1), followed by a 7-bit address, MSB first. If the controller (host) is writing, then the second byte is the data written. If the controller is reading, then the second byte sent on SPI_MOSI is ignored (except for CRC calculation). If CRC is enabled, then the controller must send as the third byte the 8-bit CRC code, which is calculated over the first two bytes. If the CRC is correct, then the values clocked in will be put into the incoming buffer. If the CRC is not correct, then the outgoing buffer is set to 0xFFFF, and the outgoing CRC is set to 0xAA (these are clocked out on the next transaction). During this transaction, the logic clocks out the contents of the outgoing buffer. If the outgoing buffer was not updated since the last transaction, then the logic will clock out 0xFFFF; and if the CRC is clocked, it will clock out 0x00 for the CRC (if enabled). Thus, the 0xFFFF00 command indicates to the controller that the outgoing buffer Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 57 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 was not updated by the internal logic before the transaction occurred. This can occur when the device did not have sufficient time to update the buffer between consecutive transactions. When the internal logic takes the write-data from the interface logic and processes it, it also causes the R/W bit, address, and data to be copied into the outgoing buffer. On the next transaction, this data is clocked back to the controller. When the controller is initiating a read, the internal logic puts the R/W bit and address into the outgoing buffer, along with the data requested. The interface computes the CRC on the two bytes in the outgoing buffer and clocks that back to the controller if CRC is enabled (with the exceptions associated with 0xFFFF, as noted above). Below are diagrams of three transaction sequences with and without CRC, assuming CPOL = 0. SPI_CS SPI_SCLK SPI_MOSI R/W bit & 7-bit address # 1 8-bit write data # 1 8-bit CRC (for previous two bytes) SPI_MISO Previous R/W bit & 7-bit address Previous 8-bit write or read data 8-bit CRC (for previous two bytes) Figure 14-5. SPI Transaction #1 Using CRC 58 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 SPI_CS SPI_SCLK SPI_MOSI R/W bit & 7-bit address # 2 8-bit write data # 2 (or don’t care if read) 8-bit CRC (for previous two bytes) SPI_MISO R/W bit & 7-bit address # 1 8-bit write data # 1 8-bit CRC (for previous two bytes) Figure 14-6. SPI Transaction #2 Using CRC SPI_CS SPI_SCLK SPI_MOSI R/W bit & 7-bit address # 3 8-bit write data # 3 (or don’t care if read) 8-bit CRC (for previous two bytes) R/W bit & 7-bit address # 2 8-bit write or read data # 2 8-bit CRC (for previous two bytes) SPI_MISO Figure 14-7. SPI Transaction #3 Using CRC Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 59 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 SPI_CS SPI_SCLK SPI_MOSI R/W bit & 7-bit address # 1 8-bit write data # 1 Previous R/W bit & 7-bit address Previous 8-bit write or read data SPI_MISO Figure 14-8. SPI Transaction #1 Without CRC 60 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 SPI_CS SPI_SCLK SPI_MOSI R/W bit & 7-bit address # 2 8-bit write data # 2 (or don’t care if read) R/W bit & 7-bit address # 1 8-bit write data # 1 SPI_MISO Figure 14-9. SPI Transaction #2 Without CRC Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 61 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 SPI_CS SPI_SCLK SPI_MOSI R/W bit & 7-bit address # 3 8-bit write data # 3 (or don’t care if read) R/W bit & 7-bit address # 2 8-bit write or read data # 2 SPI_MISO Figure 14-10. SPI Transaction #3 Without CRC The time required for the device to process commands and subcommands will differ based on the specifics of each. The direct commands generally will complete within 50 μs, while subcommands can take longer, with different subcommands requiring different duration to complete. For example, when a particular subcommand is sent, the device requires approximately 200 μs to load the 32-byte data into the internal subcommand buffer. If the host provides sufficient time for this load to complete before beginning to read the buffer (readback from addresses 0x40 to 0x5F), the device will respond with valid data, rather than 0xFFFF00. When data has already been loaded into the subcommand buffer, this data can be read back with approximately 50 μs interval between SPI transactions. More detail regarding the approximate time duration required for specific commands and subcommands is provided in the BQ76952 Technical Reference Manual (SLUUBY2). The host software should incorporate a scheme to retry transactions that may not be successful. For example, if the device returns 0xFFFFFF on SPI_MISO, then the internal clock was not powered, and the transaction will need to be retried. Similarly, if the device returns 0xFFFFAA on a transaction, this indicates the previous transaction encountered a CRC error, and so the previous transaction must be retried. And as described above, if the device returns 0xFFFF00, then the previous transaction had not completed when the present transaction was sent, which may mean the previous transaction should be retried, or at least needs more time to complete. 14.4 HDQ Communications The HDQ interface is an asynchronous return-to-one protocol where a processor communicates with the BQ76952 device using a single-wire connection to the ALERT pin or the HDQ pin, depending on the configuration. The controller (host device) and the responder (the BQ76952 device) drive the HDQ interface using an open-drain driver with a pullup resistor from the HDQ interface to a supply voltage required on the circuit board. The BQ76952 device can be changed from the default communication mode to HDQ communication mode by setting the Settings:Configuration:Comm Type configuration register or by sending a subcommand (at which point the device switches to HDQ mode immediately). 62 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Note The SWAP_COMM_MODE() subcommand immediately changes the communications interface to that selected by the Comm Type configuration, while the SWAP_TO_HDQ() subcommand immediately changes the interface to HDQ using the ALERT pin. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first. The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit 7). The R/W field directs the device to do one of the following: • • Accept the next 8 bits as data from the host to the device or Output 8 bits of data from the device to the host in response to the 7-bit command. The HDQ peripheral on the BQ76952 device can transmit and receive data as an HDQ responder only. The return-to-one data bit frame of HDQ consists of the following sections: 1. The first section is used to start the transmission by the host sending a Break (the host drives the HDQ interface to a logic-low state for a time t(B)) followed by a Break Recovery (the host releases the HDQ interface for a time t(BR)). 2. The next section is for host command transmission, where the host transmits 8 bits by driving the HDQ interface for 8 T(CYCH) time slots. For each time slot, the HDQ line is driven low for a time T(HW0) (host writing a "0") or T(HW1) (host writing a "1"). The HDQ pin is then released and remains high to complete each T(CYCH) time slot. 3. The next section is for data transmission where the host (if a write was initiated) or device (if a read was initiated) transmits 8 bits by driving the HDQ interface for 8 T(CYCH) (if host is driving) or T(CYCD) (if device is driving) time slots. The HDQ line is driven low for a time T(HW0) (host writing a "0"), T(HW1) (host writing a "1"), T(DW0) (device writing a "0"), or T(DW1) (device writing a "1"). The HDQ pin is then released and remains high to complete the time slot. The HDQ interface does not auto-increment, so a separate transaction must be sent for each byte to be transferred. 15 Cell Balancing 15.1 Cell Balancing Overview The BQ76952 device supports passive cell balancing by bypassing the current of a selected cell during charging or at rest, using either integrated bypass switches between cells, or external bypass FET switches. The device incorporates a voltage-based balancing algorithm which can optionally balance cells autonomously without requiring any interaction with a host processor. Or if preferred, balancing can be entirely controlled manually from a host processor. For autonomous balancing, the device will only balance non-adjacent cells in use (it does not consider inputs used to measure interconnect as cells in use). To avoid excessive power dissipation within the BQ76952 device, the maximum number of cells allowed to balance simultaneously can be limited by configuration setting. For host-controlled balancing, adjacent as well as non-adjacent cells can be balanced. Host-controlled balancing can be controlled using specific subcommands sent by the host. The device also returns status information regarding how long cells have been balanced through subcommands. When host-controlled balancing is initiated using subcommands, the device starts a timer and will continue balancing until the timer reaches a programmed value, or a new balancing subcommand is issued (which resets the timer). This is included as a precaution, in case the host processor initiated balancing but then stopped communication with the BQ76952 device, so that balancing would not continue indefinitely. The BQ76952 device can automatically balance cells using a voltage-based algorithm based on environmental and system conditions. Several settings are provided to control when balancing is allowed, which are described in detail in the BQ76952 Technical Reference Manual. Due to the current that flows into the cell input pins on the BQ76952 device while balancing is active, the measurement of cell voltages and evaluation of cell voltage protections by the device is modified during balancing. Balancing is temporarily disabled during the regular measurement loop while the actively balanced cell is being measured by the ADC, as well as when the cells immediately adjacent to the active cell are being measured. Similarly, balancing on the top cell is disabled while the stack voltage measurement is underway. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 63 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 This occurs on every measurement loop, and so can result in significant reduction in the average balancing current that flows. To help alleviate this, additional configuration bits are provided which cause the device to slow the measurement loop speed when cell balancing is active. The BQ76952 device will insert current-only measurements after each voltage and a temperature scan loop to slow down voltage measurements and thereby increase the average balancing current. The device includes an internal die temperature check, to disable balancing if the die temperature exceeds a programmable threshold. However, the customer should still carefully analyze the thermal effect of the balancing on the device in system. Based on the planned ambient temperature of the device during operation and the thermal properties of the package, the maximum power should be calculated that can be dissipated within the device and still ensure operation remains within the recommended operating temperature range. The cell balancing configuration can then be determined such that the device power remains below this level by limiting the maximum number of cells that can be balanced simultaneously, or by reducing the balancing current of each cell by appropriate selection of the external resistance in series with each cell. 16 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 16.1 Application Information The BQ76952 device can be used with 3-series to 16-series battery packs, supporting a top-of-stack voltage ranging from 5 V up to 80 V. To design and implement a comprehensive set of parameters for a specific battery pack, during development customers can use the Battery Management Studio (BQSTUDIO), which is a graphical user-interface tool installed on a PC. Using BQSTUDIO, the device can be configured for specific application requirements during development once the system parameters, such as fault trigger thresholds for protection, enable or disable of certain features for operation, configuration of cells, and more are known. This results in a "golden image" of settings that can then be programmed into the device registers or OTP memory. 16.2 Typical Applications A simplified application schematic for a 16-series battery pack is shown in Figure 16-1, using the BQ76952 together with an external secondary protector, a host microcontroller, and a communications transceiver. This configuration uses CHG and DSG FETs in series, together with high-side PFET devices used to implement precharge and predischarge functionality. Several points to consider in an implementation are included below: • • • • 64 The external NPN BJT used for the REGIN preregulator can be configured with its collector routed either to the cell battery stack or the middle of the protection FETs. A diode is recommended in the drain circuit of the external NPN BJT, which avoids reverse current flow from the BREG pin through the BJT base to collector in the event of a pack short circuit. This diode can be a Schottky diode if low voltage pack operation is needed, or a conventional diode can be used otherwise. A series diode is recommended at the BAT pin, together with a capacitor from the pin to VSS. These components allow the device to continue operating for a short time when a pack short circuit occurs, which may cause the PACK+ and top-of-stack voltages to drop to approximately 0 V. In this case, the diode prevents the BAT pin from being pulled low with the stack, and the device will continue to operate, drawing current from the capacitor. Generally operation is only required for a short time, until the device detects the short circuit event and disables the DSG FET. A Schottky diode can be used if low voltage pack operation is needed, or a conventional diode can be used otherwise. The diode in the BAT connection and the diode in the BJT collector should not be shared, since then the REG0 circuit might discharge the capacitor on BAT too quickly during a short circuit event. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com • • • • • SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 The recommended voltage range on the VC0 to VC4 pins extends to –0.2 V. This can be used, for example, to measure a differential voltage that extends slightly below ground, such as the voltage across a second sense resistor in parallel with that connected to the SRP and SRN pins. If a system does not use high-side protection FETs, then the PACK pin can be connected through a series 10-kΩ resistor to the top of stack. The LD pin can be connected to VSS. In this case, the LD pin can also be controlled separately, in order to wake the device from SHUTDOWN mode, such as through external circuitry which holds the LD pin at the voltage of VSS while the device stays in SHUTDOWN, and to be driven above a voltage of VWAKEONLD in order to wake from SHUTDOWN. TI recommends using 100 Ω resistors in series with the SRP and SRN pins, and a 100 nF with optional 100 pF differential filter capacitance between the pins for filtering. The routing of these components, together with the sense resistor, to the pins should be minimized and fully symmetric, with all components recommended to stay on the same side of the PCB with the device. Optional 0.1-μF filter capacitors can be added for additional noise filtering at each sense input pin to VSS. Due to thermistors often being attached to cells and possibly needing long wires to connect back to the device, it may be helpful to add a capacitor from the thermistor pin to the device VSS. However, it is important to not use too large of a value of capacitor, since this will affect the settling time when the thermistor is biased and measured periodically. A rule of thumb is to keep the time constant of the circuit < 5% of the measurement time. When Settings:Configuration:Power Config[FASTADC] = 0, the measurement time is approximately 3 ms, and with [FASTADC] = 1 the measurement time is halved to approximately 1.5 ms. When using the 18 kΩ pullup resistor with the thermistor, the time constant will generally be less than (18 kΩ) × C, so a capacitor less than 4 nF is recommended. When using the 180-kΩ pullup resistor, the capacitor should be less than 400 pF. The integrated charge pump generates a voltage on the CP1 capacitor, requiring approximately 60 ms to charge up to approximately 11 V when first enabled, when using the recommended 470 nF capacitor value. When the CHG or DSG drivers are enabled, charge redistribution occurs from the CP1 capacitor to the CHG and DSG capacitive FET loads. This will generally result in a brief drop in the voltage on CP1, which is then replenished by the charge pump. If the FET capacitive loading is large, such that at FET turn-on the voltage on CP1 drops below an acceptable level for the application, then the value of the CP1 capacitor can be increased. This has the drawback of requiring a longer startup time for the voltage on CP1 when the charge pump is first powered on, and so should be evaluated to ensure it is acceptable in the system. For example, if the CHG and DSG FETs are enabled simultaneously and their combined gate capacitance is approximately 400 nF, then changing CP1 to a value of 2200 nF will result in the 11-V charge pump level dropping to approximately 9 V, before being restored to the 11-V level by the charge pump. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 65 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 PCHG SECONDARY PROTECTOR PDSG FUSE FUSE PDSG PCHG PACK+ BREG FUSE PDSG LD PCHG NC DSG CP1 CHG PACK + BAT VC16 5V COMMUNICATIONS TRANSCEIVER COMM + VC15 REGIN + VC14 REG1 + VC13 REG2 VDD VC12 RST_SHUT GPIO : : : : : : : : : : : : : : : : : : COMM TO SYSTEM 3.3V VC11 DDSG DSG Logic Out VC10 DCHG CHG Logic Out MCU VC9 DFETOFF GPIO VC8 CFETOFF GPIO VC7 HDQ VC6 SDA SDA REG18 TS3 TS2 TS1 SRN NC VSS SRP VC0 VC1 INT + ALERT VC2 SCL VC4 VC3 + VC5 SCL GND TS + + TS + PACK- Figure 16-1. BQ76952 16-Series Cell Typical Implementation (Simplified Schematic) A full schematic of a basic monitor circuit based on the BQ76952 for a 16-series battery pack is shown below. Section 18.2 shows the board layout for this design. 66 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 TP1 BAT 16P D1 15P 14P 13P 12P 11P 100V 20 20 20 20 20 C9 220nF R8 20 20 C11 220nF R11 20 C12 220nF R12 5P 4P 3P 2P 1P 1 2 3 4 5 6 20 C14 220nF R13 20 C17 220nF R14 395021006 20 C18 220nF R16 20 C19 220nF R17 20 R18 20 R21 TS1 C21 220nF R19 TP5 20 20 CP1 47 BAT VC16 VC15 VC14 VC13 VC12 VC11 VC10 VC9 VC8 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 C22 220nF RT1 TP6 VSS RT2 CHG 45 NC 44 43 DSG PACK 42 PACK LD 41 LD PCHG 40 PDSG 39 FUSE 38 BREG 37 REGIN 36 REG1 35 REG2 34 SRP RST_SHUT 33 NC DDS G 32 SRN DCHG 31 DFETOFF 30 CFETOFF 29 HDQ 28 SDA SCL ALERT 27 26 25 VSS 17 TS1 TS2 23 TS3 24 REG18 C23 220nF PACK D2 R9 300 LD FUSE FUSE BREG 1 REGIN Q1 FCX495TA C15 C13 1uF VSS C16 22nF R15 1.0k VSS R20 1.0k VSS R22 1.0k REG1 VSS bq76952PFBR VSS 100V DSG 1uF 20 21 CHG REG1 19 22 CHG DSG 18 TP4 C20 220nF t° J3 t° 395021005 46 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C10 220nF R10 CD U1 C8 220nF R7 TP3 C5 0.47uF C7 220nF R6 10P 9P 8P 7P 6P VSS C6 220nF R5 J2 VSS C2 100pF C4 220nF 20 5P 4P 3P 2P 1P 1N C1 1uF C3 220nF R3 R4 1 2 3 4 5 100 R2 395021006 10P 9P 8P 7P 6P R1 2,4 BAT+ 1 2 3 4 5 6 3 TP2 J1 16P 15P 14P 13P 12P 11P Externa l I2C Conne ction VSS R24 10k R23 10k J4 4 3 2 1 TP7 SDA SCL PACK- 1 1 REG18 U2 PGND U3 E1 C24 2.2uF E2 BAT- NT1 Net-Tie TP8 TP9 GND TP10 GND SRP TP11 GND SRN 2 VSS SRN 2 SRP TS2 GND PGND TP12 TP13 TP14 C26 VSS VSS VSS VSS VSS WAKE 100pF C27 J5 1 2 PEC02SAAN 0.1uF R25 100 TP15 BAT- R26 100 R27 10k R28 0.001 VSS PGND Figure 16-2. BQ76952 16-Series Cell Schematic Diagram—Monitor 16P TP16 D4 Red C28 C29 0.1uF 0.1uF FUSE R29 7.5k Q2 R31 10M 7,8 5,6, 1,2,3 7,8 5,6, R32 10M 4 D5 16V Q3 1,2,3 4 R30 7.5k R33 10M D6 16V Q4 R34 0 FUSE TP17 C30 0.1uF D7 16V R35 10k C31 0.1uF PACK+ 4 3 2 TP18 1 E3 R36 5.1k 2 1 3 PACK+ PACK+ PACKPACKOutput R37 5.1k 2 R38 20k 3 J6 Q5 PMV213SN,215 1 4 D8 100V CHG TP19 C32 0.1uF D9 10V R39 5.1k CHG CD PGND PGND R40 7.50k DSG R41 5.1k VSS PACK TP21 TP20 LD TP22 PGND TP23 D10 100V PACK DSG LD R42 R43 5.1k 5.1k R44 R45 5.1k 5.1k Figure 16-3. BQ76952 16-Series Cell Schematic Diagram—Additional Circuitry Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 67 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 16.2.1 Design Requirements (Example) Table 16-1. BQ76952 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Minimum system operating voltage 40 V Cell minimum operating voltage 2.5 V Series cell count 16 Sense resistor 1 mΩ Number of thermistors 3 (using TS1, TS2, and TS3 pins, all for cells) Charge voltage 68 V Maximum charge current 8.0 A Peak discharge current 20.0 A Configuration settings programmed in OTP during customer production Protection subsystem configuration Series FET configuration, device monitors, disables FETs upon fault, recovers autonomously OV protection threshold 4.30 V OV protection delay 500 ms OV protection recovery hysteresis 100 mV UV protection threshold 2.5 V UV protection delay 20 ms UV protection recovery hysteresis 100 mV SCD protection threshold 80 mV (corresponding to a nominal 80 A, based on a 1-mΩ sense resistor) SCD protection delay 50 µs OCD1 protection threshold 68 mV (corresponding to a nominal 68 A, based on a 1-mΩ sense resistor) OCD1 protection delay 10 ms OCD2 protection threshold 56 mV (corresponding to a nominal 56 A, based on a 1-mΩ sense resistor) OCD2 protection delay 80 ms OCD3 protection threshold 28 mV (corresponding to a nominal 28 A, based on a 1-mΩ sense resistor) OCD3 protection delay 160 ms OCC protection threshold 8 mV (corresponding to a nominal 8 A, based on a 1-mΩ sense resistor) OCC protection delay 160 ms OTD protection threshold 60°C OTD protection delay 2s OTC protection threshold 45°C OTC protection delay 2s UTD protection threshold –20°C UTD protection delay 10 s UTC protection threshold 0°C UTC protection delay 5s Host watchdog timeout protection delay 5s CFETOFF pin functionality Use as CFETOFF, polarity = normally high, driven low to disable FET DFETOFF pin functionality Use as DFETOFF, polarity = normally high, driven low to disable FET ALERT pin functionality Use as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise REG1 LDO Usage Use for 3.3-V output Cell balancing Enabled when imbalance exceeds 100 mV 16.2.2 Detailed Design Procedure • 68 Determine the number of series cells. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com • • • SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 – This value depends on the cell chemistry and the load requirements of the system. For example, to support a minimum battery voltage of 40 V using Li-CO2 type cells with a cell minimum voltage of 3 V, there needs to be at least 14-series cells. – For the correct cell connections, see Section 10.1.2. Protection FET selection and configuration – The BQ76952 device is designed for use with high-side NFET protection (low-side protection NFETs can be used by leveraging the DCHG / DDSG signals) – The configuration should be selected for series versus parallel FETs, which may lead to different FET selection for charge versus discharge direction. – These FETs should be rated for the maximum: • Voltage, which should be approximately 5 V (DC) to 10 V (peak) per series cell. • Current, which should be calculated based on both the maximum DC current and the maximum transient current with some margin. • Power Dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the PCB design. – The overdrive level of the BQ76952 device charge pump should be selected based on RDS(ON) requirements for the protection FETs and their voltage handling requirements. If the FETs are selected with a maximum gate-to-source voltage of 15 V, then the 11 V overdrive mode within the BQ76952 device can be used. If the FETs are not specified to withstand this level, or there is a concern over gate leakage current on the FETs, the lower overdrive level of 5.5 V can be selected. Sense resistor selection – The resistance value should be selected to maximize the input range of the coulomb counter but not exceed the absolute maximum ratings, and avoid excessive heat generation within the resistor. • Using the normal maximum charge or discharge current, the sense resistor = 200 mV / 20.0 A = 10 mΩ maximum. • However, considering a short circuit discharge current of 80 A, the recommended maximum SRP, SRN voltage of ≈0.75 V, and the maximum SCD threshold of 500 mV, the sense resistor should be below 500 mV / 80 A= 6.25 mΩ maximum. – Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin should also be considered, so a sense resistor of 1 mΩ is suitable with a 50-ppm temperature coefficient and power rating of 1 W. The REG1 is selected to provide the supply for an external host processor, with output voltage selected for 3.3 V. – The NPN BJT used for the REG0 preregulator should be selected to support the maximum collector-toemitter voltage of the maximum charging voltage of 68 V. The gain of the BJT should be chosen so it can provide the required maximum output current with a base current level that can be provided from the BQ76952 device. – The BJT should support the maximum current expected from the REG1 (maximum of 45 mA, with short circuit current limit of up to ≈80 mA). – A diode can optionally be included in the collector circuit of the BJT, in order to avoid reverse current flow from BREG through the base-collector junction of the BJT to PACK+ during a pack short circuit event. This diode can be seen in Figure 16-2 at D2. – A large resistor (such as 10 MΩ) is recommended from BREG to VSS, to avoid any unintended leakage current that may occur during SHUTDOWN mode. 16.2.3 Application Performance Plot The error in measured temperature using an external Semitec 103-AT thermistor, the default temperature polynomial, and the internal 18-kΩ pullup resistor is shown in Figure 16-4. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 69 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Measurements taken using Semitec 103-AT thermistor, default temperature polynomial, and 18-kΩ internal pullup resistor. Figure 16-4. Thermistor Temperature Error 16.2.4 Calibration Process The BQ76952 device enables customers to calibrate the current, voltage, and temperature measurements on the customer production line. Detailed procedures are included in the BQ76952 Technical Reference Manual. The device provides the capability to calibrate individual cell voltage measurements, stack voltage, PACK pin voltage, LD pin voltage, current measurement, and individual temperature measurements. 16.3 Random Cell Connection Support The BQ76952 device supports a random connection sequence of cells to the device during pack manufacturing. For example, cell-10 in a 16-cell stack might be first connected at the input terminals leading to pins VC10 and VC9, then cell-4 may next be connected at the input terminals leading to pins VC4 and VC3, and so on. It is not necessary to connect the negative terminal of cell-1 first at VC0. As another example, consider a cell stack that is already assembled and cells already interconnected to each other, then the stack is connected to the PCB through a connector, which is plugged or soldered to the PCB. In this case, the sequence order in which the connections are made to the PCB can be random in time, they do not need to be controlled in a certain sequence. There are, however, some restrictions to how the cells are connected during manufacturing: • To avoid misunderstanding, note that the cells in a stack cannot be randomly connected to any VC pin on the device, such as the lowest cell (cell-1) connected to VC15, while the top cell (cell-16) is connected to VC4, and so on. It is important that the cells in the stack be connected in ascending pin order, with the lowest cell (cell-1) connected between VC1 and VC0, the next higher voltage cell (cell-2) connected between VC2 and VC1, and so on. • The random cell connection support is possible due to high voltage tolerance on pins VC1–VC16. Note VC0 has a lower voltage tolerance. This is because VC0 should be connected through the seriescell input resistor to the VSS pin on the PCB, before any cells are attached to the PCB. Thus, the VC0 pin voltage is expected to remain close to the VSS pin voltage during cell attach. If VC0 is not connected through the series resistor to VSS on the PCB, then cells cannot be connected in random sequence. • 70 Each of the VC1–VC16 pins includes a diode between the pin and the adjacent lower cell input pin (that is, between VC16 and VC15, between VC9 and VC8, and so on), which is reverse biased in normal operation. This means an upper cell input pin should not be driven to a low voltage while a lower cell input pin is driven to a higher voltage, since this would forward bias these diodes. During cell attach, the cell input terminals Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 should generally be floating before they are connected to the appropriate cell. It is expected that transient current will flow briefly when each cell is attached, but the cell voltages will quickly stabilize to a state without DC current flowing through the diodes. However, if a large capacitance is included between a cell input pin and another terminal (such as VSS or another cell input pin), the transient current may become excessive and lead to device heating. Therefore, it is recommended to limit capacitances applied at each cell input pin to the values recommended in the specifications. 16.4 Startup Timing At initial power up of the BQ76952 device from a SHUTDOWN state, the device progresses through a sequence of events before entering NORMAL mode operation. These are described below for an example configuration, with approximate timing shown for the cases when [FASTADC] = 0 and [FASTADC] = 1. Note When the device is configured for autonomous FET control (that is, [FET_EN] = 1), the decision to enable FETs is only evaluated every 250 ms while in NORMAL mode, which is why the FETs are not enabled until approximately 280 ms after the wakeup event, even though the data was available earlier. Table 16-2. Startup Sequence and Timing Step Comment FASTADC Setting Time (relative to wakeup event) Wakeup event Either the TS2 pin is pulled low, or the LD pin is pulled up, triggering the device to exit SHUTDOWN mode. 0, 1 0 REG1 powered This was measured with the OTP programmed to autonomously power the REG1 LDO. 0, 1 20 ms INITSTART asserted This was measured with the OTP programmed to provide the INITSTART bit in the Alarm signal on the ALERT pin. 0, 1 23 ms 0 88 ms INITCOMP and ADSCAN asserted This was measured with the OTP programmed to provide the INITCOMP and ADSCAN bits in the Alarm signal on the ALERT pin. 1 58 ms 0 221 ms FULLSCAN asserted This was measured with the OTP programmed to provide the FULLSCAN bit in the Alarm signal on the ALERT pin. 1 129 ms This was measured with the OTP programmed to autonomously enable FETs. 0 282 ms FETs enabled 1 284 ms Figure 16-5 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP with [FASTADC] = 1, [FET_EN] = 1 for autonomous FET control, setup to use three thermistors, and providing the [INITCOMP] flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 71 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 16-5. Startup Sequence Using [FASTADC] = 1, with the [INITCOMP] Flag Displayed on the ALERT Pin 16.5 FET Driver Turn-Off The high-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective FET. The CHG driver includes an internal switch which discharges the CHG pin toward the BAT pin level. The DSG FET driver will discharge the DSG pin toward the LD pin level, but it includes a more complex structure than just a switch, to support a faster turn off. When the DSG driver is triggered to turn off, the device will initially begin discharging the DSG pin toward VSS. However, since the PACK+ terminal may not fall to a voltage near VSS quickly, the DSG FET gate should not be driven significantly below PACK+, otherwise the DSG FET may be damaged due to excessive negative gate-source voltage. Thus, the device monitors the voltage on the LD pin (which is connected to PACK+ through an external series resistor) and will stop the discharge when the DSG pin voltage drops below the LD pin voltage. When the discharge has stopped, the DSG pin voltage may relax back above the LD pin voltage, at which point the device will again discharge the DSG pin toward VSS, until the DSG gate voltage again falls below the LD pin voltage. This repeats in a series of pulses which over time discharge the DSG gate to the voltage of the LD pin. This pulsing continues for approximately 100 to 200 μs, after which the driver remains in a high impedance state if within approximately 500 mV of the voltage of the LD pin. The external resistor between the DSG gate and source then discharges the remaining FET VGS voltage so the FET remains off. The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the turn-off transient. A low resistance (such as 100 Ω) will provide a fast turn-off during a short circuit event, but this may result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value (such as 1 kΩ or 4.7 kΩ) will reduce this speed and the corresponding inductive spike level. Oscilloscope captures of DSG driver turn-off are shown below, with the DSG pin driving the gate of a CSD19536KCS NFET, which has a typical Ciss of 9250 pF. Figure 16-6 shows the signals when using a 1-kΩ series gate resistor between the DSG pin and the FET gate, and a light load on PACK+, such that the voltage on PACK+ drops slowly as the FET is disabled. The pulsing on the DSG pin can be seen lasting for approximately 170 μs. 72 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 16-6. Moderate Speed DSG FET Turn-Off, Using a 1-kΩ Series Gate Resistor, and a Light Load on PACK+. A zoomed-in version of the pulsing generated by the DSG pin is shown in Figure 16-7, this time with PACK+ shorted to the top of stack. Figure 16-7. Zoomed-In View of the Pulsing on the DSG Pin During FET Turn-Off A slower turn-off case is shown in Figure 16-8, using a 4.7-kΩ series gate resistor, and the PACK+ connector shorted to the top of stack. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 73 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 16-8. A Slower Turn-Off Case Using a 4.7-kΩ Series Gate Resistor, and the PACK+ Connector Shorted to the Top of the Stack A fast turn-off case is shown in Figure 16-9, in which a 100-Ω series gate resistor is used between the DSG pin and the FET gate. Figure 16-9. A Fast Turn-Off Case with a 100-Ω Series Gate Resistor 16.6 Unused Pins Some device pins may not be needed in a particular application. The manner in which each should be terminated in this case is described below. 74 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table 16-3. Terminating Unused Pins Pin Name Recommendation 1–16, 48 VC0–VC16 Cell inputs 1, 2, and 16 should always be connected to actual cells, with cells connected between VC1 and VC0, VC2 and VC1, and VC16 and VC15. VC0 should be connected through a resistor and capacitor on the pcb to pin 17 (VSS). Pins related to unused cells (which may be cell 3–cell 15, pins 1–13) can be connected to the cell stack to measure interconnect resistance or provide a Kelvin-connection to actual cells, in which case they should include a series resistor and parallel capacitor, in similar fashion to pins connected to actual cells (see Usage of VC Pins for Cells Versus Interconnect). Another option is to short unused VC pins directly to an adjacent VC pin. All VC pins should be connected to either an adjacent VC pin, an actual cell (through R and C) or stack interconnect resistance (through R and C). 18, 20 SRP, SRN If not used, these pins should be connected to pin 17 (VSS). 19, 44 NC 21, 23, 25, 28, 29, 30, 31, 32 TS1, TS3, ALERT, HDQ, If not used, these pins can be left floating or connected to pin 17 (VSS). Any of these pins (except for TS1 and CFETOFF, TS3) may be configured with the internal weak pulldown resistance enabled during operation, although this is DFETOFF, not necessary. DCHG, DDSG 22 TS2 33 RST_SHUT 34, 35 These pins are not connected to silicon. They can be left floating or connected to an adjacent pin or connected to VSS. If the device is intended to enter SHUTDOWN mode, the TS2 pin should be left floating. If SHUTDOWN mode will not be used in the application, and the TS2 pin will not be used for a thermistor or ADCIN measurement, the TS2 pin can be left floating or connected to pin 17 (VSS). If not used, this pin should be connected to pin 17 (VSS). REG1, REG2 If not used, these pins can be left floating or connected to pin 17 (VSS). 36 REGIN If not used, this pin should be connected to pin 17 (VSS). 37 BREG If this pin is not used and pin 36 (REGIN) is also not used, both pins should be connected to pin 17 (VSS). If this pin is not used but pin 36 is used (such as driven from an external source), then this pin should be connected to pin 36 (REGIN). 38 FUSE If not used, this pin can be left floating or connected to pin 17 (VSS). 39 PDSG If not used, this pin should be left floating. 40 PCHG If not used, this pin should be left floating. 41 LD 43 DSG If not used, this pin should be left floating. 45 CHG If not used, this pin should be left floating. If the DSG driver will not be used, this pin can be connected through a series resistor to the PACK+ connector, or can be connected to pin 17 (VSS). If not used, this pin should be connected to pin 47 (BAT). 46 CP1 Note If the charge pump is enabled with CP1 connected to BAT, the device will consume an additional ≈200 µA. 17 Power Supply Requirements The BQ76952 device draws its supply current from the BAT pin, which is typically connected to the top of stack point through a series diode, to protect against any fault within the device resulting in unintended charging of the pack. A series resistor and capacitor is included to lowpass filter fast variations on the stack voltage. During a short circuit event, the stack voltage may be momentarily pulled to a very low voltage before the protection FETs are disabled. In this case, the charge on the BAT pin capacitor will temporarily support the BQ76952 device's supply current, to avoid the device losing power. 18 Layout 18.1 Layout Guidelines • The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short- Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 75 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 • • • • circuit ranges of the BQ76952 device. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩ sense resistor. In reference to the system circuitry, the following features require attention for component placement and layout: Differential Low-Pass Filter, and I2C communication. The BQ76952 device uses an integrating delta-sigma ADC for current measurements. For best performance, 100-Ω resistors should be included from the sense resistor terminals to the SRP and SRN inputs of the device, with a 0.1-μF filter capacitor placed across the SRP and SRN pins. Optional 0.1-µF filter capacitors can be added for additional noise filtering at each sense input pin to ground. All filter components should be placed as close as possible to the device, rather than close to the sense resistor, and the traces from the sense resistor routed in parallel to the filter circuit. A ground plane can also be included around the filter network to add additional noise immunity. The BQ76952 device internal REG18 LDO requires an external decoupling capacitor, which should be placed as close to the REG18 pin as possible, with minimized trace inductance, and connected to a ground plane electrically connected to VSS. The I2C clock and data pins have integrated ESD protection circuits; however, adding a Zener diode and series resistor on each pin provides more robust ESD performance. 18.2 Layout Example An example circuit layout using the BQ76952 device in a 16-series cell design is described below. The design implements the schematic shown in Figure 16-2 and Figure 16-3, and uses a 2.75-inch × 3.9-inch 2-layer circuit card assembly, with cell connections on the left edge, and pack connections along the top edge of the board. Wide trace areas are used, reducing voltage drops on the high current paths. The board layout, which is shown in Figure 18-1 and Figure 18-2, includes spark gaps with the reference designator prefix E. These spark gaps are fabricated with the board and no component is installed. 76 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 18-1. BQ76952 Two-Layer Board Layout–Top Layer Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 77 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Figure 18-2. BQ76952 Two-Layer Board Layout–Bottom Layer 78 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 19 Device and Documentation Support 19.1 Documentation Support For additional information, see the following related documents: • BQ76952 Technical Reference Manual • BQ76952 Evaluation Module User's Guide • Using Low-Side FETs with the BQ769x2 Battery Monitor Family • Cell Balancing with BQ769x2 Battery Monitors • Multiple FETs with the BQ769x2 Battery Monitors • BQ769x2 Software Development Guide • BQ769x2 Calibration and OTP Programming Guide • Pin Equivalent Diagrams for the BQ76952, BQ76942, and BQ769142 • BQ76952 High Voltage Stress Report Additional documents can be found in the product folder at BQ76952 Technical documentation. 19.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 19.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 19.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 19.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 20 Mechanical, Packaging, Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 79 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ7695201PFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7695201 BQ7695202PFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7695202 BQ7695203PFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7695203 BQ7695204PFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ7695204 BQ76952PFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ76952 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of