BQ76PL536APAPT

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 bq76PL536A 3-to-6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for Applications 1 Features 3 Description • • • The bq76PL536A device is a stackable battery monitor and protector for three-to-six lithium-ion cells in series. The bq76PL536A integrates an analog front end (AFE) along with a precision analog-to-digital converter (ADC), used to precisely measure battery cell voltages. A separate ADC is used to measure temperature. (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic PACK+ SPI FAULT CONTROL (North) SPI (North) CELL_6 GPAI AUX CBx (6) CELL_1 CONTROL (South) CONV Uninterruptible Power Systems (UPS) E-Bike and E-Scooter Large-Format Battery Systems REG50 ••• CELL_2-5 ••• bq76PL536A GPIO 2 Applications CONTROL (North) SPI (South) SPI (North) CELL_6 GPAI bq76PL536A GPIO AUX CONV HOST INTERFACE • • • ALERT TO NEXT DEVICE DRDY FAULT ALERT SPI CBx (6) ••• CELL_2-5 ••• • BODY SIZE (NOM) 10.00 mm × 10.00 mm SPI • PACKAGE HTQFP (64) ALERT • PART NUMBER bq76PL536A DRDY • Device Information(1) FAULT • Cell stacks of 192 cells can be supported by stacked bq76PL536A devices. A high-speed SPI interface connects all devices. CONV • In addition to temperature measurement, overvoltage and undervoltage are monitored per channel for protection. Non-volatile memory stores the userprogrammable protection thresholds and delay times. A FAULT output signals whenever one of these thresholds is exceeded. HO S T I NT ERF ACE (n o t u sed ) • • DRDY • • 3-to-6 Series Cell Support, All Chemistries Hot-Pluggable High-Speed Serial Peripheral Interface (SPI) for Data Communications Stackable Vertical Interface Isolation Components not Required Between Devices Industrial Temperature Range –40°C to 85°C High-Accuracy Analog-to-Digital Converter (ADC): – ±1 mV Typical Accuracy – 14-Bit Resolution, 6-µs Conversion Time – Nine ADC Inputs: 6 Cell Voltages, 1 Six-Cell Brick Voltage, 2 Temperatures, 1 GeneralPurpose Input – Dedicated Pins for Synchronizing Measurements Configuration Data Stored in Error Check/Correct (ECC)-One-Time-Programmable (OTP) Registers Built-In Comparators (Secondary Protector) for: – Overvoltage and Undervoltage Protection – Overtemperature Protection – Programmable Thresholds and Delay Times – Dedicated Fault Output Signals Cell Balancing Control Outputs With Safety Timeout – Balance Current Set by External Components Supply Voltage Range from 6 V to 30 V Continuous and 36-V Peak Low Power: – Typical 12-µA Sleep, 45-µA Idle Integrated Precision 5-V, 3-mA LDO HO S T I NT ERF ACE 1 CELL_1 South Interface (not used on bottom device) PACK- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 1 1 1 2 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics........................................... 8 Timing Characteristics – AC SPI Data Interface..... 12 Vertical Communications Bus ................................. 13 Typical Characteristics ............................................ 14 Detailed Description ............................................ 16 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 34 7.5 Programming........................................................... 35 7.6 Register Maps ......................................................... 37 8 Application and Implementation ........................ 54 8.1 Application Information............................................ 54 8.2 Typical Application ................................................. 55 8.3 Other Schematics.................................................... 58 9 Power Supply Recommendations...................... 63 9.1 Power Supply Decoupling ....................................... 63 10 Layout................................................................... 63 10.1 Layout Guidelines ................................................. 63 10.2 Layout Example .................................................... 65 11 Device and Documentation Support ................. 66 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 66 66 66 66 66 12 Mechanical, Packaging, and Orderable Information ........................................................... 66 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2016) to Revision C Page • Changed condition statement from "VBAT = 20 V" to "VBAT = 22 V" in Recommended Operating Conditions, Electrical Characteristics and , Timing Characteristics – AC SPI Data Interface tables........................................................................ 7 • Changed condition statement from "VBAT = 7.2 V to 30 V" to "VBAT = 7.2 V to 27 V" in Recommended Operating Conditions............................................................................................................................................................................... 7 • Added Receiving Notification of Documentation Updates section ....................................................................................... 66 Changes from Revision A (August 2012) to Revision B Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 • Changed description to be more concise .............................................................................................................................. 1 • Listed values and removed VCn to VCn-1 row ..................................................................................................................... 6 • Changed top two labels with bottom two labels for this row .................................................................................................. 7 • Deleted FUNCTION_CONFG[ADCTx]=00 and table note: "ADC specifications valid when device is programmed for 6-µs conversion time per channel, FUNC_CONFIG[ADCT1:0] = 01b" from ADC COMMON SPECIFICATIONS in Eletrical Characteristics section.............................................................................................................................................. 9 • Deleted table note: "ADC is factory trimmed at the conversion speed of ~6 µs/channel (FUNC_CONFIG[ADCT1:0] = 01b). Use of a different conversion-speed setting may affect measurement accuracy" from Cn (CELL) INPUTS in Eletrical Characteristics section............................................................................................................................................ 10 • Changed title to DELAY TIMES............................................................................................................................................ 11 • Changed units in equations to match unit in corresponding row ........................................................................................ 11 • Changed name from VC0 to VSS ....................................................................................................................................... 17 • Added CONV_H pin is not used........................................................................................................................................... 20 • Added TNOM table note ...................................................................................................................................................... 25 • Changed warning to caution ................................................................................................................................................ 28 2 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 • Changed text to warning ...................................................................................................................................................... 29 • Changed text to caution and added SLEEP State in text..................................................................................................... 34 • Changed TS1(2) to TS1:TS2 throughout document............................................................................................................. 35 • Deleted ADC Conversion Timing table................................................................................................................................. 50 • Changed anti-aliasing filter for VC6–VC1............................................................................................................................. 54 • Changed note wording for LDODx ....................................................................................................................................... 63 Changes from Original (June 2011) to Revision A • Page Changed the pinout image to remove the device number and package type........................................................................ 4 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 3 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 5 Pin Configuration and Functions TEST VSSD NC51 SDI_N CS_N SCLK_N SDO_N ALERT_N FAULT_N DRDY_N TS± CONV_N NC62 TS2+ BAT2 BAT1 PAP Package 64-Pin HTQFP Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VC6 1 48 GPAI+ CB6 2 47 GPAI± VC5 3 46 LDOD2 CB5 4 45 GPIO VC4 5 44 HSEL CB4 6 43 CS_H VC3 7 42 SDI_H CB3 8 41 SDO_H VC2 9 40 SCLK_H CB2 10 39 FAULT_H VC1 11 38 ALERT_H CB1 12 37 DRDY_H VC0 13 36 CONV_H VSS 14 35 VSS AGND 15 34 VSS VREF 16 33 VSS REG50 AUX NC30 CS_S SDI_S SDO_S SCLK_S VSSD FAULT_S ALERT_S DRDY_S CONV_S TS1± TS1+ LDOA LDOD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Functions PIN NAME NO. TYPE(1) DESCRIPTION AGND 15 AI Internal analog VREF (–) ALERT_H 38 O Host-to-device interface – ALERT condition detected in this or higher (North) device ALERT_N 57 I Current-mode input indicating a system status change from the next-higher bq76PL536A ALERT_S 23 OD AUX 31 O Switched current-limited output from REG50 BAT1 63 P Power-supply voltage, connect to most-positive cell +, tie to BAT2 on PCB BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB CB1 12 O Cell-balance control output 1 CB2 10 O Cell-balance control output 2 CB3 8 O Cell-balance control output 3 CB4 6 O Cell-balance control output 4 CB5 4 O Cell-balance control output 5 CB6 2 O Cell-balance control output 6 4 Current-mode output indicating a system status change to the next lower bq76PL536A Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Pin Functions (continued) PIN NAME NO. TYPE(1) DESCRIPTION Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal sink to VSS. CONV_H 36 I CONV_N 59 OD CONV_S 21 I Input from the adjacent lower bq76PL536A to initiate a conversion CS_H 43 I Host-to-device interface – active-low chip select from host. Internal 100-kΩ pullup resistor CS_N 52 OD Current-mode output used to select the next-higher bq76PL536A for SPI communication CS_S 29 I Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536A DRDY_H 37 O Host-to-device interface – conversion complete, data-ready indication DRDY_N 58 I Current-mode input indicating conversion data is ready from next-higher bq76PL536A DRDY_S 22 OD FAULT_H 39 O Host-to-device interface – FAULT condition detected in this or higher (North) device FAULT_N 56 I Current-mode input indicating a system status change from the next-higher bq76PL536A FAULT_S 24 OD Current-mode output GPAI+ 48 AI General-purpose (differential) analog input, connect to VSS if unused. GPAI– 47 AI General-purpose (differential) analog input, connect to VSS if unused. GPIO 45 IOD HSEL 44 I Host interface enable, 0 = enable, 1 = disable LDOA 17 P Internal analog 5-V LDO bypass connection, requires 2.2-µF ceramic capacitor for stability LDOD1 18 P Internal digital 5-V LDO bypass connection 1, requires 2.2-µF ceramic capacitor for stability. This pin is tied internally to LDOD2. This pin should be tied to LDOD2 externally. LDOD2 46 P Internal digital 5-V LDO bypass connection 2, requires 2.2-µF ceramic capacitor for stability. This pin is tied internally to LDOD1. This pin should be tied to LDOD1 externally. NC30 30 – No connection NC51 51 – No connection NC62 62 – No connection REG50 32 P 5-V user LDO output, requires 2.2-µF ceramic capacitor for stability SCLK_H 40 I Host-to-device interface – SPI clock from host SCLK_N 55 OD Current-mode output SPI clock to the next-higher bq76PL536A SCLK_S 26 I Current-mode input SPI clock from the next-lower bq76PL536A SDI_H 42 I Host-to-device interface – data from host to device (host MOSI signal) SDI_N 53 OD Current-mode output for SPI data to the next-higher bq76PL536A SDI_S 28 I Current-mode input for SPI data from the next-lower bq76PL536A SDO_H 41 O Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA internal pullup SDO_N 54 I Current-mode input for SPI data from the next-lower bq76PL536A SDO_S 27 OD Current-mode output for SPI data to the next-lower bq76PL536A TEST 50 I TS1+ 20 AI Differential temperature sensor input TS1– 19 AI Differential temperature sensor input TS2+ 61 AI Differential temperature sensor input TS2– 60 AI Differential temperature sensor input VC0 13 AI Sense-voltage input terminal for negative terminal of first cell (VSS) VC1 11 AI Sense voltage input terminal for positive terminal of the first cell VC2 9 AI Sense voltage input terminal for the positive terminal of the second cell VC3 7 AI Sense voltage input terminal for the positive terminal of the third cell VC4 5 AI Sense voltage input terminal for the positive terminal of the fourth cell VC5 3 AI Sense voltage input terminal for the positive terminal of the fifth cell Current-mode output to the next-higher bq76PL536A to initiate a conversion Current-mode output indicating conversion data is ready to the next lower bq76PL536A Digital open-drain I/O. A 10-kΩ to 2-MΩ pullup is recommended. Factory test pin. Connect to VSS in user circuitry. This pin includes an approximately100kΩ internal pulldown Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 5 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Pin Functions (continued) PIN NAME TYPE(1) NO. DESCRIPTION VC6 1 AI Sense voltage input terminal for the positive terminal of the sixth cell VREF 16 P Internal analog voltage reference (+), requires 10-µF, low-ESR ceramic capacitor to AGND for stability 14, 33, 34, 35 P VSS 25, 49 P VSS – – Thermal pad on bottom of PowerPAD™ package; this must be soldered to similar-size copper area on PCB and connected to VSS, to meet stated specifications herein. Provides heat-sinking to part. VSS VSSD Thermal pad (1) Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VMAX (1) MIN MAX UNIT –0.3 36 V –0.3 36 V VC1, VC2, VC3, VC4, VC5, VC6 –0.3 36 VC0 –0.3 2 TS1+, TS1–, TS2+, TS2– –0.3 6 GPAI –0.3 6 BAT1 (2) BAT voltage to any other pin BAT to any pin Input voltage, VIN GPIO –0.3 VREG50 + 0.3 VBAT – 1 VBAT + 2 CONV_S, SDI_S, SCLK_S, CS_S –2 1 CONV_N, SDI_N, SCLK_N, CS_N –0.3 36 DRDY_S, SDO_S, FAULT_S, ALERT_S –0.3 5 GPIO –0.3 VREG50 + 0.3 CB1…CB6 (CBREF = 0x00) –0.3 36 REG50, AUX –0.3 DRDY_N, SDO_N, FAULT_N, ALERT_N Output voltage, VO (1) (2) V 6 Junction temperature, TJ Storage temperature, Tstg V –65 150 °C 50 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to VSS of this device except where otherwise noted. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 6 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000 ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 6.3 Recommended Operating Conditions Typical values stated where TA = 25ºC and VBAT = 22 V, Min/Max values stated where TA = –40˚C to 85ºC and VBAT = 7.2 V to 27 V (unless otherwise noted) MIN VBAT Supply voltage BAT VCn–VC(n – 1) (1) 27 1 4.5 0 2.5 GPIO 0 VREG50 VC(n – 1) VCn 0 VREG50/2 TS1+, TS1–, TS2+, TS2– Input voltage Non-top IC in stack: DRDY_N, SDO_N, FAULT_N, ALERT_N V V BAT Non-bottom IC in stack: CONV_S, SDI_S, SCLK_S, CS_S –1 Bottom IC in stack: CONV_S, SDI_S, SCLK_S, CS_S VSS Non-bottom IC in stack: DRDY_S, SDO_S, FAULT_S, ALERT_S Output voltage UNIT BAT + 1 Top IC in stack: DRDY_N, SDO_N, FAULT_N, ALERT_N VO MAX GPAI CBn (1) VI NOM 7.2 1 Bottom IC in stack: DRDY_S, SDO_S, FAULT_S, ALERT_S VSS Non-top IC in stack: CONV_N, SDI_N, SCLK_N, CS_N BAT – 1 V Top IC in stack: CONV_N, SDI_N, SCLK_N, CS_N BAT CREG50 External capacitor REG50 pin 2.2 CVREF External capacitor VREF pin 9.2 15 µF CLDO External capacitor LDOx pin 2.2 3.3 µF TOPR Operating temperature (2) –40 85 °C (1) (2) µF 10 n = 1 to 6 Device specifications stated within this range. 6.4 Thermal Information bq76PL536A THERMAL METRIC (1) PAP (HTQFP) UNIT 64 PINS RθJA Junction-to-ambient thermal resistance 24.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10 °C/W RθJB Junction-to-board thermal resistance 8.1 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 7 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 6.5 Electrical Characteristics Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 1 12 20 µA ICCPROTECT Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 0 45 60 µA ICCBALANCE Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, or AUX; No DC load at CBx; CB_CTRL ≠ 0; CBT_CONTROL ≠ 0; CONV_H = 0 (not converting) , IO_CTRL[SLEEP] = 0 46 60 µA ICCCONVERT Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx or CBx; CONV_S = 1 (conversion active) , IO_CTRL[SLEEP] = 0 10.5 15 mA ICCTSD Supply current Thermal shutdown activated; ALERT_STATUS[TSD] = 1 ICCSLEEP 1.6 mA REG50, INTEGRATED 5-V LDO VREG50 Output voltage IREG50OUT ≤ 0.5 mA, C = 2.2 μF to 22 μF ΔVREG50LINE Line regulation 6 V ≤ BAT ≤ 27 V, IREG50OUT = 2 mA 5 5.1 V 10 25 mV 0.2 mA ≤ IREG50OUT ≤ 2 mA 15 0.2 mA ≤ IREG50OUT ≤ 5 mA 25 ΔVREG50LOAD Load regulation IREG50MAX Current limit IAUXMAX Maximum load AUX pin AUX output I = 1 mA, max. capacitance = VREG50 Capacitor: CVAUX ≤ CVREG50 / 10 RAUX 4.9 12 25 mV 35 mA 5 mA 50 Ω 1800 µA LEVEL SHIFT INTERFACE INTX1 North 1 transmitter current SCLK_N, CS_N, SDI_N, CONV_N INTX0 North 0 transmitter current CS_N, CONV_N 1 µA INTX0A North 0 transmitter current SCLK_N, SDI_N (BASE device CS_H = 1) 1 µA INTX0B North 0 transmitter current SCLK_N, SDI_N (BASE device CS_H = 0) ISRX South 1 receiver threshold ISRXH 1000 1350 50 75 110 µA SCLK_S, CS_S, SDI_S, CONV_S 430 550 680 µA South receiver hysteresis SCLK_S, CS_S, SDI_S, CONV_S 50 100 200 µA ISTX1 South 1 transmitter current ALERT_N, FAULT_S, DRDY_S 800 1100 1400 µA ISTX0 South 0 transmitter current ALERT_S, FAULT_S, DRDY_S 1 µA ISTX0B South 0 transmitter current SDO_S (BASE device CS_H = 0) INRX North 1 receiver threshold INRXH North receiver hysteresis CIN Input capacitance 8 1 4 7 µA SDO_N, ALERT_N, FAULT_N, DRDY_N 420 580 720 µA SDO_N, ALERT_N, FAULT_N, DRDY_N 50 100 200 µA 15 Submit Documentation Feedback pF Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Electrical Characteristics (continued) Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT HOST INTERFACE VOH Logic-level output voltage, high; SDO_H, FAULT_H, ALERT_H, DRDY CL = 20 pF, IOH < 5 mA (1) 4.5 VLDOD V VOL Logic-level output voltage, low; SDO_H, FAULT_H, ALERT_H, DRDY CL = 20 pF, IOL < 5 mA (1) VSS 0.5 V VIH Logic-level input voltage, high; SCLK_H, SDI_H, CS_H, CONV 2 5.2 V VIL Logic-level input voltage, low; SCLK_H, SDI_H, CS_H, CONV VSS 0.8 V CIN Input capacitance SCLK_H, SDI_H, CS_H, CONV ILKG Input leakage current SCLK_H, SDI_H, CS_H, CONV 5 pF 1 µA GENERAL PURPOSE INPUT/OUTPUT (GPIO) VIH Logic-level input voltage, Vin ≤ VREG50 high VIL Logic-level input voltage, low VOH Output high-voltage pullup voltage Supplied by external approximately100-kΩ resistor VOL Logic-level output voltage, low IOL = 1 mA CIN Input capacitance(1) ILKG Input leakage current 2 V 0.8 V VREG50 V 0.3 V 5 pF 1 µA 120 kΩ VCn V 6.6 µs CELL BALANCING CONTROL OUTPUT (CBx) CBz Output impedance VRANGE Output V 1 V < VCELL < 5 V 80 100 VCn-1 ADC COMMON SPECIFICATIONS ADC_CONTROL[ADC_ON] = 1 tCONV_START CONV high to conversion start (2) tCONV Conversion time per selected channel (4) ADC_CONTROL[ADC_ON] = 1 ILKG Input leakage current Not converting (3) 5.4 ADC_CONTROL[ADC_ON] = 0 6 500 5.4 µs 6 6.6 µs 4.5 –70 0 70 mV VUVR UV detection threshold range (7) 3300 mV ΔVUVS UV detection threshold program step 100 mV VUVH UV detection hysteresis 100 mV VUVA UV detection threshold accuracy VOTR OT detection threshold range (8) ΔVOTS OT detection threshold program step (8) VOTA OT detection threshold accuracy (8) T = 40°C to 90°C ΔVOTH OT reset hysteresis T = 40°C to 90°C 2 700 –100 VREG50 = 5 V 0 1 2 See 8% 100 (9) mV V V 0.04 0.05 12% 15% V BATTERY PROTECTION DELAY TIMES tOV OV detection delay-time range ΔtOV OV detection delay-time step tUV UV detection delay-time range ΔtUV UV detection delay-time step tOT OT detection delay-time range ΔtOT OT detection delay-time step tacr OV, UV, and OT detection delay-time accuracy (10) CUVT, (COVT) ≥ 500 µs t(DETECT) Protection comparator detection time VOT or VOV or VUV threshold exceeded by 10 mV (7) (8) (9) (10) 0 3200 ms COVT [µs] = 0 100 µs COVT [ms] = 1 100 ms 0 3200 ms CUVT[7] (µs) = 0 100 µs CUVT[7] (ms) = 1 100 ms 0 2550 10 –12% 0% ms ms 10% 100 µs COV and CUV thresholds must be set such that COV – CUV ≥ 300 mV. Using recommended components. Consult Table 2 in text for voltage levels used. See Table 2 for trip points. Under double or multiple fault conditions (of a single type), the second or greater fault may have its delay time shortened by up to the step time for the fault. For example, the second and subsequent COV faults occurring within the delay time period for the first fault may have their delay time shortened by up to 100 µs. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 11 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Electrical Characteristics (continued) Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP 6.75 7 MAX UNIT OTP EPROM PROGRAMMING CHARACTERISTICS VPROG Programming voltage VBAT ≥ 20 V tPROG Programming time VBAT ≥ 20 V IPROG Programming current VBAT ≥ 20 V 7.25 (11) 10 V 50 ms 20 mA (11) The write pulse is self-timed internally. VPROG should be applied for this time at a minimum. 6.6 Timing Characteristics – AC SPI Data Interface Typical values stated where TA = 25°C and VBAT = 22 V, Min/Max values stated where TA = –40˚C to 85°C and VBAT = 7.2 V to 27 V (unless otherwise noted), see Figure 1. PARAMETER TEST CONDITION MIN NOM MAX UNIT 10 250 1000 kHz fSCLK SCLK frequency (1) SCLKDC SCLK_H duty cycle, t(HIGH) / t(SCLK) or t(LOW) / t(SCLK) tCS,LEAD CS_H lead time, CS_H low to clock 50 SCLK/2 tCS,LAG CS_H lag time. Last clock to CS_H high 10 SCLK/2 tCS,DLY CS_H high to CS_H low (inter-packet delay requirement) tACC CS_H access time (2): CS_H low to SDO_H data out 125 250 ns tDIS CS_H disable time (2): CS_H high to SDO_H high impedance 2.5 2.7 µs tSU,SDI SDI_H input-data setup time 15 ns tHD,SDI SDI_H input-data hold time 10 ns tVALID,SDO SDO_H output-data valid time SCLK_H edge to SDO_H valid (1) (2) 12 40% 60% ns ns 3 CL ≤ 20 pF µs 75 110 ns Maximum SCLK frequency is limited by the number of bq76PL536A devices in the vertical stack. The maximum listed here may not be realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing, and so forth. See text for details. Time listed is for single device. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 6.7 Vertical Communications Bus Typical values stated where TA = 25ºC and VBAT = 20 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tHV_SCLK Propagation delay, SCLK_H to SCLK_N HOST = 0 40 ns tVB_SCLK Propagation delay, SCLK_S to SCLK_N HOST = 1 30 ns tHV_CS Propagation delay, CS_H to CS_N HOST = 0 40 ns tVB_CS Propagation delay, CS_S to CS_N HOST = 1 30 ns tHV_SDI Propagation delay, SDI_H to SDI_N HOST = 0 40 ns tVB_SDI Propagation delay, SDI_S to SDI_N HOST = 1 30 ns tHV_CONV Propagation delay, CONV_H to CONV_N HOST = 0 100 ns tVB_CONV Propagation delay, CONV_S to CONV_N HOST = 1 30 ns tHV_SDO Propagation delay, SDO_N to SDO_H HOST = 0 10 ns tVB_SDO Propagation delay, SDO_N to SDO_S HOST = 1 40 ns tHV_DRDY Propagation delay, DRDY_N to DRDY_H HOST = 0 60 ns tVB_DRDY Propagation delay, DRDY_N to DRDY_S HOST = 1 40 ns tHV_FAULT Propagation delay, FAULT_N to FAULT_H HOST = 0 55 ns tVB_FAULT Propagation delay, FAULT_N to FAULT_S HOST = 1 30 ns tHV_ALERT Propagation delay, ALERT_N to ALERT_H HOST = 0 65 ns tVB_ALERT Propagation delay, ALERT_N to ALERT_S HOST = 1 30 ns (1) Typical values are quoted in place of MIN/MAX for design guidance only. Actual propagation delay depends heavily on wiring and capacitance in the signal path. These parameters are not tested in production due to these dependencies on system design considerations. t CS, LEAD t CS,LAG CS t(SCLK ) t CS _ DLY SCLK t(HIGH) t(LOW) tSU,SDI tHD,SDI SDI tACC tVALID, SDO tDIS SDO Figure 1. SPI Host Interface Timing Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 13 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 6.8 Typical Characteristics 0.004 0.004 40qC 25qC 105qC 0.002 0.001 0 -0.001 -0.002 0.002 0.001 0 -0.001 -0.002 -0.003 -50 -25 0 25 50 75 Temperature (qC) 100 125 -0.003 -50 150 Figure 2. Total Channel Accuracy (V) for VCELL1 25 50 Temperature (qC) 75 100 125 D006 Figure 3. Total Channel Accuracy (V) for VCELL2 0.0045 40qC 25qC 105qC 0.003 VACC (V) for VCELL4 0.002 VACC (V) for VCELL3 0 VBAT = 27 V 0.003 0.001 0 -0.001 40qC 25qC 105qC 0.0015 0 -0.0015 -0.002 -0.003 -50 -25 0 25 50 Temperature (qC) 75 100 -0.003 -50 125 Figure 4. Total Channel Accuracy (V) for VCELL3 25 50 Temperature (qC) 75 100 125 D008 Figure 5. Total Channel Accuracy (V) for VCELL4 0.003 40qC 25qC 105qC 40qC 25qC 105qC VACC (V) for VCELL6 0.002 0.0015 0 -0.0015 -0.003 -50 0 VBAT = 27 V 0.0045 0.003 -25 D007 VBAT = 27 V VACC (V) for VCELL5 -25 D005 VBAT = 27 V 0.001 0 -0.001 -0.002 -25 0 25 50 Temperature (qC) 75 100 125 -0.003 -50 -25 D009 VBAT = 27 V 0 25 50 Temperature (qC) 75 100 125 D010 VBAT = 27 V Figure 6. Total Channel Accuracy (V) for VCELL5 14 40qC 25qC 105qC 0.003 VACC (V) for VCELL2 VACC (V) for VCELL1 0.003 Figure 7. Total Channel Accuracy (V) for VCELL6 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Typical Characteristics (continued) 0.045 0.03 5.1 40qC 25qC 105qC 40qC 25qC 105qC 5.05 VREG50 (V) VBAT (V) 0.015 0 -0.015 -0.03 5 4.95 -0.045 -0.06 -50 -25 0 25 50 Temperature (qC) 75 100 4.9 -50 125 -25 Figure 8. VBAT at 27 V MIN AVG MAX 100 125 D012 MIN AVG MAX 15 Output Current (PA) Output Current (PA) 75 Figure 9. REG50 Output Voltage 14 13 12 11 14 13 12 11 10 10 9 -40 25 50 Temperature (qC) 16 16 15 0 D011 9 -20 0 20 40 60 Temperature (DC) 80 100 110 8 -40 -20 0 D002 Figure 10. IBAT_Sleep at 7.2 V 20 40 60 Temperature (qC) 80 100 110 D004 D001 Figure 11. IBAT_Sleep at 27 V 120000 40qC 25qC 105qC CBZ (: 115000 110000 105000 100000 -50 -25 0 25 50 Temperature (qC) 75 100 125 D013 Figure 12. Cell Balancing Pin Impedance Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 15 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The bq76PL536A (Functional Block Diagram) is a 3-to-6 series Lithium-ion battery monitor, secondary protector and analog front end (AFE) that can be stacked vertically to monitor up to 192 cells without the need for additional isolation components between ICs. This device incorporates a precision analog-to-digital converter (ADC); independent cell voltage and temperature protection; cell balancing, and precision 5-V regulator to power user circuitry. The bq76PL536A additionally provides full (secondary) protection for overvoltage, undervoltage, and overtemperature conditions. CONV_N LDOD LDO-A LDO-D VBAT LDOA REG50 AUX 7.2 Functional Block Diagram TS2+ OT1 1.25V REF2 DRDY_N FAULT _N LEVELSHIFTED NORTH COMM’s INTERFACE ALERT_N CS_N SCLK_N TS2– 5V LDO (User Circuitry) TS1+ OT2 TS1– THERMAL SHUTDOWN OV VC6 UV SDI_N CB6 EPROM OV SDO_N VC5 REGISTERS CONV_H UV DRDY_H SDI_H DIGITAL CONTROL LOGIC SDO_H CONV_S 2.5V DRDY_S FAULT _S ALERT_S CS_S SCLK_S VREF LEVELSHIFTED SOUTH COMM’s INTERFACE + - OV CELL BALANCING 14 bit ADC LEVEL SHIFT AND MUX CS_H SCLK_H ULTRA-PRECISION BANDGAP ALERT_H CB5 HOST INTERFACE FAULT _H UV OV UV OV VC4 CB4 VC3 CB3 VC2 UV CB2 OV VC1 UV CB1 SDI_S OSC SDO_S VC0 VSS VSS GPAI– GPAI+ AGND VREF DIGITAL VSSD ANALOG GPIO REF2 PROTECTOR COMMUNICATIONS POWER Figure 13. bq76PL536A Block Diagram 16 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.3 Feature Description 7.3.1 Analog-to-Digital Conversion (ADC) 7.3.1.1 General Features The integrated 14-bit (unsigned) high-speed successive approximation register (SAR) analog-to-digital converter uses an integrated band-gap reference voltage (VREF) for the cell and brick measurements. The ADC has a frontend multiplexer for nine inputs – six cells, two temperature sensors, and one general-purpose analog input (GPAI). The GPAI input can further be multiplexed to measure the brick voltage between the BATx pin and VSS or the voltage between the GPAI+ and GPAI– pins. The ADC and reference are factory trimmed to compensate for gain, offset, and temperature-induced errors for all inputs. The measurement result is not allowed to roll over due to offset error at the top and bottom of the range. For example, a reading near zero does not underflow to 0x03ff due to offset error, and vice-versa. The converter returns 14 valid unsigned magnitude bits in the following format: Each word is returned in big-endian format in a register pair consisting of two adjacent 8-bit registers. The MSB of the word is located in the lower-address register of the pair, that is, data for cell 1 is returned in registers 0x03 and 0x04 as 00xxxxxx xxxxxxxxb. 7.3.1.2 3-to-6 Series Cell Configuration When fewer than 6 cells are used, the most-positive cell voltage of the series string should be connected to the BAT1/BAT2 pins, through the RC input network shown in the Typical Application section. Unused VCx inputs should be connected to the next VCx input down until an input connected to a cell is reached – that is, in a four cell stack, VC6 connects to VC5, which connects to VC4 (Figure 14). The internal multiplexer control can be set to scan only the inputs which are connected to cells, thereby speeding up conversions slightly. The multiplexer is controlled by the ADC_CONTROL[CN2:0] bits. 63 BAT 0.1 mF 1 kW 1 kW 1 kW 0.1 mF 1 kW 0.1 mF 1 kW 0.1 mF 16 VREF AGND 15 VSS 14 VC0 13 CB1 12 VC1 11 CB2 10 VC2 9 CB3 8 VC3 7 CB4 6 VC4 5 CB5 4 VC5 3 CB6 2 1 0.1 mF VC6 64 BAT 10 mF 1 kW Figure 14. Connecting < 6 Cells (4 Shown) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 17 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Feature Description (continued) 7.3.1.3 Cell Voltage Measurements Use the following formula (all values are in decimal) to convert the returned cell measurement value to a dc voltage (in mV). mV = (REGMSB × 256 + REGLSB) × 6250 / 16383 (1) Example: Cell_1 == 3.35 V (3350 mV); After conversion, REG_03 == 0x22; REG_04 == 0x4d 0x22 × 0x100 + 0x4d = 0x224d (8781.) 8781 × 6250 / 16,383 = 3349.89 mV ≈ 3.35 V 7.3.1.4 GPAI or VBAT Measurements The bq76PL536A features a differential input to the ADC from two external pins, GPAI+ and GPAI–. The ADC GPAI result register can be configured (via the FUNCTION_CONFIG[GPAI_SRC] to provide a measurement of the voltage on these two pins, or of the brick voltage present between the BATx pins and VC0. In the bq76PL536A device, the VBAT measurement is taken from the BATx pin to the VC0 pin, and is a separate input to the ADC mux. Because this is a separate input to the ADC, certain common system faults, such as a broken cell wire, can be easily detected using the bq76PL536A and simple firmware techniques. The GPAI measurement can be configured to use one of two references via FUNCTION_CONFIG[GPAI_REF]. Either the internal bandgap (VREF) or REG50 can be selected. When REG50 is selected, the ADC returns a ratio of the voltage at the inputs and REG50, removing the need for compensation of the REG50 voltage accuracy or drift when used as a source to excite the sensor. When the device is configured to measure VBAT (FUNCTION_CONFIG[GPAI_SRC] = 1), the device selects VREF automatically and ignores the FUNCTION_CONFIG[GPAI_REF] setting. 7.3.1.4.1 Converting GPAI Result to Voltage To convert the returned GPAI measurement value to a voltage using the internal band-gap reference (FUNCTION_CONFIG[GPAI_REF] = 1), the following formula is used. mV = (REGMSB × 256 + REGLSB) × 2500 / 16,383 • FUNCTION_CONFIG = 0100 xxxxb (2) Example: The voltage connected to the GPAI inputs == 1.25 V; After conversion, REG_01 == 0x20; REG_02 == 0x00 0x20 × 0x100 + 0x00 = 0x2000 (8192.) 8192 × 2500 / 16,383 = 1250 mV 7.3.1.4.2 Converting VBAT Result to Voltage To convert the returned VBAT measurement value to a voltage, the following formula is used. V = (REGMSB × 256 + REGLSB) × 33.333 / 214 (33.333 ≈ 6.25 / 0.1875) • FUNCTION_CONFIG = 0101 xxxxb (3) Example: The sum of the series cells connected to VC6–VC0 == 20.295 V; After conversion, REG_01 == 0x26; REG_02 == 0xf7 0x26 × 0x100 + 0xf7 = 0x26f7 (9975.) 9975 × 33.333 / 16,383 = 20.295 V 18 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Feature Description (continued) 7.3.1.5 Temperature Measurement The bq76PL536A can measure the voltage TS1+, TS1– and TS2+, TS2– differential inputs using the ADC. An external thermistor or resistor divider network typically drives these inputs. The TSn inputs use the REG50 output divided down and internally connected as the ADC reference during conversions. This produces a ratiometric result and eliminates the need for compensation or correction of the REG50 voltage drift when used to drive the temperature sensors. The REG50 reference allows an approximate 2.5-V full-scale input at the TSn inputs. The final reading is limited between 0 and 16383, corresponding to an external ratio of 0 to 0.5. Two control bits are required for the ADC to convert the TSn input voltages successfully. ADC_CONTROL[TSn] is set to cause the ADC to convert the TSn channel on the next requested conversion cycle. IO_CONTROL[TSn] is set to cause the FET switch connecting the TSn– input to VSS to close, completing the circuit of the voltage divider. The IO_CONTROL bits should only be set as needed to conserve power; at high temperatures, thermistor excitation current may be relatively high. 7.3.1.5.1 External Temperature Sensor Support (TS1+, TS1–, TS2+, and TS2–) The device is intended for use with a nominal 10 kΩ at 25ºC NTC external thermistor (AT103 equivalent) such as the Panasonic ERT-J1VG103FA, a 1% device. A suitable external resistor-capacitor network should be connected to position the response of the thermistor within the range of interest. This is typically RT= 1.47 kΩ and RB = 1.82 kΩ (1%) as shown in Figure 15. A parallel bypass capacitor in the range 1 nF to 47 nF placed across the thermistor should be added to reduce noise coupled into the measurement system. The response time delay created by this network should be considered when enabling the respective TS input prior to conversion and setting the OT delay timer. See Figure 15 for details. REG50 RTH 47 nF RT RB = 0.4 (RTH@40C – RTH@90C) TS+ RT = RTH@ 40C – 2RTH @90C – RB RB TS– Figure 15. Thermistor Connection 7.3.1.5.2 Converting TSn Result to Voltage (Ratio) To convert the returned TSn measurement value to a ratio, RTS = VTS:REG50, the following formulas are used. The setting FUNCTION_CONFIG = 0100 xxxxb is assumed. Note that the offset and gain correction are slightly different for each channel. ADC behavior: COUNT = (VTSn / REG50 × scalar) – OFFSET TS1: RTS1 = ((TEMPERATURE1_H × 256 + TEMPERATURE1_L) + 2) / 33,046 (4) (5) Example: The voltage connected to the TS1 inputs (TS1+ – TS1–) == 0.661 V; VREG50 ≈ 5 V nominal After conversion, REGMSB == 0x11; REGLSB == 0x16 ACTUAL_COUNT = 0x11 × 0x100 + 0x16 = 0x1116 (4374.) (4374 + 2) / 33,046 = 0.1324 (ratio of TSn inputs to REG50) 0.1324 × REG50 = 0.662 V Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 19 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Feature Description (continued) 7.3.1.6 ADC Band-Gap Voltage Reference The ADC and protection subsystems use separate and independent internal voltage references. The ADC band gap (VREF) is nominally 2.5 V. The reference is temperature-compensated and stable. The internal reference is brought out to the VREF pin for bypassing. A high quality 10-μF capacitor should be connected between the VREF and AGND pins, in very close physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on signal quality. The AGND pin should be connected to VSS. Device VSS connections should be brought to a single point close to the IC to minimize layout-induced errors. The device tab should also be connected to this point, and is a convenient common VSS location. The internal VREF should not be used externally to the device by user circuits. 7.3.1.7 Conversion Control 7.3.1.7.1 Convert Start Two methods are available to start a conversion cycle. The CONV_H pin may be asserted, or firmware may set the CONVERT_CTRL[CONV] bit. 7.3.1.7.1.1 Hardware Start A single interface pin (CONV_H) is used for conversion-start control by the host. A conversion cycle is started by a hardware signal when CONV_H is transitioned low-to-high by the host. The host should hold this state until the conversion cycle is complete to avoid erroneous edges causing a conversion start when the present conversion is not complete. The signal is simultaneously sent to the higher device in the stack by the assertion of the CONV_N signal. The bq76PL536A automatically sequences through the series of measurements enabled via the ADC_CONTROL register after a convert-start signal is received from either the register bit or the hardware pin. If the CONV_H pin is not used in the design, this pin must be maintained in a default low state (approximately 0 V) to allow use of the ADC_CONVERT[CONV] bit to trigger ADC conversions. If the CONV pin is kept high, the ADC_CONVERT[CONV] bit does not function, and device current consumption is increased by the signaling current, approximately 900 µA. If the CONV_H pin is not used by the user’s design, the pin may be left floating; the internal current sink to VSS maintains proper bias. 7.3.1.7.1.2 Firmware Start The CONVERT_CTRL[CONV] bit is also used to initiate a conversion by writing a 1 to the bit, which automatically resets at the end of a conversion cycle. The bit may only be written to 1; the IC always resets the bit to 0. The BROADCAST form of the packet is recommended to start all device conversions simultaneously. NOTE Designer Note: The external CONV_H (CONV_S) pin must be held in the de-asserted (=0) state to allow the CONV register bit to initiate conversions. An internal pulldown is provided on the pin to maintain this state. 20 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Feature Description (continued) 7.3.1.7.2 Data Ready The bq76PL536A signals that data is ready when the last conversion data has been stored to the associated data result register by asserting the DRDY_S pin (DRDY_H if HOST = 0) if the DRDY_N pin is also asserted (Figure 16). DRDY_S (DRDY_H) signals are cleared on the next conversion start. I-to-V Conversion V-to-I Conversion DRDY_N DRDY_S CONVERT_END S SET Q R CLR Q DRDY_H CONVERT_START DEVICE_STATUS[DRDY] Figure 16. Data-Ready Logic 7.3.1.7.3 ADC Channel Selection The ADC_CONTROL register can be configured as follows: Table 1. ADC_CONTROL Register Configuration MEASUREMENT ADC_CONTROL VCELL1 CELL_SEL = 0x00 VCELL1, VCELL2 CELL_SEL = 0x01 VCELL1, VCELL2, VCELL3 CELL_SEL = 0x02 VCELL1, VCELL2, VCELL3, VCELL4 CELL_SEL = 0x03 VCELL1, VCELL2, VCELL3, VCELL4, VCELL5 CELL_SEL = 0x04 VCELL1, VCELL2, VCELL3, VCELL4, VCELL5, VCELL6 CELL_SEL = 0x05 External thermistor input 1 TS1 = 1 External thermistor input 2 TS2 = 1 General-purpose analog input GPAI = 1 7.3.1.7.4 Conversion Time Control The ADC conversion time is fixed at approximately 6 µs per converted channel, plus 6 µs overhead at the start of the conversion. Total conversion time (µs) is approximately 6 × num_channels + 6. 7.3.1.7.5 Automatic Versus Manual Control The ADC_CONTROL[ADC_ON] bit controls powering up the ADC section and the main bandgap reference. If the bit is set to 1, the internal circuits are powered on, and current consumption by the part increases. Conversions begin immediately on command. The host CPU should wait >500 µs before initiating the first conversion after setting this bit. If the ADC_ON bit is false, an additional 500 µs is required to stabilize the reference before conversions begin. If the sampling interval (time between conversions) used is less than approximately 10 ms, manual mode should be selected to avoid shifting the voltage reference, leading to inaccuracy in the measurements. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 21 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.3.1.8 Secondary Protection The bq76PL536A integrates dedicated overvoltage and undervoltage fault detection for each cell and two overtemperature fault detection inputs for each device. The protection circuits use a separate band-gap reference from the ADC system and operate independently. The protector also uses separate I/O pins from the main communications bus, and therefore is capable of signaling faults in hardware without intervention from the host CPU. 7.3.1.8.1 Protector Functionality When a fault state is detected, the respective fault flag in the FAULT_STATUS or ALERT_STATUS registers is set. All flags in the FAULT and ALERT registers are then ORed into the DEVICE_STATUS FAULT and ALERT bits. The FAULT and ALERT bits in DEVICE_STATUS in turn cause the hardware FAULT_S or ALERT_S pin to be set. The bits in DEVICE_STATUS and the hardware pins are latched until reset by the host via SPI command, ensuring that the host CPU does not miss an event. A separate timer is provided for each fault source (cell overvoltage, cell undervoltage, overtemperature) to prevent false alarms. Each timer is programmable from 100 µs to more than 3 s. The timers may also be disabled, which causes fault conditions to be sensed immediately and not latched. The clearing of the FAULT or ALERT flag (and pin) occurs when the respective flag is written to a 1, which also restarts the respective fault timer. This also clears the FAULT_S (_H) or ALERT_S (_H) pin. If the actual fault remains present, the FAULT (ALERT) pin is again asserted at the expiration of the timer. This cycle repeats until the cause of the fault is removed. On exit from the SLEEP state, the COV, CUV, and OT fault comparators are disabled for approximately 200 µs to allow internal circuitry to stabilize and prevent false error condition detection. 7.3.1.8.1.1 Using the Protector Functions With 3-5 Cells The OV/UV condition can be ignored for unused channels by setting the FUNCTION_CONFIG[CNx] bits to the maximum number of cells connected to the device. If fewer than 6 cells are configured, the corresponding OV/UV faults are ignored. For example, if the FUNCTION_CONFIG bits are set to xxxx 1000, then the OV/UV comparators are disabled for cells 5 and 6. Correct setting of this register prevents spurious false alarms. 22 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.3.1.9 Cell Overvoltage Fault Detection (COV) When the voltage across a cell exceeds the programmed COV threshold for a period of time greater than set in the COV timer (COVT), the COV_FAULT flag for that cell is set (Figure 17). The bits in COV_FAULT are then ORed into the FAULT[COV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H) pin also to be asserted. The COV flag is latched unless COVT is programmed to 0, in which case the flag follows the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT flag, first remove the source of the fault (for example, the overvoltage condition) and then write a 1 to FAULT[COV], followed by a 0 to FAULT[COV]. See Figure 17 for details. The voltage trip point is set in the CONFIG_COV register. Set points are spaced every 50 mV. Hysteresis is provided to avoid chatter of the fault sensing. The filter delay time is set in the CONFIG_COVT register to prevent false alarms. A start-up deglitch circuit is applied to the timers to prevent false triggering. The deglitch time is 0–50 µs, and introduces a small error in the timing for short times. For both COVT and CUVT, this can cause an error greater than the 10% maximum specified for delays 5t, the time delay introduced by the RC network comprising CF, RTH, RT, and RB, to avoid false triggering of the PROTECTOR function and ALERT signal when the TS1 and/or TS2 bits are set to 1 and the inputs enabled. On exit from the SLEEP state, the OT fault comparators are disabled for approximately 200 µs to allow internal circuitry to stabilize and prevent false error-condition detection. 7.3.1.12 Fault and Alert Behavior When the FAULT_N pin is asserted by the next higher bq76PL536A in the stack, then the FAULT_S is also asserted, thereby passing the signal down the array of stacked devices if they are present. FAULT_N should always be connected to the FAULT_S of the next higher device in the stack. If no higher device exists, it should be tied to VBAT of this bq76PL536A, either directly or via a pullup resistor from approximately 10 kΩ to 1 MΩ. The FAULT_x pins are active-high and current flows when asserted. The ALERT_x pins behave in a similar manner. If the FAULT_N pin of the base device (HSEL = 0) becomes asserted, it asserts its FAULT_H signal to the host microcontroller. This signal chain may be used to create an interrupt to the CPU, or drive other compatible logic or I/O directly. See Table 3 for further details. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 25 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Table 3. Fault Detection Summary SIGNALING FAULT DETECTION PIN HSEL = 1 HSEL = 0 DEVICE_STATUS BIT SET X_STATUS BIT SET EPROM double bit error ECC logic fault detected FAULT_S FAULT_H FAULT FAULT_STATUS[I_FAULT] FORCE User set FORCE bit FAULT_S FAULT_H FAULT FAULT_STATUS[FORCE] POR Power-on reset occurred FAULT_S FAULT_H FAULT FAULT_STATUS[POR] CRC (1) CRC fail on received packet FAULT_S FAULT_H FAULT FAULT_STATUS[CRC] CUV VCx < VUV for tUV FAULT_S FAULT_H FAULT FAULT_STATUS[CUV] COV VCx > VOV for tOV FAULT_S FAULT_H FAULT FAULT_STATUS[COV] AR Address ≠ (0x01→ 0x3e) ALERT_S ALERT_H ALERT ALERT_STATUS[AR] Protected-register parity error Parity not even in protected register ALERT_S ALERT_H ALERT ALERT_STATUS[PARITY] EPROM single-bit error ECC logic fault detected and corrected ALERT_S ALERT_H ALERT ALERT_STATUS[ECC_COR] FORCE User set FORCE bit ALERT_S ALERT_H ALERT ALERT_STATUS[FORCE] Thermal shutdown Die temperature ≥ TSDTHRESHOLD ALERT_S ALERT_H ALERT ALERT_STATUS[TSD] SLEEP IC exited SLEEP mode ALERT_S ALERT_H ALERT ALERT_STATUS[SLEEP] OT2 VTS2 > VOT for tOT ALERT_S ALERT_H ALERT ALERT_STATUS[OT2] OT1 VTS1 > VOT for tOT ALERT_S ALERT_H ALERT ALERT_STATUS[OT1] (1) The CRC fault may be prevented from setting the FAULT pin by setting IO_CONFIG[7] = 1. The FAULT_STATUS[CRC] bit is still set when CRC error is detected, but the FAULT pin remains de-asserted. 7.3.1.12.1 Fault Recovery Procedure When any error flag in DEVICE_STATUS, FAULT_STATUS, or ALERT_STATUS is set and latched, the state can only be cleared by host communication via SPI. Writing to the respective FAULT_STATUS or ALERT_STATUS register bit with a 1 clears the latch for that bit. The exceptions are the two FORCE bits, which are cleared by writing a 0 to the bit. The FAULT_STATUS and ALERT_STATUS register bits are read-only, with the exception of the FORCE bit, which may be directly written to either a 1 or 0. 7.3.1.13 Secondary Protector Built-In Self-Test Features The secondary protector functions have built-in test for verifying the connections through the signal chain of ICs in the stack back to the host CPU. This verifies the wiring, connections, and signal path through the ICs by forcing a current through the signal path. To implement this feature, host firmware should set the FAULT[FORCE] or ALERT[FORCE] bit in the top-most device in the stack. The device asserts the associated pin on the South interface, and it propagates down the stack, back to the base device. The base device in turn asserts the FAULT_H (ALERT_H) pin to the host, allowing the host to check for the received signal and thereby verify correct operation. 7.3.2 Cell Balancing The bq76PL536A has six dedicated outputs (CB1…CB6) that can be used to control external N-FETs as part of a cell balancing system. The implementation of appropriate algorithms is controlled by the system host. The CB_CTRL[CBAL1–6] bits control the state of each of the outputs. The outputs are copied from the bit state of the CB_CTRL register, that is, a 1 in this register activates the external balance FET by placing a high on the associated pin. The CBx pins switch between approximately the positive and negative voltages of the cell across which the external FET is connected. This allows the use of a small, low-cost N-FET in series with a power resistor to provide cell balancing. 26 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.3.2.1 Cell Balance Control Safety Timer The CBx outputs are cleared when the internal safety timer expires. The internal safety timer (CB_TIME) value is programmed in units of seconds or minutes (range set by CB_CTRL bit 7) with an accuracy of ±10%. The timer begins when any CB_CTRL bit changes from 0 to 1. The timer is reset if all CB_CTRL bits are modified by the host from 1 to 0, or by expiration of the timing period. The timing begins counting the programmed period from start each time the CB_CTRL register is programmed from a zero to a non-zero value in the lower six bits. In the example, if the CB_TIME is set for 30 s, then one or more bits are set in the CB_CTRL register to balance the corresponding cells; then after 10 s the user firmware sets CB_CTRL to 0x00, takes a measurement and then reprograms CB_CTRL with the same or new bit pattern and the timer begins counting 30 s again before expiring and disabling balancing. This restart occurs each time the CB_CTRL bits are set to a non-zero value. If this is done at a greater rate than the balancing period for which timer CB_TIME is set, balancing is effectively never disabled – until the timer is either allowed to expire without changing the CB_CTRL register to a non-zero value, or the CB_CTRL register is set to zero by the user firmware. If the CB_CTRL register is not manipulated from zero to non-zero while the timer is running, the timer expires as expected. Alterations of the value from a non-zero to a different non-zero value do not restart the timer (such as, from 0x02 to 0x03, and so forth). While the timer is running, the host may set or reset any bit in the CB_CTRL register at any time, and the CBx output follows the bit. The host may re-program the timer at any time. The timer must always be programmed to allow the CBx outputs to be asserted. While the timer is non-zero, the CB_CTRL settings are reflected at the outputs. During periods when the timer is actively running (not expired), then DEVICE_STATUS[CBT] is set. 7.3.3 Other Features and Functions 7.3.3.1 Internal Voltage Regulators The bq76PL536A derives power from the BAT pin using several internal low dropout (LDO) voltage regulators. There are separate LDOs for internal analog circuits (5 V at LDOA), digital circuits (5 V at LDOD1 and LDOD2), and external, user circuits (5 V at REG50). The BAT pin should be connected to the most-positive cell input from cell 3, 4, 5, or 6, depending on the number of cells connected. Locate filter capacitors as close to the IC as possible. The internal LDOs and internal VREF should not be used to power external circuitry, with the exception that LDODx should be used to source power to any external pullup resistors. 7.3.3.1.1 Internal 5-V Analog Supply The internal analog supply should be bypassed at the LDOA pin with a good-quality, low-ESR, 2.2-μF ceramic capacitor. 7.3.3.1.2 Internal 5-V Digital Supply The internal digital supply should be bypassed at the LDOD1(2) pin with a good-quality, low-ESR, 2.2-μF ceramic capacitor. The two pins are connected internally and provided to enhance single-pin failure-mode fault tolerance. They should also be connected together externally. NOTE Designer Note: Because the LDODx inputs are pulled briefly to approximately 7 V during programming, the LDODx pins should not be used as sources for pullups to 5-V digital pins, such as HSEL and SPI(bus)_H connected pins. Use VREG50 instead, unless all programming is completed prior to mounting on the application PCB, in which case LDODx is a good choice. 7.3.3.1.3 Low-Dropout Regulator (REG50) The bq76PL536A has a low-dropout (LDO) regulator provided to power the thermistors and other external circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-μF capacitor is required for stable operation. The output is internally current-limited. The output is reduced to near zero if excess current is drawn, causing die temperatures to rise to unacceptable levels. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 27 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com The 2.2-µF output capacitor is required whether REG50 is used in the design or not. REG50 is disabled in SLEEP mode, and may be turned off under thermal-shutdown conditions, and therefore should not be used as a pullup source for terminating device pins where required. 7.3.3.1.4 Auxiliary Power Output (AUX) The bq76PL536A provides an approximately 1-mA auxiliary power output that is controlled through IO_CONTROL[AUX]. This output is taken directly from REG50. The current drawn from this pin must be included in the REG50 current-limit budget by the designer. 7.3.3.2 Undervoltage Lockout and Power-On Reset The device incorporates two comparators to detect low VBAT conditions. The first detects low voltage where some device digital operations are still available. The second, (POR) detects a voltage below which device operation is not ensured. 7.3.3.2.1 UVLO When the UVLO threshold voltage is sensed for a period ≥ UVLODELAY, the device is no longer able to make accurate analog measurements and conversions. The ADC, cell-balancing and fault-detection circuitry are disabled. The digital circuitry, including host CPU and vertical communications between ICs, is fully functional. Register contents are preserved with the exception that CB_CTRL is set to 0, and the UVLO bit is set in DEVICE_STATUS. 7.3.3.2.2 Power-On Reset (POR) When the POR voltage threshold or lower is sensed for a period ≥ UVLODELAY, the device is no longer able to function reliably. The device is disabled, including all fault-detection circuitry, host SPI communications, vertical communications, and so forth. After the voltage rises above the hysteresis limit longer than the delay time, the device exits the reset state, with all registers set to default conditions. The FAULT_STATUS[POR] bit is set and latched until reset by the host. The device no longer has a valid address (DEVICE_ADDRESS[AR] = 0, ADDRESS_CONTROL = 0). The device should be reprogrammed with a valid address, and any registers re-written if non-default values are desired. 7.3.3.2.3 Reset Command The bq76PL536A can also be reset by writing the reset code (0xa5) to the RESET register. All devices respond to a broadcast RESET command regardless of their current assigned address. The result is identical to a POR with the exception that the normal POR period is reduced to several hundred microseconds. 7.3.3.3 Thermal Shutdown (TSD) The bq76PL536A contains an integrated thermal shutdown circuit whose sensor is located near the REG50 LDO and has a threshold of TSD. When triggered, the REG50 regulator reduces its output voltage to zero, and the ADC is turned off to conserve power. The thermal shutdown circuit has a built-in hysteresis that delays recovery until the die has cooled slightly. When the thermal shutdown is active, the DEVICE_STATUS[TSD] bit is set. The IO_CONTROL[SLEEP] and ALERT[SLEEP] bits also become set to reduce power consumption. CAUTION In the TSD state, the following are DISABLED: • REG50 and AUX outputs • Secondary protector settings Due to the loss of REG50 and AUX outputs, any measurements (for example, voltage on a thermistor biased by either) should be considered incorrect. Any external protection schemes depending on either of these voltages will also be impacted and the system designer shall make the appropriate decisions based on this. 28 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.3.3.4 GPIO The bq76PL536A includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pullup (10 kΩ–1 MΩ, typ.) is required on this pin if used as an input. If the pullup is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a pullup is recommended in all designs to prevent an unintentional increase in current draw. 7.3.4 Communications 7.3.4.1 SPI Communications – Device to Host Device-to-host (D2H) mode is provided on the SPI interface pins for connection to a local host microcontroller, logic, and so forth. D2H communications operate in voltage mode as a standard SPI interface for ease of connection to the outside world from thebq76PL536A device. Standard TTL-compatible logic levels are presented. All relevant SPI timing and performance parameters are met by this interface. The host interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. The SPI clock is normally low; data changes on rising edges, and is sampled on the falling edge. All transfers are MSB-first. The pins of the base IC (only) in a stack should have the SCLK_H and SDI_H pins terminated with pullups to minimize current draw of the part if the host ever enters a state where the pins are not driven, that is, held in the high-impedance state by the host. In non-base devices, the _H pins are forced to be all outputs driven low when the HSEL pin is high. In non-base devices, all _H pins should remain unconnected. The CS_H has a pullup resistor of approximately 100 kΩ. SDO_H is a 3-state output and is terminated with a weak pullup. NOTE Designer Note: When VBAT is at or below the UVLO trip point voltage, the internal LDO which supplies the xxxx_H host SPI communications pins (VLODx) begins to fall out of regulation. The output high voltage on the xxxx_H pins falls off with the LDO voltage in an approximately linear manner until at the POR voltage trip point where it is reduced to approximately 3.5 V. This action is not tested in production. 7.3.5 Device-to-Device Vertical Bus (VBUS) Interface Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides common-mode voltage isolation between successive bq76PL536As. This vertical bus (VBUS) is found on the _N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed. The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of bq76PL536As. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the same name, but opposite suffix. All pins operate within the voltages present at the BAT and VSS pins. WARNING These pins may be several hundred volts above system ground, depending on their position in the stack. NOTE Designer Note: North (_N) pins of the top, most-positive device in the stack should be connected to the BAT1(2) pins of the device for correct operation of the string. South (_S) pins of the lowest, most-negative device in the stack should be connected to VSS of the device. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 29 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com The number of devices in the vertical stack and other factors limit the maximum SCLK frequency. Each device imposes an approximately 30-ns delay on the round trip communications speed, that is, from SCLK rising (an input to all devices) to the SDO pin transitioning requires approximately 30 ns per device. The designer must add to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in series with the connection, and any other wiring or cabling between devices in the system. To maximize speed, these other system components should be carefully selected to minimize delays and other detrimental effects on signal quality. Wiring and connectors should receive special attention to their transmission line characteristics. Other factors which should be considered are clock duty cycle, clock jitter, temperature effects on clock and system components, user-selected drive level for the level-shift interface, and desired design margin. The VBUS SPI interface is placed in a low-power mode when CS_H is not asserted on the base device. The CS_N/S pins are asserted by a logic high on the vertical interface bus (logically inverted from CS_H). This creates a default VBUS CS condition of logic low, reducing current consumption to a minimum. To reduce power consumption of the SPI interface to a minimum, the SCLK_H and SDI_H should be maintained at a logic low (de-asserted) while CS_H is asserted (low). Most SPI buses are operated this way by microcontrollers. The VBUS versions of these signals are not inverted from the host interface. The device also de-asserts by default the SDO_N/S pins to minimize power consumption. 7.3.6 Packet Formats 7.3.6.1 Data Read Packet When the bq76PL536A is selected (CS_S [CS_H for first device] is active and the bq76PL536A has been addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N pin of the next device down the stack. This continues to the first device in the stack, where the data in from the SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC as the last byte sent. See Figure 19 and Figure 20 for additional information. CS SDI SDO n + 1 placeholder bytes DEV ADDR REG ADDR CNT = n 0x00 0x00 0x00 0x00 0x00 0x00 0x00 READ 1 READ 2 READ n... CRC 1 byte time Figure 19. READ Packet Format Read Packet 0 Device Address R/W 0 Start Reg Address Read Length n Read Data 1 CS Assertion Read Data n CRC Figure 20. READ Packet Detail 30 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.3.6.2 Data Write Packet When the bq76PL536A is selected (CS_S is active and the bq76PL536A has been addressed) and a write request has been initiated, the bq76PL536A receives data through the SDI_S pin, which is connected to the SDO_N of the lower device. For the first device in the stack, the data is input to the SDI_H pin from the host, and transmitted up the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device checks the CRC, which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is invalid or missing, the device asserts the ALERT_S signal to the next lower device, which ripples down the stack to the ALERT_H pin on the lowest device. The host should then take action to clear the condition. See Figure 21 and Figure 22 for details. Unused or undefined register bits should be written as zeros. CS Start of next packet SDI DEV ADDR REG ADDR WRT DATA CRC DEV ADDR REG ADDR ... 1 byte time Figure 21. WRITE Packet Format Write Packet 0 Device Address R/W 1 Reg Address Reg Data CS Assertion CRC Figure 22. WRITE Packet Detail 7.3.6.3 Broadcast Writes The bq76PL536A supports broadcasting single register writes to all devices. A write to device address 0x3f is recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all registers in the stack of devices. This also permits synchronizing all ADC conversions by a firmware command sent to the CONVERT_CTRL register as an alternative to using the CONV and DRDY pins. 7.3.6.4 Communications Packet Structure The bq76PL536A has two primary communication modes through the SPI interface. These two modes enable single-byte read / write and multiple data reads. All writes are single-byte; the logical address is shifted one bit left, and the LSB = 1 for writing. All transactions are in the form of packets comprising: Table 4. Communication Packet Order BYTE DESCRIPTION #1 6-bit bq76PL536A slave address + R/W bit 0b0xxx xxxW #2 Starting data-register offset #3 Number of data bytes to be read (n) (omitted for writes) #4 to 3+n Data bytes #4+n CRC (omit if IO_CONFIG[CRC_DIS] = 1) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 31 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.3.6.5 CRC Algorithm The cyclic redundancy check (CRC) is a CRC-8 error-checking byte, calculated on all the message bytes (including addresses). It is identical in structure to the SMBus 2.0 packet error check (PEC), and is also known as the ATM-8 CRC. The CRC is appended to the message for all SPI packets by the device that supplied the data as the last byte in the packet (when IO_CONTROL[CRC] == 1). Each bus transaction requires a CRC calculation by both the transmitter and receiver within each packet. The CRC is calculated in a way that conforms to the polynomial, C(x) = x8 + ×2 + x1 + 1 and must be calculated in the order of the bits as received, MSB first. The CRC calculation includes all bytes in the transmission, including address, command, and data. When reading data from the device, the CRC is based on the ADDRESS + FIRST_REGISTER + LENGTH + returned_device_data[n]. The stuff-bytes used to clock out the data from the IC are not used as part of the calculation, although if the value 0x00 is used, the 0s have no effect on the CRC. CRC verification is performed by the receiver when the CS_x line goes false, indicating the end of a packet. If the CRC verification fails, the message is ignored (discarded), the CRC failure flag is set in the FAULT_STATUS[CRC] register, and the FAULT line becomes asserted and latched until the error is read and cleared by the host. The CRC bit returned in the FAULT_STATUS register reflects the last packet received, not the CRC condition of the packet reading the FAULT_STATUS contents. CRC errors should be handled at a high priority by the host controller, before writing to additional registers. 7.3.6.6 Data Packet Usage Examples The bq76PL536A can be enabled via the host to read just the specific voltage data which would require a total of 2 written bytes (chip address and R/W [#1] + first (starting) register offset [#2]) + LENGTH [#3] and 13 stuff bytes (12 [n] data bytes + CRC). The data packet can be expanded periodically to accommodate temperature and GPAI readings as well as device status as needed by changing the REGISTER_FIRST offset and LENGTH values. 7.3.7 Device Addressing Each individual device in the series stack requires an address to allow communication with it. Each bq76PL536A has a CS_S and CS_N that are used in assigning addresses. Once addresses have been assigned, the normal operation of the CS_N/S lines is asserted (logic high) during communications, and the appropriate bq76PL536A in the stack responds according to the address transmitted as part of the packet (Figure 23). When the bq76PL536A is reset, the DEVICE_STATUS[AR] (address request) flag is cleared, the address register is set to 0x00, and ALERT_S is set and passed down the stack. In this state, where address = 0x00, the CS_N signal is forced to a de-asserted state (CS is not passed north when an address = 0). In this manner, after a reset the host is assured that a response at address 0x00 is from the first physical device in the stack. After address assignment of the current device, the host is assured that the next response at address 0x00 is from the next physical device in the stack. Once a valid address is assigned to the device, the CS_N signal responds normally, and follows the CS_H or CS_S signal, propagating to the next device in the stack. Valid addresses are in the range 0x01 through 0x3e. 0x00 is reserved for device discovery after reset. 0x3f is reserved as a broadcast address for all devices. NOTE Designer Note: Broadcast messages are only received by devices with a valid address, and the next higher device. Any device with an address of 0x00 blocks messages to devices above it. A broadcast message may not be received by all devices in a stack in situations where some devices do not have a valid address. 32 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 All devices: ADDRESS = 0x?? (unknown) expected = # devices in stack START look_for = 0; Send BROADCAST_RESET Note: validated = one more than devices found at this point look_for++; n = 0; n++; Assign unique address (n) to this device @address 0x00 Assign ADDRESS Write Dev[0]ADDR_CTRL = n Validation test: Read same device for unique address (n) just assigned Read Dev[n] ADDR_CTRL[] Validate device was successfully found and addressed N Dev[n]ADDR_CTRL[] = n? Y This loop finds one new device per iteration n < look_for? Y N (Implied: n == look_for here) This loop resets all addressed devices, then looks for all previously found+1 devices again. Corrects any addressing faults in the stack n < expected? Y N (Implied: n == expected here) N All devices found? n == expected? Y Error() Success Figure 23. Address Discovery and Assignment Algorithm Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 33 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Once the address is written, the ADDRESS_CONTROL[AR] bit is set which is copied to the DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow (asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack. If a device loses its address through a POR or it is replaced then this device will be the highest logical device in the stack able to be addressed (0x00) as its CS_N will be disabled and the addressing process is required for this and higher devices. 7.3.8 Changes and Enhancements for bq76PL536A • Improved power management during CRC faults – Configuration bit IO_CONFIG[CRCNOFLT] (bit7) was added to disable CRC fault from asserting the FAULT pin. This feature is useful under very low-power operating conditions. • ADC accuracy improvements – The conversion timing is now fixed at 6 µs, offering improved accuracy over the original bq76PL536. • Improved ADC automatic mode functionality, allowing optimized and fully automatic internal power management (ADC_CTRL[ADC_ON] = 0) during normal operation at sample rates (time between conversions) > 10 ms. • Pin DRDY logic now indicates conversion status of all devices in the system. • Improved VBUS communications reduce noise, enhance drive levels and hysteresis to improve battery stack communications, and eliminate eight external components or more. Support for longer distances between ICs and/or higher speeds for implementing large battery stack sizes. • Improved flowchart for device addressing provided in data sheet. Spacer 7.4 Device Functional Modes 7.4.1 SLEEP Functionality The bq76PL536A provides the host a mechanism to put the part into a low-power sleep state by setting the IO_CONTROL[SLEEP] bit. When this bit is set/reset, the following actions occur as stated in the following paragraphs. 7.4.1.1 SLEEP State Entry (Bit Set) If a conversion is in progress, the device waits for it to complete, then sets DRDY true (high). The device sets the ALERT_STATUS[SLEEP] bit, which in turn causes the ALERT pin to be asserted. The device gates off all other sources of FAULT or ALERT except ALERT[SLEEP]. The existing state of the FAULT and ALERT registers is preserved. The host should service and reset the ALERT generated by the SLEEP bit being set to minimize SLEEP state current draw by writing a 1 to ALERT[SLEEP] followed by a 0 to ALERT[SLEEP]. The ALERT North-South signal chain can draw up to approximately 1 mA of current when active, so this ALERT source should be cleared prior to the host entering the SLEEP state of its own. This signaling is provided to notify the host that the unmonitored/unprotected state is being entered. The REG50 LDO is shut down and the output is allowed to float. The ADC, its reference, and clocks are disabled. The COV, CUV, and OT circuits are disabled, and their band-gap reference shut off. CAUTION The SLEEP State effectively removes protection and monitoring from the cells; the designer should take the necessary design steps and verifications to ensure the cells cannot be put into an unsafe condition by other parts of the system or usage characteristics. 34 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Device Functional Modes (continued) IO_CONTROL[TS1:TS2] bits are not modified. The host must also set these bits to zero to minimize current draw of the thermistors themselves. SPI communications are preserved; all registers may be read or written. 7.4.1.2 Sleep State Exit (Bit Reset) VREG50 operation is restored. COV, CUV, OT circuits are re-enabled. The ADC circuitry returns to its former state. Note that there is a warm-up delay associated with the ADC enable, the same delay as specified for enabling from a cold start. The FAULT and ALERT registers are restored to their pre-SLEEP state. If a FAULT or ALERT condition was present prior to SLEEP, the FAULT or ALERT pin is immediately asserted. IC_CONTROL[TS1:TS2] should be set by the host if the OT function or temperature measurement functions are desired. 7.5 Programming 7.5.1 Programming the EPROM Configuration Registers The bq76PL536A has a block of OTP-EPROM that is used for configuring the operation of the bq76PL536A. Programming of the EPROM should take place during pack/system manufacturing. A 7-V (VPP) pulse is required on the PROG pin. The part uses an internal window comparator to check the voltage, and times the internal pulse delivered to the EPROM array. The user first writes the desired values to all of the equivalent Group3 protected register addresses. The desired data is written to the appropriate address by first applying 7 V to the LDOD1(2) pins. Programming then performed by writing to the EE_EN register (address 0x3f) with data 0x91. After a time period > 1500 µs, the 7 V is removed. Nominally, the voltage pulse should be applied for approximately 2–3 ms. Applying the voltage for an extended period of time may lead to device damage. The write is self-timed internally after receipt of the command. The following flow chart (Figure 24) illustrates the procedure for programming. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 35 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Programming (continued) No Host writes data to Registers in USER Block 0x40–0x47 Verify Data in 0x40–0x47 Enable Group3 Write: Write: 0x35 to SHDW_CTRL (0x3a) Copy EPROM back to Registers Write 0x27 to SHDW_CTRL (0x3a) Write data to Registers Write: 0xnn to 0x4x Read Register block 0x40–0x4b ADDR++ ADDR > 0x4b? Contents match programmed value? Yes Yes Apply 7 V to LDOD1(2) pin Nominal time ~ 2 ms to 3 ms No Verify ECC bits Read DEVICE_STATUS [ECC_COR] Read ALERT_STATUS [PARITY] Read ALERT_STATUS [PARITY] Host enables write to USER Block Write: 0x91 to E_EN @0x3f No All == 0? Remove 7 V from LDOD1(2) pins Yes SUCCESS Programming complete FAIL Figure 24. EPROM Programming 36 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6 Register Maps 7.6.1 I/O Register Details The bq76PL536A has 48 addressable I/O registers. These registers provide status, control, and configuration information for the battery protection system. Reserved registers return 0x00. Unused registers should not be written to; the results are undefined. Unused or undefined bits should be written as zeroes, and will always read back as zeroes. Several types of registers are provided, details are in the following sections and tables. 7.6.2 Register Types 7.6.2.1 Read-Only (Group 1) These registers contain the results of conversions, or device status information set by internal logic. The contents are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are changed by either a conversion command, or when there is an internal state change (that is, a fault condition is sensed). 7.6.2.2 Read / Write (Group 2) The Read/Write register group modifies the operations or behavior of the device, or indicates detailed status in the ALERT_STATUS and FAULT_STATUS registers (Figure 25). The contents are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are changed either by a conversion command, or when there is an internal state change (that is, a fault condition is sensed). Contents may also be changed by a write from the host CPU to the register. Writes may only modify a single register at a time. If CRCs are enabled, the write packet is buffered until the CRC is checked for correctness. Packets with bad CRCs are discarded without writing the value to the register, after setting the FAULT_STATUS[CRC] flag. Unused or undefined bits in any register should be written as zeros, and will always read back as zeros. SPI DE -SERIALIZER INTERNAL DATA BUS CONTROL, STATUS & DATA REGISTERS REGISTER CRC CHECK LOGIC 7 6 5 4 3 2 1 0 WRITE FAULT _STATUS FLAGS CRC_ERR Figure 25. Register Group2 Architecture 7.6.2.3 Read / Write, Initialized From EPROM (Group3) These registers control the device configuration and functionality. The contents of the registers are initialized from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command. This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after any reset, without host CPU involvement. See Figure 26 for a simplified view. These registers may only be modified by using a special, sequential-write sequence to guard against accidental changes. The value loaded from EPROM at reset (or by command) may be temporarily overwritten by using the special write sequence. The temporary value is overwritten to the programmed EPROM initialization value by the next reset or command to reload. To write to a these protected registers, first write 0x35 to SHDW_CONTROL, immediately followed by the write to the desired register. Any intervening write cancels the special sequence. To re-initialize the entire set of Group3 registers to the EPROM defaults, write the value 0x27 to SHDW_CONTROL. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 37 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Register Maps (continued) These registers are protected further against corruption by a ninth parity bit that is automatically updated when the register is written using even parity. If the contents of the register ever become corrupted, the bad parity causes the ALERT_STATUS[PARITY] bit to become set, alerting the host CPU of the problem. The EPROM-stored constants are programmed by writing the values to the register(s), then applying the programming voltage to the LDODx pins, then issuing the EPROM_WRITE command to register E_EN. All Group3 registers are programmed simultaneously, and this operation can only be performed once to the onetime-programmable (OTP) memory cells. The process is not reversible. SPI DE-SERIALIZER INTERNAL DATA BUS REGISTER CONTROL & STATUS BITS CRC CHECK LOGIC PROTECTED REGISTER WRITE-PROTECT KEY 7 6 5 4 3 2 1 0 P STATUS FLAGS PARITY LOGIC WRITE PARITY SYNDROME CHECKER / GENERATOR 1 bit error ERROR CHECK / CORRECT (ECC) LOGIC REFRESH-PROTECT KEY POR REFRESH 2+ bit errors LOAD EPROM KEY requires sequenced write to unlock function PROGRAM VOLTAGE & TIMING CONTROL ECC_COR ECC_ERR PGM-PROTECT KEY CHECK BITS 7 6 5 4 3 2 No direct access to this register. 1 0 Cn+1... Cn C0 LOAD signal evaluates ECC syndrome bits Figure 26. Protected Register Group3 Architecture, Simplified View 7.6.2.4 Error Checking and Correcting (ECC) EPROM The EPROM used to initialize this group is also protected by error-check-and-correct (ECC) logic. The ECC bits provide a highly reliable storage solution in the presence of external disturbances. This feature cannot be disabled by user action. Implementation is fully self-contained and automatic and requires no special computations or provisioning by the user. When the Group3 contents are permanently written to EPROM, an additional array of hidden ECC-OTP cells is also automatically programmed. The ECC logic implements a Hamming code that automatically corrects all single-bit errors in the EPROM array, and senses additional multi-bit errors. If any corrections are made, the DEVICE_STATUS[ECC_COR] flag bit is set. If any multi-bit errors are sensed, the ALERT_STATUS[ECC_ERR] flag is set. The corrective action or detection is performed anytime the contents of EPROM are loaded into the registers – POR, RESET, or by REFRESH command. Note: The ECC_COR and ECC_ERR bits may glitch during OTP-EPROM writes; this is normal. If this occurs, reset the tripped bit; it should remain cleared. When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for bottom stack device) line is activated, and the ALERT_STATUS register returns the ECC_ERR and/or I_FAULT bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults in this state. EPROM bits are shipped from the factory set to 0, and must be programmed to the 1 state as required. 38 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Register Maps (continued) Table 5. Data and Control Register Descriptions ADDR GROUP ACCESS (1) RESET DESCRIPTION 0x00 1 R 0 Status register GPAI 0x01, 0x02 1 R 0 GPAI measurement data VCELL1 0x03, 0x04 1 R 0 Cell 1 voltage data VCELL2 0x05, 0x06 1 R 0 Cell 2 voltage data VCELL3 0x07, 0x08 1 R 0 Cell 3 voltage data VCELL4 0x09, 0x0a 1 R 0 Cell 4 voltage data VCELL5 0x0b, 0x0c 1 R 0 Cell 5 voltage data VCELL6 0x0d, 0x0e 1 R 0 Cell 6 voltage data TEMPERATURE1 0x0f, 0x10 1 R 0 TS1+ to TS1– differential voltage data TEMPERATURE2 0x11, 0x12 1 R 0 TS2+ to TS2– differential voltage data RSVD 0x13–0x1f – – – Reserved for future use ALERT_STATUS 0x20 2 R/W 0x80 Indicates source of ALERT signal FAULT_STATUS 0x21 2 R/W 0x08 Indicates source of FAULT signal COV_FAULT 0x22 1 R 0 Indicates cell in OV fault state CUV_FAULT 0x23 1 R 0 Indicates cell in UV fault state PRESULT_A 0x24 1 R 0 Parity result of Group3 protected registers (A) NAME DEVICE_STATUS PRESULT_B 0x25 1 R 0 Parity result of Group3 protected registers (B) 0x26–0x2f – – – Reserved for future use ADC_CONTROL 0x30 2 R/W 0 ADC measurement control IO_CONTROL 0x31 2 R/W 0 I/O pin control CB_CTRL 0x32 2 R/W 0 Controls the state of the cell-balancing outputs CBx CB_TIME 0x33 2 R/W 0 Configures the CB control FETs maximum on time RSVD ADC_CONVERT 0x34 2 R/W 0 ADC conversion start 0x35–0x39 – – – Reserved for future use SHDW_CTRL 0x3a 2 R/W 0 Controls WRITE access to Group3 registers ADDRESS_CONTROL 0x3b 2 R/W 0 Address register RESET 0x3c 2 W 0 RESET control register TEST_SELECT 0x3d 2 R/W 0 Test mode selection register RSVD 0x3e – – – Reserved for future use E_EN 0x3f 2 R/W 0 EPROM programming mode enable FUNCTION_CONFIG 0x40 3 R/W EPROM Default configuration of device IO_CONFIG 0x41 3 R/W EPROM I/O pin configuration CONFIG_COV 0x42 3 R/W EPROM Overvoltage set point CONFIG_COVT 0x43 3 R/W EPROM Overvoltage time-delay filter CONFIG_CUV 0x44 3 R/W EPROM Undervoltage setpoint CONFIG_CUVT 0x45 3 R/W EPROM Undervoltage time-delay filter CONFIG_OT 0x46 3 R/W EPROM Overtemperature set point CONFIG_OTT 0x47 3 R/W EPROM Overtemperature time-delay filter USER1 0x48 3 R EPROM User data register 1, not used by device USER2 0x49 3 R EPROM User data register 2, not used by device USER3 0x4a 3 R EPROM User data register 3, not used by device USER4 0x4b 3 R EPROM User data register 4, not used by device RSVD 0x4c–0xff – – – RSVD (1) Reserved Key: R = Read; W = Write Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 39 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.3 Register Details 7.6.3.1 DEVICE_STATUS Register (0x00) The STATUS register provides information about the current state of the bq76PL536A. Figure 27. DEVICE_STATUS Register 7 ADDR_RQST 6 FAULT 5 ALERT 4 Reserved 3 ECC_COR 2 UVLO 1 CBT 0 DRDY Table 6. DEVICE_STATUS Register Field Descriptions Bit 7 Field ADDR_RQST Type Reset Description This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct address. This bit is a copy of in the ADDRESS_CONTROL[AR] bit. 0 = Address has not been assigned 1 = Address has been assigned 6 FAULT This bit indicates that this bq76PL536A has detected a condition causing the FAULT signal to become asserted. 0 = No FAULT exists 1 = A FAULT exists. Read FAULT_STATUS to determine the cause. 5 ALERT This bit indicates that this bq76PL536A has detected a condition causing the ALERT pin to become asserted. 0 = No ALERT exists 1 = An ALERT exists. Read ALERT_STATUS to determine the cause. 4 Reserved 3 ECC_COR This bit indicates a one-bit error has been detected and corrected in the EPROM. 0 = No errors are detected in the EPROM 1 = A one-bit (single bit) error has been detected and corrected by on-chip logic. 2 UVLO This bit indicates the device VBAT has fallen below the undervoltage lockout trip point. Some device operations are not valid in this condition. 0 = Normal operation 1 = UVLO trip point reached, device operation is not ensured. 1 CBT This bit indicates the cell balance timer is running. 0 = The cell balance timer is has not started or has expired. 1 = The cell balance timer is running. 0 DRDY This bit indicates the data is ready to read (no conversions active). 0 = There are conversions running. 1 = There are no conversions running. 40 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6.4 GPAI (0x01, 0x02) Register The GPAI register reports the ADC measurement of GPAI+/GPAI– in units of LSBs. Bits 15–8 are returned at address 0x01, bits 7–0 at address 0x02. Figure 28. GPAI (0x01, 0x02) Register 15 GPAI[15] 7 GPAI [7] 14 GPAI[14] 6 GPAI [6] 13 GPAI[13] 5 GPAI [5] 12 GPAI[12] 4 GPAI [4] 11 GPAI[11] 3 GPAI [3] 10 GPAI[10] 2 GPAI [2] 9 GPAI[9] 1 GPAI [1] 8 GPAI[8] 0 GPAI [0] 7.6.5 VCELLn Register (0x03…0x0e) The VCELLn registers report the converted data for cell n, where n = 1 to 6. Bits 15–8 are returned at odd addresses (for example, 0x03), bits 7–0 at even addresses (for example, 0x04). Figure 29. VCELLn Register 15 VCELLn[15] 7 VCELLn[7] 14 VCELLn[14] 6 VCELLn[6] 13 VCELLn[13] 5 VCELLn[5] 12 VCELLn[12] 4 VCELLn[4] 11 VCELLn[11] 3 VCELLn[3] 10 VCELLn[10] 2 VCELLn[2] 9 VCELLn[9] 1 VCELLn[1] 8 VCELLn[8] 0 VCELLn[0] 7.6.6 TEMPERATURE1 Register (0x0f, 0x10) The TEMPERATURE1 register reports the converted data for TS1+ to TS1–. Bits 15–8 are returned at odd addresses (for example, 0x0f), bits 7–0 at even addresses (for example, 0x10). Figure 30. TEMPERATURE1 Register 15 TEMP1[15] 7 TEMP1[7] 14 TEMP1[14] 6 TEMP1[6] 13 TEMP1[13] 5 TEMP1[5] 12 TEMP1[12] 4 TEMP1[4] 11 TEMP1[11] 3 TEMP1[3] 10 TEMP1[10] 2 TEMP1[2] 9 TEMP1[9] 1 TEMP1[1] 8 TEMP1[8] 0 TEMP1[0] 7.6.7 TEMPERATURE2 Register (0x11, 0x12) The TEMPERATURE2 register reports the converted data for TS2+ to TS2–. Bits 15–8 are returned at odd addresses (for example, 0x11), bits 7–0 at even addresses (for example, 0x12). Figure 31. TEMPERATURE2 Register 15 TEMP2[15] 7 TEMP2[7] 14 TEMP2[14] 6 TEMP2[6] 13 TEMP2[13] 5 TEMP2[5] 12 TEMP2[12] 4 TEMP2[4] 11 TEMP2[11] 3 TEMP2[3] 10 TEMP2[10] 2 TEMP2[2] 9 TEMP2[9] 1 TEMP2[1] 8 TEMP2[8] 0 TEMP2[0] Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 41 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.8 ALERT_STATUS Register (0x20) The ALERT_STATUS register provides information about the source of the ALERT signal. The host must clear each alert flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack and wiring. Figure 32. ALERT_STATUS Register 7 AR 6 PARITY 5 ECC_ERR 4 FORCE 3 TSD 2 SLEEP 1 OT2 0 OT1 Table 7. ALERT_STATUS Register Field Descriptions Bit 7 Field AR Type Reset Description This bit indicates that the ADDR[0]…[5] bits have been written to a valid address. This bit is an inverted copy of the ADDRESS_CONTROL[AR] bit. It is not cleared until an address has been programmed in ADDRESS_CONTROL and a 1 followed by a 0 (two writes) is written to the bit. 0 = Address has been assigned. 1 = Address has not been assigned (default at RESET). 6 PARITY This bit is used to validate the contents of the protected Group3 registers. 0 = Group3 protected register(s) contents are valid. 1 = Group3 protected register(s) contents are invalid. Group3 registers should be refreshed from OTP or directly written from the host. 5 ECC_ERR This bit is used to validate the OTP register blocks. 0 = No double-bit errors (a corrected one-bit error may/may not exist) 1 = An uncorrectable error has been detected in the OTPEPROM register bank. OTP-EPROM register(s) are not valid. 4 FORCE This bit asserts the ALERT signal. It can be used to verify correct operation and connectivity of the ALERT as a part of system self-test. 0 = De-assert ALERT (default) 1 = Assert the ALERT signal. 3 TSD This bit indicates thermal shutdown is active. 0 = Thermal shutdown is inactive (default). 1 = Die temperature has exceeded TSD. 2 SLEEP This bit indicates SLEEP mode was activated. This bit is only set when SLEEP is first activated; no continuous ALERT or SLEEP status is indicated after the host resets the bit, even if the IO_CTRL[SLEEP] bit remains true. (See IO_CTRL register for details.) 0 = Normal operation 1 = SLEEP mode was activated. 1 OT2 This bit indicates an overtemperature fault has been detected via TS2. 0 = Temperature is lower than or equal to the VOT2 (or input disabled by IO_CONTROL[TS2] = 0). 1 = Temperature is higher than VOT2. 0 OT1 This bit indicates an overtemperature fault has been detected via TS1. 0 = Temperature is lower than or equal to the VOT1 (or input disabled by IO_CONTROL[TS1] = 0). 1 = Temperature is higher than VOT1. 42 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6.9 FAULT_STATUS Register (0x21) The FAULT_STATUS register provides information about the source of the FAULT signal. The host must clear each fault flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack and wiring. Figure 33. FAULT_STATUS Register 7 6 Reserved 5 I_FAULT 4 FORCE 3 POR 2 CRC 1 CUV 0 COV Table 8. FAULT_STATUS Register Field Descriptions Bit Field 7-6 Reserved 5 I_FAULT Type Reset Description The device has failed an internal register consistency check. Measurement data and protection function status may not be accurate and should not be used. 0 = No internal register consistency check fault exists. 1 = The internal consistency check has failed self-test. The host should attempt to reset the device, see the RESET section. If the fault persists, the failure should be considered uncorrectable. 4 FORCE This bit asserts the FAULT signal. It can be used to verify correct operation and connectivity of the FAULT line as a part of system self-test. 0 = Deassert FAULT (default) 1 = Assert the FAULT signal 3 POR This bit indicates a power-on reset (POR) has occurred. 0 = No POR has occurred since this bit was last cleared by the host. 1 = A POR has occurred. This notifies the host that default values have been loaded to Group1 and Group2 registers, and OTP contents have been copied to Group3 registers. 2 CRC This bit indicates a garbled packet reception by the device. 0 = No errors 1 = A CRC error was detected in the last packet received. 1 CUV This bit indicates that this bq76PL536A has detected a cell undervoltage (CUV) condition. Examine CUV_FAULT to determine which cell caused the ALERT. 0 = All cells are above the CUV threshold (default). 1 = One or more cells is below the CUV threshold. 0 COV This bit indicates that this bq76PL536A has detected a cell overvoltage (COV) condition. Examine COV_FAULT to determine which cell caused the FAULT. 0 = All cells are above the COV threshold (default). 1 = One or more cells is below the COV threshold. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 43 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.10 COV_FAULT Register (0x22) Figure 34. COV_FAULT Register 7 6 5 OV[6] Reserved 4 OV[5] 3 OV[4] 2 OV[3] 1 OV[2] 0 OV[1] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9. COV_FAULT Register Field Descriptions Bit Field 7-6 Reserved 5-0 OV[6]..[1] Type Reset Description These bits indicate which DEVICE_STATUS[COV] flag to be set. cell caused the 0 = Cell[n] does not have an overvoltage fault (default). 1 = Cell[n] does have an overvoltage fault. 7.6.11 CUV_FAULT Register (0x23) Figure 35. CUV_FAULT Register 7 6 5 UV[6] Reserved 4 UV[5] 3 UV[4] 2 UV[3] 1 UV[2] 0 UV[1] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10. CUV_FAULT Register Field Descriptions Bit Field 7-6 Reserved 5-0 UV[6]..[1] Type Reset Description These bits indicate which DEVICE_STATUS[CUV] flag to be set. cell caused the 0 = Cell[n] does not have an undervoltage fault (default). 1 = Cell[n] does have an undervoltage fault. 7.6.12 PARITY_H Register (0x24) (PRESULT_A (R/O)) The PRESULT_A register holds the parity result bits for the first eight Group3 protected registers. Figure 36. PARITY_H Register 7 OTT 6 OTV 5 CUVT 4 CUVV 3 COVT 2 COVV 1 IO 0 FUNC 7.6.13 PARITY_H Register (0x25) (PRESULT_B (R/O)) The PRESULT_B register holds the parity result bits for the second eight Group3 protected registers. Figure 37. PARITY_H Register 7 6 5 Reserved 44 4 3 USER4 Submit Documentation Feedback 2 USER3 1 USER2 0 USER1 Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6.14 ADC_CONTROL Register (0x30) The ADC_CONTROL register controls some features of the bq76PL536A. Figure 38. ADC_CONTROL Register 7 Reserved 6 ADC_ON 5 TS2 4 TS1 3 GPAI 2 CELL_SEL[2] 1 CELL_SEL[1] 0 CELL_SEL[0] LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. ADC_CONTROL Register Field Descriptions Bit Field Type Reset Description 7 Reserved Must be written as 0. 6 ADC_ON This bit forces the ADC subsystem ON. This has the effect of eliminating internal start-up and settling delays, but increases current consumption. 0 = Auto mode. ADC subsystem is OFF until a conversion is requested. The ADC is turned on, a wait is applied to allow the reference to stabilize. Automatically returns to OFF state at end of requested conversion. Note that there is a start-up delay associated with turning the ADC to the ON state in this mode. 1 = ADC subsystem is ON, regardless of conversion state. Power consumption is increased. 5-4 3 TS[1]..[0] These two bits select whether any of the temperature sensor inputs are to be measured on the next conversion sequence start. Refer to Table 12. GPAI This bit enables and disables the GPAI input to be measured on the next conversion-sequence start. 0 = GPAI is not selected for measurement. 1 = GPAI is selected for measurement. 2-0 CELL_SEL[2]..[0] These three bits select the series cells for voltage measurement translation on the next conversion sequence start. Refer to Table 13. Table 12. Temperature sensor Inputs TS[1] TS[0] MEASURE T 0 0 None (default) 0 1 TS1 1 0 TS2 1 1 Both Table 13. Series Cells for Voltage Measurement Translation CELL_SEL[2] CELL_SEL[1] CELL_SEL[0] 0 0 0 Cell 1 only 0 0 1 Cells 1-2 0 1 0 Cells 1-2-3 0 1 1 Cells 1-2-3-4 1 0 0 Cells 1-2-3-4-5 1 0 1 Cells 1-2-3-4-5-6 Other SELECTED CELL Cell 1 only Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 45 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.15 IO_CONTROL Register (0x31) The IO_CONTROL register controls some features of the bq76PL536A external I/O pins. Figure 39. IO_CONTROL Register 7 AUX 6 GPIO_OUT 5 GPIO_IN 4 3 2 SLEEP Reserved 1 TS2 0 TS1 Table 14. IO_CONTROL Register Field Descriptions Bit Field 7 AUX Type Reset Description Controls the state of the AUX output pin, which is internally connected to REG50. 0 = Open 1 = Connected to REG50 6 GPIO_OUT Controls the state of the open-drain GPIO output pin; the pin should be programmed to 1 to use the GPIO pin as an input. 0 = Output low 1 = Open-drain 5 GPIO_IN Represents the input state of GPIO pin when used as an input 0 = GPIO input is low 1 = GPIO input is high 4-3 Reserved 2 SLEEP Places the device in a low-quiescent-current state. All CUV, COV, and OT comparators are disabled. A 1-ms delay to stabilize the reference voltage is required to exit SLEEP mode and return to active COV, CUV monitoring. 0 = ACTIVE mode 1 = SLEEP mode 1-0 TSx Controls the connection of the TS1:TS2 inputs to the ADC VSS connection point. When set, the TSx(–) input is connected to VSS. These bits should be set to 0 to reduce the current draw of the system. 0 = Not connected 1 = Connected 7.6.16 CB_CTRL Register (0x32) The CB_CTRL register determines the internal cell balance output state. Figure 40. CB_CTRL Register 7 6 Reserved 5 CBAL[6] 4 CBAL[5] 3 CBAL[4] 2 CBAL[3] 1 CBAL[2] 0 CBAL[1] Table 15. CB_CTRL Register Field Descriptions Bit Field 7-6 Reserved 5-0 CBAL[n] Type Reset Description CB_CTRL b(n = 5 to 0) (CBAL(n + 1)): This bit determines if the CB(n) output is high or low. 0 = CB[n] output is low (default). 1 = CB[n] output is high (active). 46 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6.17 CB_TIME Register (0x33) The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63 minutes. When set to 0, no balancing can occur – balancing is effectively disabled. Figure 41. CB_TIME Register 7 CBT[7] 6 Reserved 5 CBT[5] 4 CBT[4] 3 CBT[3] 2 CBT[2] 1 CBT[1] 0 CBT[0] Table 16. CB_TIME Register Field Descriptions Bit Field 7 Type Reset CBT[7] Description Controls minutes/seconds counting resolution. 0 = Seconds (default) 1 = Minutes 6 Reserved 5-0 CBT[n] Sets the time duration as scaled by CBT[7] 7.6.18 ADC_CONVERT Register (0x34) The CONVERT_CTRL register is used to start conversions. Figure 42. ADC_CONVERT Register 7 6 5 4 Reserved 3 2 1 0 CONV Table 17. ADC_CONVERT Register Field Descriptions Bit Field 7-1 Reserved 0 Type Reset CONV Description This bit starts a conversion, using the settings programmed into the ADC_CONTROL register. It provides a programmatic method of initiating conversions. 0 = No conversion (default) 1 = Initiate conversion. This bit is automatically reset after conversion begins, and always returns 0 on READ. 7.6.19 SHDW_CTRL Register (0x3a) The SHDW_CTRL register controls writing to Group3 protected registers. Default at RESET = 0x00. The value 0x35 must be written to this register to allow writing to Group3 protected registers in the range 0x40–0x4f. The register always returns 0x00 on read. The register is reset to 0x00 after any successful write, including a write to non-Group3 registers. A read operation does not reset this register. Writing the value 0x27 results in all Group3 protected registers being refreshed from OTP programmed values. The register is reset to 0x00 after the REFRESH is complete. Figure 43. SHDW_CTRL Register 7 SHDW[7] 6 SHDW[6] 5 SHDW[5] 4 SHDW[4] 3 SHDW[3] 2 SHDW[2] 1 SHDW[1] 0 SHDW[0] Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 47 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.20 ADDRESS_CONTROL Register (0x3b) The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536A for communication. The default for this register is 0x00 at RESET. Figure 44. ADDRESS_CONTROL Register 7 ADDR_RQST 6 Reserved 5 ADDR[5] 4 ADDR[4] 3 ADDR[3] 2 ADDR[2] 1 ADDR[1] 0 ADDR[0] Table 18. ADDRESS_CONTROL Register Field Descriptions Bit Field 7 Type Reset ADDR_RQST Description This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct address. This bit is reflected in the DEVICE_STATUS[AR] bit. 0 = Address has not been assigned (default at RESET). 1 = Address has been assigned. 6 Reserved 5-0 ADDR[n] These bits set the device address for SPI communication. This provides to a range of addresses from 0x00 to 0x3f. Address 0x3f is reserved for broadcast messages to all connected and addressed 76PL536 devices. The default for these 6 bits is 0x00 at RESET. 7.6.21 RESET Register (0x3c) The RESET register allows the host to reset the bq76PL536A directly. Writing 0xa5 causes the device to RESET. Other values are ignored. Figure 45. RESET Register 7 RST[7] 48 6 RST[6] 5 RST[5] 4 RST[4] 3 RST[3] Submit Documentation Feedback 2 RST[2] 1 RST[1] 0 RST[0] Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6.22 TEST_SELECT Register (0x3d) The TEST_SELECT places the SPI port in a special mode useful for debug. TSEL (b7–b0) is used to place the SPI_H interface pins in a mode to support test/debug of a string of bq76PL536A devices. 0 = normal operating mode. When the sequence 0xa4, 0x25 ("JR") is written on subsequent write cycles, the device enters a special TEST mode useful for stack debugging. Writes to other registers between the required sequence bytes results in the partial sequence being voided; the entire sequence must be written again. POR, RESET, or writing a 0x00 to this register location exits this mode. In this state, SPI pin SCLK and SDI become outputs and are enabled, and reflect the state of the SCLK_S, SDI_S pins of the device. SDO remains an output. This allows observation of bus traffic mid-string. The lowest device in the string should not be set to operate in this mode. CAUTION The user is cautioned to condition the connection to a mid- or top-string device with suitable isolation circuitry to prevent injury or damage to connected devices. Programming the most-negative device on the stack in this mode prevents further communications with the stack until POR, and may result in device destruction; this condition should be avoided. Figure 46. TEST_SELECT Register 7 TSEL[7] 6 TSEL[6] 5 TSEL[5] 4 TSEL[4] 3 TSEL[3] 2 TSEL[2] 1 TSEL[1] 0 TSEL[0] 7.6.23 E_EN Register (0x3f) The E_EN register controls the access to the programming of the integrated OTP EPROM. This register should be written the value 0x91 to permit writing the USER block of EPROM. Values other than 0x00 and 0x91 are reserved and may result in undefined operation. The next read or write of any type to the device resets (closes) the write window. If a Group3 protected write occurs, the window is closed after the write. Figure 47. E_EN Register 7 E_EN[7] 6 E_EN[6] 5 E_EN[5] 4 E_EN[4] 3 E_EN[3] 2 E_EN[2] 1 E_EN[1] 0 E_EN[0] Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 49 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.24 FUNCTION_CONFIG Register (0x40) The FUNCTION_CONFIG sets the default configuration for special features of the device. Figure 48. FUNCTION_CONFIG Register 7 0 6 0 5 GPAI_REF 4 GPAI_SRC 3 CN[1] 2 CN[0] 1 0 Reserved Table 19. FUNCTION_CONFIG Register Field Descriptions Bit Field 7-6 Reserved 5 Type Reset Description GPAI_REF This bit sets the reference for the GPAI ADC measurement. 0 = Internal ADC bandgap reference 1 = VREG50 (ratiometric) 4 GPAI_SRC This bit controls multiplexing of the GPAI register and determines whether the ADC mux is connected to the external GPAI inputs, or internally to the BAT1 pin. The register results are automatically scaled to match the input. 0 = External GPAI inputs are converted to result in GPAI register 0x01–02. 1 = BAT pin to VSS voltage is measured and reported in the GPAI register. 3-2 CN[n] These two bits configure the number of series cells used. If fewer than 6 cells are configured, the corresponding OV/UV faults are ignored. For example, if the CN[x] bits are set to 10b (2), then the OV/UV comparators are ignored for cells 5 and 6. Refer to Table 20. 1-0 Reserved Table 20. Series Cells 50 CN[1] CN[0] Series Cells 0 0 6 (DEFAULT) 0 1 5 1 0 4 1 1 3 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 7.6.25 IO_CONFIG Register (0x41) The IO_CONFIG sets the default configuration for miscellaneous I/O features of the device. Figure 49. IO_CONFIG Register 7 CRCNOFLT 6 5 4 3 2 1 Reserved 0 CRC_DIS Table 21. IO_CONFIG Register Field Descriptions Bit 7 Field Type Reset CRCNOFLT Description This bit enables and disables detected CRC errors asserting the FAULT pin. 0 = CRC errors cause the FAULT[CRC] bit to be set and the FAULT pin to assert. The FAULT[CRC] bit must be reset as described in the text. 1 = CRC errors cause the FAULT[CRC] bit to be set and the FAULT pin is not asserted. The FAULT[CRC] bit must be reset as described in the text. 6-1 Reserved 0 CRC_DIS This bit enables and disables the automatic generation of the CRC for the SPI communication packet. The packet size is determined by the host as part of the read request protocol. The CRC is checked at the deassertion of the CS pin. TI recommends that this bit be changed using the broadcast address (0x3f) so that all devices in a battery stack use the same protocol. 0 = A CRC is expected, and generated as the last byte of the packet. 1 = A CRC is not used in communications. 7.6.26 CONFIG_COV Register (0x42) The CONFIG_COV register determines cell overvoltage threshold voltage. Figure 50. CONFIG_COV Register 7 DISABLE 6 Reserved 5 COV[5] 4 COV[4] 3 COV[3] 2 COV[2] 1 COV[1] 0 COV[0] Table 22. CONFIG_COV Register Field Descriptions Bit 7 Field DISABLE Type Reset Description Disables the overvoltage function when set. 0 = Overvoltage function enabled 1 = Overvoltage function disabled 6 5-0 Reserved COV[n] Configuration bits with corresponding voltage threshold 0x00 = 2 V; each binary increment adds 50 mV until 0x3c = 5 V Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 51 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 7.6.27 CONFIG_COVT Register (0x43) The CONFIG_COVT register determines cell overvoltage detection delay time. Figure 51. CONFIG_COVT Register 7 µs/ms 6 5 4 COVD[4] Reserved 3 COVD[3] 2 COVD[2] 1 COVD[1] 0 COVD[0] Table 23. CONFIG_COVT Register Field Descriptions Bit Field 7 µs/ms Type Reset Description Determines the units of the delay time, microseconds or milliseconds 0 = Microseconds 1 = Milliseconds 6-5 Reserved 4-0 COVD[n] 0x01 = 100; each binary increment adds 100 until 0x1f = 3100 Note: When this register is programmed to 0x00, the delay becomes 0s AND the COV state is NOT latched in the COV_FAULT register. In this operating mode, the overvoltage state for a cell is virtually instantaneous in the COV_FAULT register. This mode may cause system firmware to miss a dangerous cell overvoltage condition. 7.6.28 CONFIG_UV Register (0x44) The CUV register determines cell under voltage threshold voltage. Figure 52. CONFIG_UV Register 7 DISABLE 6 5 4 CUV[4] Reserved 3 CUV[3] 2 CUV[2] 1 CUV[1] 0 CUV[0] Table 24. CONFIG_UV Register Field Descriptions Bit Field 7 Type Reset DISABLE Description Disables the undervoltage function when set 0 = Undervoltage function enabled 1 = Undervoltage function disabled 6-5 Reserved 4-0 COVD[n] Configuration bits with corresponding voltage threshold 0x00 = 0.7 V; each binary increment adds 100 mV until 0x1a = 3.3 V 7.6.29 CONFIG_CUVT Register (0x45) The CONFIG_CUVT register determines cell undervoltage detection delay time. Figure 53. CONFIG_CUVT Register 7 µs/ms 52 6 5 Reserved 4 CUVD[4] 3 CUVD[3] Submit Documentation Feedback 2 CUVD[2] 1 CUVD[1] 0 CUVD[0] Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 Table 25. CONFIG_CUVT Register Field Descriptions Bit Field 7 µs/ms Type Reset Description Determines the units of the delay time, microseconds or milliseconds 0 = Microseconds 1 = Milliseconds 6-5 Reserved 4-0 CUVD[n] 0x01 = 100; each binary increment adds 100 until 0x1f = 3100 Note: When this register is programmed to 0x00, the delay becomes 0 s AND the CUV state is NOT latched in the CUV_FAULT register. In this operating mode, the undervoltage state for a cell is virtually instantaneous in the CUV_FAULT register. This mode may cause system firmware to miss a dangerous cell undervoltage condition. 7.6.30 CONFIG_OT Register (0x46) The CONFIG_OT register holds the configuration of the overtemperature thresholds for the two TS inputs. For each respective nibble (OT1 or OT2), the value 0x0 disables this function. Other settings program a trip threshold. See the Ratiometric Sensing section for details of setting this register. Values above 0x0b are illegal and should not be used. Figure 54. CONFIG_OT Register 7 OT2[3] 6 OT2[2] 5 OT2[1] 4 OT2[0] 3 OT1[3] 2 OT1[2] 1 OT1[1] 0 OT1[0] 7.6.31 CONFIG_OTT Register (0x47) The CONFIG_OTT register determines cell overtemperature detection delay time. 0x01 = 10 ms; each binary increment adds 10 ms until 0xff = 2.55 seconds. NOTE When this register is programmed to 0x00, the delay becomes 0 s AND the OT state is NOT latched in the ALERT_STATUS register. In this operating mode, the overtemperature state for a TSn input is virtually instantaneous in the register. This mode may cause system firmware to miss a dangerous overtemperature condition. Figure 55. CONFIG_OTT Register 7 COTD[7] 6 COTD[6] 5 COTD[5] 4 COTD[4] 3 COTD[3] 2 COTD[2] 1 COTD[1] 0 COTD[0] 7.6.32 USERx Register (0x48–0x4b) (USER1–4) The four USER registers can be used to store user data. The part does not use these registers for any internal function. They are provided as convenient storage for user S/N, date of manufacture, and so forth. Figure 56. USERx Register 7 USER[7] 6 USER[6] 5 USER[5] 4 USER[4] 3 USER[3] 2 USER[2] 1 USER[1] 0 USER[0] Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 53 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The bq76PL536A is a series-cell Lithium-Ion battery monitor and secondary protector for Uninterruptible Power Systems (UPS), E-Bikes and Scooters, Large-Format Battery Systems, and so forth. To allow for optimal performance in the end application, special consideration must be taken to ensure minimization of measurement error through proper printed circuit board (PCB) layout. 8.1.1 Anti-Aliasing Filter An anti-aliasing filter is required for each VCn input VC6–VC1, consisting of a 1-kΩ, 1% series resistor and 100nF capacitor. Good-quality components should be used. A 1% resistor is recommended, because the resistor creates a small error by forming a voltage divider with the input impedance of the part. The part is factorytrimmed to compensate for the error introduced by the filter. 8.1.2 Host SPI Interface Pin States The CS_H pin is active-low. The host asserts the pin to a logic zero to initiate communications. The CS pin should remain low until the end of the current packet. When the CS_H pin is asserted, the SPI receiver and interface of the device are reset and resynchronized. This action ensures that a slave device that has lost synchronization during a previous transmission or as the result of noise on the bus does not remain permanently hung. CS_H must be driven false (high) between packets; see Timing Characteristics – AC SPI Data Interface for timing details. 54 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 8.2 Typical Application Figure 57 shows the recommended reference design components. LEMI RIN RBAL CEMI CIN CFILT LEMI2 RIN2 CIN2 RBAL2 CEMI2 CFILT2 LEMI3 RIN3 CIN3 RBAL3 CFILT3 CEMI3 LEMI4 RIN4 CEMI4 RPULL1 RPULL2 RPULL3 CIN4 RBAL4 CFILT4 RPULL4 0 RPULL5 0 LEMI5 CIN5 RBAL5 CEMI5 VBAT RIN5 CVREF CFILT5 CVDD_D_1 CVDD_D_2 CVDDA_1 LEMI6 RIN6 RBAL6 CEMI6 CVDDA_2 CIN6 CREGOUT CFILT6 Figure 57. Application Schematic Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 55 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 8.2.1 Design Requirements For this design example, use the parameters listed in Table 26. Table 26. Design Parameters PARAMETER DESCRIPTION EXAMPLE VALUE UNIT CEMI EMI Capacitor 3300 pF CFILT Filter Capacitor 0.1 µF CIN Input Capacitor 0.1 µF 2.2 (minimum) µF Internal analog 5-V LDO bypass connection 1 2.2 µF CVDDA_2 Internal analog 5-V LDO bypass connection 2 0.2 µF CVDD_D_1 Capacitor for internal digital 5-V LDO bypass connection 1 2.2 µF CVDD_D_2 Capacitor for internal digital 5-V LDO bypass connection 2 0.2 µF CREGOUT REGOUT Capacitor CVDDA_1 CVREF VREF Capacitor 10 µF LEMI EMI Ferrite Resistor 500 Ω RBAL Balance Resistor 47 Ω Input Resistor 1 kΩ RPULL1-RPULL3 RIN Pullup Resistors for digital open-drain I/O 10 kΩ RPULL4-RPULL5 Pullup Resistors for general-purpose (differential) analog input (GPAI), connect to VSS if unused kΩ 8.2.2 Detailed Design Procedure Use the following for the procedure for the recommended front-end circuit: 1. Select the RC filter closest to the cell for filter requirements. Additional poles can be added with a differential capacitor to get very low fc. 2. ADC is calibrated to use RIN = 1 kΩ and CIN = 0.1 µF. 3. Select Zener diode for lowest possible reverse leakage. 4. A balance FET gate-protection diode is required (available internally). 5. Select the capacitors for LDO Filters according to Table 26. – LDO1 and LDO2 require a 2.2-µF ceramic capacitor for stability. These pins are tied together internally. Tie LDO1 to LDOD2 externally. 6. For pullup supply, the following information applies: (a) REG50 turns off in SLEEP mode (b) Use LDOD for pullups in normal use (c) Use REG50 for programming EEPROM (LDOD will see 7 V) (d) Connect GPAI+ and GPA– to VSS if unused 7. Select low impedance and polarized connectors. Numbered or colored connectors are also good options. 8. Select the input Zener TVS so that it clamps below 5.6 Vdc, with low-leakage current, and must be able to handle transient surge energy 9. Select capacitors based on temperature and environment with voltages well above the operating voltage 10. Select balancing MOSFETs according to the following: (a) Low turn on threshold voltage (must turn on with the lowest cell voltage) (b) Drain-to-source voltage and gate-to-source voltage (c) Power dissipation (d) Current based on selected bleed resistor value 11. Select the Bleed Resistor according to the following: (a) Value based on desired current (b) Wattage to handle the current and temperature rise such as 4.2 V × 47 = 0.089 A ∴ 0.37 W) 56 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 8.2.3 Application Curves Figure 58. Firmware Conversion with ADC_ON = 0 Figure 59. Firmware Conversion with ADC_ON = 1 560 µs 130 µs Figure 61. Hardware Conversion with ADC_ON = 1 Figure 60. Hardware Conversion with ADC_ON = 0 530 µs Figure 62. ZOOM IN Hardware Conversion Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 57 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 8.3 Other Schematics The device generic part number, bq76PL536, is shown in these schematics. CELL 18 + 1 3-CELL6 CELL 17 + 2 3-CELL5 CELL 16 + 3 3-CELL4 CELL 15 + 4 3-CELL3 CELL 14 + 5 3-CELL2 CELL 13 + 6 3-CELL1 7 TP5 3-CELL0 3-VBAT 3-VBAT 3-VBAT 3-VBAT 3-VBAT 3-VBAT 3-VBAT CS_N SDI_N SDO_N SCLK_N The ground (VSS) reference per circuit block is unique. The most negative connection per block "CELL0" is the ground (VSS) reference for each IC. DO NOT connect ground references from different IC's. Only the ground reference CELL0 of circuit 1 is safe to connect non-isolated test equipment grounds. CELL5 CELL4 BQ76PL536_CIRCUIT3 SHEET-4 CELL3 CELL2 CS_S SDI_S CAUTION HIGH VOLTAGE E 3-CS_S 3-SDI_S 3-SCLK_S 3-SDO_S SDO_S SCLK_S FAULT_S 3-FAULT_S R143 R144 R145 1K 1K 1K RES0603 RES0603 RES0603 GROUND PLANE OF CIRCUIT 2 3-VSS R147 1K RES0603 C85 .0033uf 50V CAP0603 2-VSS CELL 12 + 1 2-CELL6 CELL 11 + 2 2-CELL5 CELL 10 + 3 2-CELL4 CELL 9 + 4 2-CELL3 CELL 8 + 5 2-CELL2 6 2-CELL1 7 2-CELL0 CELL6 CS_N 2-CS_N 2-SDI_N SDI_N 2-SCLK_N 2-SDO_N SDO_N 2-FAULT_N R148 R149 1K 1K RES0603 RES0603 SCLK_N 2-VBAT TP4 FAULT_N COMM PINS OF THE CHIP BELOW CONV_N TO JUST BELOW THE NORTH 2-DRDY_N 2-CONV_N UNDER THE SOUTH COMM LINES R146 1K RES0603 2-ALERT_N R142 1K RES0603 EXTEND THE GROUND PLANE P2 39502-1007_7-POS 3-ALERT_S 3-DRDY_S GROUND PLANE OF CIRCUIT 3 ALERT_N 3-VSS 2-VSS DRDY_S CONV_S CELL0 ALERT_S LOCATE R143, R144, R168, R176 CLOSE TO THE MOST NORTH IC CELL1 3-CONV_S C84 .001uf 50V CAP0603 NOTES: INDIVIDUAL GROUND PLANES ARE NECESSARY FOR PROPER NOISE REJECTION AND STABILITY OF THESE CIRCUITS CELL6 DRDY_N CELL 13 - FAULT_N VBAT ALERT_N 3-VBAT TP6 DRDY_N P3 39502-1007_7-POS CONV_N 3-VBAT Full-size reference schematics are available from TI on request. LOCATE R142, R175, R192, R193 CLOSE TO THE MOST SOUTH IC CELL5 BQ76PL536_CIRCUIT2 CELL4 SHEET-3 CELL1 2-CS_S CS_S SDI_S 2-SDI_S 2-SCLK_S 2-SDO_S SDO_S SCLK_S FAULT_S 2-FAULT_S 2-ALERT_S R82 R83 R84 1K 1K 1K RES0603 RES0603 RES0603 GROUND PLANE OF CIRCUIT 2 2-VSS DRDR_S CONV_S 2-DRDY_S 2-CONV_S C51 .001uf 50V CAP0603 ALERT_S LOCATE R195, R196, R197, R199 CLOSE TO THE MOST NORTH IC CELL0 TP3 R86 1K RES0603 2-VSS GROUND PLANE OF CIRCUIT 1 1 1-CELL6 CELL 5 + 2 1-CELL5 CELL 4 + 3 1-CELL4 CELL 3 + 4 1-CELL3 CELL6 CS_N 1-CS_N 1-SDI_N SDI_N 1-SCLK_N SCLK_N 1-SDO_N R91 R92 1K 1K RES0603 RES0603 SD0_N 1-FAULT_N R85 1K RES0603 FAULT_N 1-VBAT TP2 CELL 6 + 1-DRDY_N 1-CONV_N CONV_N P1 39502-1007_7-POS C52 .0033uf 50V CAP0603 1-VSS R81 1K RES0603 DRDY_N 1-VSS 1-ALERT_N CELL 7 - CELL2 ALERT_N CELL 7 + CELL3 LOCATE R194, R198, R200, R201 CLOSE TO THE MOST SOUTH IC CELL5 P4 MTA100-HEADER-10PIN 1 VSIG 1-FAULT 2 FAULT 1-ALERT 3 ALERT 1-DRDY/TX 4 DRDY 1-CONV/RX 5 FAULT ALERT CELL4 BQ76PL536_CIRCUIT1 DRDY CELL 2 + SHEET-2 CELL3 CONV 1-CELL2 5 CELL2 1-SPI-MISO 6 GND 7 MISO R14 100 RES0603 8 MOSI 9 R13 100 RES0603 10 SCLK CS SPI-MISO CELL 1 + 1-SPI-MOSI 1-CELL1 6 SPI-MOSI CELL1 1-SPI-SCLK SPI-SCLK 1-CELL0 7 CELL0 TP1 1-SPI-SS CS_S R12 100 RES0603 1-VSS 1-CELL0 1-CELL0 SDI_S SD0_S 1-CELL0 1-CELL0 SCLK_S FAULT_S 1-CELL0 1-CELL0 DRDY_S 1-CELL0 1-CELL0 1-VSS ALERT_S SPI-SS CONV_S CELL 1 - CONV R15 100 RES0603 CAUTION HIGH VOLTAGE S001 Figure 63. Schematic (Page 1 of 4) 58 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 1-SCLK_N [1] 1-SDO_N [1] 1-SDI_N [1] [1] 1-CS_N 1-CONV_N [1] 1-DRDY_N [1] 1-ALERT_N[1] 1-FAULT_N[1] Other Schematics (continued) GROUND PLANE OF CIRCUIT 2 GROUND PLANE OF CIRCUIT 1 ** - Locate these components very close to bq76PL536 IC. 1-VBAT [1] R80 1.0K 1% RES0603 R76 1M 1% RES0603 Z9 5.1 VDC 500mW Q8 SOD-123 FDN359AN SOT-23 Z10 5.1VDC SOD-323 1-VSS 2 R57 1.0K 1% RES0603 3 ** C38 0.1uf 50V CAP0603 R49 47 RES2512 4 R45 1.0K 1% RES0603 Z7 5.1 VDC 500mW SOD-123 5 Q7 FDN359AN SOT-23 6 R44 1M 1% RES0603 R40 1.0K 1% RES0603 7 8 ** C33 0.1uf 50V CAP0603 R38 47 RES2512 9 1-VSS R32 1.0K 1% RES0603 Z5 5.1 VDC 500mW Q6 SOD-123 FDN359AN SOT-23 10 R35 1M 1% RES0603 Z6 5.1VDC SOD-323 11 R28 1.0K 1% RES0603 C32 0.1uf 50V CAP0603 R24 47 RES2512 13 1-VSS 32 31 44 TS1- CB5 GPAI+ Q4 FDN359AN SOT-23 CB4 bq76PL536 GPIO R27 1.47K 1% RES0603 60 D1 LTW-C192TL2 White LED 20 R30 100 RES0603 R33 1.82K 1% RES0603 19 47 45 VC2 VREF Q5 2N7002LT1 SOT-23 R58 0R0 RES0603 48 1-VSS C4 DNP CAP0603 C6 DNP CAP0603 C7 DNP CAP0603 R50 0R0 RES0603 1-VSS 1-FAULT [1] 1-ALERT [1] 1-DRDY/TX [1] 1-CONV/RX [1] 41 SDO_H 42 SDI_H 40 SCLK_H 43 CS_H CB3 R25 2.7K RES0603 R29 100K RES0603 R63 1.82K 1% RES0603 39 FAULT_H 38 ALERT_H 37 DRDY_H 36 CONV_H VC3 R124 10K 1% B=3435K NTC0603 61 51 NC2 30 NC1 62 NC3 VC4 T1 R71 1.47K 1% RES0603 REG50 AUX 50 TEST HSEL 55 SCLK_N 54 SDO_N 53 SDI_N 52 CS_N TS1+ VC5 16 [1] 1-SPI-MISO [1] 1-SPI-MOSI 1-SPI-SCLK [1] 1-SPI-SS [1] C23 ** 10uf 10V CAP1206 CB2 VC1 AGND CB1 LDOD1 VC0 "Bottom" part connects all _S pins to 1-VSS. 21 22 23 24 R22 1.0K 1% RES0603 Z3 5.1 VDC 500mW SOD-123 CB6 LDOA 12 ** C19 0.1uf 50V CAP0603 TS2- U1 Z8 5.1VDC SOD-323 C27 0.1uf 50V CAP0603 VC6 GPAI- 1-VSS C21 0.047uf 16V CAP0603 LDOD2 1-VSS 15 1-LDOA 17 1-LDOD 18 46 TP-VPROG1 C39 ** 2.2uf 10V CAP0805 C34 ** 0.1uf 50V CAP0603 C24 ** 2.2uf 10V CAP0805 TAB C37 0.1uf 50V CAP0603 1 R61 1M 1% RES0603 R123 10K 1% B=3435K NTC0603 T2 C46 0.047uf 16V CAP0603 C25 0.1uf 50V CAP0603 TP-VSS1 1-VSS 65 [1,2] C42 0.1uf 50V CAP0603 THERMISTOR NTC 10K OHM 1% 0603 PANASONIC PART NUMBER # ERT-J1VG103FA 1-VSS TS2+ VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 [1] 1-CELL1 1-VSS R62 1.0K 1% RES0603 BAT1 BAT2 49 35 34 33 25 14 [1] 1-CELL2 CELL 1 + 63 64 SCLK_S SDO_S SDI_S CS_S [1] 1-CELL3 CELL 2 + CELL 1 - 1-VSS ** C40 0.1uf 50V CAP0603 R69 47 RES2512 59 CONV_N 58 DRDY_N 57 ALERT_N 56 FAULT_N [1] 1-CELL4 CONV_S DRDY_S ALERT_S FAULT_S [1] 1-CELL5 CELL 4 + C26 ** 2.2uf 10V CAP0805 1-VSS C43 ** 0.1uf 50V CAP0603 R75 1.0K 1% RES0603 26 27 28 29 CELL 5 + CELL 3 + Z12 5.1VDC SOD-323 [1] 1-CELL6 C108 33pF 50V CAP0603 1-VSS R77 1.0K 1% RES0603 Z11 5.1 VDC 500mW Q9 SOD-123 FDN359AN SOT-23 CELL 6 + CAUTION HIGH VOLTAGE * C47 33pF 50V CAP0603 ** C41 0.1uf 50V CAP0603 R79 47 RES2512 C48 0.1uf 50V CAP0603 * * C105 33pF 50V CAP0603 * C113 33pF 50V CAP0603 R21 1M 1% RES0603 Z4 5.1VDC SOD-323 R18 1.0K 1% RES0603 1-VSS ** C30 0.1uf 50V CAP0603 R9 47 RES2512 C9 0.1uf 50V CAP0603 R8 1.0K 1% RES0603 Z1 5.1 VDC 500mW Q2 SOD-123 FDN359AN SOT-23 1-VSS * - Typical value shown. Actual value depends on number of IC's in stack, wiring, etc. Consult applications guide for recommended values. R7 1M 1% RES0603 Z2 5.1VDC SOD-323 1-SCLK_S 1-SDO_S 1-SDI_S 1-CS_S 1-CONV_S 1-DRDY_S 1-ALERT_S 1-FAULT_S 1-VSS CAUTION HIGH VOLTAGE S002 Figure 64. Schematic (Page 2 of 4) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 59 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 2-SCLK_N [1] 2-SDO_N [1] 2-SDI_N [1] 2-CS_N [1] 2-FAULT_N [1] 2-CONV_N [1] 2-DRDY_N [1] 2-ALERT_N[1] Other Schematics (continued) GROUND PLANE OF CIRCUIT 3 GROUND PLANE OF CIRCUIT 2 ** - Locate these components very close to bq76PL536 IC. 2-VBAT [1] R140 1.0K 1% RES0603 C82 33pF 50V CAP0603 CAUTION HIGH VOLTAGE C83 * 33pF 50V CAP0603 * C80* 33pF 50V CAP0603 THERMISTOR NTC 10K OHM 1% 0603 PANASONIC PART NUMBER # ERT-J1VG103FA C79* 33pF 50V CAP0603 ** C74 0.1uf 50V CAP0603 2-LDOD[3] C59 0.047uf 16V CAP0603 R157 10K 1% B=3435K NTC0603 T2 T1 R158 10K 1% B=3435K NTC0603 Z22 5.1 VDC 500mW Q15 SOD-123 FDN359AN SOT-23 2-VSS 2 R128 1.0K 1% RES0603 3 ** C70 0.1uf 50V CAP0603 R121 47 RES2512 R120 1.0K 1% RES0603 Z20 5.1 VDC 500mW SOD-123 1 R129 1M 1% RES0603 Z23 5.1VDC SOD-323 C72 0.1uf 50V CAP0603 2-VSS 4 Q14 FDN359AN SOT-23 5 6 R117 1.0K 1% RES0603 7 8 ** C68 0.1uf 50V CAP0603 9 R111 1.0K 1% RES0603 Z18 5.1 VDC 500mW Q13 SOD-123 FDN359AN SOT-23 2-VSS 10 R110 1M 1% RES0603 Z19 5.1VDC SOD-323 11 R109 1.0K 1% RES0603 31 32 AUX REG50 44 50 TEST HSEL CB6 TS1+ VC5 TS1- GPAI+ CB5 Q11 FDN359AN SOT-23 bq76PL536 GPIO 60 D4 LTW-C192TL2 White LED 20 R106 100 RES0603 R107 1.82K 1% RES0603 19 Q12 2N7002LT1 SOT-23 R3 0R0 RES0603 48 47 2-VSS C8 DNP CAP0603 45 C10 DNP CAP0603 R1 0R0 RES0603 C11 DNP CAP0603 2-VSS 41 SDO_H 42 SDI_H 40 SCLK_H 43 CS_H CB3 C60** 10uf 10V CAP1206 VC2 VREF 16 CB2 VC1 AGND CB1 LDOD1 LDOD2 13 R102 2.7K RES0603 R105 100K RES0603 R131 1.82K 1% RES0603 39 FAULT_H 38 ALERT_H 37 DRDY_H 36 CONV_H VC3 VC0 2-VSS 21 22 23 24 R101 1.0K 1% RES0603 CB4 R103 1.47K 1% RES0603 61 51 NC2 30 NC1 62 NC3 VC4 LDOA 12 ** C67 0.1uf 50V CAP0603 R104 47 RES2512 Z16 5.1 VDC 500mW SOD-123 TS2- GPAI- 2-VSS R119 1M 1% RES0603 R114 47 RES2512 C58 0.1uf 50V CAP0603 VC6 U2 Z21 5.1VDC SOD-323 C65 0.1uf 50V CAP0603 R134 1.47K 1% RES0603 TS2+ 15 2-VSS 2-LDOA[3] 17 2-LDOD 18 46 TP-VPROG2 C71** 2.2uf 10V CAP0805 C69 ** 0.1uf 50V CAP0603 C61** 2.2uf 10V CAP0805 C62 0.1uf 50V CAP0603 TP-VSS2 TAB [1,3] C78 0.047uf 16V CAP0603 65 CELL 1 - R130 1.0K 1% RES0603 BAT1 BAT2 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 [1] 2-CELL1 C76 0.1uf 50V CAP0603 63 64 CONV_S DRDY_S ALERT_S FAULT_S [1] 2-CELL2 CELL 1 + ** C73 0.1uf 50V CAP0603 R132 47 RES2512 [1] 2-CELL3 CELL 2 + C63** 2.2uf 10V CAP0805 2-VSS 2-VSS CELL 3 + R115 100K C75** 0.1uf 50V CAP0603 R135 1.0K 1% RES0603 49 35 34 33 25 14 [1] 2-CELL4 Z25 5.1VDC SOD-323 55 SCLK_N 54 SDO_N 53 SDI_N 52 CS_N [1] 2-CELL5 CELL 4 + 2-VSS 59 CONV_N 58 DRDY_N 57 ALERT_N 56 FAULT_N CELL 5 + 2-VSS R136 1M 1% RES0603 SCLK_S SDO_S SDI_S CS_S [1] 2-CELL6 Q16 FDN359AN SOT-23 26 27 28 29 CELL 6 + R137 1.0K 1% RES0603 Z24 5.1 VDC 500mW SOD-123 RES0603 R139 47 RES2512 C81 0.1uf 50V CAP0603 2-VSS R100 1M 1% RES0603 Z17 5.1VDC SOD-323 R99 1.0K 1% RES0603 2-VSS ** C66 0.1uf 50V CAP0603 R98 47 RES2512 C54 0.1uf 50V CAP0603 R95 1.0K 1% RES0603 Z14 5.1 VDC 500mW Q10 SOD-123 FDN359AN SOT-23 * - Typical value shown. Actual value depends on number of IC's in stack, wiring, etc. Consult applications guide for recommended values. 2-VSS R94 1M 1% RES0603 C56 * 1nF 50V CAP0603 Z15 5.1VDC SOD-323 C57* 33pF 50V CAP0603 2-VSS 2-VSS C55* 33pF 50V CAP0603 2-VSS C53* 1nF 50V CAP0603 2-VSS CAUTION HIGH VOLTAGE 2-VSS GROUND PLANE OF CIRCUIT 2 EXTEND THE GROUND PLANE [1] 2-SCLK_S [1] 2-SDO_S [1] 2-SDI_S [1] 2-CS_S [1] 2-CONV_S [1] 2-DRDY_S [1] 2-ALERT_S [1] 2-FAULT_S UNDER THE SOUTH COMM LINES TO JUST BELOW THE NORTH COMM PINS OF THE CHIP BELOW Figure 65. Schematic (Page 3 of 4) 60 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 3-SCLK_N 3-SDO_N 3-SDI_N 3-CS_N 3-CONV_N 3-DRDY_N 3-ALERT_N 3-FAULT_N Other Schematics (continued) CAUTION HIGH VOLTAGE ** - Locate these components very close to bq76PL536 IC. 3-VBAT [1] THERMISTOR NTC 10K OHM 1% 0603 PANASONIC PART NUMBER # ERT-J1VG103FA R208 1.0K 1% RES0603 C114 0.1uf 50V CAP0603 ** C103 0.1uf 50V CAP0603 R199 47 RES2512 3-VSS Z37 5.1 VDC 500mW SOD-123 3-LDOD[4] Q23 FDN359AN SOT-23 [1] 3-CELL1 CELL 1 - [1,4] R191 10K 1% B=3435K NTC0603 T2 T1 R192 10K 1% B=3435K NTC0603 C109 0.1uf 50V CAP0603 Z35 5.1 VDC 500mW Q22 SOD-123 FDN359AN SOT-23 Z36 5.1VDC SOD-323 3-VSS 2 R185 1.0K 1% RES0603 3 ** C99 0.1uf 50V CAP0603 R183 47 RES2512 C101 0.1uf 50V CAP0603 1 R186 1M 1% RES0603 4 Q21 FDN359AN SOT-23 32 AUX REG50 50 31 44 TEST HSEL CB6 TS1+ VC5 TS1- CB5 6 R179 1.0K 1% RES0603 7 8 ** C97 0.1uf 50V CAP0603 9 3-VSS R174 1.0K 1% RES0603 Z31 5.1 VDC 500mW Q20 SOD-123 FDN359AN SOT-23 10 R173 1M 1% RES0603 Z32 5.1VDC SOD-323 11 R170 1.0K 1% RES0603 13 47 3-VSS GPIO C12 DNP CAP0603 45 C13 DNP CAP0603 R4 0R0 RES0603 C14 DNP CAP0603 3-VSS 41 SDO_H 42 SDI_H 40 SCLK_H 43 CS_H CB3 C89 ** 10uf 10V CAP1206 VC2 VREF 16 CB2 VC1 AGND CB1 LDOD1 VC0 3-VSS Z30 5.1VDC SOD-323 Q19 2N7002LT1 SOT-23 39 FAULT_H 38 ALERT_H 37 DRDY_H 36 CONV_H VC3 21 22 23 24 R163 1.0K 1% RES0603 Z29 5.1 VDC 500mW Q18 SOD-123 FDN359AN SOT-23 48 LDOD2 CAP0603 R169 100 RES0603 R5 0R0 RES0603 51 NC2 30 NC1 62 NC3 bq76PL536 D5 LTW-C192TL2 White LED R171 1.82K 1% RES0603 19 LDOA 12 ** C96 0.1uf 50V R167 47 RES2512 CB4 R164 2.7K RES0603 R168 100K RES0603 20 GPAI+ VC4 R165 1.47K 1% RES0603 R188 1.82K 1% RES0603 60 TS2- GPAI5 R180 1M 1% RES0603 R177 47 RES2512 C87 0.1uf 50V CAP0603 "Top" part connects all _N pins to CELL6 of U3 VC6 U3 Z34 5.1VDC SOD-323 C94 0.1uf 50V CAP0603 TS2+ 3-VSS R181 1.0K 1% RES0603 Z33 5.1 VDC 500mW SOD-123 R194 1.47K 1% RES0603 61 3-VSS 15 3-LDOA [4] 17 3-LDOD 18 TP-VPROG3 46 C100 ** 2.2uf 10V CAP0805 TAB [1] 3-CELL2 CELL 1 + C88 0.047uf 16V CAP0603 C98 ** 0.1uf 50V CAP0603 C90 ** 2.2uf 10V CAP0805 C91 0.1uf 50V CAP0603 TP-VSS3 3-VSS 65 CELL 2 + R187 1.0K 1% RES0603 BAT1 BAT2 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 [1] 3-CELL3 63 64 3-VSS 49 35 34 33 25 14 CELL 3 + C111 0.047uf 16V CAP0603 3-VSS 3-VSS ** C102 0.1uf 50V CAP0603 R193 47 RES2512 SCLK_S SDO_S SDI_S CS_S [1] 3-CELL4 R178 100K RES0603 55 SCLK_N 54 SDO_N 53 SDI_N 52 CS_N [1] 3-CELL5 CELL 4 + C92 ** 2.2uf 10V CAP0805 3-VSS C104** 0.1uf 50V CAP0603 R196 1.0K 1% RES0603 59 CONV_N 58 DRDY_N 57 ALERT_N 56 FAULT_N CELL 5 + R197 1M 1% RES0603 Z39 5.1VDC SOD-323 CONV_S DRDY_S ALERT_S FAULT_S [1] 3-CELL6 26 27 28 29 CELL 6 + 3-REG50 R198 1.0K 1% RES0603 R162 1M 1% RES0603 R160 1.0K 1% RES0603 3-VSS ** C95 0.1uf 50V CAP0603 R155 47 RES2512 C86 0.1uf 50V CAP0603 3-VSS R153 1.0K 1% RES0603 Z27 5.1 VDC 500mW Q17 SOD-123 FDN359AN SOT-23 R152 1M 1% RES0603 * C2 1nF 50V CAP0603 Z28 5.1VDC SOD-323 C5 33pF 50V CAP0603 * 3-VSS 3-VSS C1 33pF 50V CAP0603 * 3-VSS C3 1nF 50V CAP0603 * * - Typical value shown. Actual value depends on number of IC's in stack, wiring, etc. Consult applications guide for recommended values. 3-VSS 3-VSS GROUND PLANE OF CIRCUIT 3 EXTEND THE GROUND PLANE TO JUST BELOW THE NORTH COMM PINS OF THE CHIP BELOW [1] [1] [1] [1] 3-SCLK_S 3-SDO_S 3-SDI_S 3-CS_S UNDER THE SOUTH COMM LINES [1] 3-CONV_S [1] 3-DRDY_S [1] 3-ALERT_S [1] 3-FAULT_S CAUTION HIGH VOLTAGE S004 Figure 66. Schematic (Page 4 of 4) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 61 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com PACK+ CONTROL (North) SPI FAULT ALERT CONV DRDY TO NEXT DEVICE SPI (North) CELL_6 GPAI HO S T I NT ERF ACE (n o t u sed ) AUX CBx (6) CELL_1 CONTROL (North) SPI (South) SPI ALERT FAULT DRDY CONV CONTROL (South) REG50 ••• CELL_2-5 ••• bq76PL536A GPIO SPI (North) CELL_6 GPAI AUX DRDY FAULT ALERT SPI HO S T I NT ERF ACE HOST INTERFACE CONV CBx (6) ••• CELL_2-5 ••• bq76PL536A GPIO CELL_1 South Interface (not used on bottom device) PACK- Figure 67. Simplified System Connection 62 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 9 Power Supply Recommendations 9.1 Power Supply Decoupling The LDOA, LDOD1, LDOD2 and REG50 pins all require a 2.2-µF ceramic capacitor to be placed as closely as possible to the respective pins to optimize stability. The bq76PL536A requires a power supply with between 7.2 V to 27 V inputs. When fewer than six cells are used, see Figure 14 for details. 10 Layout 10.1 Layout Guidelines For typical applications, the following guidelines and practices should be followed closely: • VREF and AGND pins require a high-quality 10-µF capacitor be connected between them, in very close physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on signal quality. – The AGND pin should be connected to VSS. Device VSS connections should be brought to a single point close to the IC to minimize layout-induced errors. The device tab should also be connected to this point, and is a convenient common VSS location. The internal VREF should not be used externally to the device by user circuits. • The internal analog supply should be bypassed at the LDOA pin with a good-quality, low-ESR, 2.2-µF ceramic capacitor. NOTE Because the LDODx inputs are pulled to approximately 7 V during programming, programming time MUST be < 50 ms. • • • • The bq76PL536A has a low-dropout (LDO) regulator provided to power the thermistors and other external circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-µF capacitor is required for stable operation. The output is internally current-limited and is reduced to near zero, if excess current is drawn, causing die temperatures to rise to unacceptable levels. The 2.2-µF output capacitor is required whether REG50 is used in the design or not. REG50 is disabled in SLEEP mode, may be turned off under thermal-shutdown conditions, and therefore should not be used as a pull-up source for terminating device pins where required. The bq76PL536A includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pull-up (10 kΩ–1 MΩ, typical) is required on this pin if used as an input. If the pull-up is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a pull-up is recommended in all designs to prevent an unintentional increase in current draw. Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides common-mode voltage isolation between successive bq76PL536As. This vertical bus (VBUS) is found on the _N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed. The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of bq76PL536As. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the same name, but opposite suffix. – All pins operate within the voltages present at the BAT and VSS pins. – The maximum SCLK frequency is limited by the number of devices in the vertical stack and other factors. Each device imposes an approximately 30-ns delay on the round trip communications speed; that is, from SCLK rise time (an input to all devices) to the SDO pin transition time requires approximately 30 ns per device. The designer must add to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in series with the connection, and any other wiring or cabling between devices in the system. When designing the layout, several considerations need to be taken into account. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 63 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com Layout Guidelines (continued) – First, in a stacked system, individual ground planes are necessary for proper noise rejection and stability of the circuits. – Second, the ground (VSS) reference per circuit block is unique. The most negative connection, per block “CELL0”, is the ground (VSS) reference for each IC. Do not connect ground references from different ICs. Only the ground reference CELL0, of the most southerly IC, is safe to connect non-isolated test equipment grounds. CAUTION Be careful as the BAT and VSS pins may be several hundred volts above system ground, depending on their position in the stack. NOTE North (_N) pins of the top, most-positive device in the stack, should be connected to the BAT1(2) pins of the device for correct operation of the string. South (_S) pins of the lowest, most-negative device in the stack, should be connected to VSS of the device. The PowerPAD™ package is a thermally enhanced standard-size IC package designed to eliminate the use of bulky heat sinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard repair procedures. See Figure 68. The PowerPAD™ package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom of the IC. This provides an extremely low-thermal resistance (RθJC) path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as a heat sink. In addition, through the use of thermal bias, the thermal pad can be directly connected to a ground plane or special heat sink structure designed into the PCB. Figure 68. Section View of PowerPAD™ Package and Top View of Solder Mask and PAD 64 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A bq76PL536A www.ti.com SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 10.2 Layout Example VSYS CBAT BAT BAT VSS Even is GPOUT is not used by host, the GPOUT pin should be pulled up Kelvin connect the BAT pins with PACK+ connection on the battery pack VDD VDD VDD RSDA RSCL Place close to gauge IC. Trace to pin and VSS should be short VSS BIN CVDD RGPOUT Battery Pack RBIN PACK+ SCL SDA GPOUT Li-Ion Cell TS SCL ,I EDWWHU\ SDFN¶V WKHUPLVWRU ZLOO not be connected to BIN pin, a 10-k pulldown resistor should be connected to the BIN pin. SDA The BIN pin should not be shorted directly to VDD or VSS. + RTHERM Protection IC PACKNFET NFET GPOUT Via connects to Power Ground Figure 69. Layout Schematic Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A 65 bq76PL536A SLUSAD3C – JUNE 2011 – REVISED OCTOBER 2016 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 66 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: bq76PL536A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) BQ76PL536APAPR ACTIVE HTQFP PAP 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 BQ76PL536A BQ76PL536APAPT ACTIVE HTQFP PAP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 BQ76PL536A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of