BQ76PL536TPAPRQ1

bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com 3 to 6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for EV and HEV Applications Check for Samples: bq76PL536-Q1 FEATURES APPLICATIONS • • • • • • • • • 1 2 • • • • • • • • • 3 to 6 Series Cell Support, All Chemistries Hot-Pluggable High-Speed SPI for Data Communications Stackable Vertical Interface No Isolation Components Required Between ICs Qualified for Automotive Applications Temperature Range –40°C to 105°C High-Accuracy Analog-to-Digital Converter (ADC): – ±1 mV Typical Accuracy – 14-Bit Resolution, 6-µs Conversion Time – Nine ADC Inputs: 6 Cell Voltages, 1 Six-Cell Brick Voltage, 2 Temperatures, 1 General-Purpose Input – Dedicated Pins for Synchronizing Measurements Configuration Data Stored in ECC-OTP Registers Built-In Comparators (Secondary Protector) for: – Over- and Undervoltage Protection – Overtemperature Protection – Programmable Thresholds and Delay Times – Dedicated Fault Output Signals Cell Balancing Control Outputs With Safety Timeout – Balance Current Set by External Components Supply Voltage Range from 6 V to 30 V Continuous and 36 V Peak Low Power: – Typical 12-µA Sleep, 45-µA Idle Integrated Precision 5-V, 3-mA LDO Electric and Hybrid Electric Vehicles E-Bike and E-Scooter Uninterruptible Power Systems (UPS) Large-Format Battery Systems DESCRIPTION The bq76PL536-Q1 is a stackable three to six series cell lithium-ion battery pack protector and analog front end (AFE) that incorporates a precision analog-to-digital converter (ADC); independent cell voltage and temperature protection; cell balancing, and a precision 5-V regulator to power user circuitry. The bq76PL536-Q1 integrates a voltage translation and precision analog-to-digital converter system to measure battery cell voltages with high accuracy and speed. The bq76PL536-Q1 provides full protection (secondary protection) for overvoltage, undervoltage, and overtemperature conditions. When safety thresholds are exceeded, the bq76PL536-Q1 sets the FAULT output. No external components are needed to configure or enable the protection features. Cell voltage and temperature protection functions are independent of the ADC system. Programmable protection thresholds and detection delay times are stored in Error Check/Correct (ECC) OTP EPROM, which increases the flexibility and reliability of the battery management system. The bq76PL536-Q1 is intended to be used with a host controller to maximize the functionality of the battery management system. However, the protection functions do not require a host controller. The bq76PL536Q1 can be stacked vertically to monitor up to 192 cells without additional isolation components between ICs. A high-speed serial peripheral interface (SPI) bus operates between each bq76PL536-Q1 to provide reliable communications through a high-voltage battery cell stack. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The host microcontroller controls cell balancing of individual cells by setting registers (via SPI) which control the appropriate CBx outputs. These outputs can be turned off via the same control, or automatically by the internal programmable safety timer. The balancing bypass current is set via an external series resistor and FET. TYPICAL IMPLEMENTATION PACK+ CONTROL (North) SPI FAULT ALERT CONV DRDY TO NEXT DEVICE SPI (North) CELL_6 bq76PL536Q1 AUX HO S T I NT ERF ACE (n o t u sed ) GPIO CBx (6) CELL_1 CONTROL (North) SPI (South) SPI ALERT FAULT DRDY CONV CONTROL (South) REG50 ••• CELL_2-5 ••• GPAI SPI (North) CELL_6 GPIO bq76PL536Q1 AUX DRDY FAULT ALERT SPI HO S T I NT ERF ACE HOST INTERFACE CONV CBx (6) ••• CELL_2-5 ••• GPAI CELL_1 South Interface (not used on bottom device) PACK- Figure 1. Simplified System Connection PIN DETAILS PIN FUNCTIONS PIN NAME NO. TYPE (1) DESCRIPTION AGND 15 AI Internal analog VREF (–) ALERT_H 38 O Host-to-device interface – ALERT condition detected in this or higher (North) device ALERT_N 57 I Current-mode input indicating a system status change from the next-higher bq76PL536-Q1 ALERT_S 23 OD AUX 31 O Switched 1-mA limited output from REG50 BAT1 63 P Power-supply voltage, connect to most-positive cell +, tie to BAT2 on PCB (1) 2 Current-mode output indicating a system status change to the next lower bq76PL536-Q1 Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power. Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com PIN NAME NO. TYPE (1) DESCRIPTION BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB CB1 12 O Cell-balance control output CB2 10 O Cell-balance control output CB3 8 O Cell-balance control output CB4 6 O Cell-balance control output CB5 4 O Cell-balance control output CB6 2 O Cell-balance control output CONV_H 36 I Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal sink to VSS. CONV_N 59 OD CONV_S 21 I Input from the adjacent lower bq76PL536-Q1 to initiate a conversion CS_H 43 I Host-to-device interface – active-low chip select from host. Internal 100-kΩ pullup resistor CS_N 52 OD Current-mode output used to select the next-higher bq76PL536-Q1 for SPI communication CS_S 29 I Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536-Q1 DRDY_H 37 O Host-to-device interface – conversion complete, data-ready indication DRDY_N 58 I Current-mode input indicating conversion data is ready from next-higher bq76PL536-Q1 DRDY_S 22 OD FAULT_H 39 O Host-to-device interface – FAULT condition detected in this or higher (North) device FAULT_N 56 I Current-mode input indicating a system status change from the next-higher bq76PL536-Q1 FAULT_S 24 OD Current-mode output GPAI+ 48 AI General-purpose (differential) analog input, connect to VSS if unused. GPAI– 47 AI General-purpose (differential) analog input, connect to VSS if unused. GPIO 45 IOD HSEL 44 I Host interface enable, 0 = enable, 1 = disable LDOA 17 P Internal analog 5-V LDO bypass connection, requires 2.2-µF ceramic capacitor for stability LDOD1 18 P Internal digital 5-V LDO bypass connection 1, requires 2.2-µF ceramic capacitor for stability. This pin is tied internally to LDOD2. This pin should be tied to LDOD2 externally. LDOD2 46 P Internal digital 5-V LDO bypass connection 2, requires 2.2-µF ceramic capacitor for stability. This pin is tied internally to LDOD1. This pin should be tied to LDOD1 externally. NC30 30 – No connection NC51 51 – No connect NC62 62 – No connect REG50 32 P 5-V user LDO output, requires 2.2-µF ceramic capacitor for stability SCLK_H 40 I Host-to-device interface – SPI clock from host SCLK_N 55 OD Current-mode output SPI clock to the next-higher bq76PL536-Q1 SCLK_S 26 I Current-mode input SPI clock from the next-lower bq76PL536-Q1 SDI_H 42 I Host-to-device interface – data from host to device (host MOSI signal) SDI_N 53 OD Current-mode output for SPI data to the next-higher bq76PL536-Q1 SDI_S 28 I Current-mode input for SPI data from the next-lower bq76PL536-Q1 SDO_H 41 O Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA internal pullup SDO_N 54 I Current-mode input for SPI data from the next-lower bq76PL536-Q1 SDO_S 27 OD Current-mode output for SPI data to the next-lower bq76PL536-Q1 TEST 50 I TS1+ 20 AI Differential temperature sensor input TS1– 19 AI Differential temperature sensor input TS2+ 61 AI Differential temperature sensor input TS2– 60 AI Differential temperature sensor input VC0 13 AI Sense-voltage input terminal for negative terminal of first cell (VSS) VC1 11 AI Sense voltage input terminal for positive terminal of the first cell Current-mode output to the next-higher bq76PL536-Q1 to initiate a conversion Current-mode output indicating conversion data is ready to the next lower bq76PL536-Q1 Digital open-drain I/O. A 10-kΩ to 2-MΩ pullup is recommended. Factory test pin. Connect to VSS in user circuitry. This pin includes ~100-kΩ internal pulldown Copyright © 2011, Texas Instruments Incorporated 3 bq76PL536-Q1 SLUSAB1 – MAY 2011 PIN NAME NO. www.ti.com TYPE (1) DESCRIPTION VC2 9 AI Sense voltage input terminal for the positive terminal of the second cell VC3 7 AI Sense voltage input terminal for the positive terminal of the third cell VC4 5 AI Sense voltage input terminal for the positive terminal of the fourth cell VC5 3 AI Sense voltage input terminal for the positive terminal of the fifth cell VC6 1 AI Sense voltage input terminal for the positive terminal of the sixth cell VREF 16 P Internal analog voltage reference (+), requires 10-µF, low-ESR ceramic capacitor to AGND for stability VSS 14, 33, 34, 35 P VSS VSSD 25, 49 P VSS – – Thermal pad on bottom of PowerPAD™ package; this must be soldered to similar-size copper area on PCB and connected to VSS, to meet stated specifications herein. Provides heat-sinking to part. Thermal pad PINOUT DIAGRAM NC51 TEST VSSD BAT1 NC62 TS2+ TS2– CONV_N DRDY_N ALERT_N FAULT_N SCLK_N SDO_N SDI_N CS_N BAT2 PAP Package (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS AGND VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bq78PL536 TQFP-64 48 47 46 45 44 43 GPAI+ GPAI– LDOD2 GPIO HSEL CS_H 42 41 40 39 38 37 36 35 34 33 SDI_H SDO_H SCLK_H FAULT_H ALERT_H DRDY_H CONV_H VSS VSS VSS SDI_S CS_S NC30 AUX REG50 TS1+ CONV_S DRDY_S ALERT_S FAULT_S VSSD SCLK_S SDO_S LDOA LDOD1 TS1– 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0071-04 4 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com ORDERING INFORMATION (1) TA PACKAGE PART NO. –40°C To 105°C 64 TQFP PowerPAD package bq76PL536TPAPQ1 (1) The bq76PL536TPAPQ1 can be ordered in tape and reel as bq76PL536TPAPTQ1 (quantity 1000) or bq76PL536TPAPRQ1 (quantity 250). LDOD LDO-A LDO-D VBAT LDOA REG50 AUX FUNCTIONAL BLOCK DIAGRAM bq76PL536 CONV_N TS2+ OT1 1.25V REF2 DRDY_N TS2– 5V LDO (User Circuitry) FAULT _N TS1– SHIFTED NORTH COMM’s INTERFACE ALERT_N CS_N SCLK_N TS1+ OT2 THERMAL SHUTDOWN OV VC6 UV SDI_N CB6 EPROM OV SDO_N VC5 REGISTERS CONV_H UV DRDY_H SDI_H DIGITAL CONTROL LOGIC SDO_H CONV_S 2.5V DRDY_S FAULT _S ALERT_S CS_S SCLK_S VREF LEVEL SHIFTED SOUTH COMM’s INTERFACE + - CELL BALANCING 14 bit ADC LEVEL SHIFT AND MUX SCLK_H ULTRA-PRECISION BANDGAP CS_H HOST INTERFACE FAULT _H ALERT_H CB5 OV UV OV UV OV VC4 CB4 VC3 CB3 VC2 UV CB2 OV VC1 UV CB1 SDI_S OSC SDO_S VC0 VSS VSS GPAI– GPAI+ DIGITAL AGND VREF ANALOG VSSD GPIO REF2 PROTECTOR COMMUNICATIONS POWER Figure 2. bq76PL536-Q1 Block Diagram Copyright © 2011, Texas Instruments Incorporated 5 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage range, VMAX BAT1, BAT2 (1) (2) –0.3 to 2 0 to 36 TS1+, TS1–, TS2+, TS2– –0.3 to 6 GPAI –0.3 to 6 GPIO –0.3 to VREG50 + 0.3 DRDY_N, SDO_N, FAULT_N, ALERT_N VBAT – 1 to VBAT + 2 CONV_S, SDI_S, SCLK_S, CS_S –2 to 1 CONV_N, SDI_N, SCLK_N, CS_N –0.3 to 36 V –0.3 to 5 –0.3 to VREG50 + 0.3 GPIO CB1…CB6 (CBREF = 0x00) –0.3 to 36 REG50, AUX –0.3 to 6 Storage temperature range, Tstg (2) V VC0 Junction temperature (1) –0.3 to 36 –0.3 to 36 DRDY_S, SDO_S, FAULT_S, ALERT_S Output voltage range, VO UNIT VC1–VC6 VCn to VCn-1, n=1 to 6 Input voltage range, VIN VALUE V 150 °C –65 to 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to VSS of this device except VCn–VC(n+1), where n = 1 to 6 cell voltage. RECOMMENDED OPERATING CONDITIONS Typical values stated where TA = 25ºC and BAT = 20 V, Min/Max values stated where TA = –40˚C to 105ºC and BAT = 7.2 V to 30 V (unless otherwise noted) MIN VBAT Supply voltage BAT VO, Output voltage range 7.2 27 1 4.5 GPAI 0 2.5 0 VREG50 CBn (1) TS1+, TS1–, TS2+, TS2– VC(n – 1) VCn 0 VREG50/2 Non-top IC in stack DRDY_N, SDO_N, FAULT_N, ALERT_N BAT + 1 Top IC in stack DRDY_N, SDO_N, FAULT_N, ALERT_N BAT Non-bottom IC in stack CONV_S, SDI_S, SCLK_S, CS_S –1 Bottom IC in stack CONV_S, SDI_S, SCLK_S, CS_S VSS Non-bottom IC in stack CONV_N, SDI_N, SCLK_N, CS_N 1 Bottom IC in stack CONV_N, SDI_N, SCLK_N, CS_N VSS Non-top IC in stack DRDY_S, SDO_S, FAULT_S, ALERT_S Top IC in stack DRDY_S, SDO_S, FAULT_S, ALERT_S External capacitor REG50 pin 2.2 CVREF External capacitor VREF pin 9.2 CLDO External capacitor LDOx pin (1) (2) 6 Operating temperature (2) UNIT V V V BAT – 1 CREG50 TOPR MAX VCn–VC(n – 1) (1) GPIO VI, Input voltage range NOM BAT µF 15 µF 2.2 3.3 µF –40 105 °C 10 n = 1 to 6 Device specifications stated within this range. Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS SUPPLY CURRENT Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT 12 20 µA ICCSLEEP Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 1 ICCPROTECT Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, AUX, or CBx; CB_CTRL = 0; CBT_CONTROL = 0; CONV_H = 0 (not converting), IO_CTRL[SLEEP] = 0 45 60 µA ICCBALANCE Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx, or AUX; No DC load at CBx; CB_CTRL ≠ 0; CBT_CONTROL ≠ 0; CONV_H = 0 (not converting) , IO_CTRL[SLEEP] = 0 46 60 µA ICCCONVERT Supply current No load at REG50, SCLK_N, SDI_N, SDO_N, FAULT_N, CONV_N, DRDY_S, ALERT_N, TSx or CBx; CONV_S = 1 (conversion active) , IO_CTRL[SLEEP] = 0 10.5 15 mA ICCTSD Supply current Thermal shutdown activated; ALERT_STATUS[TSD] = 1 1.6 mA REG50, INTEGRATED 5-V LDO Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION VREG50 Output voltage IREG50OUT ≤ 0.5 mA, C = 2.2 μF to 22 μF ΔVREG50LINE Line regulation 6 V ≤ BAT ≤ 27 V, IREG50OUT = 2 mA ΔVREG50LOAD Load regulation IREG50MAX Current limit IAUXMAX Maximum load AUX pin AUX output I = 1 mA, max. capacitance = VREG50 Capacitor: CVAUX ≤ CVREG50 / 10 RAUX MIN TYP MAX 4.9 5 5.1 V 10 25 mV 0.2 mA ≤ IREG50OUT ≤ 2 mA 15 0.2 mA ≤ IREG50OUT ≤ 5 mA 25 12 25 UNIT mV 35 mA 5 mA 50 Ω LEVEL SHIFT INTERFACE Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) TEST CONDITION MIN TYP MAX UNIT INTX1 North 1 transmitter current PARAMETER SCLK_N, CS_N, SDI_N, CONV_N 755 840 1020 µA INTX0 North 0 transmitter current CS_N, CONV_N 1 µA INTX0A North 0 transmitter current SCLK_N, SDI_N (BASE device CS_H = 1) INTX0B North 0 transmitter current SCLK_N, SDI_N (BASE device CS_H = 0) ISRX South 1 receiver threshold ISRXH ISTX1 1 µA 6 8 10 µA SCLK_S, CS_S, SDI_S, CONV_S 525 620 665 µA South receiver hysteresis SCLK_S, CS_S, SDI_S, CONV_S 100 200 350 µA South 1 transmitter current ALERT_N, FAULT_S, DRDY_S 925 1040 1200 µA ISTX0 South 0 transmitter current ALERT_S, FAULT_S, DRDY_S 1 µA ISTX0A South 0 transmitter current SDO_S (BASE device CS_H = 1) ISTX0B South 0 transmitter current SDO_S (BASE device CS_H = 0) INRX North 1 receiver threshold INRXH North receiver hysteresis CIN Input capacitance Copyright © 2011, Texas Instruments Incorporated 1 µA 10 20 30 µA SDO_N, ALERT_N, FAULT_N, DRDY_N 350 420 580 µA SDO_N, ALERT_N, FAULT_N, DRDY_N 100 200 350 µA 15 pF 7 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com HOST INTERFACE Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION VOH Logic-level output voltage, high; SDO_H, FAULT_H, ALERT_H, DRDY CL = 20 pF, IOH < 5 mA (1) VOL Logic-level output voltage, low; SDO_H, FAULT_H, ALERT_H, DRDY CL = 20 pF, IOL < 5 mA (1) VIH Logic-level input voltage, high; SCLK_H, SDI_H, CS_H, CONV VIL Logic-level input voltage, low; SCLK_H, SDI_H, CS_H, CONV CIN Input capacitance SCLK_H, SDI_H, CS_H, CONV ILKG Input leakage current SCLK_H, SDI_H, CS_H, CONV (1) MIN TYP MAX UNIT 4.5 VLDOD V VSS 0.5 V 2 5.2 V VSS 0.8 V 5 pF 1 µA Total simultaneous current drawn from all pins is limited by LDOD current to ≤10 mA. GENERAL PURPOSE INPUT/OUTPUT (GPIO) Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN Vin ≤ VREG50 VIH Logic-level input voltage, high VIL Logic-level input voltage, low VOH Output high-voltage pullup voltage Supplied by external ~100-kΩ resistor VOL Logic-level output voltage, low IOL = 1 mA CIN Input capacitance(1) ILKG Input leakage current TYP MAX 2 UNIT V 0.8 V VREG50 V 0.3 V 5 pF 1 µA CELL BALANCING CONTROL OUTPUT (CBx) Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER CBz Output impedance VRANGE Output V TEST CONDITIONS 1 V < VCELL < 5 V MIN TYP MAX UNIT 80 100 120 kΩ VCn V VCn-1 ANALOG-TO-DIGITAL CONVERTER ADC Common Specifications Typical values stated where TA = 25°C and BAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and BAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER tCONV_START CONV high to conversion start (1) TEST CONDITION (2) (3) ADC_CONTROL[ADC_ON] = 1 MAX 6 6.6 Conversion time per selected channel (3) (4) ILKG Input leakage current Not converting 5.4 UNIT µs µs 500 tCONV 8 TYP 5.4 ADC_CONTROL[ADC_ON] = 0 ADC_CONTROL[ADC_ON] = 1 FUNCTION_CONFG[ADCTx]=00 (1) (2) (3) (4) MIN 6 6.6 µs VOT for tOT ALERT_S ALERT_H ALERT ALERT_STATUS[OT2] OT1 VTS1 > VOT for tOT ALERT_S ALERT_H ALERT ALERT_STATUS[OT1] Fault Recovery Procedure When any error flag in DEVICE_STATUS[], FAULT_STATUS[], or ALERT_STATUS[] is set and latched, the state can only be cleared by host communication via SPI. Writing to the respective FAULT_STATUS or ALERT_STATUS register bit with a 1 clears the latch for that bit. The exceptions are the two FORCE bits, which are cleared by writing a 0 to the bit. The FAULT_STATUS[] and ALERT_STATUS[] register bits are read-only, with the exception of the FORCE bit, which may be directly written to either a 1 or 0. Secondary Protector Built-In Self-Test Features The secondary protector functions have built-in test for verifying the connections through the signal chain of ICs in the stack back to the host CPU. This verifies the wiring, connections, and signal path through the ICs by forcing a current through the signal path. To implement this feature, host firmware should set the FAULT[FORCE] or ALERT[FORCE] bit in the top-most device in the stack. The device asserts the associated pin on the South interface, and it propagates down the stack, back to the base device. The base device in turn asserts the FAULT_H (ALERT_H) pin to the host, allowing the host to check for the received signal and thereby verify correct operation. CELL BALANCING The bq76PL536-Q1 has six dedicated outputs (CB1…CB6) that can be used to control external N-FETs as part of a cell balancing system. The implementation of appropriate algorithms is controlled by the system host. The CB_CTRL[CBAL1–6] bits control the state of each of the outputs. The outputs are copied from the bit state of the CB_CTRL register, i.e., a 1 in this register activates the external balance FET by placing a high on the associated pin. The CBx pins switch between approximately the positive and negative voltages of the cell across which the external FET is connected. This allows the use of a small, low-cost N-FET in series with a power resistor to provide cell balancing,. 24 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Cell Balance Control Safety Timer The CBx outputs are cleared when the internal safety timer expires. The internal safety timer (CB_TIME) value is programmed in units of seconds or minutes (range set by CB_CTRL bit 7) with an accuracy of ±10%. The timer begins when any CB_CTRL bit changes from 0 to 1. The timer is reset if all CB_CTRL bits are modified by the host from 1 to 0, or by expiration of the timing period. The timing begins counting the programmed period from start each time the CB_CTRL[] register is programmed from a zero to a non-zero value in the lower six bits. In example, if the CB_TIME[] is set for 30 s, then one or more bits are set in the CB_CTRL[] register to balance the corresponding cells; then after 10 s the user firmware sets CB_CTRL[] to 0x00, takes a measurement, then reprograms CB_CTRL[] with the same or new bit pattern, the timer begins counting 30 s again before expiring and disabling balancing. This restart occurs each time the CB_CTRL bits are set to a non-zero value. If this is done at a greater rate than the balancing period for which timer CB_TIME[] is set, balancing is effectively never disabled – until the timer is either allowed to expire without changing the CB_CTRL[] register to a non-zero value, or the CB_CTRL[] register is set to zero by the user firmware. If the CB_CTRL[] register is not manipulated from zero to non-zero while the timer is running, the timer expires as expected. Alterations of the value from a non-zero to a different non-zero value do not restart the timer (i.e., from 0x02 to 0x03, etc). While the timer is running, the host may set or reset any bit in the CB_CTRL[] register at any time, and the CBx output follows the bit. The host may re-program the timer at any time. The timer must always be programmed to allow the CBx outputs to be asserted. While the timer is non-zero, the CB_CTRL[] settings are reflected at the outputs. During periods when the timer is actively running (not expired), then DEVICE_STATUS[CBT] is set. OTHER FEATURES AND FUNCTIONS Internal Voltage Regulators The bq76PL536-Q1 derives power from the BAT pin using several internal low dropout (LDO) voltage regulators. There are separate LDOs for internal analog circuits (5 V at LDOA), digital circuits (5 V at LDOD1 and LDOD2), and external, user circuits (5 V at REG50). The BAT pin should be connected to the most-positive cell input from cell 3, 4, 5, or 6, depending on the number of cells connected. Locate filter capacitors as close to the IC as possible. The internal LDOs and internal VREF should not be used to power external circuitry, with the exception that LDODx should be used to source power to any external pullup resistors. Internal 5-V Analog Supply The internal analog supply should be bypassed at the LDOA pin with a good-quality, low-ESR, 2.2-μF ceramic capacitor. Internal 5-V Digital Supply The internal digital supply should be bypassed at the LDOD1(2) pin with a good-quality, low-ESR, 2.2-μF ceramic capacitor. The two pins are connected internally and provided to enhance single-pin failure-mode fault tolerance. They should also be connected together externally. Designer Note: Because the LDODx inputs are pulled briefly to ~7 V during programming, the LDODx pins should not be used as sources for pullups to 5-V digital pins, such as HSEL and SPI(bus)_H connected pins. Use VREG50 instead, unless all programming is completed prior to mounting on the application PCB, in which case LDODx is a good choice. Low-Dropout Regulator (REG50) The bq76PL536-Q1 has a low-dropout (LDO) regulator provided to power the thermistors and other external circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-μF capacitor is required for stable operation. The output is internally current-limited. The output is reduced to near zero if excess current is drawn, causing die temperatures to rise to unacceptable levels. The 2.2-µF output capacitor is required whether REG50 is used in the design or not. Copyright © 2011, Texas Instruments Incorporated 25 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com REG50 is disabled in SLEEP mode, and may be turned off under thermal-shutdown conditions, and therefore should not be used as a pullup source for terminating device pins where required. Auxiliary Power Output (AUX) The bq76PL536-Q1 provides an approximately 1-mA auxiliary power output that is controlled via IO_CONTROL[AUX]. This output is taken directly from REG50. The current drawn from this pin must be included in the REG50 current-limit budget by the designer. Undervoltage Lockout and Power-On Reset The device incorporates two comparators to detect low VBAT conditions. The first detects low voltage where some device digital operations are still available. The second, (POR) detects a voltage below which device operation is not ensured. UVLO When the UVLO threshold voltage is sensed for a period ≥ UVLODELAY, the device is no longer able to make accurate analog measurements and conversions. The ADC, cell-balancing and fault-detection circuitry are disabled. The digital circuitry, including host CPU and vertical communications between ICs, is fully functional. Register contents are preserved with the exception that CB_CTRL is set to 0, and the UVLO bit is set in DEVICE_STATUS[]. Power-On Reset (POR) When the POR voltage threshold or lower is sensed for a period ≥ UVLODELAY, the device is no longer able to function reliably. The device is disabled, including all fault-detection circuitry, host SPI communications, vertical communications, etc. After the voltage rises above the hysteresis limit longer than the delay time, the device exits the reset state, with all registers set to default conditions. The FAULT_STATUS[POR] bit is set and latched until reset by the host. The device no longer has a valid address (DEVICE_ADDRESS[AR] = 0, ADDRESS_CONTROL[] = 0). The device should be reprogrammed with a valid address, and any registers re-written if non-default values are desired. Reset Command The bq76PL536-Q1 can also be reset by writing the reset code (0xa5) to the RESET register. All devices respond to a broadcast RESET command regardless of their current assigned address. The result is identical to a POR with the exception that the normal POR period is reduced to several hundred microseconds. Thermal Shutdown (TSD) The bq76PL536-Q1 contains an integrated thermal shutdown circuit whose sensor is located near the REG50 LDO and has a threshold of TSD. When triggered, the REG50 regulator reduces its output voltage to zero, and the ADC is turned off to conserve power. The thermal shutdown circuit has a built-in hysteresis that delays recovery until the die has cooled slightly. When the thermal shutdown is active, the DEVICE_STATUS[TSD] bit is set. The IO_CONTROL[SLEEP] and ALERT[SLEEP] bits also become set to reduce power consumption. WARNING The secondary protector settings are DISABLED in the TSD state. CAUTION Temperature measurement and monitoring do not function due to loss of power if the thermistors are powered from the REG50 or AUX pins and TSD occurs. Protection-dependent schemes implemented by the designer which depend on the REG50 voltage also may not function as a result of loss of the REG50 output. 26 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com GPIO The bq76PL536-Q1 includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pullup (10 kΩ–1 MΩ, typ.) is required on this pin if used as an input. If the pullup is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a pullup is recommended in all designs to prevent an unintentional increase in current draw. SLEEP Functionality The bq76PL536-Q1 provides the host a mechanism to put the part into a low-power sleep state by setting the IO_CONTROL[SLEEP] bit. When this bit is set/reset, the following actions occur: Sleep State Entry (bit set) If a conversion is in progress, the device waits for it to complete, then sets DRDY true (high). The device sets the ALERT_STATUS[SLEEP] bit, which in turn causes the ALERT pin to be asserted. The device gates off all other sources of FAULT or ALERT except ALERT[SLEEP]. The existing state of the FAULT and ALERT registers is preserved. The host should service and reset the ALERT generated by the SLEEP bit being set to minimize SLEEP state current draw by writing a 1 to ALERT[SLEEP] followed by a 0 to ALERT[SLEEP]. The ALERT North-South signal chain can draw up to ~1 mA of current when active, so this ALERT source should be cleared prior to the host entering the SLEEP state of its own. This signaling is provided to notify the host that the unmonitored/unprotected state is being entered. The REG50 LDO is shut down and the output is allowed to float. The ADC, its reference, and clocks are disabled. The COV, CUV, and OT circuits are disabled, and their band-gap reference shut off. Note that this effectively removes protection and monitoring from the cells; the designer should take the necessary design steps and verifications to ensure the cells cannot be put into an unsafe condition by other parts of the system or usage characteristics. IO_CONTROL[TS1(2)] bits are not modified. The host must also set these bits to zero to minimize current draw of the thermistors themselves. SPI communications are preserved; all registers may be read or written. Sleep State Exit (Bit Reset) VREG50 operation is restored. COV, CUV, OT circuits are re-enabled. The ADC circuitry returns to its former state. Note that there is a warm-up delay associated with the ADC enable, the same delay as specified for enabling from a cold start. The FAULT and ALERT registers are restored to their pre-SLEEP state. If a FAULT or ALERT condition was present prior to SLEEP, the FAULT or ALERT pin is immediately asserted. IO_CONTROL[TS1(2)] should be set by the host if the OT function or temperature measurement functions are desired. COMMUNICATIONS SPI Communications – Device to Host Device-to-host (D2H) mode is provided on the SPI interface pins for connection to a local host microcontroller, logic, etc. D2H communications operate in voltage mode as a standard SPI interface for ease of connection to the outside world from the bq76PL536-Q1 device. Standard TTL-compatible logic levels are presented. All relevant SPI timing and performance parameters are met by this interface. The host interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. The SPI clock is normally low; data changes on rising edges, and is sampled on the falling edge. All transfers are MSB-first. Copyright © 2011, Texas Instruments Incorporated 27 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com The pins of the base IC (only) in a stack should have the SCLK_H and SDI_H pins terminated with pullups to minimize current draw of the part if the host ever enters a state where the pins are not driven, i.e., held in the high-impedance state by the host. In non-base devices, the _H pins are forced to be all outputs driven low when the HSEL pin is high. In non-base devices, all _H pins should remain unconnected. The CS_H has a pullup resistor of approximately 100 kΩ. SDO_H is a 3-state output and is terminated with a weak pullup. Designer Note: When VBAT is at or below the UVLO trip point voltage, the internal LDO which supplies the xxxx_H host SPI communications pins (VLODx) begins to fall out of regulation. The output high voltage on the xxxx_H pins falls off with the LDO voltage in an approximately linear manner until at the POR voltage trip point it is reduced to approximately 3.5 V. This action is not tested in production. Application Notes on the Host SPI Interface Pin States The CS_H pin is active-low. The host asserts the pin to a logic zero to initiate communications. The CS pin should remain low until the end of the current packet. When the CS_H pin is asserted, the SPI receiver and interface of the device are reset and resynchronized. This action ensures that a slave device that has lost synchronization during a previous transmission or as the result of noise on the bus does not remain permanently hung. CS_H must be driven false (high) between packets; see AC Timing Characteristics for timing details. Device-to-Device Vertical Bus (VBUS) Interface Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides common-mode voltage isolation between successive bq76PL536-Q1s. This vertical bus (VBUS) is found on the _N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed. The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of bq76PL536-Q1s. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the same name, but opposite suffix. All pins operate within the voltages present at the BAT and VSS pins. Use caution; these pins may be several hundred volts above system ground, depending on their position in the stack. Designer Note: North (_N) pins of the top, most-positive device in the stack should be connected to the BAT1(2) pins of the device for correct operation of the string. South (_S) pins of the lowest, most-negative device in the stack should be connected to VSS of the device. The maximum SCLK frequency is limited by the number of devices in the vertical stack and other factors. Each device imposes an approximately 30-ns delay on the round trip communications speed, i.e., from SCLK rising (an input to all devices) to the SDO pin transitioning requires ~30 ns per device. The designer must add to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in series with the connection, and any other wiring or cabling between devices in the system. To maximize speed, these other system components should be carefully selected to minimize delays and other detrimental effects on signal quality. Wiring and connectors should receive special attention to their transmission line characteristics. Other factors which should be considered are clock duty cycle, clock jitter, temperature effects on clock and system components, user-selected drive level for the level-shift interface, and desired design margin. The VBUS SPI interface is placed in a low-power mode when CS_H is not asserted on the base device. The CS_N/S pins are asserted by a logic high on the vertical interface bus (logically inverted from CS_H). This creates a default VBUS CS condition of logic low, reducing current consumption to a minimum. To reduce power consumption of the SPI interface to a minimum, the SCLK_H and SDI_H should be maintained at a logic low (de-asserted) while CS_H is asserted (low). Most SPI buses are operated this way by microcontrollers. The VBUS versions of these signals are not inverted from the host interface. The device also de-asserts by default the SDO_N/S pins to minimize power consumption. 28 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Packet Formats Data Read Packet When the bq76PL536-Q1 is selected (CS_S [CS_H for first device] is active and the bq76PL536-Q1 has been addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N pin of the next device down the stack. This continues to the first device in the stack, where the data in from the SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC as the last byte sent. CS n + 1 placeholder bytes SDI DEV ADDR REG ADDR CNT = n 0x00 0x00 0x00 0x00 SDO 0x00 0x00 0x00 READ 1 READ 2 READ n... CRC 1 byte time Figure 8. READ Packet Format Read Packet 0 Device Address R/W 0 Start Reg Address Read Length n Read Data 1 CS Assertion Read Data n CRC Figure 9. READ Packet Detail Data Write Packet When the bq76PL536-Q1 is selected (CS_S is active and the bq76PL536-Q1 has been addressed) and a write request has been initiated, the bq76PL536-Q1 receives data through the SDI_S pin, which is connected to the SDO_N of the lower device. For the first device in the stack, the data is input to the SDI_H pin from the host, and transmitted up the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device checks the CRC, which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is invalid or missing, the device asserts the ALERT_S signal to the next lower device, which ripples down the stack to the ALERT_H pin on the lowest device. The host should then take action to clear the condition. Unused or undefined register bits should be written as zeros. CS Start of next packet SDI DEV ADDR REG ADDR WRT DATA CRC DEV ADDR REG ADDR ... 1 byte time Figure 10. WRITE Packet Format Copyright © 2011, Texas Instruments Incorporated 29 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Write Packet 0 Device Address R/W 1 Reg Address Reg Data CS Assertion CRC Figure 11. WRITE Packet Detail Broadcast Writes The bq76PL536-Q1 supports broadcasting single register writes to all devices. A write to device address 0x3f is recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all registers in the stack of devices. This also permits synchronizing all ADC conversions by a firmware command sent to the CONVERT_CTRL[] register as an alternative to using the CONV and DRDY pins. Communications Packet Structure The bq76PL536-Q1 has two primary communication modes via the SPI interface. These two modes enable single-byte read / write and multiple data reads. All writes are single-byte; the logical address is shifted one bit left, and the LSB = 1 for writing. All transactions are in the form of packets comprising: BYTE DESCRIPTION #1 6-bit bq76PL536-Q1 slave address + R/W bit 0b0xxx xxxW #2 Starting data-register offset #3 Number of data bytes to be read (n) (omitted for writes) #4 to 3+n Data bytes #4+n CRC (omit if IO_CONFIG[CRC_DIS] = 1) CRC Algorithm The cyclic redundancy check (CRC) is a CRC-8 error-checking byte, calculated on all the message bytes (including addresses). It is identical in structure to the SMBus 2.0 packet error check (PEC), and is also known as the ATM-8 CRC. The CRC is appended to the message for all SPI packets by the device that supplied the data as the last byte in the packet (when IO_CONTROL[CRC] == 1). Each bus transaction requires a CRC calculation by both the transmitter and receiver within each packet. The CRC is calculated in a way that conforms to the polynomial, C(x) = x8 + x2 + x1 + 1 and must be calculated in the order of the bits as received, MSB first. The CRC calculation includes all bytes in the transmission, including address, command, and data. When reading data from the device, the CRC is based on the ADDRESS + FIRST_REGISTER + LENGTH + returned_device_data[n]. The stuff-bytes used to clock out the data from the IC are not used as part of the calculation, although if the value 0x00 is used, the 0s have no effect on the CRC. CRC verification is performed by the receiver when the CS_x line goes false, indicating the end of a packet. If the CRC verification fails, the message is ignored (discarded), the CRC failure flag is set in the FAULT_STATUS[CRC] register, and the FAULT line becomes asserted and latched until the error is read and cleared by the host. The CRC bit returned in the FAULT_STATUS[] register reflects the last packet received, not the CRC condition of the packet reading the FAULT_STATUS contents. CRC errors should be handled at a high priority by the host controller, before writing to additional registers. Data Packet Usage Examples The bq76PL536-Q1 can be enabled via the host to read just the specific voltage data which would require a total of 2 written bytes (chip address and R/W [#1] + first (starting) register offset [#2]) + LENGTH [#3] and 13 stuff bytes (12 [n] data bytes + CRC). 30 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 www.ti.com SLUSAB1 – MAY 2011 The data packet can be periodically expanded to accommodate temperature and GPAI readings as well as device status as needed by changing the REGISTER_FIRST offset and LENGTH values. Device Addressing Each individual device in the series stack requires an address to allow it to be communicated with. Each bq76PL536-Q1 has a CS_S and CS_N that are used in assigning addresses. Once addresses have been assigned, the normal operation of the CS_N/S lines is asserted (logic high) during communications, and the appropriate bq76PL536-Q1 in the stack responds according to the address transmitted as part of the packet. When the bq76PL536-Q1 is reset, the DEVICE_STATUS[AR] (address request) flag is cleared, the address register is set to 0x00, and ALERT_S is set and passed down the stack. In this state, where address = 0x00, the CS_N signal is forced to a de-asserted state (CS is not passed north when an address = 0). In this manner, after a reset the host is assured that a response at address 0x00 is from the first physical device in the stack. After address assignment of the current device, the host is assured that the next response at address 0x00 is from the next physical device in the stack. Once a valid address is assigned to the device, the CS_N signal responds normally, and follows the CS_H or CS_S signal, propagating to the next device in the stack. Valid addresses are in the range 0x01 through 0x3e. 0x00 is reserved for device discovery after reset. 0x3f is reserved as a broadcast address for all devices. Designer Note: Broadcast messages are only received by devices with a valid address, and the next higher device. Any device with an address of 0x00 blocks messages to devices above it. A broadcast message may not be received by all devices in a stack in situations where some devices do not have a valid address. Copyright © 2011, Texas Instruments Incorporated 31 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com All devices: ADDRESS = 0x?? (unknown) expected = # devices in stack START look_for = 0; Send BROADCAST_RESET Note: validated = one more than devices found at this point look_for++; n = 0; n++; Assign unique address (n) to this device @address 0x00 Assign ADDRESS Write Dev[0]ADDR_CTRL = n Validation test: Read same device for unique address (n) just assigned Read Dev[n] ADDR_CTRL[] Validate device was successfully found and addressed N Dev[n]ADDR_CTRL[] = n? Y This loop finds one new device per iteration n < look_for? Y N (Implied: n == look_for here) This loop resets all addressed devices, then looks for all previously found+1 devices again. Corrects any addressing faults in the stack n < expected? Y N (Implied: n == expected here) N All devices found? n == expected? Y Error() Success Figure 12. Address Discovery and Assignment Algorithm 32 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Once the address is written, the ADDRESS_CONTROL[AR] bit is set which is copied to the DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow (asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack. If a device loses its address through a POR or it is replaced then this device will be the highest logical device in the stack able to be addressed (0x00) as its CS_N will be disabled and the addressing process is required to be undertaken for this, and higher devices. REGISTER ARCHITECTURE I/O Register Details The bq76PL536-Q1 has 48 addressable I/O registers. These registers provide status, control, and configuration information for the battery protection system. Reserved registers return 0x00. Unused registers should not be written to; the results are undefined. Unused or undefined bits should be written as zeros, and will always read back as zeros. Several types of registers are provided, detailed as follows. Register Types Read-Only (Group 1) These registers contain the results of conversions, or device status information set by internal logic. The contents are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are changed by either a conversion command, or when there is an internal state change (i.e., a fault condition is sensed). Read / Write (Group 2) This register group modifies the operations or behavior of the device, or indicates detailed status in the ALERT_STATUS[] and FAULT_STATUS[] registers. The contents are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are changed either by a conversion command, or when there is an internal state change (i.e., a fault condition is sensed). Contents may also be changed by a write from the host CPU to the register. Writes may only modify a single register at a time. If CRCs are enabled, the write packet is buffered until the CRC is checked for correctness. Packets with bad CRCs are discarded without writing the value to the register, after setting the FAULT_STATUS[CRC] flag. Unused or undefined bits in any register should be written as zeros, and will always read back as zeros. SPI DE -SERIALIZER INTERNAL DATA BUS CONTROL, STATUS & DATA REGISTERS REGISTER CRC CHECK LOGIC 7 6 5 4 3 2 1 0 WRITE FAULT _STATUS FLAGS CRC_ERR Figure 13. Register Group2 Architecture Copyright © 2011, Texas Instruments Incorporated 33 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Read / Write, Initialized From EPROM (Group3) These registers control the device configuration and functionality. The contents of the registers are initialized from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command. This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after any reset, without host CPU involvement. These registers may only be modified by using a special, sequential-write sequence to guard against accidental changes. The value loaded from EPROM at reset (or by command) may be temporarily overridden by using the special write sequence. The temporary value is overwritten to the programmed EPROM initialization value by the next reset or command to reload. To write to a these protected registers, first write 0x35 to SHDW_CONTROL[], immediately followed by the write to the desired register. Any intervening write cancels the special sequence. To re-initialize the entire set of Group3 registers to the EPROM defaults, write the value 0x27 to SHDW_CONTROL[]. These registers are further protected against corruption by a ninth parity bit that is automatically updated when the register is written using even parity. If the contents of the register ever become corrupted, the bad parity causes the ALERT_STATUS[PARITY] bit to become set, alerting the host CPU of the problem. The EPROM-stored constants are programmed by writing the values to the register(s), then applying the programming voltage to the LDODx pins, then issuing the EPROM_WRITE command to register E_EN[]. All Group3 registers are programmed simultaneously, and this operation can only be performed once to the one-time-programmable (OTP) memory cells. The process is not reversible. SPI DE-SERIALIZER INTERNAL DATA BUS REGISTER CONTROL & STATUS BITS CRC CHECK LOGIC PROTECTED REGISTER WRITE-PROTECT KEY 7 6 5 4 3 2 1 0 P STATUS FLAGS PARITY LOGIC WRITE PARITY SYNDROME CHECKER / GENERATOR 1 bit error ERROR CHECK / CORRECT (ECC) LOGIC REFRESH-PROTECT KEY POR REFRESH EPROM KEY requires sequenced write to unlock function 2+ bit errors LOAD PROGRAM VOLTAGE & TIMING CONTROL ECC_COR ECC_ERR PGM-PROTECT KEY CHECK BITS 7 6 5 4 No direct access to this register. 3 2 1 0 Cn+1... Cn C0 LOAD signal evaluates ECC syndrome bits Figure 14. Protected Register Group3 Architecture, Simplified View Error Checking and Correcting (ECC) EPROM The EPROM used to initialize this group is also protected by error-check-and-correct (ECC) logic. The ECC bits provide a highly reliable storage solution in the presence of external disturbances. This feature cannot be disabled by user action. Implementation is fully self-contained and automatic and requires no special computations or provisioning by the user. When the Group3 contents are permanently written to EPROM, an additional array of hidden ECC-OTP cells is also automatically programmed. The ECC logic implements a Hamming code that automatically corrects all single-bit errors in the EPROM array, and senses additional multi-bit errors. If any corrections are made, the DEVICE_STATUS[ECC_COR] flag bit is set. If any multi-bit errors are sensed, the ALERT_STATUS[ECC_ERR] flag is set. The corrective action or detection is performed anytime the contents of EPROM are loaded into the registers – POR, RESET, or by SHADOW_LOAD command. Note: The ECC_COR and ECC_ERR bits may glitch during OTP-EPROM writes; this is normal. If this occurs, reset the tripped bit; it should remain cleared. 34 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for bottom stack device) line is activated, and the ALERT_STATUS[] register returns the ECC_ERR and/or I_FAULT bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults in this state. EPROM bits are shipped from the factory set to 0, and must be programmed to the 1 state as required. Table 3. Data and Control Register Descriptions ADDR GROUP ACCESS (1) RESET DESCRIPTION 0x00 1 R 0 Status register GPAI 0x01, 0x02 1 R 0 GPAI measurement data VCELL1 0x03, 0x04 1 R 0 Cell 1 voltage data VCELL2 0x05, 0x06 1 R 0 Cell 2 voltage data VCELL3 0x07, 0x08 1 R 0 Cell 3 voltage data VCELL4 0x09, 0x0a 1 R 0 Cell 4 voltage data VCELL5 0x0b, 0x0c 1 R 0 Cell 5 voltage data VCELL6 0x0d, 0x0e 1 R 0 Cell 6 voltage data TEMPERATURE1 0x0f, 0x10 1 R 0 TS1+ to TS1– differential voltage data TEMPERATURE2 0x11, 0x12 1 R 0 TS2+ to TS2– differential voltage data RSVD 0x13–0x1f – – – Reserved for future use ALERT_STATUS 0x20 2 R/W 0x80 Indicates source of ALERT signal FAULT_STATUS 0x21 2 R/W 0x08 Indicates source of FAULT signal COV_FAULT 0x22 1 R 0 Indicates cell in OV fault state CUV_FAULT 0x23 1 R 0 Indicates cell in UV fault state PRESULT_A 0x24 1 R 0 Parity result of Group3 protected registers (A) PRESULT_B 0x25 1 R 0 Parity result of Group3 protected registers (B) NAME DEVICE_STATUS 0x26–0x2f – – – Reserved for future use ADC_CONTROL 0x30 2 R/W 0 ADC measurement control IO_CONTROL 0x31 2 R/W 0 I/O pin control CB_CTRL 0x32 2 R/W 0 Controls the state of the cell-balancing outputs CBx CB_TIME 0x33 2 R/W 0 Configures the CB control FETs maximum on time ADC_CONVERT 0x34 2 R/W 0 ADC conversion start 0x35–0x39 – – – Reserved for future use SHDW_CTRL 0x3a 2 R/W 0 Controls WRITE access to Group3 registers ADDRESS_CONTROL 0x3b 2 R/W 0 Address register RESET 0x3c 2 W 0 RESET control register TEST_SELECT 0x3d 2 R/W 0 Test mode selection register RSVD 0x3e – – – Reserved for future use E_EN 0x3f 2 R/W 0 EPROM programming mode enable FUNCTION_CONFIG 0x40 3 R/W EPROM Default configuration of device IO_CONFIG 0x41 3 R/W EPROM I/O pin configuration CONFIG_COV 0x42 3 R/W EPROM Overvoltage set point CONFIG_COVT 0x43 3 R/W EPROM Overvoltage time-delay filter CONFIG_CUV 0x44 3 R/W EPROM Undervoltage setpoint CONFIG_CUVT 0x45 3 R/W EPROM Undervoltage time-delay filter CONFIG_OT 0x46 3 R/W EPROM Overtemperature set point CONFIG_OTT 0x47 3 R/W EPROM Overtemperature time-delay filter USER1 0x48 3 R EPROM User data register 1, not used by device USER2 0x49 3 R EPROM User data register 2, not used by device USER3 0x4a 3 R EPROM User data register 3, not used by device RSVD RSVD (1) Key: R = Read; W = Write Copyright © 2011, Texas Instruments Incorporated 35 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Table 3. Data and Control Register Descriptions (continued) NAME ADDR GROUP ACCESS (1) RESET DESCRIPTION USER4 0x4b 3 R EPROM User data register 4, not used by device RSVD 0x4c–0xff – – – 36 Reserved Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com REGISTER DETAILS DEVICE_STATUS REGISTER (0x00) 7 AR 6 FAULT 5 ALERT 4 – 3 ECC_COR 2 UVLO 1 CBT 0 DRDY The STATUS register provides information about the current state of the bq76PL536-Q1. [7] (ADDR_RQST) This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct address. This bit is a copy of in the ADDRESS_CONTROL[AR] bit. 0 = Address has not been assigned 1 = Address has been assigned [6] (FAULT): This bit indicates that this bq76PL536-Q1 has detected a condition causing the FAULT signal to become asserted. 0 = No FAULT exists 1 = A FAULT exists. Read FAULT_STATUS[] to determine the cause. [5] (ALERT): This bit indicates that this bq76PL536-Q1 has detected a condition causing the ALERT pin to become asserted. 0 = No FAULT exists 1 = An ALERT exists. Read ALERT_STATUS[] to determine the cause. [4] (not implemented) [3] (ECC_COR): This bit indicates a one-bit error has been detected and corrected in the EPROM. 0 = No errors are detected in the EPROM 1 = A one-bit (single bit) error has been detected and corrected by on-chip logic. [2] (UVLO): This bit indicates the device VBAT has fallen below the undervoltage lockout trip point. Some device operations are not valid in this condition. 0 = Normal operation 1 = UVLO trip point reached, device operation is not ensured. [1] (CBT): This bit indicates the cell balance timer is running. 0 = The cell balance timer is has not started or has expired. 1 = The cell balance timer is running. [0] (DRDY): This bit indicates the data is ready to read (no conversions active). 0 = There are conversion(s) running. 1 = There are no conversion(s) running. Copyright © 2011, Texas Instruments Incorporated 37 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com GPAI (0x01, 0x02) 15 GPAI[15] 7 GPAI [7] 14 GPAI [14] 6 GPAI [6] 13 GPAI [13] 5 GPAI [5] 12 GPAI [12] 4 GPAI [4] 11 GPAI [11] 3 GPAI [3] 10 GPAI [10] 2 GPAI [2] 9 GPAI [9] 1 GPAI [1] 8 GPAI [8] 0 GPAI [0] 9 VCELLn[9] 1 VCELLn[1] 8 VCELLn[8] 0 VCELLn[0] The GPAI register reports the ADC measurement of GPAI+/GPAI– in units of LSBs. Bits 15–8 are returned at address 0x01, bits 7–0 at address 0x02. VCELLn REGISTER (0x03…0x0e) 15 VCELLn[15] 7 VCELLn[7] 14 VCELLn[14] 6 VCELLn[6] 13 VCELLn[13] 5 VCELLn[5] 12 VCELLn[12] 4 VCELLn[4] 11 VCELLn[11] 3 VCELLn[3] 10 VCELLn[10] 2 VCELLn[2] The VCELLn registers report the converted data for cell n, where n = 1 to 6. Bits 15–8 are returned at odd addresses (e.g. 0x03), bits 7–0 at even addresses (e.g. 0x04). TEMPERATURE1 REGISTER (0x0f, 0x10) 15 TEMP1[15] 7 TEMP1[7] 14 TEMP1[14] 6 TEMP1[6] 13 TEMP1[13] 5 TEMP1[5] 12 TEMP1[12] 4 TEMP1[4] 11 TEMP1[11] 3 TEMP1[3] 10 TEMP1[10] 2 TEMP1[2] 9 TEMP1[9] 1 TEMP1[1] 8 TEMP1[8] 0 TEMP1[0] The TEMPERATURE1 register reports the converted data for TS1+ to TS1–. Bits 15–8 are returned at odd addresses (e.g., 0x0f), bits 7–0 at even addresses (e.g., 0x10). TEMPERATURE2 REGISTER (0x11, 0x12) 15 TEMP2[15] 7 TEMP2[7] 14 TEMP2[14] 6 TEMP2[6] 13 TEMP2[13] 5 TEMP2[5] 12 TEMP2[12] 4 TEMP2[4] 11 TEMP2[11] 3 TEMP2[3] 10 TEMP2[10] 2 TEMP2[2] 9 TEMP2[9] 1 TEMP2[1] 8 TEMP2[8] 0 TEMP2[0] The TEMPERATURE2 register reports the converted data for TS2+ to TS2–. Bits 15–8 are returned at odd addresses (e.g., 0x11), bits 7–0 at even addresses (e.g., 0x12). ALERT_STATUS REGISTER (0x20) 7 AR 6 PARITY 5 ECC_ERR 4 FORCE 3 TSD 2 SLEEP 1 OT2 0 OT1 The ALERT_STATUS register provides information about the source of the ALERT signal. The host must clear each alert flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack and wiring. [7] AR This bit indicates that the ADDR[0]…[5] bits have been written to a valid address. This bit is an inverted copy of the ADDRESS_CONTROL[AR] bit. It is not cleared until an address has been programmed in ADDRESS_CONTROL and a 1 followed by a 0 (two writes) is written to the bit. 0 = Address has been assigned. 1 = Address has not been assigned (default at RESET). 38 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com [6] (PARITY): This bit is used to validate the contents of the protected Group3 registers. 0 = Group3 protected register(s) contents are valid. 1 = Group3 protected register(s) contents are invalid. Group3 registers should be refreshed from OTP or directly written from the host. [5] (ECC_ERR): This bit is used to validate the OTP register blocks. 0 = No double-bit errors (a corrected one-bit error may/may not exist) 1 = An uncorrectable error has been detected in the OTP-EPROM register bank. OTP-EPROM register(s) are not valid. [4] (FORCE): This bit asserts the ALERT signal. It can be used to verify correct operation and connectivity of the ALERT as a part of system self-test. 0 = Deassert ALERT (default) 1 = Assert the ALERT signal. [3] (TSD): This bit indicates thermal shutdown is active. 0 = Thermal shutdown is inactive (default). 1 = Die temperature has exceeded TSD. [2] (SLEEP): This bit indicates SLEEP mode was activated. This bit is only set when SLEEP is first activated; no continuous ALERT or SLEEP status is indicated after the host resets the bit, even if the IO_CTRL[SLEEP] bit remains true. (See IO_CTRL[] register for details.) 0 = Normal operation 1 = SLEEP mode was activated. [1] (OT2): This bit indicates an overtemperature fault has been detected via TS2. 0 = Temperature is lower than or equal to the VOT2 (or input disabled by IO_CONTROL[TS2] = 0). 1 = Temperature is higher than VOT2. [0] (OT1): This bit indicates an overtemperature fault has been detected via TS1. 0 = Temperature is lower than or equal to the VOT1 (or input disabled by IO_CONTROL[TS1] = 0). 1 = Temperature is higher than VOT1. FAULT_STATUS REGISTER (0x21) 7 – 6 – 5 I_FAULT 4 FORCE 3 POR 2 CRC 1 CUV 0 COV The FAULT_STATUS register provides information about the source of the FAULT signal. The host must clear each fault flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the IC stack and wiring. [7] (not implemented) [6] (not implemented) [5] (I_FAULT): The device has failed an internal register consistency check. Measurement data and protection function status may not be accurate and should not be used. 0 = No internal register consistency check fault exists. Copyright © 2011, Texas Instruments Incorporated 39 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com 1 = The internal consistency check has failed self-test. The host should attempt to reset the device, see the RESET section. If the fault persists, the failure should be considered uncorrectable. [4] (FORCE): This bit asserts the FAULT signal. It can be used to verify correct operation and connectivity of the FAULT line as a part of system self-test. 0 = Deassert FAULT (default) 1 = Assert the FAULT signal. [3] (POR): This bit indicates a power-on reset (POR) has occurred. 0 = No POR has occurred since this bit was last cleared by the host. 1 = A POR has occurred. This notifies the host that default values have been loaded to Group1 and Group2 registers, and OTP contents have been copied to Group3 registers. [2] (CRC): This bit indicates a garbled packet reception by the device. 0 = No errors 1 = A CRC error was detected in the last packet received. [1] (CUV): This bit indicates that this bq76PL536-Q1 has detected a cell undervoltage (CUV) condition. Examine CUV_FAULT[] to determine which cell caused the ALERT. 0 = All cells are above the CUV threshold (default). 1 = One or more cells is below the CUV threshold. [0] (COV): This bit indicates that this bq76PL536-Q1 has detected a cell overvoltage (COV) condition. Examine COV_FAULT[] to determine which cell caused the FAULT. 0 = All cells are below the COV threshold (default). 1 = One or more cells is above the COV threshold. COV_FAULT REGISTER (0x22) 7 – 6 – [0..5] (OV[1]..[6]): 5 OV[6] 4 OV[5] 3 OV[4] 2 OV[3] 1 OV[2] 0 OV[1] These bits indicate which cell caused the DEVICE_STATUS[COV] flag to be set. 0 = Cell[n] does not have an overvoltage fault (default). 1 = Cell[n] does have an overvoltage fault. CUV_FAULT REGISTER (0x23) 7 – b0..5 (UV[1]..[6]): 6 – 5 UV[6] 4 UV[5] 3 UV[4] 2 UV[3] 1 UV[2] 0 UV[1] These bits indicate which cell caused the DEVICE_STATUS[CUV] flag to be set. 0 = Cell[n] does not have an undervoltage fault (default). 1 = Cell[n] does have an undervoltage fault. PARITY_H REGISTER (0x24) (PRESULT_A (R/O)) 7 OTT 40 6 OTV 5 CUVT 4 CUVV 3 COVT 2 COVV 1 IO 0 FUNC Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com The PRESULT_A register holds the parity result bits for the first eight Group3 protected registers. PARITY_H REGISTER (0x25) (PRESULT_B (R/O)) 7 0 6 0 5 0 4 0 3 USER4 2 USER3 1 USER2 0 USER1 The PRESULT_B register holds the parity result bits for the second eight Group3 protected registers. ADC_CONTROL REGISTER (0x30) 7 – 6 ADC_ON 5 TS2 4 TS1 3 GPAI 2 CELL_SEL[2] 1 CELL_SEL[1] 0 CELL_SEL[0] The ADC_CONTROL register controls some features of the bq76PL536-Q1. [7] not implemented. Must be written as 0. [6] (ADC_ON): This bit forces the ADC subsystem ON. This has the effect of eliminating internal start-up and settling delays, but increases current consumption. 0 = Auto mode. ADC subsystem is OFF until a conversion is requested. The ADC is turned on, a wait is applied to allow the reference to stabilize. Automatically returns to OFF state at end of requested conversion. Note that there is a start-up delay associated with turning the ADC to the ON state in this mode. 1 = ADC subsystem is ON, regardless of conversion state. Power consumption is increased. [5..4] (TS[1]..[0]): [3] (GPAI): These two bits select whether any of the temperature sensor inputs are to be measured on the next conversion sequence start. TS[1] TS[0] Measure T 0 0 None (default) 0 1 TS1 1 0 TS2 1 1 Both This bit enables and disables the GPAI input to be measured on the next conversion-sequence start. 0 = GPAI is not selected for measurement. 1 = GPAI is selected for measurement. [2–0] (CELL_SEL): These three bits select the series cells for voltage measurement translation on the next conversion sequence start. CELL_SEL[2] CELL_SEL[1] CELL_SEL[0] 0 0 0 Cell 1 only 0 0 1 Cells 1-2 0 1 0 Cells 1-2-3 0 1 1 Cells 1-2-3-4 1 0 0 Cells 1-2-3-4-5 1 0 1 Cells 1-2-3-4-5-6 Other Copyright © 2011, Texas Instruments Incorporated SELECTED CELL Cell 1 only 41 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com IO_CONTROL REGISTER (0x31) 7 AUX 6 GIPI_OUT 5 GPIO_IN 4 0 3 0 2 SLEEP 1 TS2 0 TS1 The IO_CONTROL register controls some features of the bq76PL536-Q1 external I/O pins. [7] (AUX): Controls the state of the AUX output pin, which is internally connected to REG50. 0 = Open 1 = Connected to REG50 [6] (GPIO_OUT): Controls the state of the open-drain GPIO output pin; the pin should be programmed to 1 to use the GPIO pin as an input. 0 = Output low 1 = Open-drain [5] (GPIO_IN): Represents the input state of GPIO pin when used as an input 0 = GPIO input is low. 1 = GPIO input is high. [4] Not implemented. Must be written as 0. [3] Not implemented. Must be written as 0. [2] (SLEEP): Places the device in a low-quiescent-current state. All CUV, COV, and OT comparators are disabled. A 1-ms delay to stabilize the reference voltage is required to exit SLEEP mode and return to active COV, CUV monitoring. 0 = ACTIVE mode 1 = SLEEP mode [1..0] (TSx) Controls the connection of the TS1(2) inputs to the ADC VSS connection point. When set, the TSx(–) input is connected to VSS. These bits should be set to 0 to reduce the current draw of the system. 0 = Not connected 1 = Connected CB_CTRL REGISTER (0x32) 7 – 6 – 5 CBAL[6] 4 CBAL[5] 3 CBAL[4] 2 CBAL[3] 1 CBAL[2] 0 CBAL[1] The CB_CTRL register determines the internal cell balance output state. CB_CTRL b(n = 5 to 0) (CBAL(n + 1)): This bit determines if the CB(n) output is high or low. 0 = CB[n] output is low (default). 1 = CB[n] output is high (active). 42 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com CB_TIME REGISTER (0x33) 7 CBT[7] 6 – 5 CBT[5] 4 CBT[4] 3 CBT[3] 2 CBT[2] 1 CBT[1] 0 CBT[0] The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63 minutes. When set to 0, no balancing can occur – balancing is effectively disabled. [7] Controls minutes/seconds counting resolution. 0 = Seconds (default) 1 = Minutes [5..0] Sets the time duration as scaled by CBT.7 ADC_CONVERT REGISTER (0x34) 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CONV The CONVERT_CTRL register is used to start conversions. [0] (CONV): This bit starts a conversion, using the settings programmed into the ADC_CONTROL[] register. It provides a programmatic method of initiating conversions. 0 = No conversion (default) 1 = Initiate conversion. This bit is automatically reset after conversion begins, and always returns 0 on READ. SHDW_CTRL REGISTER (0x3a) 7 SHDW[7] 6 SHDW[6] 5 SHDW[5] 4 SHDW[4] 3 SHDW[3] 2 SHDW[2] 1 SHDW[1] 0 SHDW[0] The SHDW_CTRL register controls writing to Group3 protected registers. Default at RESET = 0x00. The value 0x35 must be written to this register to allow writing to Group3 protected registers in the range 0x40–0x4f. The register always returns 0x00 on read. The register is reset to 0x00 after any successful write, including a write to non-Group3 registers. A read operation does not reset this register. Writing the value 0x27 results in all Group3 protected registers being refreshed from OTP programmed values. The register is reset to 0x00 after the REFRESH is complete. Copyright © 2011, Texas Instruments Incorporated 43 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com ADDRESS_CONTROL REGISTER (0x3b) 7 AR 6 0 5 ADDR[5] 4 ADDR[4] 3 ADDR[3] 2 ADDR[2] 1 ADDR[1] 0 ADDR[0] The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536-Q1 for communication. The default for this register is 0x00 at RESET. [7] (ADDR_RQST): This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct address. This bit is reflected in the DEVICE_STATUS[AR] bit 0 = Address has not been assigned (default at RESET). 1 = Address has been assigned. [5..0] (ADDR): These bits set the device address for SPI communication. This provides to a range of addresses from 0x00 to 0x3f. Address 0x3f is reserved for broadcast messages to all connected and addressed 76PL536 devices. The default for these 6 bits is 0x00 at RESET. RESET REGISTER (0x3c) 7 RST[7] 6 RST[6] 5 RST[5] 4 RST[4] 3 RST[3] 2 RST[2] 1 RST[1] 0 RST[0] 2 TSEL[2] 1 TSEL[1] 0 TSEL[0] The RESET register allows the host to reset the bq76PL536-Q1 directly. Writing 0xa5 causes the device to RESET. Other values are ignored. TEST_SELECT REGISTER (0x3d) 7 TSEL[7] 6 TSEL[6] 5 TSEL[5] 4 TSEL[4] 3 TSEL[3] The TEST_SELECT places the SPI port in a special mode useful for debug. TSEL (b7–b0) is used to place the SPI_H interface pins in a mode to support test/debug of a string of bq76PL536-Q1 devices. 0 = normal operating mode. When the sequence 0xa4, 0x25 ("JR") is written on subsequent write cycles, the device enters a special TEST mode useful for stack debugging. Writes to other registers between the required sequence bytes results in the partial sequence being voided; the entire sequence must be written again. POR, RESET, or writing a 0x00 to this register location exits this mode. In this state, SPI pin SCLK and SDI become outputs and are enabled, and reflect the state of the SCLK_S, SDI_S pins of the device. SDO remains an output. This allows observation of bus traffic mid-string. The lowest device in the string should not be set to operate in this mode. The user is cautioned to condition the connection to a mid- or top-string device with suitable isolation circuitry to prevent injury or damage to connected devices. Programming the most-negative device on the stack in this mode prevents further communications with the stack until POR, and may result in device destruction; this condition should be avoided. E_EN REGISTER (0x3f) 7 E_EN[7] 6 E_EN [6] 5 E_EN [5] 4 E_EN [4] 3 E_EN [3] 2 E_EN [2] 1 E_EN [1] 0 E_EN [0] The E_EN register controls the access to the programming of the integrated OTP EPROM. This register should be written the value 0x91 to permit writing the USER block of EPROM. Values other than 0x00 and 0x91 are reserved and may result in undefined operation. The next read or write of any type to the device resets (closes) the write window. If a Group3 protected write occurs, the window is closed after the write. 44 Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com FUNCTION_CONFIG REGISTER (0x40) 7 ADCT[1] 6 ADCT[0] 5 GPAI_REF 4 GPAI_SRC 3 CN[1] 2 CN[0] 1 – 0 0 The FUNCTION_CONFIG sets the default configuration for special features of the device. [7..6] (ADCT[0,1]): These bits set the conversion timing of the ADC measurement. [5] (GPAI_REF): ADCT[1] ADCT[0] ~Conversion Time (μs) 0 0 3 0 1 6 (recommended) 1 0 12 1 1 24 This bit sets the reference for the GPAI ADC measurement. 0 = Internal ADC bandgap reference 1 = VREG50 (ratiometric) [4] (GPAI_SRC): This bit controls multiplexing of the GPAI register and determines whether the ADC mux is connected to the external GPAI inputs, or internally to the BAT1 pin. The register results are automatically scaled to match the input. 0 = External GPAI inputs are converted to result in GPAI register 0x01–02. 1 = BAT pin to VSS voltage is measured and reported in the GPAI register. [3..2] (CN[1..0]): These two bits configure the number of series cells used. If fewer than 6 cells are configured, the corresponding OV/UV faults are ignored. For example, if the CN[x] bits are set to 10b (2), then the OV/UV comparators are ignored for cells 5 and 6. CN[1] CN[0] SERIES CELLS 0 0 6 (DEFAULT) 0 1 5 1 0 4 1 1 3 IO_CONFIG REGISTER (0x41) 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CRC_DIS The IO_CONFIG sets the default configuration for miscellaneous I/O features of the device. [0] (CRC_DIS): This bit enables and disables the automatic generation of the CRC for the SPI communication packet. The packet size is determined by the host as part of the read request protocol. The CRC is checked at the deassertion of the CS pin. TI recommends that this bit be changed using the broadcast address (0x3f) so that all devices in a battery stack use the same protocol. 0 = A CRC is expected, and generated as the last byte of the packet. 1 = A CRC is not used in communications. Copyright © 2011, Texas Instruments Incorporated 45 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com CONFIG_COV REGISTER (0x42) 7 DISABLE 6 – 5 COV[5] 4 COV[4] 3 COV[3] 2 COV[2] 1 COV[1] 0 COV[0] The CONFIG_COV register determines cell overvoltage threshold voltage. [7] (DISABLE): Disables the overvoltage function when set 0 = Overvoltage function enabled 1 = Overvoltage function disabled [5..0] (COV[5]…[0]): Configuration bits with corresponding voltage threshold 0x00 = 2 V; each binary increment adds 50 mV until 0x3c = 5 V. CONFIG_COVT REGISTER (0x43) 7 µs/ms 6 – 5 – 4 COVD[4] 3 COVD[3] 2 COVD[2] 1 COVD[1] 0 COVD[0] The CONFIG_COVT register determines cell overvoltage detection delay time. [7] (µs/ms): Determines the units of the delay time, microseconds or milliseconds 0 = Microseconds 1 = Milliseconds [4..0] COVD: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100 Note: When this register is programmed to 0x00, the delay becomes 0s AND the COV state is NOT latched in the COV_FAULT[] register. In this operating mode, the overvoltage state for a cell is virtually instantaneous in the COV_FAULT[] register. This mode may cause system firmware to miss a dangerous cell overvoltage condition. CONFIG_UV REGISTER (0x44) 7 DISABLE 6 – 5 – 4 CUV[4] 3 CUV[3] 2 CUV[2] 1 CUV[1] 0 CUV[0] The CUV register determines cell under voltage threshold voltage. [7] (DISABLE): Disables the undervoltage function when set 0 = Undervoltage function enabled 1 = Undervoltage function disabled [5..0] (CUV[4]…[0]): 46 Configuration bits with corresponding voltage threshold 0x00 = 0.7 V; each binary increment adds 100 mV until 0x1a = 3.3 V. Copyright © 2011, Texas Instruments Incorporated bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com CONFIG_CUVT REGISTER (0x45) 7 µs/ms 6 – 5 – 4 CUVD[4] 3 CUVD[3] 2 CUVD[2] 1 CUVD[1] 0 CUVD[0] The CONFIG_CUVT register determines cell overvoltage detection delay time. [7] (µs/ms): Determines the units of the delay time, microseconds or milliseconds 0 = Microseconds 1 = Milliseconds [4..0] CUVD: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100. Note: When this register is programmed to 0x00, the delay becomes 0s AND the CUV state is NOT latched in the CUV_FAULT[] register. In this operating mode, the overvoltage state for a cell is virtually instantaneous in the CUV_FAULT[] register. This mode may cause system firmware to miss a dangerous cell undervoltage condition. CONFIG_OT REGISTER (0x46) 7 OT2[3] 6 OT2[2] 5 OT2[1] 4 OT2[0] 3 OT1[3] 2 OT1[2] 1 OT1[1] 0 OT1[0] The CONFIG_OT register holds the configuration of the overtemperature thresholds for the two TS inputs. For each respective nibble (OT1 or OT2), the value 0x0 disables this function. Other settings program a trip threshold. See the Ratiometric Sensing section for details of setting this register. Values above 0x0b are illegal and should not be used. CONFIG_OTT REGISTER (0x47) 7 COTD[7] 6 COTD[6] 5 COTD[5] 4 COTD[4] 3 COTD[3] 2 COTD[2] 1 COTD[1] 0 COTD[0] The CONFIG_OTT register determines cell overtemperature detection delay time. 0x01 = 10 ms; each binary increment adds 10 ms until 0xff = 2.55 seconds. Note: When this register is programmed to 0x00, the delay becomes 0s AND the OT state is NOT latched in the ALERT_STATUS[] register. In this operating mode, the overtemperature state for a TSn input is virtually instantaneous in the register. This mode may cause system firmware to miss a dangerous overtemperature condition. USERx REGISTER (0x48–0x4b) (USER1–4) 7 USER[7] 6 USER[6] 5 USER[5] 4 USER[4] 3 USER[3] 2 USER[2] 1 USER[1] 0 USER[0] The four USER registers can be used to store user data. The part does not use these registers for any internal function. They are provided as convenient storage for user S/N, date of manufacture, etc. Copyright © 2011, Texas Instruments Incorporated 47 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com PROGRAMMING THE EPROM CONFIGURATION REGISTERS The bq76PL536-Q1 has a block of OTP-EPROM that is used for configuring the operation of the bq76PL536-Q1. Programming of the EPROM should take place during pack/system manufacturing. A 7-V (VPP) pulse is required on the PROG pin. The part uses an internal window comparator to check the voltage, and times the internal pulse delivered to the EPROM array. The user first writes the desired values to all of the equivalent Group3 protected register addresses. The desired data is written to the appropriate address by first applying 7 V to the LDOD1(2) pins. Programming then performed by writing to the EE_EN register (address 0x3f) with data 0x91. After a time period > 1500 µs, the 7 V is removed. Nominally, the voltage pulse should be applied for approximately 2–3 ms. Applying the voltage for an extended period of time may lead to device damage. The write is self-timed internally after receipt of the command. The following flow chart illustrates the procedure for programming. No Host writes data to Registers in USER Block 0x40–0x47 Verify Data in 0x40–0x47 Enable Group3 Write: Write: 0x35 to SHDW_CTRL (0x3a) Copy EPROM back to Registers Write 0x27 to SHDW_CTRL (0x3a) Write data to Registers Write: 0xnn to 0x4x Read Register block 0x40–0x4b ADDR++ ADDR > 0x4b? Contents match programmed value? Yes Apply 7 V to LDOD1(2) pin Nominal time ~ 2 ms to 3 ms No Yes Verify ECC bits Read DEVICE_STATUS [ECC_COR] Read ALERT_STATUS [PARITY] Read ALERT_STATUS [PARITY] Host enables write to USER Block Write: 0x91 to E_EN @0x3f No All == 0? Remove 7 V from LDOD1(2) pins Yes Programming complete SUCCESS FAIL Figure 15. EPROM Programming 48 Copyright © 2011, Texas Instruments Incorporated 2-VSS C84 .001uf 50V CAP0603 7 TP5 6 5 4 3 3 4 5 6 CELL 10 + CELL 9 + CELL 8 + CELL 7 + 6 7 CELL 1 + CELL 1 - TP1 4 5 3 CELL 4 + CELL 3 + 2 CELL 5 + CELL 2 + 1 CELL 6 + P1 39502-1007_7-POS 1-VSS C51 .001uf 50V CAP0603 TP3 7 2 CELL 11 + CELL 7 - 1 CELL 12 + P2 39502-1007_7-POS CELL 13 - CELL 13 + CELL 14 + CELL 15 + CELL 16 + 1 1-VSS TP2 2-VSS TP4 3-VSS CAUTION HIGH VOLTAGE GROUND PLANE OF CIRCUIT 3 GROUND PLANE OF CIRCUIT 1 GROUND PLANE OF CIRCUIT 2 COMM PINS OF THE CHIP BELOW TO JUST BELOW THE NORTH UNDER THE SOUTH COMM LINES EXTEND THE GROUND PLANE GROUND PLANE OF CIRCUIT 2 3-CELL6 1-CELL0 1-CELL1 1-CELL2 1-CELL3 1-CELL4 1-CELL5 1-CELL6 1-VBAT 2-CELL0 2-CELL1 2-CELL2 2-CELL3 2-CELL4 2-CELL5 2-CELL6 2-VBAT 3-CELL0 3-CELL1 3-CELL2 3-CELL3 3-CELL4 3-CELL5 CELL6 3-VBAT CELL0 CELL1 CELL2 CELL3 CELL4 CELL5 CONV_N CELL6 CELL0 CELL1 CELL2 CELL3 CELL4 CELL5 CELL0 CELL1 CELL2 CELL3 CELL4 CELL5 CELL6 R81 1K RES0603 3-VBAT R143 R144 R145 1K 1K 1K RES0603 RES0603 RES0603 CONV_S R142 1K RES0603 3-VBAT BQ76PL536_CIRCUIT3 SHEET-4 3-VBAT LOCATE R143, R144, R168, R176 CLOSE TO THE MOST NORTH IC R146 1K RES0603 R147 1K RES0603 R148 R149 1K 1K RES0603 RES0603 LOCATE R195, R196, R197, R199 CLOSE TO THE MOST NORTH IC SHEET-3 BQ76PL536_CIRCUIT2 LOCATE R142, R175, R192, R193 CLOSE TO THE MOST SOUTH IC DRDY_N R82 R83 R84 1K 1K 1K RES0603 RES0603 RES0603 DRDR_S R85 1K RES0603 R86 1K RES0603 R91 R92 1K 1K RES0603 RES0603 SHEET-2 BQ76PL536_CIRCUIT1 LOCATE R194, R198, R200, R201 CLOSE TO THE MOST SOUTH IC DRDY_N DRDY_S 2 DRDY_N DRDY_S 3-DRDY_S 2-DRDY_N 2-DRDY_S 1-DRDY_N 1-CELL0 CELL 18 + 3-VBAT 3-ALERT_S 2-ALERT_N 2-ALERT_S 1-ALERT_N CELL 17 + ALERT_N ALERT_S ALERT_N ALERT_S ALERT_N ALERT_S VBAT FAULT_N FAULT_S 3-VBAT FAULT_N FAULT_S 3-FAULT_S 2-FAULT_N 2-FAULT_S 1-FAULT_N 1-CELL0 TP6 SCLK_S P3 39502-1007_7-POS 3-VBAT 2-SCLK_S 1-SCLK_N 1-CELL0 3-CONV_S SCLK_N SCLK_S SCLK_S SCLK_N FAULT_S FAULT_N SDO_S SD0_N SD0_S 2-CONV_N SDO_N SDO_S SDO_N 3-SCLK_S SCLK_N 2-SCLK_N 3-SDO_S 2-SDO_N 2-SDO_S 1-SDO_N 1-CELL0 CONV_N 3-VBAT 3-SDI_S 2-SDI_N 2-SDI_S 1-SDI_N 1-CELL0 2-CONV_S SDI_N SDI_S SDI_N SDI_S SDI_N SDI_S CONV_S CONV_N CONV_S CS_N CS_S CS_N CS_S CS_N CS_S 1-CONV_N 1-CELL0 3-VBAT 3-CS_S 2-CS_N 2-CS_S 1-CS_N 1-CELL0 Copyright © 2011, Texas Instruments Incorporated 1-CELL0 FAULT SPI-SS SPI-SCLK SPI-MOSI SPI-MISO CONV DRDY ALERT 1-SPI-SS 1-SPI-SCLK 1-SPI-MOSI 1-SPI-MISO 1-CONV/RX 1-DRDY/TX 1-ALERT 1-FAULT E 2-VSS 1-VSS 2-VSS C85 .0033uf 50V CAP0603 C52 .0033uf 50V CAP0603 3-VSS R12 100 RES0603 R13 100 RES0603 R14 100 RES0603 R15 100 RES0603 CAUTION HIGH VOLTAGE 1-VSS FAULT 10 9 8 7 6 5 4 SCLK CS MOSI MISO GND CONV DRDY ALERT VSIG 1 3 2 P4 MTA100-HEADER-10PIN DO NOT connect ground references from different IC's. Only the ground reference CELL0 of circuit 1 is safe to connect non-isolated test equipment grounds. The ground (VSS) reference per circuit block is unique. The most negative connection per block "CELL0" is the ground (VSS) reference for each IC. S001 NOTES: INDIVIDUAL GROUND PLANES ARE NECESSARY FOR PROPER NOISE REJECTION AND STABILITY OF THESE CIRCUITS www.ti.com bq76PL536-Q1 SLUSAB1 – MAY 2011 REFERENCE SCHEMATIC Figure 16. Schematic (Page 1 of 4) 49 CELL 1 + 1-VSS [1] 1-CELL2 [1] 1-CELL1 CELL 2 + [1,2] [1] 1-CELL3 CELL 3 + CELL 1 - [1] 1-CELL5 [1] 1-CELL4 CELL 5 + [1] 1-CELL6 CELL 4 + CELL 6 + C9 0.1uf 50V CAP0603 C19 0.1uf 50V CAP0603 C27 0.1uf 50V CAP0603 C37 0.1uf 50V CAP0603 C42 0.1uf 50V CAP0603 C48 0.1uf 50V CAP0603 Q7 FDN359AN SOT-23 R9 47 RES2512 Q4 FDN359AN SOT-23 Z1 5.1 VDC 500mW Q2 SOD-123 FDN359AN SOT-23 Z3 5.1 VDC 500mW SOD-123 R24 47 RES2512 Z5 5.1 VDC 500mW Q6 SOD-123 FDN359AN SOT-23 R38 47 RES2512 Z7 5.1 VDC 500mW SOD-123 R49 47 RES2512 Z9 5.1 VDC 500mW Q8 SOD-123 FDN359AN SOT-23 R69 47 RES2512 SOT-23 Z11 5.1 VDC 500mW Q9 SOD-123 FDN359AN R79 47 RES2512 Z2 5.1VDC SOD-323 Z4 5.1VDC SOD-323 Z6 5.1VDC SOD-323 Z8 5.1VDC SOD-323 Z10 5.1VDC SOD-323 Z12 5.1VDC SOD-323 R7 1M 1% RES0603 R8 1.0K 1% RES0603 C30 0.1uf 50V CAP0603 ** R18 1.0K 1% RES0603 R21 1M 1% RES0603 R22 1.0K 1% RES0603 C32 0.1uf 50V CAP0603 ** R28 1.0K 1% RES0603 R35 1M 1% RES0603 R32 1.0K 1% RES0603 ** C33 0.1uf 50V CAP0603 R40 1.0K 1% RES0603 R44 1M 1% RES0603 R45 1.0K 1% RES0603 ** C38 0.1uf 50V CAP0603 R57 1.0K 1% RES0603 R61 1M 1% RES0603 R62 1.0K 1% RES0603 ** C40 0.1uf 50V CAP0603 R75 1.0K 1% RES0603 R76 1M 1% RES0603 R77 1.0K 1% RES0603 ** C41 0.1uf 50V CAP0603 1-VSS 1-VSS 1-VSS 1-VSS 1-VSS 1-VSS 1-VSS 13 12 11 10 9 8 7 6 5 4 3 2 1 63 64 VC0 CB1 VC1 CB2 VC2 CB3 VC3 CB4 VC4 CB5 VC5 CB6 VC6 BAT1 BAT2 1-VSS C43 ** 0.1uf 50V CAP0603 * C113 33pF 50V CAP0603 1-CONV_N [1] 1-DRDY_N [1] 1-ALERT_N[1] 1-FAULT_N[1] bq76PL536 U1 "Bottom" part connects all _S pins to 1-VSS. 59 CONV_N 58 DRDY_N 57 ALERT_N 56 FAULT_N CONV_S DRDY_S ALERT_S FAULT_S 21 22 23 24 1-CONV_S 1-DRDY_S 1-ALERT_S 1-FAULT_S R80 1.0K 1% RES0603 1-SCLK_N [1] 1-SDO_N [1] 1-SDI_N [1] [1] 1-CS_N SCLK_S SDO_S SDI_S CS_S 26 27 28 29 1-SCLK_S 1-SDO_S 1-SDI_S 1-CS_S 1-VBAT [1] 1-VSS * C105 33pF 50V CAP0603 * 47 48 VREF LDOD2 LDOD1 LDOA AGND 16 46 18 17 15 C39 ** 2.2uf 10V CAP0805 C34 ** 0.1uf 50V CAP0603 1-VSS C24 ** 2.2uf 10V CAP0805 C25 0.1uf 50V CAP0603 1-LDOA R50 0R0 RES0603 R27 1.47K 1% RES0603 1-VSS R124 10K 1% B=3435K NTC0603 R30 100 RES0603 R29 100K RES0603 D1 LTW-C192TL2 White LED 1-VSS Q5 2N7002LT1 SOT-23 R25 2.7K RES0603 1-VSS TP-VSS1 TP-VPROG1 1-LDOD CAUTION HIGH VOLTAGE S002 [1] 1-SPI-MISO [1] 1-SPI-MOSI 1-SPI-SCLK [1] 1-SPI-SS [1] C23 ** 10uf 10V CAP1206 C7 DNP CAP0603 R58 0R0 RES0603 T1 41 SDO_H 42 SDI_H 40 SCLK_H 43 CS_H C6 DNP CAP0603 R33 1.82K 1% RES0603 R71 1.47K 1% RES0603 R123 10K 1% B=3435K NTC0603 1-FAULT [1] 1-ALERT [1] 1-DRDY/TX [1] 1-CONV/RX [1] 45 C4 DNP CAP0603 T2 R63 1.82K 1% RES0603 C21 0.047uf 16V CAP0603 THERMISTOR NTC 10K OHM 1% 0603 PANASONIC PART NUMBER # ERT-J1VG103FA 39 FAULT_H 38 ALERT_H 37 DRDY_H 36 CONV_H GPIO 51 NC2 30 NC1 62 NC3 GPAI- 19 20 60 61 C46 0.047uf 16V CAP0603 CAUTION HIGH VOLTAGE ** - Locate these components very close to bq76PL536 IC. * - Typical value shown. Actual value depends on number of IC's in stack, wiring, etc. Consult applications guide for recommended values. 1-VSS TS1- TS1+ TS2- TS2+ 1-VSS C26 ** 2.2uf 10V CAP0805 * C108 33pF 50V CAP0603 GPAI+ C47 33pF 50V CAP0603 GROUND PLANE OF CIRCUIT 1 50 TEST 44 HSEL 32 REG50 31 AUX VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 49 35 34 33 25 14 TAB 65 50 55 SCLK_N 54 SDO_N 53 SDI_N 52 CS_N GROUND PLANE OF CIRCUIT 2 bq76PL536-Q1 SLUSAB1 – MAY 2011 www.ti.com Figure 17. Schematic (Page 2 of 4) Copyright © 2011, Texas Instruments Incorporated [1,3] CELL 1 - 2-VSS [1] 2-CELL2 [1] 2-CELL1 [1] 2-CELL3 CELL 3 + CELL 2 + [1] 2-CELL4 CELL 1 + [1] 2-CELL5 CELL 5 + [1] 2-CELL6 CELL 4 + CELL 6 + Q14 FDN359AN SOT-23 Z14 5.1 VDC 500mW Q10 SOD-123 FDN359AN SOT-23 R98 47 RES2512 Q11 FDN359AN SOT-23 R104 47 RES2512 Z18 5.1 VDC 500mW Q13 SOD-123 FDN359AN SOT-23 R114 47 RES2512 Z20 5.1 VDC 500mW SOD-123 R121 47 RES2512 Z22 5.1 VDC 500mW Q15 SOD-123 FDN359AN SOT-23 Z16 5.1 VDC 500mW SOD-123 C54 0.1uf 50V CAP0603 C58 0.1uf 50V CAP0603 C65 0.1uf 50V CAP0603 C72 0.1uf 50V CAP0603 Q16 FDN359AN SOT-23 R132 47 RES2512 Z24 5.1 VDC 500mW SOD-123 C76 0.1uf 50V CAP0603 C81 0.1uf 50V CAP0603 R139 47 RES2512 Z15 5.1VDC SOD-323 Z17 5.1VDC SOD-323 Z19 5.1VDC SOD-323 Z21 5.1VDC SOD-323 Z23 5.1VDC SOD-323 Z25 5.1VDC SOD-323 R94 1M 1% RES0603 R95 1.0K 1% RES0603 ** C66 0.1uf 50V CAP0603 R99 1.0K 1% RES0603 R100 1M 1% RES0603 R101 1.0K 1% RES0603 ** C67 0.1uf 50V CAP0603 R109 1.0K 1% RES0603 R110 1M 1% RES0603 R111 1.0K 1% RES0603 ** C68 0.1uf 50V CAP0603 R117 1.0K 1% RES0603 R119 1M 1% RES0603 R120 1.0K 1% RES0603 ** C70 0.1uf 50V CAP0603 R128 1.0K 1% RES0603 R129 1M 1% RES0603 R130 1.0K 1% RES0603 ** C73 0.1uf 50V CAP0603 R135 1.0K 1% RES0603 R136 1M 1% RES0603 R137 1.0K 1% RES0603 ** C74 0.1uf 50V CAP0603 R140 1.0K 1% RES0603 2-VSS 2-VSS 2-VSS 2-VSS 2-VSS 2-VSS 2-VSS * VC0 CB1 VC1 CB2 VC2 CB3 VC3 CB4 VC4 CB5 VC5 CB6 VC6 BAT1 BAT2 2-VSS C56 * 1nF 50V CAP0603 13 12 11 10 9 8 7 6 5 4 3 2 1 63 64 2-VSS C75** 0.1uf 50V CAP0603 C82 33pF 50V CAP0603 GPIO 45 2-VSS COMM PINS OF THE CHIP BELOW TO JUST BELOW THE NORTH UNDER THE SOUTH COMM LINES EXTEND THE GROUND PLANE GROUND PLANE OF CIRCUIT 2 2-LDOD 2-LDOA[3] R1 0R0 RES0603 TP-VSS2 TP-VPROG2 R103 1.47K 1% RES0603 2-VSS R158 10K 1% B=3435K NTC0603 R106 100 RES0603 R105 100K RES0603 D4 LTW-C192TL2 White LED CAUTION HIGH VOLTAGE * - Typical value shown. Actual value depends on number of IC's in stack, wiring, etc. Consult applications guide for recommended values. 2-VSS C62 0.1uf 50V CAP0603 T1 R3 0R0 RES0603 R157 10K 1% B=3435K NTC0603 R134 1.47K 1% RES0603 C11 DNP CAP0603 R107 1.82K 1% RES0603 C61** 2.2uf 10V CAP0805 C10 DNP CAP0603 T2 R131 1.82K 1% RES0603 C59 0.047uf 16V CAP0603 2-VSS C69 ** 0.1uf 50V CAP0603 C60** 10uf 10V CAP1206 C8 DNP CAP0603 C78 0.047uf 16V CAP0603 THERMISTOR NTC 10K OHM 1% 0603 PANASONIC PART NUMBER # ERT-J1VG103FA ** - Locate these components very close to bq76PL536 IC. CAUTION HIGH VOLTAGE C71** 2.2uf 10V CAP0805 C53* 1nF 50V CAP0603 46 18 17 15 16 2-VSS LDOD2 LDOD1 LDOA AGND VREF 41 SDO_H 42 SDI_H 40 SCLK_H 43 CS_H 39 FAULT_H 38 ALERT_H 37 DRDY_H 36 CONV_H C55* 33pF 50V CAP0603 2-VSS 47 48 19 20 60 61 2-VSS C63** 2.2uf 10V CAP0805 C79* 33pF 50V CAP0603 51 NC2 30 NC1 62 NC3 GPAI- GPAI+ TS1- TS1+ TS2- TS2+ C80* 33pF 50V CAP0603 2-LDOD[3] 2-VSS C83 * 33pF 50V CAP0603 C57* 33pF 50V CAP0603 2-VSS bq76PL536 U2 GROUND PLANE OF CIRCUIT 3 RES0603 2-VBAT [1] 2-CONV_N [1] 2-DRDY_N [1] 2-ALERT_N[1] 2-FAULT_N [1] 59 CONV_N 58 DRDY_N 57 ALERT_N 56 FAULT_N CONV_S DRDY_S ALERT_S FAULT_S 21 22 23 24 R115 100K 50 TEST 44 HSEL 32 REG50 2-SCLK_N [1] 2-SDO_N [1] 2-SDI_N [1] 2-CS_N [1] 55 SCLK_N 54 SDO_N 53 SDI_N 52 CS_N SCLK_S SDO_S SDI_S CS_S 26 27 28 29 [1] 2-SCLK_S [1] 2-SDO_S [1] 2-SDI_S [1] 2-CS_S 31 AUX VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 49 35 34 33 25 14 TAB 65 Copyright © 2011, Texas Instruments Incorporated [1] 2-CONV_S [1] 2-DRDY_S [1] 2-ALERT_S [1] 2-FAULT_S GROUND PLANE OF CIRCUIT 2 2-VSS S003 Q12 2N7002LT1 SOT-23 R102 2.7K RES0603 www.ti.com bq76PL536-Q1 SLUSAB1 – MAY 2011 Figure 18. Schematic (Page 3 of 4) 51 [1] 3-CELL1 [1,4] CELL 1 + CELL 1 - 3-VSS [1] 3-CELL2 CELL 2 + [1] 3-CELL4 [1] 3-CELL3 [1] 3-CELL5 CELL 5 + CELL 4 + CELL 3 + [1] 3-CELL6 CELL 6 + C86 0.1uf 50V CAP0603 C87 0.1uf 50V CAP0603 C94 0.1uf 50V CAP0603 C101 0.1uf 50V CAP0603 C109 0.1uf 50V CAP0603 R177 47 RES2512 Q21 FDN359AN SOT-23 Z27 5.1 VDC 500mW Q17 SOD-123 FDN359AN SOT-23 R155 47 RES2512 Z29 5.1 VDC 500mW Q18 SOD-123 FDN359AN SOT-23 R167 47 RES2512 Z31 5.1 VDC 500mW Q20 SOD-123 FDN359AN SOT-23 Z33 5.1 VDC 500mW SOD-123 R183 47 RES2512 Z35 5.1 VDC 500mW Q22 SOD-123 FDN359AN SOT-23 R193 47 RES2512 Q23 FDN359AN SOT-23 Z37 5.1 VDC 500mW SOD-123 R199 47 RES2512 Z28 5.1VDC SOD-323 Z30 5.1VDC SOD-323 Z32 5.1VDC SOD-323 Z34 5.1VDC SOD-323 Z36 5.1VDC SOD-323 Z39 5.1VDC SOD-323 R152 1M 1% RES0603 R153 1.0K 1% RES0603 ** C95 0.1uf 50V CAP0603 R162 1M 1% RES0603 R160 1.0K 1% RES0603 R163 1.0K 1% RES0603 ** C96 0.1uf 50V CAP0603 R170 1.0K 1% RES0603 R173 1M 1% RES0603 R174 1.0K 1% RES0603 ** C97 0.1uf 50V CAP0603 R179 1.0K 1% RES0603 R180 1M 1% RES0603 R181 1.0K 1% RES0603 ** C99 0.1uf 50V CAP0603 R185 1.0K 1% RES0603 R186 1M 1% RES0603 R187 1.0K 1% RES0603 ** C102 0.1uf 50V CAP0603 R196 1.0K 1% RES0603 R197 1M 1% RES0603 R198 1.0K 1% RES0603 ** C103 0.1uf 50V CAP0603 3-VSS 3-VSS 3-VSS 3-VSS 3-VSS 3-VSS * 3-VSS C2 1nF 50V CAP0603 VC0 CB1 VC1 CB2 VC2 CB3 VC3 CB4 VC4 CB5 VC5 CB6 VC6 BAT1 BAT2 3-VSS CAUTION HIGH VOLTAGE 3-VSS 13 12 11 10 9 8 7 6 5 4 3 2 1 63 64 C104** 0.1uf 50V CAP0603 3-VSS bq76PL536 U3 3-VSS GPIO 45 * 3-VSS EXTEND THE GROUND PLANE UNDER THE SOUTH COMM LINES COMM PINS OF THE CHIP BELOW TO JUST BELOW THE NORTH 3-VSS TP-VSS3 TP-VPROG3 3-LDOD 3-LDOA [4] R4 0R0 RES0603 R165 1.47K 1% RES0603 3-VSS R192 10K 1% B=3435K NTC0603 R169 100 RES0603 R168 100K RES0603 * - Typical value shown. Actual value depends on number of IC's in stack, wiring, etc. Consult applications guide for recommended values. C91 0.1uf 50V CAP0603 T1 R5 0R0 RES0603 R191 10K 1% B=3435K NTC0603 R194 1.47K 1% RES0603 C14 DNP CAP0603 R171 1.82K 1% RES0603 C90 ** 2.2uf 10V CAP0805 3-VSS T2 THERMISTOR NTC 10K OHM 1% 0603 PANASONIC PART NUMBER # ERT-J1VG103FA R188 1.82K 1% RES0603 C88 0.047uf 16V CAP0603 C13 DNP CAP0603 C98 ** 0.1uf 50V CAP0603 C89 ** 10uf 10V CAP1206 C12 DNP CAP0603 C111 0.047uf 16V CAP0603 C100 ** 2.2uf 10V CAP0805 C3 1nF 50V CAP0603 46 18 17 15 16 3-VSS LDOD2 LDOD1 LDOA AGND VREF 41 SDO_H 42 SDI_H 40 SCLK_H 43 CS_H 39 FAULT_H 38 ALERT_H 37 DRDY_H 36 CONV_H C1 33pF 50V CAP0603 * 47 48 19 20 60 61 51 NC2 30 NC1 62 NC3 GPAI- GPAI+ TS1- TS1+ TS2- TS2+ 3-VSS C92 ** 2.2uf 10V CAP0805 GROUND PLANE OF CIRCUIT 3 3-VSS C5 33pF 50V CAP0603 * 3-LDOD[4] R178 100K RES0603 3-REG50 "Top" part connects all _N pins to CELL6 of U3 3-CONV_N 3-DRDY_N 3-ALERT_N 3-FAULT_N 59 CONV_N 58 DRDY_N 57 ALERT_N 56 FAULT_N CONV_S DRDY_S ALERT_S FAULT_S 21 22 23 24 [1] 3-CONV_S [1] 3-DRDY_S [1] 3-ALERT_S [1] 3-FAULT_S C114 0.1uf 50V CAP0603 3-SCLK_N 3-SDO_N 3-SDI_N 3-CS_N 55 SCLK_N 54 SDO_N 53 SDI_N 52 CS_N SCLK_S SDO_S SDI_S CS_S 26 27 28 29 3-SCLK_S 3-SDO_S 3-SDI_S 3-CS_S ** - Locate these components very close to bq76PL536 IC. D5 LTW-C192TL2 White LED 3-VSS S004 Q19 2N7002LT1 SOT-23 R164 2.7K RES0603 SLUSAB1 – MAY 2011 [1] [1] [1] [1] R208 1.0K 1% RES0603 50 3-VBAT [1] 44 HSEL 32 REG50 31 AUX VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 49 35 34 33 25 14 TAB 65 52 TEST CAUTION HIGH VOLTAGE bq76PL536-Q1 www.ti.com Figure 19. Schematic (Page 4 of 4) Full-size reference schematics are available from TI on request. Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ76PL536TPAPRQ1 NRND HTQFP PAP 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 76PL536Q1 BQ76PL536TPAPTQ1 NRND HTQFP PAP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 76PL536Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of