BQ7716
SLUSAX0E – DECEMBER 2012 – REVISED APRIL 2021
BQ7716xy Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
1 Features
3 Description
•
•
•
•
The BQ7716xy device family provides an overvoltage
monitor and protector for Li-Ion battery pack
systems. Each cell is monitored independently for
an overvoltage condition. For quicker production-line
testing, the BQ7716xy device provides a Customer
Test Mode with greatly reduced delay time.
•
•
•
2-, 3-, and 4-series cell overvoltage protection
External capacitor-programmed delay timer
Fixed OVP threshold
High-accuracy overvoltage protection:
±10 mV
Low power consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT)
Low leakage current per cell input < 100 nA
Small package footprint
– 8-pin WSON (3.00 mm × 4.00 mm)
In the BQ7716xy device, an external delay timer is
initiated upon detection of an overvoltage condition on
any cell. Upon expiration of the delay timer, the output
is triggered into its active state (either high or low,
depending on the configuration). The external delay
timer feature also includes the ability to detect an
open or shorted delay capacitor on the CD pin, which
will similarly trigger the output driver in an overvoltage
condition.
2 Applications
•
•
•
Power tools
UPS battery backup
Light electric vehicles
– eBike
– eScooter
– Pedal assist bicycles
Table 3-1. Device Information Table(1)
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
BQ771600
WSON (8)
3.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet and the Device Comparison Table.
C VD
VDD
OUT
R VD
V4
CD
V3
VSS
V2
V1
CCD
R IN
CIN
Cell 2
R IN
Cell 1
CIN
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ7716
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Receiving Notification of Documentation Updates..16
12.2 Support Resources................................................. 16
12.3 Trademarks............................................................. 16
12.4 Electrostatic Discharge Caution..............................16
12.5 Export Control Notice..............................................16
12.6 Glossary..................................................................16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2015) to Revision E (April 2021)
Page
• Removed Product Preview devices.................................................................................................................... 3
• Removed Product Preview devices.................................................................................................................... 6
Changes from Revision C (August 2014) to Revision D (July 2015)
Page
• Changed QFN to WSON ................................................................................................................................... 1
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Changed the BQ771605 to Production Data...................................................................................................... 3
• Added table note 2, which was hidden inadvertently..........................................................................................4
• Moved Pin Details to Feature Description section ............................................................................................. 9
• Moved from Application Information section to Design Requirements section ................................................14
2
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5 Device Comparison Table
PART NUMBER
(1)
OVP (V)
OV HYSTERESIS (V)
TAPE AND REEL
(LARGE)
OUTPUT DRIVE
TAPE AND REEL (SMALL)
BQ771600
4.3
0.3
CMOS Active High
BQ771600DPJR
BQ771600DPJT
BQ771601
4.225
0.05
CMOS Active High
BQ771601DPJR
BQ771601DPJT
BQ771602
4.225
0.05
NCH Active Low, Open Drain
BQ771602DPJR
BQ771602DPJT
BQ771604
4.2
0.05
CMOS Active High
BQ771604DPJR
BQ771604DPJT
BQ771605
3.85
0.25
NCH Active Low
BQ771605DPJR
BQ771605DPJT
BQ771611
4.35
0.3
CMOS Active High
BQ771611DPJR
BQ771611DPJT
BQ771612
3.9
0.3
CMOS Active High
BQ771612DPJR
BQ771612DPJT
BQ7716xy future options(1)
3.85–4.65
0–0.3
CMOS Active High or NCH Active
Low, Open Drain
BQ7716xyTBD
BQ7716xyTBD
Contact TI.
6 Pin Configuration and Functions
VDD
1
8
OUT
V4
2
7
CD
V3
3
6
VSS
V2
4
5
V1
Figure 6-1. DPJ Package 8-Pin WSON Top View
Table 6-1. Pin Functions
PIN
(1)
TYPE
DESCRIPTION
NAME
NO.
I/O(1)
CD
7
I/O
OUT
8
OA
VDD
1
P
VSS
6
P
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
V1
5
I
Sense input for positive voltage of the lowest cell in the stack
V2
4
I
Sense input for positive voltage of the second cell from the bottom of the stack
V3
3
I
Sense input for positive voltage of the third cell from the bottom of the stack
V4
2
I
Sense input for positive voltage of the fourth cell from the bottom of the stack
External capacitor connection for delay timer
Output drive for overvoltage fault signal
Power supply
IA = Input Analog, OA = Output Analog, P = Power Connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage range(2)
Input voltage
range(2)
Output voltage range(2)
MIN
MAX
UNIT
VDD–VSS
–0.3
30
V
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
–0.3
30
V
OUT–VSS
–0.3
30
V
110
°C
150
°C
See package
dissipation rating.
Continuous total power dissipation, PTOT
Functional temperature
–40
Lead temperature (soldering, 10 s), TSOLDER
300
Storage temperature, Tstg
–65
(1)
(2)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Absolute maximum ratings for input voltage range, output voltage range, and supply voltage are assured by design and not tested in
production.
7.2 ESD Ratings
VESD Rating
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
VALUE
UNIT
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1)
(2)
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
VDD
(1)
NOM
MAX UNIT
Supply voltage
3
20
V
V4–V3, V3–V2, V2–
V1, V1–VSS, or CD–
VSS
Input voltage range
0
5
V
TA
Operating ambient temperature range
–40
110
°C
(1)
See Section 9.2.
7.4 Thermal Information
BQ7716xy
THERMAL METRIC(1)
DPJ (WSON)
UNIT
8 PINS
4
RθJA
Junction-to-ambient thermal resistance
56.6
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
56.4
°C/W
RθJB
Junction-to-board thermal resistance
30.6
°C/W
ψJT
Junction-to-top characterization parameter
1.0
°C/W
ψJB
Junction-to-board characterization parameter
37.8
°C/W
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BQ7716xy
THERMAL METRIC(1)
DPJ (WSON)
UNIT
8 PINS
RθJC(bot)
(1)
Junction-to-case(bottom) thermal resistance
11.3
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 14.4V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE PROTECTION THRESHOLD VCx
V(PROTECT)
Overvoltage
Detection
VOV
BQ771600
4.300
V
BQ771601
4.225
V
BQ771602
4.225
V
BQ771604
4.200
V
BQ771605
3.850
V
BQ771611
4.350
V
BQ771612
OV Detection
Hysteresis
VHYS
VOA
OV Detection
Accuracy
VOADRIFT
OV Detection
Accuracy Across
Temperature
3.900
V
BQ771600
250
300
400
mV
BQ771601
25
50
75
mV
BQ771602
25
50
75
mV
BQ771604
25
50
75
mV
BQ771605
200
250
300
mV
BQ771611
250
300
400
mV
BQ771612
250
300
400
mV
TA = 25°C
–10
10
mV
TA = –40°C
–40
44
mV
TA = 0°C
–20
20
mV
TA = 60°C
–24
24
mV
TA = 110°C
–54
54
mV
2
µA
0.1
µA
SUPPLY AND LEAKAGE CURRENT
6
ICC
Supply Current
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
(See Figure 8-3.)
IIN
Input Current at Vx
Pins
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
(See Figure 8-3.)
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Typical values stated where TA = 25°C and VDD = 14.4V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVE OUT, CMOS ACTIVE HIGH VERSIONS ONLY
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
= 14.4 V, IOH = 100 µA
VOUT1
6
If three of four cells are short circuited, only one cell
Output Drive Voltage,
remains powered and > VOV, VDD = Vx (cell voltage),
Active High
IOH = 100 µA
VDD – 0.3
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, IOL = 100 µA measured into OUT pin
IOUTH1
OUT Source Current
(During OV)
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
= 14.4 V, OUT = 0 V. Measured out of OUT pin
IOUTL1
OUT Sink Current
(No OV)
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, OUT = VDD.
Measured into OUT pin
V
250
0.5
V
400
mV
4.5
mA
14
mA
400
mV
14
mA
100
nA
OUTPUT DRIVE OUT, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
VOUT2
Output Drive Voltage, (V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
Active Low
= 14.4 V, IOL = 100 µA measured into OUT pin
IOUTH2
OUT Sink Current
(During OV)
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
= 14.4 V. OUT = VDD.
Measured into OUT pin
IOUTLK
OUT Pin Leakage
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
VDD = 14.4 V, OUT = VDD. Measured out of OUT pin
250
0.5
DELAY TIMER
tCD
OV Delay Time
VCD
CD Fault Detection
External Comparator The CD pin will first be quickly charged to this value
Threshold, Initial
before being discharged back to VSS.
Charge Value
CCD = 0.1 µF
1
1.5
2
tCHGDELAY
CD Charging Delay
OVP to OUT delay with CD shorted to ground
ICHG
OV Detection
Charging Current
CD pin fast charging current from VSS to VCD to begin
delay countdown
300
µA
IDSG
OV Detection
Discharging Current
CD pin discharging current from VDELAY to VSS
100
nA
1.5
20
s
V
170
ms
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7.6 Typical Characteristics
8
Figure 7-1. Overvoltage Threshold (OVT) vs.
Temperature
Figure 7-2. Hysteresis VHYS vs. Temperature
Figure 7-3. IDD Current Consumption vs.
Temperature at VDD = 16 V
Figure 7-4. ICELL vs. Temperature
at VCELL= 9.2 V
Figure 7-5. Output Current IOUT vs. Temperature
Figure 7-6. VOUT vs. VDD
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8 Detailed Description
8.1 Overview
In the BQ7716xy family of devices for overvoltage protection, each cell is monitored independently and an
external delay timer is initiated if an overvoltage condition is detected when any cell voltage is higher than the
protection voltage threshold, VOV. After the delay time expires, the OUT pin is inserted.
For quicker production-line testing, the device provides a Customer Test Mode with greatly reduced delay time.
8.2 Functional Block Diagram
PACK+
R VD
C VD
VDD
VC4
CIN
RIN
VC3
CIN
RIN
VC2
Sensing Circuit
RIN
CIN
RIN
VOV
Enable
Delay
Charging/ Active
Discharging
Circuit
OUT
VC1
CIN
VSS
CD
CCD
PACK–
8.3 Feature Description
In the BQ7716xy device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a
timer circuit is activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it
with a fixed current back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT
terminal goes from inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD
pin successfully begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error
is detected in either direction, it will similarly trigger the OUT pin to become active. See Figure 8-1 for reference.
For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present),
and is high impedance when inactive (no OV).
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Cell Voltage (V)
(V4–V3, V3–V2, V2–V1, V1–VSS)
SLUSAX0E – DECEMBER 2012 – REVISED APRIL 2021
VOV
VOV –VHYS
t DELAY
OUT (V)
Figure 8-1. Timing for Overvoltage Sensing
Figure 8-2 shows an overview of the behavior of the CD pin during an OV sequence.
Fault condition
present
Fault response
becomes active
VCD
V(CD)
t CHGDELAY
t CD
ICHG
I(CD)
IDSG
VOUT1
V(OUT)
Note: Active High OUT version shown
Figure 8-2. CD Pin Mechanism
8.3.1 Sense Positive Input for Vx
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
10
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8.3.2 Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either active HIGH or LOW options.
8.3.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.4 External Delay Capacitor, CD
This terminal is connected to an external capacitor that is used for setting the delay timer during an overvoltage
fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the
OV threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
To calculate the delay, use the following equation:
tCD (s) = K × CCD (µF), where K = 10 to 20 range.
(1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (s) = 10 × 0.1 = 1 s (Minimum)
tCD (s) = 20 × 0.1 = 2 s (Maximum)
Note
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3).
The OUT pin is inactive and if configured:
•
•
Active high is low
Active low is being externally pulled up and is an open drain
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceeds the overvoltage threshold, VOV for
configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The
OUT pin will either pull high internally, if configured as active high, or will be pulled low internally, if configured as
active low. When all of the cell voltages fall below the (VOV–VHYS), the device returns to NORMAL mode
8.4.3 Customer Test Mode
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CHGDELAY) value, which has a maximum of
170 ms.
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CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into Customer
Test Mode. Also avoid exceeding Absolute Maximum Voltages for the individual cell voltages (V4–
V3), (V3–V2), (V2–V1), and (V1–VSS). Stressing the pins beyond the rated limits may cause
permanent damage to the device.
Figure 8-3 shows the timing for the Customer Test Mode.
OV Condition
V(VCELL)
≤ 170 ms
V(OUT)
CD pin held low
V(CD)
Figure 8-3. Timing for Customer Test Mode
Figure 8-4 shows the measurement for current consumption for the product for both VDD and Vx.
I CC
IIN
VDD
OUT
V4
CD
IIN
V3
VSS
IIN
V2
V1
Cell4
Cell3
Cell2
IIN
Cell1
Figure 8-4. Configuration for IC Current Consumption Test
12
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Figure 9-1 shows each external component.
CVD
VDD
OUT
RVD
Cell 4
R IN
C IN
V4
CD
CCD
Cell 3
R IN
V3
VSS
V2
V1
C IN
R IN
C IN
Cell 2
Cell1
R IN
C IN
Figure 9-1. Application Configuration
Note
In the case of an Open Drain Active Low configuration, an external pull-up resistor is required on the
OUT terminal.
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements.
Note
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this recommended value
changes the accuracy of the cell voltage measurements and VOV trigger level.
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9.2 Typical Application
C VD
CVD
VDD
OUT
VDD
OUT
RVD
R VD
V4
CD
V4
CD
V3
VSS
V2
V1
CCD
V3
CCD
VSS
RIN
CIN
Cell 3
V1
V2
RIN
R IN
Cell 2
R IN
Cell 1
CIN
Cell 2
CIN
Cell 1
CIN
RIN
Figure 9-2. 2-Series Cell Configuration with
Capacitor-Programmed Delay
CIN
Figure 9-3. 3-Series Cell Configuration with
Capacitor-Programmed Delay
Note
In these application examples of 2 s and 3 s, an external pull-up resistor is required on the OUT
terminal to configure for an Open Drain Active Low operation.
9.2.1 Design Requirements
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements.
Table 9-1. Design Parameters
PARAMETER
EXTERNAL COMPONENT
Voltage monitor filter resistance
MIN
NOM
RIN
900
Voltage monitor filter capacitance
CIN
Supply voltage filter resistance
RVD
MAX
1000
UNIT
1100
Ω
0.01
0.1
µF
100
1K
Ω
1
µF
Supply voltage filter capacitance
CVD
0.1
CD external delay capacitance
CCD
0.1
OUT Open drain version pull-up
resistance to PACK+
ROUT
100k
µF
Ω
9.2.2 Detailed Design Procedure
1. Determine the number of cells in series. The device supports a 2-S to 4-S cell configuration. For 2S and 3S,
the top unused pin(s) should be shorted as shown in Figure 9-2 and Figure 9-3.
2. Determine the overvoltage protection delay. Follow the calculation example described in Section 8.3.4.
Select the correct capacitor to connect to the CD pin.
3. Follow the application schematic to connect the device. If the OUT pin is configured to open drain, an
external pull-up resistor should be used. Refer to the Out Sink Current specification, IOUTH2 to ensure a
proper pull-up resistor value is used, so that the OUT pin sink current is able to pull down the pin during OV
condition.
14
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9.2.3 Application Curves
Figure 9-4. Hysteresis VHYS vs. Temperature
Figure 9-5. IDD Current Consumption vs.
Temperature at VDD = 16 V
10 Power Supply Recommendations
The maximum power of this device is 20 V on VDD.
11 Layout
11.1 Layout Guidelines
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for CD pin should be placed close to the IC terminals.
11.2 Layout Example
Place the RC filters close to the
device terminals
Power Trace Line
Pack +
VDD
OUT
V4
CD
V3
VSS
Pack PWPD
VCELL3
V2
OUT
V1
VCELL2
VCELL1
Place close to the CD pin
Figure 11-1. Layout
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Product Folder Links: BQ7716
15
BQ7716
www.ti.com
SLUSAX0E – DECEMBER 2012 – REVISED APRIL 2021
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
12.6 Glossary
TI Glossary
16
This glossary lists and explains terms, acronyms, and definitions.
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Product Folder Links: BQ7716
BQ7716
www.ti.com
SLUSAX0E – DECEMBER 2012 – REVISED APRIL 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: BQ7716
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
BQ771600DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
771600
Samples
BQ771600DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
771600
Samples
BQ771601DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
771601
Samples
BQ771601DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
771601
Samples
BQ771602DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
771602
Samples
BQ771602DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
771602
Samples
BQ771604DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771604
Samples
BQ771604DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
771604
Samples
BQ771605DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
771605
Samples
BQ771605DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
771605
Samples
BQ771611DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
771611
Samples
BQ771611DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
771611
Samples
BQ771612DPJR
ACTIVE
WSON
DPJ
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
771612
Samples
BQ771612DPJT
ACTIVE
WSON
DPJ
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
771612
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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