BQ77915
BQ77915
SLUSCU0I – MARCH 2018 – REVISED SEPTEMBER
2020
SLUSCU0I – MARCH 2018 – REVISED SEPTEMBER 2020
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BQ77915 3-Series to 5-Series Stackable Ultra-Low Power Primary Protector with
Autonomous Cell Balancing and HIBERNATE Mode
1 Features
3 Description
•
The BQ77915 device is a low-power battery pack
protector that implements a suite of voltage, current,
and temperature protections and a smart cell
balancing algorithm without microcontroller (MCU)
control. The device's stackable interface provides
simple scaling to support battery cell applications from
3 series to 20 series or more. Protection thresholds
and delays are factory-programmed and available in a
variety of configurations. Separate overtemperature
and undertemperature thresholds for discharge (OTD
and UTD) and charge (OTC and UTC) are provided
for added flexibility.
•
•
•
•
•
•
•
•
•
•
Ultra-low quiescent current: 8 µA typ. (NORMAL
mode), 2 µA (HIBERNATE mode)
Full suite of voltage, current, and temperature
protections
Smart passive cell balancing removes cell-to-cell
imbalance
Scalable cell count from 3 series to 20 series or
more
Voltage protection (accuracy ±10 mV for OV,
±18 mV for UV)
– Overvoltage: 3 V to 4.575 V
– Undervoltage: 1.2 V to 3 V
Open cell and open-wire detection (OW)
Current protection
– Overcurrent discharge 1: –10 mV to –85 mV
– Overcurrent discharge 2: –20 mV to –170 mV
– Short-circuit discharge: –40 mV to –340 mV
Temperature protection
– Overtemperature charge: 45°C or 50°C
– Overtemperature discharge: 65°C or 70°C
Additional features:
– Independent charge (CHG) and discharge
(DSG) FET drivers
– Smart cell balancing algorithm with integrated
FETs (up to 50-mA balancing current), also
supports external FETs for higher cell-balancing
current
– Ultra-low power HIBERNATE mode
– High 36-V absolute maximum rating per cell
input
– Resistor programmable overcurrent (OCD1/2)
delay
SHUTDOWN mode: 0.5-µA maximum
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Device Information
Part Number (1)
(1)
Body Size (NOM)
TSSOP–24
7.70 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
PACK+
VDD
+
–
CTRD
VTB
CTRC
VC5
TS
bq77915
+
–
VC0
LPWR
CBO
SRN
VDD
+
–
DSG
CHG
CBI
CTRD
CTRC
VTB
VC5
TS
bq77915
+
–
Power tools, garden tools
Robotic cleaners, vacuum cleaners, hoverboards
e-bikes
10.8-V to 72-V packs
LD
PRES
VSS
SRP
2 Applications
•
•
•
•
Package
BQ77915
LD
PRES
VC0
LPWR
VSS
SRP
CBO
SRN
DSG
CHG CBI
PACK–
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Table............................................................. 7
8.5 Electrical Characteristics.............................................8
8.6 Typical Characteristics.............................................. 12
9 Detailed Description......................................................14
9.1 Overview................................................................... 14
9.2 Functional Block Diagram......................................... 15
9.3 Feature Description...................................................15
9.4 Device Functional Modes..........................................32
10 Application and Implementation................................ 34
10.1 Application Information........................................... 34
10.2 Typical Application.................................................. 40
11 Power Supply Recommendations..............................45
12 Layout...........................................................................46
12.1 Layout Guidelines................................................... 46
12.2 Layout Example...................................................... 47
13 Device and Documentation Support..........................48
13.1 Documentation Support.......................................... 48
13.2 Receiving Notification of Documentation Updates..48
13.3 Support Resources................................................. 48
13.4 Trademarks............................................................. 48
13.5 Electrostatic Discharge Caution..............................48
13.6 Glossary..................................................................48
14 Mechanical, Packaging, and Orderable
Information.................................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (June 2020) to Revision I (September 2020)
Page
• Added the Functional Safety-Capable feature....................................................................................................1
Changes from February 24, 2020 to June 18, 2020 (from Revision G (February 2020) to
Revision H (June 2020))
Page
• Added the BQ7791508 device to the Device Comparison Table .......................................................................3
Changes from Revision E (June 2019) to Revision F (September 2019)
Page
• Changed the BQ7791501 and BQ7791502 devices to catalog devices ............................................................3
Changes from Revision F (September 2019) to Revision G (February 2020)
Page
• Added the BQ7791506 device............................................................................................................................3
Changes from Revision D (January 2019) to Revision E (June 2019)
Page
• Added the BQ7791504 device to Production Data............................................................................................. 3
• Changed the resistor names between the CHG/DSG pins of the top device and the CTRC/CTRD pins of the
bottom device in Figure 9-14 ........................................................................................................................... 30
• Changed RCRTC to RCTRC in Table 10-1 .......................................................................................................... 40
Changes from Revision C (December 2018) to Revision D (January 2019)
Page
• Changed the OCDP connection in the top BQ77915 device in Figure 9-14 ....................................................30
Changes from Revision B (November 2018) to Revision C (December 2018)
Page
• Added the BQ7791502 device to Production Data............................................................................................. 3
2
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5 Description (continued)
The device achieves pack protection via the integrated independent CHG and DSG low-side NMOS FET drivers,
which may be disabled through two control pins. These control pins may also be used to achieve cell protection
solutions for higher series (6 series and beyond) in a simple and economical manner. To do this, simply cascade
a higher device CHG and DSG outputs to the immediate lower device control pins. For added flexibility,
discharge overcurrent protection delays can be programmed using a resistor connected from the OCDP pin to
VSS.
The BQ77915 protector achieves a smart passive cell-balancing algorithm via integrated FETs for cell balancing
currents up to 50 mA. For higher cell-balancing current requirements, external FETs can be connected. A
HIBERNATE mode intended for shipping and storage of the battery packs enables ultra-low power operation.
The BQ77915 protector is intended for battery packs where no host monitoring is required.
6 Device Comparison Table
Unless otherwise specified, the device has, by default, a state comparator enabled with a 1.875-mV threshold. A
filtered fault detection is used by default.
OV
UV
OW
OCD1
OCD2
SCD
OCC
Threshold
(mV)
Delay
(s)
Hyst
(mV)
Threshold
(mV)
Delay
(s)
Hyst
(mV)
Load
Removal
Recovery
(Y/N)
BQ7791500
4200
1
200
2900
1
400
Y
100
60
180
60
180
120
0.96
60
BQ7791501
4250
1
200
2800
1
400
Y
100
35
180
60
180
120
0.96
20
BQ7791502
4200
1
200
2900
1
400
Y
100
70
180
70
180
120
0.96
70
BQ7791504
4275
1
100
2000
1
200
N
BQ7791506
3800
1
200
2500
1
400
Y
100
50
700
100
350
300
0.4
60
BQ7791508
4200
4.5
100
3000
4.5
200
Y
100
70
1420
140
700
300
0.4
60
Part Number
Threshold
(mV)
Delay
(ms)
Threshold
(mV)
Delay (ms)
Threshold
(mV)
Delay
(ms)
Threshold
(mV)
Disabled
Temperature (°C)(1)
Current Fault Recovery
Cell Balancing
VSTEP (VCBTH –
VCBTL)
(mV)
OTD
OTC
UTD
UTC
VSTART (V)
VHYST (VOV –
VFC) (mV)
BQ7791500
N/A
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
45
–10
0
3.8
100
100
BQ7791501
N/A
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
70
50
–20
0
3.8
100
100
BQ7791502
N/A
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
45
–10
0
3.8
100
100
BQ7791504
Disabled
3.5
50
50
BQ7791506
N/A
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
50
–10
0
3.5
100
50
BQ7791508
500
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
50
–20
–5
3.8
100
50
Part Number
(1)
Delay
(ms)
Current
(nA)
Method
N/A
Disabled
These thresholds are targets, based on temperature, but they are dependent on external components that could vary based on
customer selection. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to VTB
and TS. Actual thresholds must be determined in mV; refers to the overtemperature and undertemperature mV threshold in the
Electrical Characteristics table.
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7 Pin Configuration and Functions
VDD
1
24
CTRD
AVDD
2
23
CTRC
VC5
3
22
PRES
VC4
4
21
CBO
VC3
5
20
CCFG
VC2
6
19
VTB
VC1
7
18
TS
VC0
8
17
OCDP
VSS
9
16
CBI
SRP
10
15
LPWR
SRN
11
14
LD
DSG
12
13
CHG
Not to scale
Figure 7-1. PW Package 24-Pin TSSOP Top View
Pin Functions
NUMBER
4
NAME
I/O
DESCRIPTION
1
VDD
P(1)
2
AVDD
O
3
VC5
I
4
VC4
I
5
VC3
I
6
VC2
I
7
VC1
I
8
VC0
I
9
VSS
P
Analog ground
10
SRP
I
Current sense input connecting to the battery side of the sense resistor
11
SRN
I
Current sense input connecting to the pack side of the sense resistor
12
DSG
O
DSG FET driver output
13
CHG
O
CHG FET driver output
14
LD
I
PACK– load removal detection
15
LPWR
O
HIBERNATE mode communication pin. Connect to the PRES pin of the lower device in a stack
configuration. For a single device, leave the LPWR pin floating.
16
CBI
I
Cell balancing input. Leave the CBI pin floating to disable cell balancing, and do not drive with
an external supply. Drive the pin low to enable cell balancing. In a stacked configuration,
connect the CBI pin of an upper device to the CBO pin of the immediate lower device.
17
OCDP
I
Connecting a resistor from this pin to VSS programs the OCD1/2 fault detection delay. Connect
to a 10-MΩ resistor to VSS for the upper devices in a stack.
18
TS
I
Thermistor measurement input. Connect a 10-kΩ resistor to the VSS pin if the function is not
used.
19
VTB
O
Thermistor bias output
20
CCFG
I
Cell in-series configuration input
21
CBO
O
Cell balancing output. Connect through a 10-k resistor to the CBI pin of the upper device in a
stacked configuration. For a single device, leave the CBO pin floating.
22
PRES
I
HIBERNATE mode input. Drive high for NORMAL mode operation. Leave the PRES pin
floating for HIBERNATE mode. Connect to the LPWR pin of the upper device in a stack
configuration.
Supply voltage
Analog supply (only connect to a capacitor)
Cell voltage sense inputs
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NUMBER
(1)
SLUSCU0I – MARCH 2018 – REVISED SEPTEMBER 2020
NAME
I/O
23
CTRC
I
24
CTRD
I
DESCRIPTION
CHG and DSG override inputs
I = Input, O = Output, P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). All values are referenced to VSS unless
otherwise noted.(1)
MIN
MAX
UNIT
–0.3
36
V
LD
–30
20
V
PRES
–0.3
36
V
VC0, SRN, SRP, TS, AVDD, CCFG, CBI
–0.3
3.6
V
DSG
–0.3
20
V
CHG
–30
20
V
CBO
–0.3
36
V
LPWR
–30
3.6
V
VTB, OCDP
–0.3
3.6
V
VDD, VC5, VC4, VC3, VC2, VC1, CTRD, CTRC
VI
Input voltage
VO
Output voltage
VO
Output voltage
II
Input current
IO
IO
LD, CHG
500
µA
DSG
1
mA
Output current
CHG, DSG
1
mA
Output current
Cell Balancing current (VC5, VC4, VC3, VC2, VC1, VC0)
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
(1)
–65
50
mA
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
VBAT
VI
Supply voltage
Input voltage range
25
VC5-VC4, VC4-VC3, VC3VC2, VC2-VC1, VC1-VC0
0
5
CTRD, CTRC
0
(VDD + 5)
CCFG, CBI
0
AVDD
PRES
0
16
–0.2
0.8
0
16
LD
6
Output voltage range
MAX
3
SRN, SRP
VO
NOM
VDD
TS
0
VTB
CHG, DSG
0
16
VTB, AVDD, LPWR
0
3
CBO
0
VDD
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UNIT
V
V
V
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Over operating free-air temperature range (unless otherwise noted)
MIN
TOPR
Operating free-range temperature
RINE
Cell monitor filter resistance (External Cell
balancing)
± 5% tolerance
CINE
Cell monitor filter capacitance (External Cell
balancing)
RINI
NOM
–40
MAX
85
UNIT
°C
1
kΩ
± 10% tolerance
0.1
µF
Cell monitor filter resistance (Internal Cell
balancing. 50-mA balancing current at 4.2-V
cell voltage)
± 5% tolerance
33
Ω
CINI
Cell monitor filter capacitance (Internal Cell
balancing)
± 10% tolerance
1
µF
kΩ
RVDD
Supply voltage filter resistance
± 5% tolerance
1
CVDD
Supply voltage filter capacitance
± 20% tolerance
1
µF
RTS
Thermistor
103AT, ± 3% tolerance
10
kΩ
RTS_PU
Thermistor pullup resistor to VTB
± 1% tolerance
10
kΩ
RGS_CHG
CHG FET gate-source resistor
± 5% tolerance
1
MΩ
RGS_DSG
DSG FET gate-source resistor
± 5% tolerance
1
MΩ
RDSG
DSG gate resistor, System designers should
adjust this parameter to meet the desirable FET ± 5% tolerance
rise/fall time.
4.5
kΩ
± 5% tolerance. System
designers should adjust this
parameter to meet the
desirable FET rise/fall time.
1
kΩ
± 5% tolerance. If additional
components are used to
protect the CHG FET and/or to
enable load removal detection
for UV recovery.
1
MΩ
10
MΩ
RCHG
RCTRC
CHG gate resistor
CTRC current limit resistor
± 5% tolerance
RCTRD
CTRD current limit resistor
± 5% tolerance
10
MΩ
RLD
LD resistor for load removal detection
± 5% tolerance
470
kΩ
RCB
Resistor between CBO of lower device and CBI
± 5% tolerance
of upper device
10
kΩ
RHIB
Resistor between LPWR of upper device and
PRES of upper device
± 5% tolerance
10
kΩ
RSNS
Current sense resistor for current protection.
System designers should change this
parameter according to the application current
protection requirement.
± 1% tolerance
1
mΩ
8.4 Thermal Table
Over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC
BQ77915
PW (TSSOP)
24 PINS
UNIT(1)
RΘJA
Junction-to-ambient thermal resistance
88.9
°C/W
RΘJC(top)
Junction-to-case thermal resistance
26.5
°C/W
RΘJB
Junction-to-board thermal resistance
43.5
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
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Over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC
ψJB
(1)
Junction-to-board characterization parameter
BQ77915
PW (TSSOP)
24 PINS
UNIT(1)
43
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics
Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and
VDD = 3 to 25 V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VPOR
POR threshold
VDD rising, 0 to 6 V
VSHUT
Shutdown threshold
VDD falling, 6 to 0 V
VAVDD
AVDD voltage
CVDD = 1 µF
4
V
2
3.25
V
2.1
3.6
V
8
15
µA
48
80
µA
2
3
μA
SUPPLY AND LEAKAGE CURRENT
ICC
NORMAL mode current
Cell1 through Cell5 = 4 V, VDD = 20
V, No cell balancing
Cell balancing cells 3, 4 or 5
IHIB
HIBERNATE mode current
Cell1 through Cell5 = 4 V, VDD = 20
V, HIBERNATE mode
ICFAULT
Fault condition current
State comparator on
IOFF
SHUTDOWN mode current
VDD < VSHUT, CTRC/CTRD floating
ILKG_OW_DIS
Input leakage current at VCx pins
All cell voltages = 4 V, open-wire
disable configuration
ILKG_100nA
Open-wire sink current at VCx pins
All cell voltages = 4 V, 100-nA
configuration
ILKG_200nA
Open-wire sink current at VCx pins
ILKG_400nA
Open-wire sink current at VCx pins
10
15
µA
0.5
µA
–100
0
100
nA
30
110
175
nA
All cell voltages = 4 V, 200-nA
configuration
95
210
315
nA
All cell voltages = 4 V, 400-nA
configuration
220
425
640
nA
PROTECTION ACCURACIES
VOV
Overvoltage programmable
threshold range
3000
4575
mV
VUV
Undervoltage programmable
threshold range
1200
3000
mV
TA = 25°C, OV detection accuracy
–10
10
mV
TA = 25°C, UV detection accuracy
–18
18
mV
TA = 0 to 60°C
–28
26
mV
TA = –40 to +85°C
–40
40
mV
VVA
OV, UV, detection accuracy
VHYS_OV
OV hysteresis programmable
threshold range
0
400
mV
VHYS_UV
UV hysteresis programmable
threshold range
0
800
mV
VOTD
Overtemperature in discharge
programmable threshold
VOTD_REC
8
Overtemperature in discharge
recovery
Threshold for 65°C based on a 10k
pullup and 103AT thermistor
19.69%
20.56%
21.86%
VTB
Threshold for 70°C based on a 10k
pullup and 103AT thermistor
17.28%
18.22%
19.51%
VTB
Recovery threshold at 55°C for
when VOTD is at 65°C based on a
10k pullup and 103AT thermistor
25.18%
26.12%
27.44%
VTB
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Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and
VDD = 3 to 25 V unless otherwise noted.
PARAMETER
VOTC
VOTC_REC
VUTD
VUTD_REC
VUTC
Overtemperature in charge
programmable threshold
Overtemperature in charge
recovery
Undertemperature in discharge
programmable threshold
Undertemperature in discharge
recovery
Undertemperature in charge
programmable threshold
VUTC_REC
Undertemperature in Charge
Recovery
VOCC
MIN
TYP
MAX
UNIT
Recovery threshold at 60°C for
when VOTD is at 70°C based on a
10k pullup and 103AT thermistor
TEST CONDITIONS
22.05%
23.2%
24.24%
VTB
Threshold for 45°C based on a 10k
pullup and 103AT thermistor
32.14%
32.94%
34.54%
VTB
Threshold for 50°C based on a 10k
pullup and 103AT thermistor
29.15%
29.38%
31.45%
VTB
Recovery threshold at 35°C for
when VOTD is at 45°C based on a
10k pullup and 103AT thermistor
38.63%
40.97%
40.99%
VTB
Recovery threshold at 40°C for
when VOTD is at 50°C based on a
10k pullup and 103AT thermistor
36.18%
36.82%
38.47%
VTB
Threshold for –20°C based on a 10k
pullup and 103AT thermistor
86.41%
87.14%
89.72%
VTB
Threshold for –10°C based on a 10k
pullup and 103AT thermistor
80.04%
80.94%
83.10%
VTB
Recovery threshold at –10°C for
when VUTD is at –20°C based on a
10k pullup and 103AT thermistor
80.04%
80.94%
83.10%
VTB
Recovery threshold at 0°C for when
VUTD is at –10°C based on a 10k
pullup and 103AT thermistor
71.70%
73.18%
74.86%
VTB
Threshold for –5°C based on a 10k
pullup and 103AT thermistor
75.06%
77.22%
78.32%
VTB
Threshold for 0°C based on a 10k
pullup and 103AT thermistor
71.70%
73.18%
74.86%
VTB
Recovery threshold at 5°C for when
VUTC is at –5°C based on a 10k
pullup and 103AT thermistor
68.80%
69.73%
71.71%
VTB
Recovery threshold at 10°C for
when VUTC is at 0°C based on a 10k
pullup and 103AT thermistor
64.67%
65.52%
67.46%
VTB
5
80
mV
Overcurrent charge programmable
threshold range, (VSRP-VSRN)
VOCD1
Overcurrent discharge 1
programmable threshold range
–85
–10
mV
VOCD2
Overcurrent discharge 2
programmable threshold range
–170
–20
mV
VSCD
Short circuit discharge
programmable threshold range
–340
–40
mV
VCCAL
OCD1 detection accuracy at lower
VOCD1 ≤ 20 mV
thresholds
–30 %
30 %
VCCAH
OCC, OCD1, OCD2, SCD
detection accuracy
VOCD1 > 20 mV; all OCC, OCD2
and SCD threshold ranges
–20 %
20 %
VOW
Open-wire fault voltage threshold
at VCx per cell with respect to
VCx-1
Voltage falling on VCx, 3.6 V to 0 V
VOW_HYS
Hysteresis for open wire fault
Voltage rising on VCx, 0 V to 3.6 V
450
500
550
100
mV
mV
PROTECTION DELAYS
tOVn_DELAY
Overvoltage detection delay time
0.5-s delay option
0.4
0.5
0.8
1-s delay option
0.8
1
1.4
2-s delay option
1.8
2
2.7
s
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Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and
VDD = 3 to 25 V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4
4.5
5.2
1-s delay option
0.8
1
1.5
2-s delay option
1.8
2
2.7
4.5-s delay option
4
4.5
5.5
9-s delay option
8
9
10.2
4.5-s delay option
tUVn_DELAY
Undervoltage detection delay time
UNIT
s
tOWn_DELAY
Open-wire detection delay time
3.6
4.5
5.3
s
tOTC_DELAY
Overtemperature charge detection
delay time
3.6
4.5
5.3
s
tUTC_DELAY
Undertemperature charge
detection delay time
3.6
4.5
5.3
s
tOTD_DELAY
Overtemperature discharge
detection delay time
3.6
4.5
5.3
s
tUTD_DELAY
Undertemperature discharge
detection delay time
3.6
4.5
5.3
s
tOCD1_DELAY
Overcurrent discharge 1 detection
delay time
10-ms delay option
8
10
15
20-ms delay option
17
20
26
45-ms delay option
36
45
52
90-ms delay option
78
90
105
180-ms delay option
155
180
205
350-ms delay option
320
350
405
700-ms delay option
640
700
825
1420-ms delay option
1290
1420
1620
4
5
8
5-ms delay option
tOCD2_DELAY
Overcurrent discharge 2 detection
delay time
10-ms delay option
8
10
15
20-ms delay option
17
20
26
45-ms delay option
36
45
52
90-ms delay option
78
90
105
180-ms delay option
155
180
205
350-ms delay option
320
350
405
ms
ms
700-ms delay option
640
700
825
tSCD_DELAY
Short-circuit detection delay time
960-µs delay option
528
960
1450
us
tSCD_DELAY
Short-circuit detection delay time
400-µs delay option
220
400
610
µs
tOCC_DELAY
Overcurrent charge detection
delay time
8
10
12
ms
250-ms option
225
250
275
tCD_REC
Overcurrent discharge 1,
Overcurrent discharge 2,
Overcurrent charge and shortcircuit recovery delay time
500-ms option
450
500
550
VDD ≥ 12 V, CL = 10 nF
11
12
14
V
VDD < 12 V, CL = 10 nF
VDD – 1.5
VDD
V
0.5
V
150
µs
ms
CHARGE AND DISCHARGE FET DRIVERS
VFETON
CHG/DSG on
VFETOFF
CHG/DSG off
1-mA resistive load, CHG clamped
to ground when CHG/DSG is off.
tCHGON
CHG on rise time
CL = 10 nF, 10% to 90%
50
tDSGON
DSG on rise time
CL = 10 nF, 10% to 90%
2
75
µs
tCHGOFF
CHG off fall time
CL = 10 nF, 90% to 10%
15
30
µs
tDSGOFF
DSG off fall time
CL = 10 nF, 90% to 10%
5
15
µs
10
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Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and
VDD = 3 to 25 V unless otherwise noted.
PARAMETER
TEST CONDITIONS
RCHGOFF
CHG off resistance
CHG off and pin held at 2V
RDSGOFF
DSG off resistance
DSG off and pin held at 100 mV
MIN
TYP
MAX
UNIT
0.3
0.5
0.75
kΩ
10
16
Ω
CELL BALANCING
VHYST
Hysteresis between overvoltage
and full charge voltage range
(VOV – VFC, 4 steps of 50 mV)
TA = 25°C
50
200
mV
VSTEP
Difference between the cell
balancing threshold
voltages (VCBTH – VCBTL, 4
steps of 50 mV)
TA = 25°C
50
200
mV
VCBIL
CBI low threshold
tCBI_DEG
CBI deglitch period
0.5
RBAL
Cell balancing internal FET
resistance
Cell1 through Cell5 = 4 V, VDD = 20
V
DBAL
Cell balancing duty cycle
Only one cell balanced in the stack
tBAL
Odd and even cell group balancing
duration
100
8
12
V
ms
20
Ω
90 %
521
ms
HIBERNATE MODE
VPRESH
PRES High Threshold
1.25
1.5
1.75
V
tPRES_DEG_ENT
PRES deglitch time (hibernate
entry)
4.5
s
tPRES_DEG_EXT
PRES deglitch time (hibernate exit)
10
ms
CTRC AND CTRD CONTROL
VCTR1
Enable FET driver (VSS)
With respect to VSS. Enabled <
MAX
VCTR2
Enable FET driver (Stacked)
Enabled > MIN
0.6
VDD + 2.2
V
V
VCTRDIS
Disable FET driver
Disabled between MIN and MAX
VCTRMAXV
CTRC and CTRD clamp voltage
ICTR = 600 nA
2.04
tCTRDEG_ON
CTRC and CTRD deglitch for ON
signal
8
ms
tCTRDEG_OFF
CTRC and CTRD deglitch for OFF
signal
8
ms
VDD + 2.8
VDD + 4
VDD + 0.7
V
VDD + 5
V
CURRENT STATE COMPARATOR
VSTATE_D
Discharge qualification threshold1
Measured at SRP-SRN
–1.875
mV
VSTATE_D_HYS
Discharge qualification threshold1
hysteresis
Measured at SRP-SRN
–1.25
mV
VSTATE_C
Charge qualification threshold1
Measured at SRP-SRN
1.875
mV
VSTATE_C_HYS
Charge qualification threshold1
hysteresis
Measured at SRP-SRN
1.25
mV
tSTATE
State detection qualification time
1.2
ms
LOAD DETECTION AND LOAD REMOVAL DETECTION
VLDCLAMP
LD clamp voltage
ILDCLAMP = 300 µA
ILDCLAMP
LD clamp current
VLDCLAMP = 18 V
VLDT
LD threshold
OPEN pack terminals
RLD_INT
LD input resistance when enabled
Measured to VSS
tLD_DEG
LD detection de-glitch
16
1.25
19
1.3
20
V
450
µA
1.35
200
1
1.5
V
kΩ
2.3
ms
CCFG PIN
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Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and
VDD = 3 to 25 V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
VCCFGL
CCFG threshold low (ratio of
VAVDD)
3-cell configuration
VCCFGH
CCFG threshold high (ratio of
VAVDD)
4-cell configuration
65%
VCCFGHZ
CFG threshold high-Z (ratio of
VAVDD)
5-cell configuration, CCFG floating,
internally biased
25%
tCCFG_DEG
CCFG deglitch
TYP
MAX
UNIT
10%
AVDD
100%
AVDD
45%
AVDD
33%
6
ms
CUSTOMER TEST MODE
VCTM
Customer test mode entry voltage
at VDD
VDD > VC5 + VCTM, TA = 25°C
8.5
tCTM_ENTRY
Delay time to enter and exit
customer test mode
VDD > VC5 + VCTM, TA = 25°C
50
tCTM_DELAY
Delay time of faults while in
customer test mode
TA = 25°C
200
ms
tCTM_OC_REC
Fault recovery time of OCD1,
OCD2, and SCD faults while in
customer test mode
250-ms and 500-ms options, TA =
25°C
100
ms
0
5
10
V
ms
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-4
LPWR Current (PA)
I PRES (PA)
8.6 Typical Characteristics
0
4
8
12
16
20
24
28
Voltage Applied to Pin (V)
32
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-30
-25
-20
-15
-10
-5
Voltage applied (V)
D001
Figure 8-1. Current into the PRES Pin
D002
Figure 8-2. LPWR Current
0.7
1.2
CTRC Current
CTRD Current
Bal
No bal
1.1
1
0.6
0.9
0.8
0.5
0.6
ICBO (PA)
Current (PA)
0.7
0.4
0.3
0.2
0.5
0.4
0.3
0.2
0.1
0
0.1
-0.1
-0.2
0
-0.3
-0.4
-0.1
0
2.5
5
7.5
10
12.5
15
17.5
20
Applied Voltage (V)
-0.5
-0.6
0
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
V CBO - Top of Stack (V)
D003
Figure 8-3. CTRC and CTRD Current
12
22.5
5.4
D004
Figure 8-4. CBO Current Input at 18 V
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80
3.28
ICBI
AVDD
3.2
60
3.12
50
3.04
40
2.96
30
2.88
20
2.8
10
2.72
0
2.64
-10
2.56
-20
2.48
-30
2.4
-40
2.32
-50
2.24
-60
2.16
-70
AVDD (V)
ICBI (PA)
70
2.08
-80
-0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
V CBI
3
3.3
2
3.6
D005
Figure 8-5. CBI Input Current vs. VCBI
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9 Detailed Description
9.1 Overview
The BQ77915 device is a full-feature stackable primary protector for li-ion/li-polymer batteries with a smart cellbalancing algorithm. The device implements a suite of protections including:
• Cell voltage: overvoltage, undervoltage
• Current: overcurrent charge, overcurrent discharge 1 and 2, short circuit discharge
• Temperature: overtemperature and undertemperature in charge and discharge
• PCB: cell open-wire connection
• FET body diode protection
Protection thresholds and delays are factory-programmed and available in a variety of configurations.
The BQ77915 device supports 3-series to 5-series cell configurations. Up to four devices can be stacked to
support ≥6-series cell configurations, providing protections up to a 20-series cell configuration. It is possible to
support greater than 20-series cell configurations, but with careful consideration of delays.
The device has an ultra-low current HIBERNATE mode for shipping and storage. The device also features a
smart cell-balancing algorithm to minimize cell-to-cell imbalance. The device has built-in CHG and DSG drivers
for low-side N-channel FET protection, which automatically opens up the CHG and/or DSG FETs after protection
delay time when a fault is detected. A set of CHG/DSG overrides is provided to allow disabling of the CHG
and/or DSG driver externally. Although the host system can use this function to disable the FET control, the main
usage of these pins is to channel down the FET control signal from the upper device to the lower device in a
cascading configuration in ≥6-series battery packs.
9.1.1 Device Functionality Summary
Table 9-1. Device Functionality Summary
FAULT DESCRIPTOR
OV
14
FAULT RECOVERY METHOD and SETTING OPTIONS
Overvoltage
3 V to 4.575 V (25-mV step)
0.5, 1, 2, 4.5 s
Hysteresis
0, 100, 200, 400 mV
UV
Undervoltage
1.2 V to 3 V
(100-mV step for < 2.5 V,
50-mV step for ≥ 2.5 V)
1, 2, 4.5, 9 s
Load Removal + Hysteresis
0, 200, 400, 800 mV
OW
Open wire (cell to pcb
disconnection)
0 (disabled), 100 nA, 200 nA,
400 nA
4.5 s
Restore bad VCx to pcb connection
VCx > VOW
OTD(1)
Overtemperature during
discharge
65°C or 70°C
4.5 s
Hysteresis or Load Removal + Hysteresis
10°C
OTC(1)
Overtemperature during
charge
45°C or 50°C
4.5 s
Hysteresis
10°C
UTD(1)
Undertemperature during
discharge
–20°C or –10°C
4.5 s
Hysteresis
10°C
UTC (1)
Undertemperature during
charge
–5°C or 0°C
4.5 s
Hysteresis
10°C
OCC
Overcurrent during charge
5 mV to 80 mV (5-mV step)
10 ms
Timer auto-release and load detection, timer
auto-release only, load detection only
OCD1
Overcurrent1 during
discharge
–10 mV to –85 mV (5-mV step)
10, 20, 45, 90, 180, 350, 700,
1420 ms
OCD2
Overcurrent1 during
discharge
–20 mV to –170 mV (10-mV
step)
5, 10, 20, 45, 90, 180, 350,
700 ms
Short circuit discharge
–40 mV to –340 mV (20-mV
step)
400, 960 µs
CTRC
CHG signal override control
Disable via external control or
via CHG signal from the upper
device in stack configuration
tCTRDEG_ON
Enable via external control or via CHG signal
from the upper device in stack configuration
tCTRDEG_OFF
CTRD
DSG signal override control
Disable via external control or
via DSG signal from the upper
device in stack configuration
tCTRDEG_ON
Enable via external control or via DSG signal
from the upper device in stack configuration
tCTRDEG_OFF
SCD
(1)
FAULT DETECTION THRESHOLD and DELAY OPTIONS
Timer auto-release and load removal, timer
auto-release only, load removal only
250 ms or 500 ms
These thresholds are target-based on temperature, but they are dependent on external components that could vary based on
customer selections. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to
VTB and TS. Actual thresholds must be determined in mV; refers to the over- and undertemperature mV threshold in the Electrical
Characteristics table.
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Table 9-2. Cell Balancing Threshold Summary
NAME
Description
Options
VSTART
Start threshold for cell balancing
3.5 V, 3.8 V
VHYST
Hysteresis between overvoltage and full charge voltage range (VOV
– VFC)
50 mV, 100 mV, 150 mV, 200 mV
VSTEP
Difference between the cell balancing threshold voltages (VCBTH –
VCBTL)
50 mV, 100 mV, 150 mV, 200 mV
9.2 Functional Block Diagram
CCFG
VDD
Configuration
Logic
BG
Reference
Bias
AVDD
VDIG Regulator
& Shutdown
VTB
POR
VC5
TS
VC4
VC3
MUX
Compare
1
EEPROM
VC2
CTRC
Stack
Interface
VC1
CTRD
VC0
Open
Wire
Bq77915
Control
Logic
CHG
Driver
CHG
DSG Driver
DSG
CBI
Cell
Balancing
CBO
MUX
Load
Detection
Compare
2
OCD½
Delay
SRP
LD
OCDP
State
Compare
SRN
Clock
And
WDT
Hibernate
Mode
LPWR
PRES
VSS
9.3 Feature Description
9.3.1 Protection Summary
Two comparators are time-multiplexed to detect all of the protection fault conditions, and to measure cell
voltages for balancing. Each of the comparators runs on a time-multiplexed schedule and cycles through the
assigned protection fault checks and voltage measurements. Comparator 1 checks for OV, UV, OW, OTC, OTD,
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UTC, and UTD protection faults and measure individual cell voltages for balancing. Comparator 2 checks for
OCD1, OCD2, SCD, and OCC protection faults. For OV, UV, and OW protection faults and cell balancing, every
cell is checked individually in a round-robin fashion, starting with cell 1 and ending with the highest selected cell.
The number of the highest cell is configured using the CCFG pin.
Devices can be ordered with various timing and hysteresis settings. See Table 9-1 for more details.
9.3.2 Fault Operation
9.3.2.1 Operation in OV
An OV fault detection occurs when at least one of the cell voltages is measured above the OV threshold, VOV for
a time of OV delay, tOVn_DELAY. The CHG FET is turned off. The OV fault recovers when the voltage of the cell in
fault is below the (OV threshold – OV hysteresis, VHYS_OV) for a time of OV delay.
The device assumes an OV fault after reset, and clears automatically after an OV delay if all cell voltages are
below the OV threshold minus hysteresis. In the event of an overvoltage fault condition on a particular cell, the
balancing FET corresponding to that cell is turned on until the cell voltage drops to the full charge voltage or until
the cell has recovered from overvoltage fault condition, whichever occurs earlier. See Cell Balancing for more
details.
The state comparator is turned on when CHG is turned off. If a discharge current is detected, the device
immediately switches the CHG back on. The response time of the state comparator is typically in 700 µs and
should not pose any disturbance in the discharge event.
9.3.2.2 Operation in UV
A UV fault detection is when at least one of the cell voltages is measured below the UV threshold, VUV, for a
duration of a UV delay, tUVn_DELAY. The DSG FET is turned off. The UV fault recovers when:
•
•
The voltage of the cell in fault goes above the (UV threshold + UV hysteresis, VHYS_UV) for a time of a UV
delay OR
The voltage of the cell in fault goes above the (UV threshold + UV hysteresis, VHYS_UV) for a time of a UV
delay and the load is removed.
The state comparator might turn on the DSG FET before the cell voltage recovers to protect the body diode.
To minimize device supply current when a UV fault has occurred or CTRD was driven to the DISABLED state,
the BQ77915 device disables all discharge overcurrent detection blocks. Upon recovery from the fault or when
CTRD is no longer externally driven, all discharge overcurrent detection blocks are reactivated.
9.3.2.3 Operation in OW
An OW fault detection is when at least one of the cell voltages is measured below the OW threshold, VOW, for a
duration of OW delay, tOWn_DELAY. CHG and DSG are turned off. The OW fault recovers when the cell voltage in
fault is above the OW threshold + OW hysteresis, VOW_HYS, for a time of OW delay.
The tOWn_DELAY time starts when the voltage at a given cell is detected below the VOW threshold and is not from
the time that the actual event of an open wire occurs. During an open-wire event, it is common that the device
detects an undervoltage and/or overvoltage fault before detecting an open-wire fault. This may occur due to the
differences in fault thresholds, fault delays, and the VCx pin filter capacitor values. To ensure that CHG and DSG
return to normal operation mode, the OW, OV, and UV faults' recovery conditions must be met.
9.3.2.4 Operation in OCD1
An OCD1 fault is when the discharge load is high enough that the voltage across the RSNS resistor (VSRP–VSRN)
is measured below the OCD1 voltage threshold, VOCD1, for a duration of OCD1 delay, tOCD1_DELAY. CHG and
DSG are turned off.
The OCD1 fault recovers when:
•
•
•
16
Load removal is detected only, VLD < VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load removal is detected.
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9.3.2.5 Operation in OCD2
An OCD2 fault is when the discharge load is high enough that the voltage across the RSNS resistor (VSRP–VSRN)
is measured below the OCD2 voltage threshold, VOCD2, for a duration of OCD2 delay, tOCD2_DELAY. CHG and
DSG are turned off.
The OCD2 fault recovers when:
•
•
•
Load removal detected only, VLD < VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load removal is detected.
9.3.2.6 Programming the OCD1/2 Delay Using the OCDP Pin
OCD1 and OCD2 detection delays are programmed by the resistor connected from the OCDP pin to VSS. The
device checks for the resistor value at power-up. For the bottom device in a stack, Table 9-3 shows how the
resistor values should be chosen.
Table 9-3. OCD1/2 Delay Using OCDP Pin
Resistor Value
OCD1 Delay
OCD2 Delay
750 kΩ±1%
1420 ms
700 ms
604 kΩ±1%
700 ms
350 ms
487 kΩ±1%
350 ms
180 ms
383 kΩ±1%
180 ms
90 ms
294 kΩ±1%
90 ms
45 ms
196 kΩ±1%
45 ms
100 kΩ±1%
20 ms
EEPROM Delay Options (EC Table)
The OCD2 delay is roughly half of the OCD1 delay when any of the first six resistors are connected from the
OCDP pin to VSS. However, if a 100-kΩ resistor is connected, the OCD1 and OCD2 delays are independent of
each other and can be chosen to have any value provided in the EC table.
For any device other than the bottom device in a stacked configuration, a 10-MΩ resistor must be connected
from the OCDP pin of that device to the VSS pin of the device.
If the OCDP pin is left open, the OCD1 and OCD2 delays are determined by the EEPROM settings.
9.3.2.7 Operation in SCD
An SCD fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP–VSRN),
is measured below the SCD voltage threshold, VSCD, for a duration of SCD delay, tSCD_DELAY. CHG and DSG are
turned off.
The SCD fault recovers when:
•
•
•
Load removal detected only, VLD < VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load removal is detected.
9.3.2.8 Operation in OCC
An OCC fault is when the charging current is high enough that the voltage across the RSNS resistor, (VSRP–
VSRN), is measured above the OCC voltage threshold, VOCC, for a duration of OCC delay, tOCC_DELAY. CHG and
DSG are turned off.
The OCC fault recovers when:
•
•
•
Load detected only, VLD > VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load is detected.
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9.3.2.9 Overcurrent Recovery Timer
The timer expiration method activates an internal recovery timer as soon as the initial fault condition exceeds the
OCD1/OCD2/SCD/OCC time. When the recovery timer reaches its limit, both of the CHG and DSG drivers are
turned back on. If the combination option of the timer expiration AND load removal/detection is used, then the
load removal/detection condition is only evaluated upon expiration of the recovery timer, which can have an
expiration period of tCD_REC.
9.3.2.10 Load Detection and Load Removal Detection
The load detection and removal detection features are implemented with the LD pin. When no undervoltage fault
and current fault conditions are present, the LD pin is held in an open-drain state. Once any UV, OCD1, OCD2,
OCC, or SCD fault occurs and load removal or detection is selected as device of the recovery conditions, a high
impedance pulldown path to VSS is enabled on the LD pin. With an external load still present, the LD pin will be
externally pulled high: It is internally clamped to VLDCLAMP and should also be resistor-limited through RLD
externally to avoid conducting excessive current. If the LD pin voltage exceeds VLDT for tLD_DEG, it is interpreted
as a load present condition and is one of the recovery mechanisms selectable for an OCC fault. When the load
is eventually removed, the internal high-impedance path to VSS should be sufficient to pull the LD pin below
VLDT for tLD_DEG. This is interpreted as a load removed condition and is one of the recovery mechanisms
selectable for UV, OCD1, OCD2, and SCD faults.
Table 9-4. Load State
LD PIN
LOAD STATE
≥ VLDT for tLD_DEG
Load present
< VLDT for tLD_DEG
Load removed
9.3.2.11 Operation in OTC
An OTC fault is when the temperature increases such that the voltage across an NTC thermistor goes below the
OTC voltage threshold, VOTC, for an OTC delay time, tOTC_DELAY. CHG is turned off. The state comparator is
turned on when CHG is turned off. If a discharge current is detected, the device immediately switches the CHG
back on. The response time of the state comparator is typically in 700 µs and should not pose any disturbance in
the discharge event. The OTC fault recovers when the voltage across the thermistor goes above the OTC
recovery threshold, VOTC_REC, for an OTC delay time.
9.3.2.12 Operation in OTD
An OTD fault is when the temperature increases such that the voltage across an NTC thermistor goes below the
OTD voltage threshold, VOTD, for an OTD delay time, tOTD_DELAY. CHG and DSG are turned off.
The OTD fault recovers when:
•
•
The voltage across thermistor gets above OTD recovery threshold, VOTD_REC, for a time of OTD delay OR
The voltage across thermistor gets above OTD recovery threshold, VOTD_REC, for a time of OTD delay and
load is removed.
9.3.2.13 Operation in UTC
A UTC fault occurs when the temperature decreases such that the voltage across an NTC thermistor gets above
the UTC voltage threshold, VUTC, for a time of a UTC delay, tUTC_DELAY. CHG is turned off. The state comparator
is turned on when CHG is turned off. If a discharge current is detected, the device will immediately switch the
CHG back on. The response time of the state comparator is typically in 700 µs and should not pose any
disturbance in the discharge event. The UTC fault recovers when the voltage across thermistor gets below UTC
recovery threshold, VUTC_REC, for a time of UTC delay.
9.3.2.14 Operation in UTD
A UTD fault occurs when the temperature decreases such that the voltage across an NTC thermistor goes
above the UTD voltage threshold, VUTD, for a UTD delay time, tUTD_DELAY. CHG and DSG are turned off. The
UTD fault recovers when the voltage across thermistor gets below UTD recovery threshold, VUTD_REC, for a time
of UTD delay.
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9.3.3 Protection Response and Recovery Summary
Table 9-5 summarizes how each fault condition affects the state of the DSG and CHG output signals, as well as
the recovery conditions required to resume charging and/or discharging. As a rule, the CHG and DSG output
drivers are enabled only when no respective fault conditions are present. When multiple simultaneous faults
(such as an OV and OTD) are present, all faults must be cleared before the FET can resume operation.
Table 9-5. Fault Condition, State, and Recovery Methods
FAULT
FAULT TRIGGER CONDITION
CHG
DSG
RECOVERY METHOD
CTRC disabled
CTRC disabled for deglitch
delay time
OFF
—
CTRC must be enabled for deglitch delay time
CTRD disabled
CTRD disabled for deglitch
delay time
—
OFF
CTRD must be enabled for deglitch delay time
OV
V(Cell) rises above VOV for
delay time
OFF
—
UV
V(Cell) drops below VUV for
delay time
—
OW
VCX – VCX–1 < VOW for delay
time
OCC
TRIGGER DELAY
RECOVERY
DELAY
tCTRDEG_ON
tCTRDEG_OFF
V(Cell) drops below VOV – VHYS_OV for delay
tOVn_DELAY
OFF
DSG FET turned on after Load is removed and
V(Cell) rises above VUV + VHYS_UV for delay.
tUVn_DELAY
OFF
OFF
Bad VCX recovers such that VCX – VCX–1 >
VOW + VOW_HYS for delay
tOWn_DELAY
(VSRP – VSRN) > VOCC for
delay time
OFF
OFF
Recovery delay expires, OR
LD detects > VLDT, OR
Recovery delay expires + LD detects > VLDT
tOCC_DELAY
tCD_REC
OCD1, OCD2,
SCD
(VSRP – VSRN) < VOCD1,
VOCD2, or VSCD for delay
time
OFF
OFF
Recovery delay expires, OR
LD detects < VLDT, OR
Recovery delay expires + LD detects < VLDT
tOCD1_DELAY,
tOCD2_DELAY,
tSCD_DELAY
tCD_REC
OTC(1)
Temperature rises above TOTC
for delay time
OFF
—
Temp drops below TOTC – TOTC_REC for delay
tOTC_DELAY
OTD(1)
Temperature rises above TOTD
for delay time
OFF
OFF
Temp drops below TOTD – TOTD_REC for delay,
OR
Temp drops below TOTD – TOTD_REC for delay
and Load is removed
tOTD_DELAY
UTC(1)
Temperature drops below TUTC
for delay time
OFF
—
Temperature rises above TUTC + TUTC_REC for
delay
tUTC_DELAY
UTD(1)
Temp drops below TUTD for
delay time
OFF
OFF
Temp rises above TUTD + TUTD_REC for delay
tUTD_DELAY
(1)
TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected
thermistor resistance.
To prevent FET damage, there are times when the CHG FET or DSG FET may be enabled even though a fault
event has occurred. See the State Comparator section for details.
9.3.4 Cell Balancing
Cell balancing is performed by comparing the cell voltages with respect to cell balancing threshold voltages,
evaluating the results of the comparison and controlling the cell balancing FET, which over a period of time will
allow for closer cell voltages, thereby extending battery pack life. The conditions for performing cell balancing
are: CBI is connected to VSS, no device in the stack is in a fault condition, and the pack is charging. The State
Comparator section lists the conditions for the device's charging state.
CBI is the cell balancing input pin. It enables cell balancing function for the device.
•
•
Leave the CBI pin floating to disable cell balancing. An internal circuit pulls up the CBI pin to AVDD in this
case.
Connect CBI to VSS to enable cell balancing.
In a single device, cell balancing of all the odd numbered cells can happen at the same time, and balancing of all
the even numbered cells can also happen at the same time, but odd and even cells are not balanced at the
same time. When devices are stacked on top of each other, it must be ensured in the PCB layout that the trace
from VC5 pin to a cell and the trace from the VC0 pin of the next upper device to the immediately higher cell are
kept separate.
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All cell balancing FETs are turned off during voltage measurements. If odd numbered and even numbered cells
need balancing at the same time, one single cycle time tBAL is dedicated for odd numbered cells alone followed
by the next tBAL dedicated for even numbered cells alone. See an example of adjacent cell balancing in Figure
9-1.
Figure 9-1. Balancing cells 1, 2, and 3
In a stacked configuration, the CBO pin of the bottom device should be connected to the CBI pin of the next
upper device through a 10-kΩ resistor and so forth.
When a cell is in OV, its corresponding balancing FET will be turned on if CBI is connected to VSS and if there
are no discharge faults anywhere in the stack. The balancing FET will be ON until the cell voltage drops to VFC
or VOV – VHYS_OV, whichever occurs earlier.
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VOV
VFC
CV5
VCBTH
CV3
CV1
CV4
VCBTL
CV2
VSTART
Figure 9-2. Cell-Balancing Algorithm
VCBTL is the lower cell balancing threshold and VCBTH is the upper cell balancing threshold. In Figure 9-2, the
balancing FET will be turned on only for the cell CV5. The BQ77915 VSTART is set at 3.8 V; therefore, cell
balancing starts only when individual cell voltages exceed 3.8 V. The difference between VCBTH and VCBTL can
be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV. The difference between
the VOV and VFC can also be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV.
When using the integrated MOSFETs for cell balancing, the cell monitor filter resistance RINI controls the amount
of cell balancing current the device can supply to the cells. Internal cell balancing should be used for cell
balancing currents up to 50 mA. External MOSFETs have to be used if higher cell balancing currents are
required. In the case of external balancing, the balancing current is controlled by the resistor RCB in series with
the external MOSFET, as shown in Figure 9-3. The pin filter resistance RINE should be 1 kΩ and the capacitance
CINE should be 0.1 µF. The gate bias voltage necessary to turn on the FET connected to Cell(n) is generated by
the resistor RINE connected to the VC(n–1) pin. The external MOSFET must be selected with a threshold voltage
less than 1.7 V.
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RVDD
PACK+
CVDD
CVDD
RINE
RCB
CINE
RINE
VDD
CTRD
AVDD
CTRC
VC5
PRES
PRES
VC4
CBO
CBO
VC3
CCFG
VC2
VTB
VC1
RCB
bq77915
VC0
CINE
RINE
RCB
CINE
TS
RTS_PU
RTS
ROCD
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
RDSG
CBI
RCHG
RINE
RCB
CINE
RLD
RINE
RCB
CINE
RINE
RGS
CINE
RGS
RSNS
PACK±
Figure 9-3. Cell Balancing with External MOSFETs
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9.3.5 HIBERNATE Mode Operation
Tool
Trigger
PACK+
R2
PRES
VDD
+
System /
Charger
Internal Weak
Pull-Down
±
bq77915
+
LPWR
±
VSS
R3
PRES
VDD
+
Internal Weak
Pull-Down
±
bq77915
+
LPWR
±
VSS
DSG
CHG
Q2
Q3
PACK±
Figure 9-4. HIBERNATE Mode Simplified Schematic 1
PACK+
R2
+
System /
Charger
PRES
VDD
Internal Weak
Pull-Down
±
bq77915
+
±
LPWR
VSS
R3
PRES
+
VDD
Internal Weak
Pull-Down
±
bq77915
+
±
LPWR
VSS
DSG
Q3
CHG
Q2
PACK±
Figure 9-5. HIBERNATE Mode Simplified Schematic 2
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The BQ77915 device has two dedicated pins (PRES and LPWR) for HIBERNATE mode operation. Most of the
internal circuitry is turned off in HIBERNATE mode to save power. Charge and discharge FETs are turned off and
all fault protections are disabled.
The PRES pin has an internal pulldown connected to the pin, which pulls PRES low. When the PRES pin is left
floating (the system or charger is not connected to the pack), the load is not connected, and the device is not in
any fault condition, the device enters HIBERNATE mode after tPRES_DEG_ENT time. Once in HIBERNATE mode,
the system or the charger should drive this pin high (>VPRESH) through the resistor R2 for NORMAL mode
operation. When the battery pack (in HIBERNATE mode) is inserted to the tool/system or when a charger is
connected to the pack, the system has to provide a pull-up to the PRES pin, which puts the device back to
NORMAL mode. The device will exit HIBERNATE mode after a tPRES_DEG_EXT deglitch time.
In a stacked configuration, connect the LPWR pin of an upper device to the PRES pin of a lower device through
the resistor R3.
9.3.6 Configuration CRC Check and Comparator Built-In-Self-Test
To improve reliability, the device has a built-in CRC check for all the factory-programmable configurations, such
as the thresholds and delay time settings. When the device is set up in the factory, a corresponding CRC value
is also programmed to the memory. During normal operation, the device compares the configuration setting
against the programmed CRC periodically. A CRC error will reset the digital circuitry and increment the CRC
fault counter. The digital reset forces the device to reload the configuration as an attempt to correct the
configurations. A correct CRC check reduces the CRC fault counter. Three CRC fault counts will turn off both the
CHG and DSG drivers. If FETs are opened due to a CRC error, only a POR can recover the FET state and reset
the CRC fault.
In addition to the CRC check, the device also has built-in-self-test (BIST) on the comparators. The BIST runs in a
scheduler, and each comparator is checked for a period of time. If a fault is detected for the entire check period,
the particular comparator is considered at fault, and the CHG and DSG FETs are turned off. The BIST continues
to run by the scheduler even if a BIST fault is detected. If the next BIST result is good, the FET driver resumes
normal operation.
The CRC check and BIST check do not affect the normal operation of the device. However, there is not specific
indication when a CRC or BIST error is detected besides turning off the CHG and DSG drivers. If there is no
voltage, current, or temperature fault condition present, but CHG and DSG drivers remain off, it is possible either
CRC or BIST error is detected. Users can POR the device to reset the device.
9.3.7 Fault Detection Method
9.3.7.1 Filtered Fault Detection
The device detects a fault once the applicable fault is triggered after accumulating sufficient trigger sample
counts. The filtering scheme is based on a simple add/subtract. Starting with the triggered sample count cleared,
the counts go up for a sample that is taken across the tested condition (for example, above the fault threshold
when looking for a fault) and the counts go down for a sample that is taken before the tested condition (that is,
below the fault threshold). Figure 9-6 shows an example of a signal that triggers a fault when accumulating five
counts above the fault threshold. Once a fault has been triggered, the trigger sample counts reset.
Note
With a filtered detection, when the input signal falls below the fault threshold, the sample count does
not reset but only counts down, as shown in Figure 9-6. Therefore, it is normal to observe a longer
delay time if a signal is right at the detection threshold. The noise can push the delay count to be
counting up and down, resulting in a longer time for the delay counter to reach its final accumulated
trigger target.
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Based on fault trigger after 5 counts
Fault Threshold
Recovery Threshold
FAULT
FAULT
Sample
Triggered Sample Count
0
1
2
3
4
0
0
0
1
2
3
4
5
0
0
0
0
0
0
Looking for a fault
0
0
0
0
0
1
2
0
Looking for a recovery
1
2
3
4
5
0
0
Looking for a fault
Figure 9-6. Filtered Fault Detection
9.3.8 State Comparator
A small, low-offset analog state comparator monitors the sense resistor voltage (SRP–SRN) to determine when
the pack is in a DISCHARGE state less than a minimum threshold, VSTATE_D, or a CHARGE state greater than a
maximum threshold, VSTATE_C. The state comparator is used to turn the CHG FET on to prevent damage/
overheating during discharge in fault states that call for having only the CHG FET off, and vice versa for the DSG
FET during charging in fault that call for having only the DSG FET off. Also, the state comparator is turned on in
NORMAL mode (CHG and DSG FETs on) during cell balancing to ensure that cell balancing is performed only
when the pack is charging.
Table 9-6 summarizes when the state comparator is operational. The state comparator is only on during faults
detected that call for only one FET to be turned off, and also in NORMAL mode during cell balancing to ensure
that cell balancing is performed only when the pack is charging.
Table 9-6. State Comparator Operation Summary in Fault Conditions
CHG
DSG
NORMAL mode, no cell balancing
MODE
ON
ON
STATE COMP
OFF
NORMAL mode, cell balancing
ON
ON
VSTATE_C detection
UV, CTRD
ON
OFF
VSTATE_C detection
OV, UTC, OTC, CTRC
OFF
ON
VSTATE_D detection
OCD1, OCD2, SCD, OCC, UTD, OTD, OW
OFF
OFF
OFF
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VSTATE_D_HYS
VSTATE_C_HYS
PACK IS DISCHARGING
PACK IS CHARGING
PACK IS CHARGING
PACK IS DISCHARGING
SRP - SRN
VSTATE_D
0V
VSTATE_C
Figure 9-7. State Comparator Thresholds
Any time a CHG fault is present and a DSG fault is not present, the device will enable the state comparator. If
the pack is in a fault state where charging is prohibited but discharging is permitted (OV, OTC, UTC, and CTRC),
a discharge may occur. When this happens, the CHG FET driver will be turned on to avoid damage, as it will
otherwise carry the discharge current through its body diode. The state comparator (with the VSTATE_D threshold
and VSTATE_D_HYS hysteresis) remains on for the entire duration of a CHG fault with no DSG fault event.
If there is a DSG fault under CTRD conditions, the DSG FET would be turned on if charge is detected. The state
comparator (with VSTATE_C threshold and VSTATE_C_HYS hysteresis) remains on for the entire duration of a DSG
fault with no CHG fault event.
9.3.9 DSG FET Driver Operation
The DSG pin is driven high only when no related faults (UV, OW, OTD, UTD, OCD1, OCD2, SCD, OCC, and
CTRD disabled) are present and the device is not in HIBERNATE mode of operation. It is a fast switching driver
with a target on resistance of about 15 Ω–20 Ω and an off resistance of RDSGOFF. It is designed to enable
customers to select the optimized RGS value to archive the desirable FET rise and fall time per the application
requirement and the choice of FET characteristics. When the DSG FET is turned off, the DSG pin drives low and
all discharge overcurrent protections (OCD1, OCD2, SCD) are disabled to better conserve power. These resume
operation when the DSG FET is turned on. The device provides FET body diode protection through the state
comparator if one FET driver is on and the other FET driver is off.
The DSG driver may be turned on to prevent FET damage if the battery pack is charging while a discharge
inhibit fault condition is present. This is done by the state comparator. The state comparator (with VSTATE_C
threshold and VSTATE_C_HYS hysteresis) remains on for the entire duration of a DSG fault with no CHG fault
event.
• If (SRP–SRN) ≤ (VSTATE_C – VSTATE_C_HYS) and no charge event is detected, the DSG FET output will remain
OFF due to the presence of a DSG fault.
• If (SRP–SRN) > VSTATE_C and a charge event is detected, the DSG FET output will turn ON for body diode
protection.
See the Section 9.3.8 section for details.
The presence of any related faults, as shown in Figure 9-8, results in the DSGFET_OFF signal.
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DSGFET_OFF_UVn
DSGFET_OFF_OCD1
DSGFET_OFF_OCD2
DSGFET_OFF_OCC
HIBERNATE
DSGFET_OFF
DSGFET_OFF_SCD
DSGFET_OFF_UTD
DSGFET_OFF_OTD
OWn
CTRD
Figure 9-8. Faults that Can Qualify DSGFET_OFF
9.3.10 CHG FET Driver Operation
The CHG pin is driven high only when no related faults (OV, OW, OTC, UTC, OTD, UTD, OCD1, OCD2, SCD,
OCC, and CTRC disabled) are present and the pack is not in HIBERNATE mode of operation. The CHG pin is
used to drive the CHG FET, which is designed to be used on the single device configuration or used by the
bottom device in a stack configuration.
Turning off the CHG pin has no influence on the overcurrent protection circuitry. The CHG pin is designed to turn
on very quickly; the internal on resistance is about 2 kΩ. The CHG FET turn off relies on the external resistor
connected in parallel to the gate-source nodes of the NCH power FET.
The CHG FET may be turned on to protect the FET's body diode if the pack is charging, even if a charging
inhibit fault condition is present. This is done through the state comparator. The state comparator (with VSTATE_D
threshold and VSTATE_D_HYS hysteresis) remains on for the entire duration of a DSG fault with no CHG fault
event.
• If (SRP–SRN) > (VSTATE_D + VSTATE_D_HYS) and no discharge event is detected, the CHG FET output will
remain OFF due to the presence of a CHG fault.
• If (SRP–SRN) ≤ VSTATE_D and a discharge event is detected, the CHG FET output will turn ON for body diode
protection.
The CHGFET_OFF signal is a result of the presence of any related faults as shown in Figure 9-9.
CHGFET_OFF_OVn
CHGFET_OFF_UTC
CHGFET_OFF_OTC
CHGFET_OFF_OCD1
CHGFET_OFF_OCD2
CHGFET_OFF_OCC
CHGFET_OFF
HIBERNATE
CHGFET_OFF_SCD
CHGFET_OFF_UTD
CHGFET_OFF_OTD
OWn
CTRC
Figure 9-9. Faults that Can Qualify CHGFET OFF
9.3.11 External Override of CHG and DSG Drivers
The device allows direct disabling of the CHG and DSG drivers through the CTRC and CTRD pins, respectively.
Figure 9-10 shows the operation of the CTRC and CTRD pins. To support the simple-stack solution for highercell count packs, these pins are designed to operate above the device’s VDD level. Connect a 10-MΩ resistor
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between a lower device CTRC and CTRD input pins to an upper device's CHG and DSG output pins (see the
schematics in Section 9.3.13).
CTRC only enables or disables the CHG pin, while CTRD only enables or disables the DSG pin. When the CTRx
pin is in the DISABLED region, the respective FET pin will be off, regardless of the state of the protection
circuitry. When the CTRx pin is in either ENABLED region, the protection circuitry determines the state of the
FET driver.
Note
In any event where CTRC is disabled, CTRD is enabled, no DSG FET related faults are present, and
(SRP–SRN) < VSTATE_D, the CHG output pin will be held high regardless. In any event where CTRD is
disabled, CTRC is enabled, no charge FET related faults present, and (SRP–SRN) > VSTATE_C, the
DSG output pin will be held high regardless.
Both CTRx pins apply the fault-detection filtered method to improve the robustness of the signal detection. The
counter counts up if an ENABLED signal is sampled; the counter counts down if a DISABLED signal is sampled.
When the counter counts up from 0% to > 70% of its full range, which takes about 7-ms typical of a solid signal,
the CTRx pins take the signal as ENABLED. If the counter counts down from 100% to < 30% of its full range,
which takes about 7-ms typical of a solid signal, the CTRx pins take the signal as DISABLED. From a 0 count
counter (solid DISABLE), a solid ENABLE signal takes about tCTRDEG_ON time to deglitch. From a 100% count
(solid ENABLE), a solid DISABLE signal takes about tCTRDEG_OFF time to deglitch. Although such a filter scheme
provides a certain level of noise tolerance, it is highly recommended to shield the CTRx traces and keep the
traces as short as possible in the PCB layout design. The CTRx deglitch time will add onto the FET response
timing on OV, UV, and OW faults in a stack configuration. The tCTRDEG_OFF time adds an additional delay to the
fault detection timing and the tCTRDEG_ON time adds an additional delay to the fault recovery timing.
ENABLED
VCTR2
VCTRDIS (max)
VDD
DISABLED
(FET OFF)
VCTRDIS (min)
VCTR1
ENABLED
VSS
CHG driver set by CTRC
DSG driver set by CTRD
Figure 9-10. CTRC, CTRD Voltage Levels
9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
The BQ77915 device supports 3-series, 4-series, or 5-series packs. To avoid accidentally detecting a UV fault on
unused (shorted) cell inputs, the device must be configured for the specific cell count of the pack. This is set with
the configuration pin, CCFG, which is mapped as shown in Table 9-7. The device periodically checks the CCFG
status and takes tCCFG_DEG time to detect the pin status.
Table 9-7. CCFG Configurations
CCFG
CONFIGURATION
CONNECT TO
< VCCFGL for tCCFG_DEG
3 cells
VSS
Within VCCFGM for tCCFG_DEG
4 cells
AVDD
> VCCFGH for tCCFG_DEG
5 cells
Floating
The CCFG pin should be tied to the recommended net from Table 9-7. The device compares the CCFG input
voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is
for 5 series, leave the CCFG pin floating. The internal pin bias is approximately 33% of the AVDD voltage for 5series configuration.
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RVDD
PACK+
CVDD
CVDD
VDD
CTRD
AVDD
CTRC
VC5
PRES
VC4
CBO
VC3
CCFG
VC2
RIN
VC1
bq77915
VC0
RIN
RHIB
RTS_PU
VTB
TS
RTS
ROCD
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
RDSG
CIN
RCHG
RIN
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACK–
Figure 9-11. 3-Series Configuration with Cell Balancing and HIBERNATE Mode Disabled
RVDD
PACK+
CVDD
CVDD
RIN
CIN
VDD
CTRD
AVDD
CTRC
VC5
PRES
VC4
CBO
VC3
CCFG
VC2
RIN
VC1
CIN
RIN
CIN
bq77915
PRES
RTS_PU
VTB
TS
VC0
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
RDSG
RTS
ROCD
RCB
RCHG
RIN
CIN
RIN
RLD
CIN
RGS
RGS
RSNS
PACK–
Figure 9-12. 4-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
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RVDD
PACK+
CVDD
CVDD
RIN
CIN
RIN
CTRD
AVDD
CTRC
VC5
PRES
VC4
CBO
VC3
CCFG
VC2
VTB
VC1
CIN
RIN
CIN
RIN
RIN
VDD
bq77915
TS
VC0
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
RDSG
CIN
PRES
RTS_PU
RTS
ROCD
RCB
RCHG
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACK–
Figure 9-13. 5-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
9.3.13 Stacking Implementations
Higher than 5-series cell packs may be supported by daisy-chaining multiple devices. Each device ensures OV,
UV, OW, OTC, OTD, UTC, and UTD protections of its directly monitored cells, while any fault conditions
automatically disable the global CHG and/or DSG FET driver.
Note
Upper devices do not provide OCC, OCD1, OCD2, or SCD protections, as these are based on pack
current. For the BQ77915 device used on the upper stack, the SRP and SRN pins should be shorted
to prevent false detection.
To configure higher-cell packs, follow this procedure:
•
•
•
•
•
•
•
•
•
30
Each device must have a connection on at least each of its three lowest cell input pins.
It is highly recommended to connect higher cell count to the upper devices (for example, for a 7-series
configuration, connect four cells on the upper device and three cells on the bottom device). This is to provide
stronger CTRx signal to the bottom device.
Ensure that each device’s CCFG pin is configured appropriately for its specific number of cells (that is, three,
four, or five cells).
Connect the upper CHG pins with an RCTRx to the immediate lower device CTRC pin.
Connect the upper DSG pins with an RCTRx to the immediate lower device CTRD pin.
All upper devices should have their SRP and SRN pins shorted to their VSS pins.
Connect the upper CBI pins with an RCB to the immediate lower device CBO pin.
Connect the upper LPWR pins with an RHIB to the immediate lower device PRES pin.
Connect the upper OCDP pins with a 10-MΩ resistor to VSS. Use the lower OCDP pin to program the
OCD1/2 delay.
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RVDD
PACK+
CVDD
CVDD
RIN
CIN
RIN
VDD
CTRD
AVDD
CTRC
VC5
PRES
VC4
CBO
VC3
CCFG
VC2
VTB
VC1
CIN
bq77915
VC0
RIN
CIN
RIN
RTS_PU
RTS
TS
10 0Ÿ
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
RCTRC
RCTRD
CIN
RIN
PRES
R2
CIN
RLD
CIN
RIN
RHIB
RVDD
RCB
CVDD
CVDD
RIN
CIN
RIN
VDD
CTRD
AVDD
CTRC
VC5
PRES
VC4
CBO
VC3
CCFG
VC2
VTB
VC1
CIN
RIN
CIN
RIN
RTS
TS
VC0
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
ROCD
RCB
RDSG
CIN
RIN
bq77915
RTS_PU
RCHG
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACK±
Figure 9-14. 10-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
9.3.14 Zero-Volt Battery Charging Inhibition
Once the device is powered up, it can pull the CHG pin up if the VDD ≥ VSHUT, which varies from about 1 V per
cell on a 3-series configuration to about 0.6 V per cell on a 5-series configuration. If the battery stack voltage
falls below VSHUT, the device is in SHUTDOWN mode and the CHG driver is no longer active and charging is not
allowed unless VDD rises above VPOR again.
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9.4 Device Functional Modes
9.4.1 Power Modes
9.4.1.1 Power On Reset (POR)
The device powers up when VDD ≥ VPOR. At POR, the following events occur:
•
•
•
A typical of 5-ms hold-off delay applies to both CHG and DSG drivers, keeping both drivers in the OFF state.
This is to provide time for the internal LDO voltage to ramp up.
The CTRC and CTRD deglitch occurs. During the deglitch time, the CHG and DSG driver remains off. Note
that the deglitch time masks out the 5-ms hold-off delay.
The device assumes an OV fault at POR; thus, the CHG driver is off for OV recovery time if all the cell
voltages are < (VOV – VHYS_OV). The OV recovery time starts after the 5-ms hold-off delay. If device reset
occurs when any cell voltage is above the OV hysteresis range, the CHG driver will remain off until an OV
recovery condition is met.
9.4.1.2 NORMAL Mode
This is the normal operation mode. All configured protections are active, no fault is detected, and both CHG and
DSG drivers are enabled. HIBERNATE mode is deactivated. While the device is in NORMAL mode, cell
balancing occurs if all the necessary conditions for balancing are valid. Refer to the Cell Balancing section for
details.
9.4.1.3 FAULT Mode
If any configured protection fault is detected, the device enters the FAULT mode. In this mode, the CHG and/or
DSG driver can be turned off depending on the fault. Refer to Fault Condition, State, and Recovery Methods for
details. When one of the FET drivers (either CHG or DSG) is turned off, while the other FET driver is still on, the
state comparator is activated for FET body diode protection.
9.4.1.4 HIBERNATE Mode
If the PRES pin is left floating, the device enters HIBERNATE mode operation. In this mode, all fault detection
and cell balancing is deactivated and the CHG and DSG drivers are turned off to reduce power consumption to
ultra-low levels. This mode of operation is recommended when the battery packs are in shipping or storage. The
device can be brought back to NORMAL mode by driving PRES high.
9.4.1.5 SHUTDOWN Mode
This is the lowest power consumption state of the device when VDD falls below VSHUT. In this mode, all fault
detections, CHG and DSG drivers are disabled. The device will wake up and enter NORMAL mode when VDD
rises above VPOR.
32
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VDD falls below shutdown voltage threshold
VDD falls below shutdown voltage threshold
Shutdown Mode
VDD falls below shutdown voltage threshold
Detect any of the following: OV, UV, OW,
OCD1/2, SCD, OCC, OTC/D, UTC/D, CTRC/D
Meet the corresponding fault
recovery condition
Fault Mode
- Protections ON
- One or both FET Drivers OFF
- Cell Balancing disabled
-CB FETs ON in OV (depending on conditions)
PRES is floating, part enters hibernate
mode after 4.5 seconds
Normal Mode
- Protections ON
- FET Drivers ON
- Cell Balancing allowed
PRES is pulled high, part exits
hibernate mode after 10ms
PRES is floating, part enters hibernate mode
after 4.5 seconds
Hibernate Mode
- Protections OFF
- Both FET Drivers OFF
- Cell Balancing disabled
- Minimal Circuit is ON
Figure 9-15. Various Operational Modes
9.4.1.6 Customer Fast Production Test Modes
The BQ77915 device supports the ability to greatly reduce production test time by cutting down on protection
fault delay times. To shorten fault times, place the BQ77915 device into Customer Test Mode (CTM). CTM is
triggered by raising VDD to VCTM voltage above the highest cell input pin (that is, VC5) for tCTM_ENTRY time.
The CTM is expected to be used in single-chip designs only. CTM is not supported for stacked designs. Once
the device is in CTM, all fault delays and non-current fault's recovery delay times reduce to a value of
tCTM_DELAY. The fault recovery time for overcurrent faults (OCD1, OCD2, OCC, and SCD) is reduced to
tCTM_OC_REC.
Verification of protection fault functionality can be accomplished in a reduced timeframe in CTM. Reducing the
VDD voltage to the same voltage applied to the highest-cell input pin for tCTM_ENTRY will exit CTM.
In CTM, with reduced time for all internal delays, qualification of all faults will be reduced to a single instance.
Thus, in this mode, fault-condition qualification is more susceptible to transients, so take care to have fault
conditions clearly and cleanly applied during test mode to avoid false triggering of fault conditions during CTM.
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10 Application and Implementation
Note
Information in the following applications sections is not device of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The BQ77915 device is a low power stackable battery pack protector with integrated low-side NMOS FET
drivers. The device protects and recovers without MCU control. The following section highlights several
recommended implementation when using the device.
10.1.1 Recommended System Implementation
10.1.1.1 CHG and DSG FET Rise and Fall Time
The CHG and DSG FET drivers are designed to have fast switching time. Customers should select a proper gate
resistor (RCHG and RDSG in the reference schematic) to set to the desired rise/fall time.
CHG
DSG
Select proper gate
resistor to adjust
the desired rise/fall
time
RDSG
RCHG
RGS_DSG
RGS_CHG
Q2 Q1
RSNS
PACK-
Figure 10-1. Select Proper Gate Resistor for FET Rise and Fall Time
The CHG FET fall time is generally slower because it is connected to the PACK– terminal. The CHG driver will
pull to VSS quickly when the driver is signaled to turn off. Once the gate of the CHG FET reaches ground or
Vgsth, the PACK– will start to fall below ground, the CHG signal will follow suit in order to turn off the CHG FET.
This portion of the fall time is strongly dependent on the FET characteristic, the number of FETs in parallel, and
the value of the gate-source resistor (RGS_CHG).
34
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Strong pull down by the CHG driver
when the device is initially signaled to
turn off CHG.
Once the CFET gate voltage reach PACK-, PACKvoltage starts to fall below ground. The gate
voltage is then relying on RGS_CHG to fall with
PACK- to keep the CHG FET off.
Figure 10-2. CHG FET Fall Time
10.1.1.2 Protecting CHG and LD
Because both CHG and LD are connected to PACK– terminal, these pins are specially designed to sustain an
absolute max of –30 V. The device can be used in a wide variety of applications, and it is possible to expose the
pins lower than –30-V absolute max rating.
To protect the pins, TI recommends to put a PMOS FET in series of the CHG pin, and a diode in series of the LD
pin, as shown below.
DSG
CHG
LD
Q3 and the LD pin diode are used to
keep CHG and LD away from any
voltages below VSS. Apply these
components when CHG and LD pins can
be exposed beyond the absolute -30V.
Q3
RDSG
RCHG
RLD
RGS_DSG
RGS_CHG
Q2
Q3 will allow RGS_CHG to keeps Q1 OFF,
since all voltages below this FET can
^(}oo}Á_ W =1MŸ)
RGS_DSG
Q2
This zener clamp may be
needed to prevent the Vgs of Q1
excesses absolute max rating.
Q1
16V
RSNS
PACK-
Figure 10-4. Protecting the CHG FET from High Voltage on PACK–
DSG
LD
CHG
Q3
RCHG
(1MŸ )
RDSG
RGS_DSG
Q2
Q1
RLD
RGS_CHG
(>=1MŸ)
16V
RSNS
PACKFigure 10-5. Optional Components Combining and Protections
10.1.1.4 Using Load Detect for UV Fault Recovery
A larger CHG FET gate-source resistor is required if load removal is enabled as a device of the UV recovery
criteria. When the load removal circuit is enabled, the device is internally connected to Vss. Because in a UV
fault, the CHG driver remains on, it creates a resistor divider path to the load detect circuit.
36
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PACK+
bq77915
Load Detect
block
VLDT
LD
pin
RLD_INT
FET driver
block
VFETON
LOAD
CHG
pin
RCHG
RLD
16V
CFET
RGS_CHG
PACK-
Figure 10-6. Load Detect Circuit During UV Fault
To ensure load removal is detected properly during a UV fault, TI recommends to use 3.3 MΩ for RGS_CHG
(instead of a typical 1 MΩ when load removal is NOT required for UV recovery). RCHG can stay in 1 MΩ as
recommended when using CHG FET protection components. The CHG FET rise time impact is minimized, as
described in Protecting the CHG FET. On a stacked configuration, connect the LD pin as shown in Figure 10-7 if
load removal is used for a UV fault recovery. If load detection is not required for a UV fault recovery, a larger
value of RGS_CHG can be used (that is, 10 MΩ), and the LD pin on the upper devices can be left floating.
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Ra is used to keep the LD pin pull
down when load detect circuit is
not activated
bq77915
LD
pin
Upper
device
Vss
pin
Ra
(1M)
Must have block
diode on the upper
device.
RLD
bq77094/5
LD
pin
Bottom
device
Vss
pin
RLD
Diode for the bottom
device is optional.
Use if the LD pin will
be exposed lower
than -30V.
PACK-
Figure 10-7. Simplified Circuit: LD Connection On Upper Device When Using for UV Fault Recovery
10.1.1.5 Temperature Protection
The device detects temperature by checking the voltage divided by RTS_PU and RTS, with the assumption of
using 10 KΩ RTS_PU and 103AT NTC for RTS. System designers should always check the thermistor resistance
characteristic and refer to the temperature protection threshold specification in the Electrical Characteristics table
to determine if a different pull up resistor should be used. If a different temperature trip pint is required, it is
possible to scale the threshold using this equation: Temperature Protection Threshold = RTS/(RTS + RTS_PU).
Example: Scale OTC trip points from 50°C to 55°C
The OTC protection can be set to 45°C or 50°C. When the device's OTC threshold is set to 50°C, it is referred to
configure the VOTC parameter to 29.38% of VTB (typical), with the assumption of RTS_PU = 10 KΩ and RTS =
103AT or similar NTC (which the NTC resistance at 50°C = 4.16KΩ). The VOTC specification is the resistor
divider ratio of RTS_PU and RTS.
The VOTC, VOTD, VUTC, and VUTD configuration options are fixed in the device. Hence, the actual temperature trip
point can only adjust by using a different B-value NTC and/or using a different RTS_PU.
In this example, the 103AT NTC resistance at 55°C is 3.536 KΩ. By changing the RTS_PU from 10 KΩ to 8.5 KΩ,
we can scale the actual OTC temperature trip point from 50°C to 55°C. Because the RTS_PU value is smaller, this
change affects all the other temperature trip points and scales OTD, UTC, and UTD with the largest impact to
OTD.
10.1.1.6 Adding RC Filters to the Sense Resistor
Current fault is sensed through voltage across sense resistor. Optional RC filters can be added to the sense
resistor to improve stability.
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SRP
0.1 µF
SRN
0.1 µF
100 Ÿ
0.1 µF
100 Ÿ
R SNS
PACK-
Figure 10-8. Optional Filters Improve Current Measurement
10.1.1.7 Using the State Comparator in an Application
The state comparator has built-in hysteresis and tSTATE qualification time. In a typical application, the sense
resistor is selected according to the application current, which is not usually close to the state comparator
threshold. Current variation slowly through the hysteresis range causes the FET body diode protection to toggle
on and off.
10.1.1.7.1 Examples
As an example, using a 5-Ah battery, with 1C-rate (5 A) charge and 2C-rate (10 A) discharge, the sense resistor
is mostly 3 mΩ or less.
The typical current to turn on the FET body diode protection is 625 mA using this example. The typical current to
turn off the FET body diode protection with the 3-mΩ sense resistor is 417 mA. Using this example, a > 1 A
current, either charge or discharge should provide a solid FET body diode protection detection. A momentary
drop through the hysteresis threshold will not cause the body diode protection to drop, but drops of 2 ms or more
will cause the FET to toggle.
Observe the device behavior during an OV event (and no other fault is detected). In an OV event, the CHG FET
is off and the DSG FET is on. If a discharge of >1 A occurs, the device would turn on the CHG FET to allow the
full discharge current to pass through. Once the overcharged cell is discharged to the OV recovery level, the OV
fault is recovered and CHG driver turns on (or remains on in this scenario) and the state comparator is turned
off.
If the discharge current drops below the V(STATE_D_HYS) threshold for longer than tSTATE when the device is still in
an OV fault, the CHG FET may toggle on and off until the overcharged cell voltage is reduced down to the OV
recovery level. When the OV fault recovered, the CHG FET will be turned on solidly and the state comparator is
off.
Without the FET body diode protection, if a discharge occurs during an OV fault state, the discharge current can
only pass through the CHG FET body diode until the OV fault is recovered. This increases the risk of damaging
the CHG FET if the MOSFET is not rated to sustain such current through its body diode. It also increases the
FET temperature as current is now carried through the body diode.
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10.2 Typical Application
RVDD
PACK+
CVDD
CVDD
RIN
CIN
RIN
CTRD
AVDD
CTRC
VC5
PRES
VC4
CBO
VC3
CCFG
VC2
VTB
VC1
CIN
bq77915
VC0
RIN
CIN
CS
RIN
CS
RIN
VDD
PRES
RTS_PU
RTS
ROCD
OCDP
VSS
CBI
SRP
LPWR
SRN
LD
DSG
CHG
RDSG
CIN
CIN
TS
RHIB
RCHG
RCHG2
CS
RLD
CIN
RIN
RS
RS
RGS
RGS
RSNS
PACK±
Figure 10-9. The BQ77915 Device with Five Cells
10.2.1 Design Requirements
For this design example, use the parameters shown in Table 10-1.
Table 10-1. Design Parameters
PARAMETER
RIN
DESCRIPTION
VALUES
Cell voltage sensing (VCx pins) filter resistor. System designers should change this
parameter to adjust the cell balance current.
1 kΩ ±5%
CIN
Cell voltage sensing (VCx pins) filter capacitor
RVDD
Supply voltage filter resistor
CVDD
Supply voltage filter capacitor
1 µF ±20%
RS
Current sensing input filter resistor
100 Ω ±5%
CS
Current sensing input filter capacitor
RTS
NTC thermistor
RTS_PU
Thermistor pullup resistor to VTB pin, assuming using 103AT NTC or NTC with similar
resistance-temperature characteristic
RGS_CHG
CHG FET gate-source Load removal is enabled for UV recovery.
resistor
Load removal is disabled for UV recovery.
RGS_DSG
DSG FET gate-source resistor
40
0.1 µF ±10%
1 kΩ ±5%
0.1 µF ±10%
103AT, 10 kΩ ±3%
10 kΩ ±1%
3.3 MΩ ±5%
1 MΩ ±5%
1 MΩ ±5%
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Table 10-1. Design Parameters (continued)
PARAMETER
RCHG
DESCRIPTION
CHG gate resistor
VALUES
System designers should adjust this parameter to meet the
desired FET rise/fall time.
1 kΩ ±5%
If additional components are used to protect the CHG FET
and/or to enable load removal detection for UV recovery
1 MΩ ±5%
RDSG
DSG gate resistor. System designers should adjust this parameter to meet the desired
FET rise/fall time.
4.5 kΩ ±5%
RCTRC and RCTRD
CTRC and CTRD current limit resistor
10 MΩ ±5%
RHIB
PRES pullup resistor for NORMAL mode
10 kΩ ±5%
ROCD
OCDP discharge overcurrent protection delay pulldown resistor. System designers
should change this parameter for the desired delay.
100 kΩ ±1%
RCB
CBI pulldown resistor between stacked devices to enable balancing
RLD
LD resistor for load removal detection
RSNS
Current sense resistor for current protection. System designers should change this
parameter according to the application current protection requirement.
10 kΩ ±5%
450 KΩ ±5%
1 mΩ ±1%
10.2.2 Detailed Design Procedure
The following is the detailed design procedure:
1. Select the number of devices needed for the number of cells in the system, and for the configuration of the
protection thresholds.
2. Select the proper sense resistor value based on the application current. The sense resistor should enable
detection of the highest current protection, as well as the short circuit current.
3. Set the temperature protection using a 103AT NTC (or an NTC with similar specifications). If using a different
type of NTC, a different RTS_PU may be used for the application. Refer to the actual temperature detection
threshold voltage to determine the RTS_PU value.
4. Connect the CCFG pin correctly for each device based on the number of cells in series.
5. Enable cell balancing if desired.
6. Select the configuration parameters and input filter resistors to set the current.
7. Review the Recommended System Implementation to determine if optional components should be added to
the schematic.
10.2.2.1 Design Example
This example shows how to design protection for an 18-V Li-ion battery pack using 4.2-V cells with the following
requirements:
• The system will operate from 15 V to 21.5 V.
• The battery must allow 4-A continuous current.
• The battery must protect with 8-A discharge current > 500 ms.
• The battery must have short circuit protection in < 2 ms.
• The system is for operation in an office environment: 10°C to 30°C.
• The cell normal charge voltage is 4.2 ±0.05 V to 0.05 C.
• The cell cutoff voltage is 2.75 V.
• The charge temperature is 0°C to 45°C.
• A cell configuration is selected to provide 5 Ah over the system range of operation.
• The cell assembly is capable of > 30-A short circuit current.
• Cell balancing is desired with a current of 10% of termination current.
• Low current drain is desired when the pack is removed from the system.
• Load removal for fault recovery is required. Recovery by connecting the charger is acceptable.
To start the design:
1. Start the schematic:
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•
An 18-V pack using 3.6-V nominal cells requires a 5-series configuration. A single BQ77915 device is
needed.
• Follow the 5-series reference schematic in this document. Follow the recommended design parameters in
Design Requirements.
• Because a single device is needed, CTRC and CTRD are connected directly to GND.
• The power FET used in this type of application usually has an absolute maximum of 20-V Vgs. For an 18V pack design, transient voltage during an OCD may exceed 20 V, so the diode across the 1-MΩ RCHG2 is
used. RCHG helps to slow the charge FET from turning on.
• Because a charger connection for UV recovery is acceptable, the condition in Section 10.1.1.4 is not a
concern. A 1-MΩ RGS_CHG can be used for the schematic.
• The optional sense input filter is selected for the circuit.
• Because low current storage is desired, the PRES pin is brought out of the pack for control by the system.
The standard recommended RHIB value is used.
• Because cell balancing is required:
– Connect the CBI pin to VSS.
– Determine the resistance for the RIN filter resistors. Since the charge taper current will be 0.05 × 5 A or
250 mA, 10% is 25 mA. With a 4.1-V cell, 25 mA would require 164-Ω resistance. This resistance
includes the internal RBAL resistance and two RIN resistors. 75-Ω resistors are selected for RIN.
2. Decide the value of the sense resistor, RSNS.
• When selecting the value of RSNS, ensure the voltage drop across SRP and SRN is within the available
current protection threshold range.
• In this example, only one protection threshold is specified. The minimum available OCD threshold is the –
10-mV OCD1 threshold, but this would result in an odd value for RSNS and the tolerance of the threshold is
30%. Using the –60-mV threshold of the BQ77915 configuration, a 10-mΩ sense resistor would give a 6-A
nominal OCD threshold. With the 20% tolerance, 4 A can pass without OCD and 8 A will always cross the
threshold.
• A 30-A SCD with a 10-mΩ sense resistor would be a nominal 300-mV threshold. Tolerance must be
considered and the protection threshold can be lower than the battery capability. The 120-mV threshold of
the BQ77915 configuration with a 10-mΩ RSNS will give a 12-A nominal short circuit threshold.
• Select RSNS = 10 mΩ for this example.
3. Determine the remaining BQ77915 protection configuration:
• Charging the cells at a lower than maximum voltage allows a margin on setting the OV threshold. The
system could allow a 4.15-V OV, while the cells might allow a 4.3-V OV. Since the charge voltage will be
4.1 V/cell, this is the desired VFC point of the BQ77915 device. The 4200-mV OV threshold and 100 mV
VOV – VFC of the BQ77915 device are suitable.
• OV hysteresis and delay values are not specified requirements. A 1-s delay will be selected. Some
hysteresis is desired to prevent cycling if the battery were to reach OV. 200 mV is acceptable.
• The system will stop operation at a nominal 3 V per cell, while the cells could operate to 2.75 V. Some
margin below the 3 V should be allowed, because cell voltages may vary at low states of charge. A 2750mV threshold option is available, but the existing BQ77915 configuration has the 2900 threshold.
• UV hysteresis and delay are not specified requirements. A 1-s delay is selected. Generally, a larger UV
hysteresis will avoid system cycling from automatic recovery; however, in this design load, removal is
required and charger connection is expected for UV recovery. The value could vary, but 400 mV is
selected.
• Open-wire protection is selected at the 100-nA level.
• tOCD1 or tOCD2 could be programmed to 350 ms to protect in less than 500 ms, or the default BQ77915 180
ms is used. However, the 350 ms can be selected with ROCD. Use 604 kΩ 1% for ROCD.
• The 2-ms SCD response time allows either SCD delay selection.
• Overcurrent charge protection is not specified in the requirements. The BQ77915 60-mV setting will allow
a 1C charge.
• For temperature protections, the 0°C to 45°C charge temperature thresholds match the range for the cells.
Use the lower range for discharge.
42
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•
The VCBTH – VCBTHL determines the voltage spread during constant current charge when balancing will
be allowed. 100 mV allows some spread without balancing.
• See the summary in Table 10-2.
4. Review the available release in the Device Comparison Table to determine if it is a suitable option. In this
example, the BQ7791500 configuration is suitable. If it is not suitable for your design, contact a TI
representative for further assistance and for information on BQ77915 PRODUCT PREVIEW devices.
Table 10-2. Design Example Configuration
Protection
Threshold
Hysteresis
Delay
Recovery Method
OV
4.2 V
200 mV
1 s (default setting)
Hysteresis
UV
2.9 V
400 mV
1 s (default setting)
Hysteresis + load removal
OW
100 nA
(default setting)
—
—
(VCx – VCx–1) > 600 mV (typical)
OCD1
60 mV
—
180 ms
Load removal only
OCD2
60 mV
—
180 ms (350 ms using
ROCD)
Load removal only
SCD
120 mV
—
960 µs
Load removal only
OCC
60 mV
-—
Fixed at 10 ms
Load detection only
OTC
45°C
10°C
4.5 s
Hysteresis
OTD
65°C
10°C
4.5 s
Hysteresis
UTC
0°C
10°C
4.5 s
Hysteresis
UTD
–10°C
10°C
4.5 s
Hysteresis
VOV – VFC
100 mV
—
—
—
VCBTH – VCBTL
100 mV
—
—
—
VSTART
3.8 V
—
—
—
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10.2.3 Application Curves
44
Figure 10-10. OV Fault Protection
Figure 10-11. OV Fault Recovery
Figure 10-12. OV and OCD2 Faults Protection
Figure 10-13. Detect OTC Fault While in Discharge
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Figure 10-14. OW Fault Protection—Open Cell1 To
PCB Connection
Figure 10-15. OW Fault Protection, Low Voltage—
Open Cell1 Connection
11 Power Supply Recommendations
The recommended cell voltage range is up to 5 V. If three cells in series are connecting to the BQ77915 device,
the unused VCx pins should be shorted to the highest unused VCx pin. The recommended VDD range is from 3
V to 25 V. This implies the device is still operational when cell voltage is depleted down to the ~1.5-V range.
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12 Layout
12.1 Layout Guidelines
1. Match SRN and SRP traces.
2. RIN filters, VDD, AVDD filters, and the CVDD capacitor should be placed close to the device pins.
3. Separate the device ground plane (low current ground) from the high current path. Filter capacitors should
reference to the low current ground path or device Vss.
4. In a stack configuration, the RCTRD and RCTRC should be placed closer to the lower device CTRD and CTRC
pins.
5. RGS should be placed near the FETs.
6. In a stacked configuration, it must be ensured in the PCB layout that the trace from the VC5 pin to a cell and
the trace from the VC0 pin of the next upper device to the immediately higher cell are kept separate.
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12.2 Layout Example
High current Path
Place filters
close to IC pins
RC
Filters
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
VC0
VSS
SRP
SRN
DSG
Connect the device
ground at the lower
oo[• oo- on each
cell group
Place filters
VDD
close to IC pins
AVDD
VC5
VC4
VC3
RC
VC2
Filters
VC1
VC0
VSS
SRP
SRN
Connect the bottom DSG
CTRD
CTRC
PRES
CBO
CCFG
VTB
TS
OCDP
CBI
LPWR
LD
CHG
CTRD
CTRC
PRES
CBO
CCFG
VTB
TS
OCDP
CBI
LPWR
LD
CHG
device ground at BAT-.
Use BAT- as the mutual
point to connect high
and low current path
PACK+
Low current, local
ground for each device
Place resistors
close to the input
pins
Low current, local
device ground.
Separate from high
power path
PACK-
Figure 12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• BQ77915 3–5S Low-Power Protector Evaluation Module User's Guide (SLUUBU2)
• BQ77915 Functional Safety FIT Rate, FMD, and PinFMA Application Report (SLUAA46 )
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ7791500PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ77915
BQ7791500PWT
ACTIVE
TSSOP
PW
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ77915
BQ7791501PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791501
BQ7791501PWT
ACTIVE
TSSOP
PW
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791501
BQ7791502PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791502
BQ7791502PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791502
BQ7791504PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791504
BQ7791504PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791504
BQ7791506PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791506
BQ7791506PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791506
BQ7791508PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791508
BQ7791508PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7791508
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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