BQ78PL114RGZR

bq78PL114 www.ti.com................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009 PowerLAN™ Master Gateway Battery Management Controller With PowerPump™ Cell Balancing Technology FEATURES 1 • bq78PL114 Designed for Managing 3- to 8-Series-Cell Battery Systems • bq78PL114S12 Firmware Upgrade Supports 3to 12-Series-Cell Battery Systems – Adds Support for LCD and Electronic Paper Displays or EPDs – Configurable for 11-A, 26-A, or 110-A Operating Currents • Systems With More Than Four Series Cells Require External bq76PL102 Dual-Cell Monitors • SmartSafety Features: – Prevention: Optimal Cell Management – Diagnosis: Improved Sensing of Cell Problems – Fail Safe: Detection of Event Precursors • Rate-of-Change Detection of All Important Cell Characteristics: – Voltage – Impedance – Cell Temperature • PowerPump Technology Transfers Charge Efficiently From Cell to Cell During All Operating Conditions, Resulting in Longer Run Time and Cell Life – bq78PL114S12 Adds User-Configurable PowerPump Cell-Balancing Modes • High-Resolution 18-Bit Integrating Delta-Sigma Coulomb Counter for Precise Charge-Flow Measurements and Gas Gauging • Multiple Independent Δ-Σ ADCs: One-per-Cell Voltage, Plus Separate Temperature, Current, and Safety • Simultaneous, Synchronous Measurement of Pack Current and Individual Cell Voltages • Very Low Power Consumption – bq78PL114: < 250 µA Active, < 150 µA Standby, < 40 µA Ship, and < 1 µA Undervoltage Shutdown 23 • • • • • – bq78PL114S12: < 300 µA Active, < 185 µA Standby, < 85 µA Ship, and < 1 µA Undervoltage Shutdown Accurate, Advanced Temperature Monitoring of Cells and MOSFETs With up to 12 Sensors Fail-Safe Operation of Pack Protection Circuits: Up to Three Power MOSFETs and One Secondary Safety Output (Fuse) Fully Programmable Voltage, Current, Balance, and Temperature-Protection Features External Inputs for Auxiliary MOSFET Control Smart Battery System 1.1 Compliant via SMBus APPLICATIONS • • • Portable Medical Instruments and Test Equipment Mobility Devices (E-Bike) Uninterruptible Power Supplies and Hand-Held Tools DESCRIPTION The bq78PL114 master gateway battery controller is part of a complete Li-Ion control, monitoring, and safety solution designed for large series cell strings. The bq78PL114 and bq78PL114S12 along with bq76PL102 PowerLAN™ dual-cell monitors provide complete battery-system control, communications, and safety functions for a structure of three up to twelve series cells. This PowerLAN system provides simultaneous, synchronized voltage and current measurements using one A/D per-cell technology. This eliminates system-induced noise from measurements and allows the precise, continuous, real-time calculation of cell impedance under all operating conditions, even during widely fluctuating load conditions. PowerPump technology transfers charge between cells to balance their voltage and capacity. Balancing is possible during all battery modes: charge, discharge, and rest. Highly efficient charge-transfer circuitry nearly eliminates energy loss while providing true real-time balance between cells, resulting in longer run-time and improved cycle life. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerLAN, PowerPump, bqWizard are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated bq78PL114 SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Temperature is sensed by up to 12 external sensors and one on-chip sensor. This permits accurate temperature monitoring of each cell individually. Firmware is then able to compensate for the temperature-induced effects on capacity, impedance, and OCV on a cell-by-cell basis, resulting in superior charge/ discharge and balancing control. External MOSFET control inputs provide user- definable direct hardware control over MOSFET states. Smart control prevents excessive current through MOSFET body diodes. Auxiliary inputs can be used for enhanced safety and control in large multicell arrays. The bq78PL114 is completely user-configurable, with parametric tables in flash memory to suit a variety of cell chemistries, operating conditions, safety controls, and data reporting needs. It is easily configured using the supplied bqWizard™ graphical user interface (GUI). The device is fully programmed and requires no algorithm or firmware development. The bq78PL114 can be upgraded to the bq78PL114S12 by downloading the bq78PL114S12 firmware. The firmware can be downloaded using the bqWizard application or during manufacturing. Upgrading to the bq78Pl114S12 changes the functionality of the LED1–LED5, LEDEN, and N/C pin #29. The bq78PL114S12 pin functions of LED1/SEG1–LED5/SEG5, PSH/BP/TP, and FIELD support LED, LCD, and electronic paper displays (EPDs). The user can configure the bq78PL114S12 for the desired display type. In this document all descriptions for the bq78PL114 apply to the bq78PL114S12 except where different bq78PL114S12 functionality is specifically described. 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 bq78PL114 www.ti.com................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009 V1 P1N P1S XT1 FLASH CELL 4 DSG EFCID Balance Temp CELL 3 EFCIC Voltage SPROT RISC CPU Voltage Balance Temp Second-Level Safety CSBAT Coulomb Counter CCBAT CSPACK Current A/D Voltage Balance Temp PowerLAN Communication Link Reset Logic RSTN VLDO1 CHG First-Level Safety and FET Control SRAM V2 P2N P2S XT2 Balance Temp PRE CELL 2 V3 P3N P3S XT3 Voltage CELL 1 P-LAN V4 P4N P4S XT4 2.5 V LDO Core / CPU Measure GPIO Internal Oscillator Watchdog SMBus CCPACK 6 LED1–5, LEDEN SMBCLK SMBDAT Internal Temperature I/O Safety B0320-02 Figure 1. bq78PL114 Internal Block Diagram Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 3 bq78PL114 SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com P-LAN V1 P1N P1S XT1 FLASH CELL 4 DSG EFCID Balance Temp CELL 3 EFCIC Voltage SPROT RISC CPU Voltage Balance Temp Second-Level Safety CSBAT Coulomb Counter CCBAT CSPACK Current A/D Voltage Balance Temp PowerLAN Communication Link Reset Logic RSTN VLDO1 CHG First-Level Safety and FET Control SRAM V2 P2N P2S XT2 Balance Temp PRE CELL 2 V3 P3N P3S XT3 Voltage CELL 1 V4 P4N P4S XT4 Core / CPU Measure Internal Oscillator Watchdog 2.5 V LDO GPIO SMBus CCPACK 7 LED1–5/SEG1–5, PSH/BP/TP, FIELD SMBCLK SMBDAT Internal Temperature I/O Safety B0320-03 Figure 2. bq78PL114S12 Internal Block Diagram 4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 bq78PL114 www.ti.com................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009 – Pack Positive SMBus Pack Negative + Pack Protection Circuits and Fuse PowerLAN Master Gateway Battery Controller bq78PL114 PowerLAN Communication Link RSENSE Example 8-cell configuration shown bq76PL102 Cell Monitor With PowerPump Balancing bq76PL102 Cell Monitor With PowerPump Balancing B0332-01 Figure 3. Example bq78PL114 PowerLAN Multicell System Implementation (8 Cells) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 5 bq78PL114 B0332-02 Pack Positive SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com Pack Negative V2 T2 V1 T1 V2 T2 V1 T1 9 V2 T2 8 V1 T1 7 V2 T2 6 V1 T1 5 V4 XT4 10 4 V3 XT3 11 3 V2 XT2 12 2 V1 XT1 SMBus PowerLAN Master Gateway Battery Controller bq78PL114S12 PowerLAN Communication Link bq76PL102 Dual-Cell Monitor Bq76PL102 Dual-Cell Monitor Example 12-cell configuration shown bq76PL102 Dual-Cell Monitor Bq76PL102 Dual-Cell Monitor Pack Protection Circuits and Fuse 1 RSENSE Figure 4. Example bq78PL114S12 System Implementation (12 Cells) 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 bq78PL114 www.ti.com................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009 ORDERING INFORMATION Product Cell Configuration (1) Package Package Designator Temperature Range bq78PL114 3 to 8 series cells QFN-48, 7-mm × 7-mm RGZ –40°C to 85°C bq78PL114S 12 3 to 12 series cells N/A N/A N/A (1) Ordering Number Quantity, Transport Media bq78PL114RGZT 250, tape and reel bq78PL114RGZR 2500, tape and reel N/A Firmware download and upgrade For configurations consisting of more than four series cells, additional bq76PL102 parts must be used. AVAILABLE OPTIONS V1 XT1 XT2 V2 VLDO2 V3 XT3 XT4 V4 SMBDAT SMBCLK 46 45 44 43 42 41 40 39 38 37 DSG 47 1 VSS CHG 48 bq78PL114 RGZ Package (Top View) 36 LED5 2 35 LED4 PRE 3 34 LED3 EFCIC 4 33 LED2 EFCID 5 32 LED1 CCBAT 6 31 LEDEN Thermal Pad 24 RSTN P-LAN 25 23 12 P4N OSCO 22 NC P4S 26 21 11 P3N OSCI 20 NC P3S 27 19 10 SDI3 CSPACK 18 NC SDO2 28 17 9 P2N CSBAT 16 NC P2S 29 15 8 P1N VLDO1 14 SPROT SDI1 30 13 7 SDO0 CCPACK P0023-16 Figure 5. bq78PL114 Pinout bq78PL114 TERMINAL FUNCTIONS NAME NO. TYPE (1) DESCRIPTION CCBAT 6 IA Coulomb counter input (sense resistor), connect to battery negative CCPACK 7 IA Coulomb counter input (sense resistor), connect to pack negative CHG 1 O Charge MOSFET control (active-high, low opens MOSFET) CSBAT 9 IA Current sense input (safety), connect to battery negative CSPACK 10 IA Current sense input (safety), connect to pack negative DSG 2 O Discharge MOSFET control (active-high, low opens MOSFET) EFCIC 4 I External charge MOSFET control input (1) I – input, IA – analog input, O – output, OA – analog output, P – power Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 7 bq78PL114 SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com bq78PL114 TERMINAL FUNCTIONS (continued) NAME NO. TYPE (1) DESCRIPTION EFCID 5 I External discharge MOSFET control input LED1 32 O LED1 – open-drain, active-low LED2 33 O LED2 – open-drain, active-low LED3 34 O LED3 – open-drain, active-low LED4 35 O LED4 – open-drain, active-low LED5 36 O LED5 – open-drain, active-low LEDEN 31 IO LEDEN – common-anode drive (active-low) and pushbutton input NC 26 IO Connect 1-MΩ resistor to VSS NC 27 I Connect 1-MΩ resistor to VSS NC 28, 29 O No connect OSCI 11 I External oscillator input (no connect, internal oscillator used) OSCO 12 O External oscillator output (no connect, internal oscillator used) P1N 15 O Charge-balance gate drive, cell 1 north P2S 16 O Charge-balance gate drive, cell 2 south P2N 17 O Charge-balance gate drive, cell 2 north P3N 21 O Charge-balance gate drive, cell 3 north P3S 20 O Charge-balance gate drive, cell 3 south P4N 23 O Charge-balance gate drive, cell 4 north P4S 22 O Charge-balance gate drive, cell 4 south P-LAN 24 IO PowerLAN I/O to external bq76PL102 nodes PRE 3 O Precharge MOSFET control (active-high) RSTN 25 I Device reset, active-low SDI1 14 I Connect to SDO0 via a capacitor SDI3 19 I Internal PowerLAN connection – connect to SDO2 through a 0.01-µF capacitor SDO0 13 O Requires 100-kΩ pullup resistor to VLDO1 SDO2 18 O Internal PowerLAN connection – connect to SDI3 through a 0.01-µF capacitor SMBCLK 37 IO SMBus clock signal SMBDAT 38 IO SMBus data signal SPROT 30 O Secondary protection output, active-high (FUSE) V1 47 IA Cell-1 positive input V2 44 IA Cell-2 positive input V3 42 IA Cell-3 positive input V4 39 IA Cell-4 positive input VLDO1 8 P Internal LDO-1 output, bypass with 10-µF capacitor to VSS VLDO2 43 P Internal LDO-2 output, bypass with 10-µF capacitor to V2 VSS 48 IA Cell-1 negative input XT1 46 IA External temperature-sensor-1 input XT2 45 IA External temperature-sensor-2 input XT3 41 IA External temperature-sensor-3 input XT4 40 IA External temperature-sensor-4 input – – P Thermal pad. Connect to VSS 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 bq78PL114 www.ti.com................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009 V1 XT1 XT2 V2 VLDO2 V3 XT3 XT4 V4 SMBDAT SMBCLK 46 45 44 43 42 41 40 39 38 37 DSG 47 1 VSS CHG 48 bq78PL114S12 RGZ Package (Top View) 36 LED5/SEG5 2 35 LED4/SEG4 PRE 3 34 LED3/SEG3 EFCIC 4 33 LED2/SEG2 EFCID 5 32 LED1/SEG1 CCBAT 6 31 PSH/BP/TP Thermal Pad 24 RSTN P-LAN 25 23 12 P4N OSCO 22 NC P4S 26 21 11 P3N OSCI 20 NC P3S 27 19 10 SDI3 CSPACK 18 NC SDO2 28 17 9 P2N CSBAT 16 FIELD P2S 29 15 8 P1N VLDO1 14 SPROT SDI1 30 13 7 SDO0 CCPACK P0023-20 Figure 6. bq78PL114S12 Pinout bq78PL114S12 TERMINAL FUNCTIONS NAME NO. TYPE (1) DESCRIPTION CCBAT 6 IA Coulomb counter input (sense resistor), connect to battery negative CCPACK 7 IA Coulomb counter input (sense resistor), connect to pack negative CHG 1 O Charge MOSFET control (active-high, low opens MOSFET) CSBAT 9 IA Current sense input (safety), connect to battery negative CSPACK 10 IA Current sense input (safety), connect to pack negative DSG 2 O Discharge MOSFET control (active-high, low opens MOSFET) EFCIC 4 I External charge MOSFET control input EFCID 5 I External discharge MOSFET control input FIELD 29 O EPD field segment LED1/SEG1 32 O LED1 – open-drain, active-low, LCD and EPD segment 1 LED2/SEG2 33 O LED2 – open-drain, active-low, LCD and EPD segment 2 LED3/SEG3 34 O LED3 – open-drain, active-low, LCD and EPD segment 3 LED4/SEG4 35 O LED4 – open-drain, active-low, LCD and EPD segment 4 LED5/SEG5 36 O LED5 – open-drain, active-low, LCD and EPD segment 5 N/C 26, 27 IO Connect 1-MΩ resistor to VSS N/C 28 O No connect OSCI 11 I External oscillator input (no connect, internal oscillator used) (1) I – input, IA – analog input, O – output, OA – analog output, P – power Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 9 bq78PL114 SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com bq78PL114S12 TERMINAL FUNCTIONS (continued) NO. TYPE (1) OSCO 12 O External oscillator output (no connect, internal oscillator used) P1N 15 O Charge-balance gate drive, cell 1 north P2N 17 O Charge-balance gate drive, cell 2 north P2S 16 O Charge-balance gate drive, cell 2 south P3N 21 O Charge-balance gate drive, cell 3 north P3S 20 O Charge-balance gate drive, cell 3 south P4N 23 O Charge-balance gate drive, cell 4 north P4S 22 O Charge-balance gate drive, cell 4 south P-LAN 24 IO PowerLAN I/O to external bq76PL102 nodes PRE 3 O Precharge MOSFET control (active-high) PSH/BP/TP 31 IO Pushbutton detect for LED display, LCD backplane, EPD top plane and charge pump RSTN 25 I Device reset, active-low SDI1 14 I Connect to SDO0 via a capacitor SDI3 19 I Internal PowerLAN connection – connect to SDO2 through a 0.01-µF capacitor SDO0 13 O Requires 100-kΩ pullup resistor to VLDO1 SDO2 18 O Internal PowerLAN connection – connect to SDI3 through a 0.01-µF capacitor SMBCLK 37 IO SMBus clock signal SMBDAT 38 IO SMBus data signal SPROT 30 O Secondary protection output, active-high (FUSE) V1 47 IA Cell-1 positive input V2 44 IA Cell-2 positive input V3 42 IA Cell-3 positive input V4 39 IA Cell-4 positive input VLDO1 8 P Internal LDO-1 output, bypass with 10-µF capacitor to VSS VLDO2 43 P Internal LDO-2 output, bypass with 10-µF capacitor to V2 VSS 48 IA Cell-1 negative input XT1 46 IA External temperature-sensor-1 input XT2 45 IA External temperature-sensor-2 input XT3 41 IA External temperature-sensor-3 input XT4 40 IA External temperature-sensor-4 input – – P Thermal pad. Connect to VSS NAME 10 DESCRIPTION Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): bq78PL114 bq78PL114 www.ti.com................................................................................................................................................ SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) RANGE UNITS TA Operating free-air temperature (ambient) –40 to 85 °C Tstg Storage temperature –65 to 150 °C V4–V3 Maximum cell voltage –0.5 to 5.0 V V3–V2 Maximum cell voltage –0.5 to 5.0 V V2–V1 Maximum cell voltage –0.5 to 5.0 V V1–VSS Maximum cell voltage –0.5 to 5.0 V Voltage on LEDEN, SPROT, CCBAT, CCPACK, CSBAT, CSPACK, XT1, XT2, OSCI, OSCO, P-LAN Maximum voltage on any I/O pin with respect to VSS –0.5 to (VLDO1 + 0.5) V Voltage on PSH/BP/TP (bq78PL114S12) Maximum voltage range with respect to VSS –0.5 to (VLDO1 + 0.5) V Voltage on LED1–LED5 Maximum voltage on I/O pin with respect to VSS –0.5 to 5.5 V Voltage on LED1/SEG1–LED5/SEG5 (bq78PL114S12) Maximum voltage on I/O pin –0.5 to 5.5 V Voltage on XT3, XT4 Maximum voltage range with respect to V2 (V2 – 0.5) to (VLDO2 + 0.5) V EFCIC, EFCID Maximum voltage range with respect to VSS –0.5 to 5.5 V Voltage on SMBCLK, SMBDAT Maximum voltage range with respect to VSS –0.5 to 6 V Voltage on PRE, CHG, DSG Maximum voltage range with respect to VSS –0.5 to (VLDO1 + 0.5) V Current through PRE, CHG, DSG, LED1–LED5, P-LAN Maximum current source/sink 20 mA Current through LED1/SEG1–LED5/SEG5, (bq78PL114S12, LED mode) Maximum current source/sink 20 mA VLDO1 maximum current Maximum current draw from VLDO 20 mA ESD tolerance JEDEC, JESD22-A114 human-body model, R = 1500 Ω, C = 100 pF 2 kV Lead temperature, soldering Total time < 3 seconds 300 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VSUP Supply voltage—V1, V2, V3, V4 2.3 VStartup Minimum startup voltage—V1, V2 2.9 VIN Input cell voltage range—V(n+1) – V(n), n = 1, 2, 3, 4 CVLDO1 VLDO 1 capacitor—VLDO1 2.2 CVLDO2 VLDO 2 capacitor—VLDO2 2.2 CVn Cell-voltage capacitor—Vn NOM MAX 4.5 Product Folder Link(s): bq78PL114 V V 0 4.5 V 10 47 µF 10 47 µF µF 1 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated UNIT 11 bq78PL114 SLUS850B – SEPTEMBER 2008 – REVISED APRIL 2009................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C (unless otherwise noted) DC Characteristics PARAMETER VCELL (1) IDD ISTBY ISHIP IECUV TEST CONDITIONS TYP Operating range Cells balanced Operating-mode current Measure / report state, bq78PLL114 250 Measure / report state, bq78PLL114S12 300 SMBCLK = SMBDAT = L, bq78PLL114 100 SMBCLK = SMBDAT = L, bq78PLL114S12 185 Standby-mode current Ship-mode current Extreme cell under voltage shutdown current MAX 2.3 4.5 bq78PLL114 30 bq78PLL114S12 85 SPROT, LEDEN, IOL < 4 mA PSH/BP/TP(bq78PL114S12), FIELD(bq78PL114S12) VOH (2) SPROT, LEDEN, IOH < –4 mA PSH/BP/TP(bq78PL114S12), FIELD(bq78PL114S12) VIL SPROT, LEDEN, PSH/BP/TP(bq78PL114S12), FIELD(bq78PL114S12) VIH SPROT, LEDEN, PSH/BP/TP(bq78PL114S12), FIELD(bq78PL114S12) UNIT V µA µA µA All cells < 2.7 V and any cell < ECUV set point VOL (1) (2) MIN 0 1 µA 0.5 V VLDO1 – 0.1 V 0.25 VLDO1 0.75 VLDO1 V V Device should be configured to enter shutdown state when cell voltages are below 2.5 V. Does not apply to SMBus pins. Voltage-Measurement Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Measurement range 12 TYP 2.5 Resolution 0°C to 60°C Submit Documentation Feedback MAX 4.5