BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
Programmable Gamma-Voltage Generator
with Integrated Two-Bank Memory and External EEPROM
FEATURES
DESCRIPTION
•
•
•
•
The BUF12840 offers 12 programmable gamma
channels
with
external
electrically
erasable
programmable read-only memory (EEPROM) read
capabilities.
1
2
•
•
•
•
•
10-BIT RESOLUTION
12-CHANNEL P-GAMMA
READS FROM EXTERNAL EEPROM
TWO INDEPENDENT PIN-SELECTABLE
MEMORY BANKS
RAIL-TO-RAIL OUTPUT:
– 300mV Min Swing-to-Rail (10mA)
– 200mV Min Swing-to-Rail (5mA)
LOW SUPPLY CURRENT
SUPPLY VOLTAGE: 9V to 20V
DIGITAL SUPPLY: 2V to 5.5V
TWO-WIRE INTERFACE: Supports 400kHz and
3.4MHz Operation
APPLICATIONS
•
TFT-LCD REFERENCE DRIVERS
VSD
BKSEL
The BUF12840 is manufactured using Texas
Instruments’ proprietary, state-of-the-art, high-voltage
CMOS process. This process offers very dense logic
and high supply voltage operation of up to 20V. The
BUF12840 is offered in a QFN-24 package, and is
specified from –40°C to +95°C.
FEATURES
VS
OUT0
¼
¼
¼
¼
¼
OUT1
DAC Register Bank1
DAC Register Bank0
All gamma channels offer a rail-to-rail output that
typically swings to within 200mV of either supply rail
with a 5mA load. All channels are programmed using
a two-wire interface that supports standard operations
up to 400kHz and high-speed data transfers up to
3.4MHz.
RELATED PRODUCTS
BUF12840
1
The BUF12840 has two separate memory banks that
allow simultaneous storage of two different gamma
curves to facilitate switching between gamma curves.
PRODUCT
22-Channel Gamma Correction Buffer
BUF22821
12-Channel Gamma Correction Buffer
BUF12800
20-Channel Programmable Buffer, 10-Bit, VCOM
BUF20800
16-/20-Channel Programmable Buffer with Memory
BUF20820
Programmable VCOM Driver
BUF01900
18V Supply, Traditional Gamma Buffers
BUF11704
22V Supply, Traditional Gamma Buffers
BUF11705
OUT9
OUT10
OUT11
SDA
SCL
Control (IF and Memory)
A0
LD
External
Memory
Control
EA0 EA1 EN
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
PACKAGE MARKING
TRANSPORT MEDIA, QUANTITY
BUF12840
VQFN-24
RGE
BUF12840
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
PARAMETER
BUF12840
UNIT
Supply Voltage
VS
+22
V
Supply Voltage
VSD
+6
V
–0.5 to +6
V
±10
mA
Supply Input Terminals, SCL, SDA, A0, BKSEL, EA0, EA1, EN, LD: Voltage
Supply Input Terminals, SCL, SDA, A0, BKSEL, EA0, EA1, EN, LD: Current
Output Short-Circuit (2)
Continuous
Operating Temperature
–40 to +95
°C
–65 to +150
°C
+125
°C
Storage Temperature
Junction Temperature
(1)
(2)
TJ
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Short-circuit to ground. Exposed thermal die is soldered to the PCB using thermal vias. Refer to Texas Instruments application report
QFN/SON PCB Attachment (SLUS271).
THERMAL INFORMATION
BUF12840
THERMAL METRIC (1)
RGE
UNITS
24 PINS
θJA
Junction-to-ambient thermal resistance
35.6
θJC(top)
Junction-to-case(top) thermal resistance
40.5
θJB
Junction-to-board thermal resistance
10.0
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
9.9
θJC(bottom)
Junction-to-case(bottom) thermal resistance
3.0
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +95°C.
At TA = +25°C, VS = +18V, and VSD = +5V, unless otherwise noted.
BUF12840
PARAMETER
CONDITIONS
MIN
TYP
17.7
17.85
MAX
UNIT
ANALOG GAMMA BUFFER CHANNELS
Reset value
Code 0
0
OUT1 to OUT12 output swing: high
Code = 1023, sourcing 10mA
OUT1 to OUT12 output swing: low
Code = 0, sinking 10mA
OUT1 to OUT12 output swing: high
Code = 1023, sourcing 5mA
OUT1 to OUT12 output swing: low
Code = 0, sinking 5mA
Continuous output current
See note
Output accuracy
vs Temperature
0.07
17.8
V
V
0.2
30
V
mA
Code 512
±20
Code 512
±25
μV/°C
Bits
INL
VOUT = GND + 0.3V to VS – 0.3V
0.3
Differential nonlinearity
DNL
VOUT = GND + 0.3V to VS – 0.3V
0.3
Load regulation, 10mA
REG
Code 512 or VCC/2, IOUT = +5mA to –5mA step
0.5
Integral nonlinearity
V
0.3
17.9
0.07
(1)
V
±50
mV
Bits
1.5
mV/mA
20
V
ANALOG POWER SUPPLY
Operating range
Total analog supply current
9
IS
Outputs at midscale with no load
6.5
Over temperature
10
mA
19
mA
DIGITAL INPUT/OUTPUT (2)
Logic 1 input voltage
VIH
Logic 0 input voltage
VIL
Logic 0 output voltage
VOL
0.7 × VSD
ISINK = 3mA
Input leakage
Clock frequency
fCLK
EEPROM read clock speed
V
0.15
0.4
V
±0.01
±10
μA
Standard/Fast mode
400
kHz
High-Speed mode
3.4
MHz
87
100
kHz
7
10
μs
5.5
V
90
150
μA
115
175
μA
1.5
1.7
V
–40
+95
°C
–40
+95
°C
–65
+150
°C
Master mode
BANK switching delay
V
0.3 × VSD
71
LD pin = 0, VOUT = 50% of code 1023
DIGITAL POWER SUPPLY
Operating range
Digital supply current (1)
VSD
ISD
2.0
Two-Wire bus inactive
Over temperature
Power-on reset
POR
1.1
TEMPERATURE RANGE
Specified range
Operating range
Storage range
(1)
(2)
Junction temperature < +125°C
Observe maximum power dissipation. Exposed thermal die is soldered to the PCB using thermal vias. Refer to Texas Instruments
application report QFN/SON PCB Attachment (SLUS271).
Refers to pins EA0, EA1, EN, LD, SCL, SDA, A0, and BKSEL.
Copyright © 2010–2011, Texas Instruments Incorporated
3
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
PIN CONFIGURATION
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
24
23
22
21
20
19
RGE PACKAGE
4mm × 4mm VQFN-24
(TOP VIEW)
(1)
OUT5
1
18
GNDD
OUT4
2
17
BKSEL
OUT3
3
16
A0
OUT2
4
15
SDA
OUT1
5
14
SCL
OUT0
6
13
LD
9
10
11
12
VSD
EA1
EA0
EN
8
GNDA
(1)
VS
7
Exposed Thermal Pad
(Bottom Side)
NOTE: (1) GNDA and GNDD must be connected together.
PIN DESCRIPTIONS
4
PIN NO.
NAME
1
OUT5
DAC output 5
DESCRIPTION
2
OUT4
DAC output 4
3
OUT3
DAC output 3
4
OUT2
DAC output 2
5
OUT1
DAC output 1
6
OUT0
DAC output 0
7
VS
8
GNDA
VS connected to analog supply
Analog ground; must be connected to digital ground (GNDD)
9
VSD
Digital supply; connected to logic supply
10
EA1
EEPROM select bit 1. EA1 should be tied to logic '0' if autoread is not used.
11
EA0
EEPROM select bit 0. EA0 should be tied to logic '0' if autoread is not used.
12
EN
EEPROM enable. EN must be '0' if autoread is not used.
13
LD
Latch pin
14
SCL
Serial clock
15
SDA
Serial data
16
A0
17
BKSEL
Slave address
Bank select
18
GNDD
Digital ground; must be connected to digital ground (GNDA)
19
OUT11
DAC output 11
20
OUT10
DAC output 10
21
OUT9
DAC output 9
22
OUT8
DAC output 8
23
OUT7
DAC output 7
24
OUT6
DAC output 6
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +18V, and VSD = +5V, unless otherwise noted.
ANALOG SUPPLY CURRENT HISTOGRAM
1200
18
17.5
17
16.5
16
15.5
15
3
2.5
2
1.5
1
0.5
0
1000
Output Swing High
Occurrence
Output Voltage (V)
OUTPUT VOLTAGE vs OUTPUT CURRENT
(Channels 1–12)
800
600
400
Output Swing Low
200
0
0
25
50
75
100
125
5
150
5.5
6
6.5
7
7.5
8
Analog Supply Current (mA)
Output Current (mA)
Figure 1.
Figure 2.
ANALOG SUPPLY CURRENT vs TEMPERATURE
OUTPUT VOLTAGE vs TEMPERATURE
8.5
9.02
8
9.015
7.5
9.01
Initial Voltage (V)
Analog Supply Current (mA)
10 Typical Units Shown
7
6.5
6
5.5
9.005
9
8.995
8.99
5
8.985
4.5
8.98
4
-50
-25
0
25
50
75
100
125
-50
0
-25
Temperature (°C)
25
50
75
100
125
Temperature (°C)
Figure 3.
Figure 4.
DIGITAL SUPPLY CURRENT vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
94
0.15
0.1
90
88
Error (LSB)
Digital Supply Current (mA)
92
86
84
82
0.05
0
-0.05
80
78
-0.1
76
74
-0.15
-50
-25
0
25
50
75
Temperature (°C)
Figure 5.
Copyright © 2010–2011, Texas Instruments Incorporated
100
125
0
256
512
768
1024
Input Code
Figure 6.
5
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = +18V, and VSD = +5V, unless otherwise noted.
BKSEL SWITCHING TIME DELAY
(LD Pin = 0)
INTEGRAL LINEARITY ERROR
0.15
0.1
Error (LSB)
BKSEL (2V/div)
0.05
7ms
0
18V
-0.05
DAC Channel
(9V/div)
-0.1
0V
-0.15
0
256
768
512
10ms/div
1024
Input Code
Figure 7.
Figure 8.
Output Voltage (2V/div)
LARGE-SIGNAL STEP RESPONSE
Time (2ms/div)
Figure 9.
6
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
APPLICATION INFORMATION
GENERAL
The BUF12840 programmable voltage reference
allows fast and easy adjustment of 12 programmable
gamma reference outputs, each with 10-bit resolution.
The BUF12840 is programmed through a high-speed,
two-wire interface. The final gamma values can be
automatically loaded from an external EEPROM. The
BUF12840 has two separate memory banks, allowing
simultaneous storage of two different gamma curves
to facilitate dynamic switching between gamma
curves.
The BUF12840 can be powered using an analog
supply voltage from 9V to 20V, and a digital supply
from 2V to 5.5V. The digital supply must be applied
before the analog supply to avoid excessive current
and power consumption, or possibly even damage to
the device if left connected only to the analog supply
for extended periods of time. See Figure 10 for a
typical configuration of the BUF12840. Note that the
analog power, VS, does not need to be on during any
interface communication.
TWO-WIRE BUS OVERVIEW
The
BUF12840
communicates
over
an
industry-standard, two-wire interface to receive data
in slave mode. This model uses a two-wire,
open-drain interface that supports multiple devices on
a single bus. Bus lines are driven to a logic low level
only. The device that initiates the communication is
called a master, and the devices controlled by the
master are slaves. The master generates the serial
clock on the clock signal line (SCL), controls the bus
access, and generates the START and STOP
conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line (SDA)
from a high to a low logic level while SCL is high. All
slaves on the bus shift in the slave address byte on
the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
high. Any change in SDA while SCL is high is
interpreted as a START or STOP condition.
Once all data have been transferred, the master
generates a STOP condition, indicated by pulling
SDA from low to high while SCL is high. The
BUF12840 acts as a slave device after 10ms; before
that, it is the master and drives SCL and SDA.
ADDRESSING THE BUF12840
The address of the BUF12840 is 111010x, where x is
the state of the A0 pin. When the A0 pin is low, the
device acknowledges on address 74h (1110100). If
the A0 pin is high, the device acknowledges on
address 75h (1110101). Table 1 shows the A0 pin
settings and the BUF12840 address options.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
Table 1. Quick Reference of BUF12840 Addresses
BUF12840 ADDRESS
ADDRESS
A0 pin is low
(device acknowledges on address 74h)
1110100
A0 pin is high
(device acknowledges on address 75h)
1110101
Table 2. Quick Reference of Command Codes
COMMAND
CODE
General-Call Reset
Address byte of 00h followed by a data byte of 06h.
High-Speed Mode
00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
Copyright © 2010–2011, Texas Instruments Incorporated
7
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
0.1mF
VS
VS
1mF
EA1
EA0
EN
LD
GNDD
GNDA
A0
A1
Power PAD
SCL
SDA
EEPROM
GNDD
GNDD
TCON
0.1mF
10kW
SDA
SCL
BKSEL
A0
VSD
I/O
I/O
SDA
SCL
0.1mF
VSD
10kW
Source Drivers
BUF12840
VSD
VSD
Figure 10. Typical Application Configuration
DATA RATES
The two-wire bus operates in one of three speed
modes:
• Standard: allows a clock frequency of up to
100kHz;
• Fast: allows a clock frequency of up to 400kHz;
and
• High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz.
The BUF12840 is fully compatible with all three
modes. No special action is required to use the
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed
mode, send a special address byte of 00001 xxx, with
SCL ≤ 400kHz, following the START condition; where
xxx are bits unique to the Hs-capable master, which
can be any value. This byte is called the Hs master
8
code. Table 2 provides a reference for the
High-speed mode command code. (Note that this
configuration is different from normal address
bytes—the low bit does not indicate read/write
status.) The BUF12840 responds to the High-speed
command regardless of the value of these last three
bits. The BUF12840 does not acknowledge this byte;
the
communication
protocol
prohibits
acknowledgment of the Hs master code. Upon
receiving a master code, the BUF12840 switches on
its Hs mode filters, and communicates at up to
3.4MHz. Additional high-speed transfers may be
transmitted without resending the Hs mode byte by
generating a repeat START without a STOP. The
BUF12840 switches out of Hs mode with the next
STOP condition.
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
10ms
is updated at this moment.
The entire DAC register D9-D0
Ackn
D0
D1
D2
D3
D4
D5
D6
D7
Ackn
D8
D9
D10
D11
D12
D13
D14
D15 = 1, all DAC outputs are updated when the current DAC register is updated.
D15
Ackn
R0
R1
R2
R3
R4
D5
D6
D7
Ackn
W
A0
A1
A0
A1
A2
A6
A6
SDA_In
Device_Out
A5
A4
A3
Device Address
DAC_OUTPUT
SCL
Write single DAC register. R4-R0 specify DAC address.
A2
R2
R3
R4
D5
D6
D7
Ackn
W
Ackn
Write
Write Operation
DAC address pointer. D7-D5 must be 000.
R1
R0
Method 1: Method 1 is used when it is desirable to
have the DAC output voltage change immediately
after writing to a DAC register. For each write
transaction, the master sets data bit 15 to a '1'. The
DAC output voltage update occurs after receiving the
16th data bit for the currently-written register, as
shown in Figure 11.
A3
D11
D12
D13
Ackn
Ackn
D15
D14
Because the BUF12840 features a double-buffered
register structure, updating the digital-to-analog
converter (DAC) register is not the same as updating
the DAC output voltage. There are two methods for
updating the DAC output voltages.
A4
D6
D10
D9
D8
Ackn
DAC MSbyte. D14 must be 0.
SOFTWARE DAC OUTPUT UPDATE
Method 2: Method 2 is used when it is desirable to
have all DAC output voltages change at the same
time. First, the master writes to the desired DAC
channels with data bit 15 a '0'. Then, when writing the
last desired DAC channel, the master sets data bit 15
to a '1'. All DAC channels are updated at the same
time after receiving the 16th data bit.
Ackn
D7
The BUF12840 outputs are capable of a full-scale
voltage output change in typically 5μs, see Figure 9;
no intermediate steps are required. The outputs are
also capable of a full-scale output change using the
BKSEL or LD pin in typically 7µs, see Figure 8.
A5
D0
D1
D2
D3
D5
D4
DAC LSbyte
(1)
Start
Where:
CODE can vary from 0 to 1023.
Ackn
Buffer output values are determined by the analog
supply voltage (VS) and the decimal value of the
binary input code used to program that buffer. The
value is calculated using Equation 1:
CODE
VOUT = VS ´
1024
Ackn
Stop
DAC VOLTAGE OUTPUT CODE
Figure 11. Write DAC_OUT Register Timing
Copyright © 2010–2011, Texas Instruments Incorporated
9
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
EEPROM ADDRESS SELECT PINS
EA0 and EA1 are used to select the proper EEPROM
size. Table 4 shows the start and stop address to
load each of the DAC registers. The state of the
select pins must be set before the auto read function
is activated.
Enable Pin
The status of EN at power-on reset (POR)
determines the modes of operation of the BUF12840,
as described in Table 3. If EN = 1, the BUF12840
acts as a master; after the data download finishes,
the BUF12840 enters slave mode. If EN = 0, the
BUF12840 skips the master mode and enters slave
mode directly. Once in slave mode after POR,
changing the status of EN has no effect on the
BUF12840 unless the user issues a GCR
(general-call reset) or RA (read again) command.
mode operation is needed, EN should be tied to
DVSS; it is recommended that after POR occurs wait
at least 15ms before addressing the BUF12840.
Figure 12 shows how EN affects the operation of the
BUF12840 in a typical application.
The BUF12840 tries to read up to 10 times spaced
1ms apart during POR, which can occur if the
EEPROM is not ready or if the two-wire bus is kept
busy by another device. By the end of the tenth
attempt, if the download cannot be started, the
BUF12840 goes into slave mode. This action ensures
that the BUF12840 enters slave mode within 25ms
from the POR condition, regardless if the download is
successful or not.
POR
Initialize DAC Output
Load DAC with All 0s
Table 3. EN Modes of Operation
ENABLE EN
LOGIC LEVEL
EEPROM AUTO
READ
Low
0
Disabled
High
1
Enabled
Set
EN = 1
After a POR condition is detected by the BUF12840,
a 10ms window occurs. As long as EN goes high in
this window, the BUF12840 downloads data from the
EEPROM. It is recommended that this pin be tied to
DVDD if the application allows. However, if only slave
No
Yes
EEPROM
Download
The BUF12840
Enters Slave Mode
Figure 12. Effect of EN in a Typical Set Up
Table 4. EEPROM Configuration
REGISTER BANK0
(1)
(2)
10
REGISTER BANK1
EA0
EA1
START WORD
ADDRESS
END WORD
ADDRESS
START WORD
ADDRESS
END WORD
ADDRESS
ACCEPTABLE
EEPROM (1) (2)
0
0
0
23
24
47
1k, 2k, 4k, 8k, 16k
0
1
361
384
405
428
2k, 4k, 8k, 16k
1
0
0
23
24
47
32k, 64k, 128k, 256k
and larger
1
1
361
384
405
428
32k, 64k, 128k, 256k
and larger
Any applicable EEPROM chip select pins (A2, A1, A0) must be hardwired to GND.
When EA0 = 0 and EA1 = 1, it is required that the types of EEPROM that supports Page/Block address definition with chip select pins
(for example, A0 is part of the Word Address).
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
POWER-ON RESET (POR) AUTO READ
FUNCTION
Figure 14 depicts the BUF12840 POR Master Mode
auto read function and timing. The BUF12840 makes
the first attempt to read the external EEPROM 5ms
after the POR (power-on reset) condition is met, as
shown in Figure 13. Following the initial 5ms wait
period, the BUF12840 queries the EEPROM with a
digital word that includes an EEPROM address and
acknowledge request. If communication with the
EEPROM is established, the download finishes in
10ms.
However, if the first read attempt is not successful,
the BUF12840 waits for 1ms and then tries to start
the download again. This process repeats itself until a
successful acknowledge from the EEPROM is
detected or until 10 read attempts have been made. If
at any time during this process the BUF12840 does
detect a successful acknowledge from the EEPROM
and the EN pin is properly set, the BUF12840 initiates
the upload and reads the contents of the EEPROM,
which takes approximately 10ms to complete. The
DAC outputpower-on reset value is 0V. The state of
VS (analog supply voltage) does not affect POR or
the auto read function.
Immediately after power up, all DAC outputs are set
to 0V. During the auto-read function, values are
written into the DAC registers as they are being read
from the EEPROM. Once the auto-read function is
complete, all values are simultaneously loaded from
the DAC registers to the DAC outputs. Therefore, all
values change together. This action is performed
regardless of the state of the LD pin and occurs by
default after auto-read is completed.
Once the information is downloaded from the
EEPROM, the BUF12840 automatically goes into
slave mode, where all slave mode operations are
supported. The BUF12840 remains in slave mode
until another POR, GCR (general-call reset), or RA
(read again) condition is met.
The EN pin should be set to a high level within 15ms
of crossing the POR condition. If the EN pin active
high state is not detected during the first 10 query
attempts, the BUF12840 automatically enters slave
mode. If the master mode auto read function must be
terminated at any time during the auto read process,
the EN pin can be set to a low '0' level that forces the
BUF12840 into slave mode and the automatic
download process to stop. If an EEPROM
acknowledge is not detected during the possible 10
read attempts, the BUF12840 automatically goes into
slave mode following the tenth read attempt. Note
that the analog power, VS, does not need to be on
during any interface communication.
VSD
tOFF ³ 100ms
POR (1.1V)
tF (min) ³ 500ms
tR (min) ³ 10ms
Figure 13. POR
Copyright © 2010–2011, Texas Instruments Incorporated
11
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
POR
Time = 0
5ms
1.5V
POR Activates Master Mode
EEPROM Address + Acknowledge
¼
Idle
SDA
900ms
1ms
5ms
EN (high, '1') should be enabled prior to a query pulse and
before the 10th query attempt to remain in master mode.
¼
EN
Time (ms)
Framing Pulse for EEPROM Query
10ms
General Case
1st
EEPROM
Query
5ms
Wait
5
Case 1
EEPROM Ready on
Fourth Read Attempt
6
5
Case 3
EEPROM Not Ready
in 5ms
5
n
7
3rd
EEPROM
Query if
2nd Failed
2nd
EEPROM
Query if
1st Failed
6
7
10ms
10th
EEPROM
Query if
9thFailed
¼
14
n+1
Time (ms)
EEPROM Data Loaded
BUF12840 Eneters Slave Mode
Time (ms)
10th Query Successful,
Data Now Downloaded
From EEPROM
10ms
¼
EEPROM Data Loaded
BUF12840 Eneters Slave Mode
(m + 10ms)
19
15
nth
EEPROM
Query if
(n-1) Failed
¼
n
m
4th Query Successful,
Data Now Downloaded
From EEPROM
9
8
3rd
EEPROM
Query if
2nd Failed
mth Query Successful,
Data Now Downloaded
From EEPROM
¼
n+1
8
7
6
nth
EEPROM
Query if
(n-1) Failed
¼
4th
3rd
EEPROM EEPROM
Query if
Query if
2nd Failed 3rd Failed
2nd
EEPROM
Query if
1st Failed
1st
EEPROM
Query
5ms
Wait
7
6
1st
EEPROM
Query
5ms
Wait
3rd
EEPROM
Query if
2nd Failed
2nd
EEPROM
Query if
1st Failed
1st
EEPROM
Query
5ms
Wait
5
Case 2
EEPROM Ready on
Tenth Read Attempt
2nd
EEPROM
Query if
1st Failed
25
9th
EEPROM
Query if
8th Failed
13
EEPROM Data Loaded
BUF12840 Eneters Slave Mode
Time (ms)
10th
EEPROM
Query if
9th Failed
14
EEPROM Data Loaded
BUF12840 Eneters Slave Mode
15
Time (ms)
Figure 14. POR Master Mode Auto Read Function and Timing Diagram
MASTER MODE CLOCK SPEED
In master mode, the BUF12840 generates it own
clock and puts it on the SCL pin. The frequency is
nominally 87kHz, with a maximum value of 100kHz
and a minimum value of 71kHz. When the BUF12840
has exclusive access to the two-wire bus, it takes a
maximum of 10ms to download both banks of data
from the moment power becomes valid. However,
when the BUF12840 is in master mode, if there is
contention on the two-wire bus because of another
active master, the BUF12840 activates its clock
synchronization and arbitration engine. In this case, it
may take longer for the BUF12840 to finish the
download.
12
The BUF12840 can only synchronize with other
masters that operate in Standard Mode (clock speed
≤ 100kHz). It is not recommended to have another
master with higher speed operating at the same time.
Note that once in slave mode, the BUF12840
supports clock speeds up to 3.4MHz.
GENERAL-CALL RESET
The BUF12840 responds to software general-call
reset (GCR). Upon receiving a GCR command, the
BUF12840 enters master mode and downloads data
from the EEPROM as if the power supply was just
switched on.
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
READ AGAIN
When the BUF12840 is in slave mode, a read again
(RA) command can be issued to restart an EEPROM
data download. The RA command follows this
process:
1. Send the BUF12840 device address with write
bit: 11101000 if A0 = 0 or 11101010 if A0 = 1; the
BUF12840 acknowledges this byte.
2. Send register address 00011100; the BUF12840
acknowledges this byte.
3. Send two bytes of data xxxxxxxx and xxxxxxx1,
where x is don’t care; the BUF12840
acknowledges both bytes.
DAC OUTPUT UPDATE (Using the LD Pin)
Because the BUF12840 features a double-buffered
register structure, updating the DAC register is not
the same as updating the DAC output voltage.
There are three methods for launching transferred
data from the storage registers into the DACs to
update the DAC output voltage. It is essential that
BKSEL be set to the desired bank because BKSEL
determines which bank is loaded.
Method 1: Set the latch pin low (LD = low) to update
each DAC output voltage whenever its corresponding
register is updated.
Copyright © 2010–2011, Texas Instruments Incorporated
Method 2: Set LD high to allow all DAC output
voltages to retain the respective values during data
transfer until LD goes low, which simultaneously
updates the output voltages of all 12 DACs to the
new register values.
Method 3 (software mode): LD is maintained high
and all 12 DACs are updated when the master writes
a '1' in bit 15 of any DAC register. The update occurs
after receiving the 16-bit data for the currently-written
register.
Use methods 2 and 3 to transfer a future data set into
the first bank of registers in advance to prepare for a
very fast update of DAC output voltages.
The general-call reset (GCR) and the power-up reset
updates the DACs regardless of the state of the latch
pin. For a list of DAC addresses; see Table 5.
BKSEL PIN
The BUF12840 has the ability to store two distinct
gamma curves in two different memory banks. One of
the two available banks is selected using the external
input pin, BKSEL. When this pin is low, BANK0 is
selected; when this pin is high, BANK1 is selected.
The two-wire master also has the ability to update
(acquire) the DAC registers with the last programmed
nonvolatile memory values using software control.
The bank to be acquired depends on the state of
BKSEL.
13
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
WRITE BOTH BANKS OF DAC REGISTERS
In slave mode, writes to both banks are accomplished
through the two-wire bus; there are different register
address for the two banks. The BKSEL pin does not
impact writing to each of the banks. Table 5 details
the DAC addresses for each bank.
DAC_OUT voltages update with the appropriate bank
values based on a combination of LD and BKSEL
pins.
Case 1
Case 2
Case 1: DAC_OUT updates to BANK1 because the
LD pin is low and BKSEL is high. Case 2: DAC_OUT
updates to BANK0 because BKSEL and the LD pin
are low. Case 3: DAC_OUT does not update when
the LD pin is high. Case 4: DAC_OUT updates to
BANK0 because the LD pin and BKSEL are low.
Case 5: DAC_OUT updates to BANK1 because the
LD pin is low and BKSEL is high.
Case 3
Case 4
Case 5
LD
BKSEL
DAC Out
BANK1
BANK0
10ms
BANK1
BANK1
BANK0
10ms
10ms
Figure 15. LD/BKSEL Function and DAC Output TIming Diagram
Table 5. BANK0 and BANK1 DAC Addresses
14
GAMMA
BUFFER
OUTPUT
BANK0
BANK1
REGISTER
R4
R3
R2
R1
R0
REGISTER
R4
R3
R2
R1
R0
OUT0
Register 0 BANK0
0
0
0
0
0
Register 0 BANK1
1
0
0
0
0
OUT1
Register 1 BANK0
0
0
0
0
1
Register 1 BANK1
1
0
0
0
1
OUT2
Register 2 BANK0
0
0
0
1
0
Register 2 BANK1
1
0
0
1
0
OUT3
Register 3 BANK0
0
0
0
1
1
Register 3 BANK1
1
0
0
1
1
OUT4
Register 4 BANK0
0
0
1
0
0
Register 4 BANK1
1
0
1
0
0
OUT5
Register 5 BANK0
0
0
1
0
1
Register 5 BANK1
1
0
1
0
1
OUT6
Register 6 BANK0
0
0
1
1
0
Register 6 BANK1
1
0
1
1
0
OUT7
Register 7 BANK0
0
0
1
1
1
Register 7 BANK1
1
0
1
1
1
OUT8
Register 8 BANK0
0
1
0
0
0
Register 8 BANK1
1
1
0
0
0
OUT9
Register 9 BANK0
0
1
0
0
1
Register 9 BANK1
1
1
0
0
1
OUT10
Register 10 BANK0
0
1
0
1
0
Register 10 BANK1
1
1
0
1
0
OUT11
Register 11 BANK0
0
1
0
1
1
Register 11 BANK1
1
1
0
1
1
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
TIMING DIAGRAMS
Figure 16 describes the timing operations on the
BUF12840. Parameters for Figure 16 are defined in
Table 6. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the
SDA line, from high to low, while the SCL line is high,
defines a START condition. Each data transfer is
initiated with a START condition, denoted as S in
Figure 16.
Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer
terminates with a repeated START or STOP
condition, denoted as P in Figure 16.
t(LOW)
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
limited and is determined by the master device. The
receiver acknowledges data transfer.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
period of the Acknowledge clock pulse. Setup and
hold times must be taken into account. On a master
receive, data transfer termination can be signaled by
the master generating a Not-Acknowledge on the last
byte that has been transmitted by the slave.
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 16. Two-Wire Timing Diagram
Table 6. Timing Characteristics for Figure 16
STANDARD MODE
PARAMETER
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
0.1
0
0.4
0
3.4
MHz
SCL operating frequency
f(SCL)
0
Bus free time between
STOP and START condition
t(BUF)
4000
600
160
Hold time after repeated
START condition. After this
period, the first clock is
generated.
t(HDSTA)
100
100
100
ns
Repeated START condition
setup time
t(SUSTA)
100
100
100
ns
STOP condition setup time
t(SUSTO)
100
100
100
ns
Data hold time
t(HDDAT)
1 (1)
0 (1)
0 (2)
ns
Data setup time
ns
t(SUDAT)
250
100
10
ns
SCL clock low period
t(low)
4700
1300
160
ns
SCL clock high period
t(high)
4000
600
60
Clock/data fall time
Clock/data rise time
for SCLK ≤ 100kHz
(1)
(2)
tF
tR
300
ns
300
160
ns
300
300
160
ns
1000
1000
ns
For cases with a fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater
than 20ns.
For cases with a fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than
10ns.
Copyright © 2010–2011, Texas Instruments Incorporated
15
16
Figure 17. General-Call Reset Timing
SDA
SCL
SDA
SCL
Start
High-Speed Command
Start
General-Call Reset Command
Address Byte = 00h
Address Byte = 00001xxx (HS Master Code)
Ackn
Ackn
Device enters high-speed mode at ACK clock pulse.
Device exits high-speed mode with stop condition.
No Ackn
Device begins reset at arrow and is in reset until ACK clock pulse.
Then the device acquires memory, etc., as it does at power-up.
Address Byte = 06h
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
Figure 18. High-Speed Mode Timing
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to
improve the picture quality in LCD TV applications.
The brightness in each picture frame is analyzed and
the gamma curves are adjusted on a frame-by-frame
basis. The gamma curves are typically updated
during the short vertical blanking period in the video
signal. Figure 19 shows a block diagram using the
BUF12840 for dynamic gamma control.
The BUF12840 is ideally suited for rapidly changing
the gamma curves as a result of its unique topology:
• Double register input structure to the DAC
• Fast serial interface
• Simultaneous updating of all DACs by software.
See the Read/Write Operations section to write to
all registers and the Output Latch sections.
END-USER SELECTED GAMMA CONTROL
The double register input structure saves
programming time by allowing updated DAC values to
be pre-stored into the first register bank. Storage of
this data can occur while a picture is still being
displayed. Because the data are only stored into the
first register bank, the DAC output values remain
unchanged—the display is unaffected. During the
vertical sync period, the DAC outputs (and therefore,
the gamma voltages) can be quickly updated either
by using an additional control line connected to the
LD pin, or through software—writing a '1' in bit 15 of
any DAC register. For details on the operation of the
double register input structure, see the Output Latch
section.
Example: Update all 12 registers simultaneously via
software.
Step 1: Check if the LD pin is placed in a high
state.
Step 2: Write DAC registers 1-12 with bit 15
always '0'.
Step 3: Write any DAC register a second time
with identical data. Make sure that bit 15 is '1'. All
DAC channels are updated simultaneously after
receiving the last bit of data.
Example: Update all 12 registers simultaneously via
hardware.
Step 1: Toggle the BKSEL pin to the desired
gamma curve, either Bank0 or Bank1.
Step 2: Toggle the LD pin low. When this occurs,
all 12 internal DAC registers are updated after
1µs. The output then slews to the new voltage
level. The time to change between two gamma
voltage settings is then dependent on the slew
rate of the DAC plus the gamma buffer and the
change in voltage required. This value can be
obtained by referring to the Large-Signal Step
Response curve (Figure 9).
Histogram
Gamma
Adjustment
Algorithm
Digital
Picture
Data
Black
White
BUF12840
Gamma References
A through L
Timing Controller/Microcontroller
Source Driver
Source Driver
Figure 19. Dynamic Gamma Control
Copyright © 2010–2011, Texas Instruments Incorporated
17
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
READ/WRITE OPERATIONS
The BUF12840 is able to read from a single DAC or
multiple DACs, or write to the register of a single
DAC, or multiple DACs in a single communication
transaction. DAC addresses for BANK0 begin with
00000, which corresponds to Register 0, through
01011, which corresponds to Register 11. DAC
addresses for BANK1 begin with 10000, which
corresponds to Register 0, through 11011, which
corresponds to Register 11; see Table 5. Write
commands are performed by setting the read/write bit
LOW. Setting the read/write bit HIGH performs a read
transaction.
Writing
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send a DAC address byte. Bits D7−D5 are
unused and should be set to 0. Bits D4−D0 are
the DAC address; see Table 5. Only DAC
addresses 00000 to 01011 and 10000 to 11011
are valid and acknowledged.
4. Send two bytes of data for the specified DAC.
Begin by sending the most significant byte first
(bits D15−D8, of which only bits D9 and D8 are
used), followed by the least significant byte (bits
D7−D0). The DAC register is updated after
receiving the second byte.
5. Send a STOP condition on the bus.
See Figure 20.
www.ti.com
The BUF12840 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register is not updated. Updating the DAC register is
not the same as updating the DAC output voltage;
see the Output Latch section.
The process of updating multiple registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master continues to send
data for the next register. The BUF12840
automatically and sequentially steps through
subsequent registers as additional data are sent. The
process continues until all desired registers have
been updated or a STOP condition is sent.
To write to multiple registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send either the Register 0 address byte to start
at the first DAC or send the address of whichever
DAC is the first to be updated. The BUF12840
begins with this DAC and steps through
subsequent DACs in sequential order.
4. Send the bytes of data. The first two bytes are for
the DAC addressed in step 3. Its register is
automatically updated after receiving the second
byte. The next two are for the following DAC. The
DAC register is updated after receiving the fourth
byte. The last two bytes are for Register 11. The
DAC register is updated after receiving the 24th
byte. For each DAC, begin by sending the most
significant byte (bits D15−D8, of which only bits
D9 and D8 have meaning), followed by the least
significant byte (bits D7−D0).
5. Send a STOP condition on the bus.
See Figure 21.
When the DAC registers are written through a
two-wire communication, changing the BKSEL pin
does not affect the communication because the
banks have different addresses. However, when
loading the DACs through an I2C communication, the
bank to be loaded is decided by the BKSEL pin.
Therefore, if the BKSEL pin is switched during a
two-wire load, the new value of BKSEL determines
the bank that is loaded.
18
Copyright © 2010–2011, Texas Instruments Incorporated
A6
A5
A5
Copyright © 2010–2011, Texas Instruments Incorporated
A6
A6
SDA_In
Start
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A1
A1
A0
A0
W
W
Write
A4
A4
A2
A2
Ackn
Ackn
Ackn
D7
D7
Write Operation
A3
A3
Device Address
A1
A1
W
W
Ackn
Ackn
Ackn
D7
D7
Write Operation
D6
D6
D6
D6
D5
D5
R4
R4
R3
R3
R2
R2
R1
R1
D5
D5
R0
R0
R3
R3
Ackn
Ackn
Ackn
R4
R4
R0
R0
Ackn
Ackn
D14
D14
D14
D14
D13
D13
D12
D12
D11
D11
D13
D13
D12
D12
D11
D11
D10
D10
DAC MSbyte. D14 must be 0.
D9
D9
D8
D8
Ackn
Ackn
Ackn
D7
D7
D10
D10
D9
D9
D8
D8
Ackn
Ackn
Ackn
D7
D7
D14
D14
D15
D15
D12
D12
D13
D13
D11
D11
D10
D10
DAC 12 MSbyte. D14 must be 0.
D9
D9
D6
D6
D8
D8
Ackn
Ackn
Ackn
D5
D5
D4
D4
D7
D7
D3
D3
D6
D6
DAC (pointer) LSbyte
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D15
DAC (pointer) MSbyte. D14 must be 0.
R1
R1
Ackn
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D15
R2
R2
DAC address pointer. D7-D5 must be 000.
DAC address pointer. D7-D5 must be 000.
A0
A0
Write
D2
D1
D1
D5
D5
D0
D0
Ackn
D5
D5
D4
D4
D3
D3
DAC 12 LSbyte
D2
D2
is updated at this moment.
D1
D1
D0
D0
Ackn
Ackn
is updated at this moment.
The entire DAC register D9-D0
D2
D2
Ackn
Stop
D1
D1
D15
D15
D14
D14
D0
D0
Ackn
Ackn
Ackn
D13
D13
Stop
DAC (pointer + 1) MSbyte. D14 must be 0.
D3
D3
Ackn
Ackn
D4
D4
The entire DAC register D9-D0
D2
D6
D6
DAC LSbyte
www.ti.com
Device_Out
SCL
Figure 20. Write SIngle DAC Register Timing
Write multiple DAC registers. R4-R0 specify DAC address.
A6
SDA_In
Device_Out
SCL
Start
Write single DAC register. R4-R0 specify DAC address.
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
Figure 21. Write Multiple DACs Register Timing
19
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
The BUF12840 acknowledges each byte. To
terminate communication, send a STOP or START
condition on the bus. Only DACs that have received
both bytes are updated.
Reading
To read the register of one DAC:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send a DAC address byte. Bits D7−D5 are
unused and should be set to 0. Bits D4−D0 are
the DAC address; see Table 5. Only DAC
addresses 00000 to 01011 and 10000 to 11011
are valid and acknowledged.
4. Send a START or STOP/START condition on the
bus.
5. Send correct device address and read/write bit =
HIGH. The BUF12840 acknowledges this byte.
6. Receive two bytes of data. They are for the
specified DAC. The first received byte is the most
significant byte (bits D15−D8, of which only bits
D9 and D8 have meaning); the next is the least
significant byte (bits D7−D0).
7. Acknowledge after receiving each byte.
8. Send a STOP condition on the bus.
See Figure 22.
20
www.ti.com
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not sending the acknowledge.
To read multiple DAC registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF12840 acknowledges this byte.
3. Send either the Register 0 address byte to start
at the first DAC or send the address byte for
whichever DAC is the first in the sequence of
DACs to be read. The BUF12840 begins with this
DAC and steps through subsequent DACs in
sequential order.
4. Send the device address and read/write bit =
HIGH.
5. Receive bytes of data. The first two bytes are for
the specified DAC. The first received byte is the
most significant byte (bits D15−D8, of which only
bits D9 and D8 have meaning). The next byte is
the least significant byte (bits D7−D0).
6. Acknowledge after receiving each byte.
7. When all desired DACs have been read, send a
STOP or START condition on the bus.
See Figure 23.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not sending the acknowledge.
Copyright © 2010–2011, Texas Instruments Incorporated
A6
A3
Copyright © 2010–2011, Texas Instruments Incorporated
A2
A2
A1
A1
A0
A0
W
W
Ackn
Ackn
Ackn
D7
D7
Read operation.
A6
A6
SDA_In
Device_Out
Start
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
Read multiple DAC registers. R4-R0 specify DAC address.
A3
Write
A1
A1
D6
D6
A0
A0
D5
D5
W
W
Write
R4
R4
R2
R2
Ackn
Ackn
Ackn
D7
D7
Read operation.
R3
R3
DAC address pointer. D7-D5 must be 000.
R1
R1
Ackn
Ackn
Start
A6
A6
A5
A5
D6
D6
D5
D5
R4
R4
R3
R3
R2
R2
Start DAC address pointer. D7-D5 must be 000.
R0
R0
Ackn
R1
R1
A4
A4
R0
R0
A3
A3
A2
A2
Ackn
Ackn
Ackn
Device Address
A1
Start
A1
A0
A6
A5
A5
Ackn
Ackn
Ackn
D14
D14
A4
A4
A3
A3
Device Address
D15
D15
A2
A2
D13
D13
A1
A1
D12
D12
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
A0
A0
D11
D11
D8
D8
R
R
Ackn
Ackn
Ackn
D7
D7
D8
D8
Ackn
Ackn
D9
D9
Ackn
Read
D10
D10
DAC MSbyte. D15-D10 have no meaning.
DAC 12 MSbyte. D15-D10 have no meaning.
D15
A6
R
R
D15
A0
Read
D15
D15
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
DAC LSbyte.
D2
D2
D6
D6
D14
D14
D5
D5
D12
D12
D4
D4
D3
D3
DAC 12 LSbyte.
D13
D13
D11
D11
D2
D2
D10
D10
D1
D1
D9
D9
DAC (pointer) MSbyte. D15-D10 have no meaning.
Ackn
Ackn
Ackn
D0
D0
D1
D1
D8
Ackn
Ackn
Ackn
Ackn
Ackn
D8
Ackn
D0
D0
Stop
No Ackn
No Ackn
Stop
www.ti.com
SCL
A4
A4
A5
A5
A6
Device Address
SDA_In
Start
Read single DAC register. R4-R0 specify DAC address.
Device_Out
SCL
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
Figure 23. Read Multiple DACs Register Timing
Figure 22. Read Single Register Timing
21
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
OUTPUT PROTECTION
VS
The BUF12840 output stages can safely source and
sink the current levels indicated in Figure 1. However,
there are other modes where precautions must be
taken to prevent to the output stages from being
damaged by excessive current flow. The outputs
(OUT1 through OUT12) include electrostatic
discharge (ESD) protection diodes, as shown in
Figure 24. Normally, these diodes do not conduct and
are passive during typical device operation. Unusual
operating conditions can occur where the diodes may
conduct, potentially subjecting them to high, even
damaging current levels. These conditions are most
likely to occur when a voltage applied to an output
exceeds (VS) + 0.5V, or drops below GND – 0.5V.
ESD Current
Steering
Diodes
BUF12840
Schottky
Diode
OUTX
or
VCOM
External Capacitor
(not recommended)
One common scenario where this condition can occur
is when the output pin is connected to a sufficiently
large capacitor, and the BUF12840 power-supply
source (VS) is suddenly removed. Removing the
power-supply source allows the capacitor to
discharge through the current-steering diodes. The
energy released during the high current flow period
causes the power dissipation limits of the diode to be
exceeded. Protection against the high current flow
may be provided by placing a Schottky diode, as
shown in Figure 24. This diode must be capable of
discharging the capacitor without allowing more than
0.5V to develop across the internal ESD
current-steering diodes. It is not recommended that
large capacitors be connected to the output of the
gamma buffers.
Figure 24. Output Pins ESD Protection
Current-Steering Diodes
DVDD
Logic Input
Digital Input
ESD
Only
DVSS
Figure 25. Digital Input Model
Figure 26 shows a simplified schematic of the SDA
and SCL input/output pins. As shown, there are no
ESD cells or diodes to supply; therefore, the input to
the device can go above ground but must be lower
than 6V.
Figure 25 shows a simplified schematic of the input
pins A0, BKSEL, EN, EA0, EA1, and LD. As shown,
there are no ESD cells or diodes to supply; therefore,
the input to the device can go above supply but must
be lower than 6V.
DVDD
Digital Input/Output
Logic Output
ESD
Only
Logic Input
DVSS
Figure 26. Digital Input/Output Model
22
Copyright © 2010–2011, Texas Instruments Incorporated
BUF12840
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October, 2010) to Revision A
•
Page
Corrected error in x-axis value for Figure 9 .......................................................................................................................... 6
Copyright © 2010–2011, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BUF12840AIRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 95
BUF
12840
BUF12840AIRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 95
BUF
12840
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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