BUF634ADEVM

User's Guide SBOU221 – February 2019 BUF634AD Evaluation module The BUF634ADEVM is an evaluation module (EVM) for the BUF634A high-speed buffer in the D (8-pin SOIC) package. The BUF634ADEVM features two BUF634A devices and is designed to quickly demonstrate the functionality and versatility of the buffer. Optionally, the buffers can be configured as outputs for a dual SOIC amplifier in a composite loop. The EVM is ready to connect to power, signal sources, and test instruments by using onboard connectors. The default configuration uses split supplies and subminiature version A (SMA) input and output connecters with a 50-Ω output impedance for standard test equipment. The EVM can be easily configured for other connections and single-supply operation. Dual-channel path configuration is also available for the RCA™ audio input jacks and a 3.5-mm output jack. Throughout this document, the terms EVM and evaluation module are synonymous with the BUF634ADEVM. Table 1 lists the related documentation available through the Texas Instruments web site at www.ti.com. Table 1. Related Documentation Device Literature Number BUF634A SBOS948 BUF634 SBOS030 OPA2810 SBOS789 Trademarks RCA is a trademark of Technicolor SA. All other trademarks are the property of their respective owners. SBOU221 – February 2019 Submit Documentation Feedback BUF634AD Evaluation module Copyright © 2019, Texas Instruments Incorporated 1 Overview 1 www.ti.com Overview This section provides a general description of the BUF634ADEVM. Table 2 lists the input and output limits for the BUF634ADEVM. Table 2. EVM Input and Output Limits MIN TYP MAX UNIT Split-supply voltage range (VS+ – VS–) PARAMETERS ±2.4 ±12 ±13.5 V Single-supply voltage range (VS– = ground) 4.75 24 27 V 3.7 4.5 mA Supply current, IS 3 (VS+) + 0.3 to (VS–) –0.3 Input voltage, VI Output drive, IO with ±12-V or 24-V supply 1.1 48 64 V mA Power Connections The BUF634ADEVM is equipped with banana jacks for easy connection of power. The positive supply input is labeled V+, the negative supply input is labeled V–, and ground is labeled GND. 1.1.1 Split-Supply Operation To operate in split supply, apply the positive supply voltage to V+, the negative supply voltage to V–, and the ground reference from supply to GND. 1.1.2 Single-Supply Operation To operate in single supply, apply jumper V– to GND and apply the positive supply voltage to V+. Inputs and outputs must be biased per data sheet specifications for proper operation. 1.2 Input and Output Connections The BUF634ADEVM is equipped with SMA connectors for easy connection to benchtop signal generators and analysis equipment. Additionally, the EVM also includes RCA input jacks and a 3.5-mm output jack that can be used with the two BUF634A devices in a differential audio buffer configuration. The connections to the SMA outputs include 50–Ω termination resistors for easy connection to 50–Ω impedance test equipment. The inputs are high impedance but can be easily terminated to 50 Ω as well by populating resistors R1 and R4. For best results in the default configuration, route the outputs to test equipment using cables with a 50–Ω characteristic impedance and the connect the inputs to the signal source with as short of cables as possible. 1.2.1 Use With a Dual SOIC Amplifier in a Composite Loop The BUF634ADEVM features the option to configure the devices in two composite amplifier loops using a dual SOIC package amplifier, such as the OPA2810. In the composite loop, the BUF634A forms an output driving stage for the chosen input amplifier and, with the dual paths on the EVM, forms a differential composite amplifier useful for applications such as audio amplification. When configuring the EVM to use the composite loop, populate device U1, resistors R2, R3, R4, and R5, and capacitors C2, and C4, and remove resistors R11 and R16. 2 BUF634AD Evaluation module SBOU221 – February 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Schematic, Layout, and Bill of Materials www.ti.com 2 Schematic, Layout, and Bill of Materials This section provides a complete schematic diagram, board layouts, and bill of materials for the BUF634AEVM. 2.1 Schematic Figure 1 shows a schematic for the BUF634ADEVM. 1 2 3 4 Power Supply Caps for U1 VS+ J5 5 Power Supply Caps for U2 6 Power Supply Caps for U3 L1 HI1206N800R-10 J8 V+ 1 TP1 GND A C7 DNP 1uF C5 50V 6.8uF 3 2 C9 DNP 0.1uF C15 C17 C11 C13 1uF 0.1uF 1uF 0.1uF A J6 EJ508A GND GND J9 GND GND 1 3 2 J7 DNPC20 100V 0.01uF VS- EJ508A C19 100V 0.01uF C21 100V 0.01uF L2 HI1206N800R-10 V- C6 50V 6.8uF DNPC8 DNPC10 50V 25V 1uF 0.1uF C16 50V 1uF C18 25V 0.1uF C12 50V 1uF C14 25V 0.1uF GND B B U1C VS+ 8 V+ DNP V- 4 VS- OPA2810IDR R3 DNP 1.0k R6 DNP 1.0k VS- C1 DNP GND C2 10pF DNP 50V 50V 10pF R13 0 U3 BW V+ 7 3 VIN VO 6 2 R19 R10 DNP 0 0 3 R14 0 1 2 5 8 OPA2810IDR 2 3 4 5 R17 DNP 0 ADNP R4 DNP 49.9 R11 0 J3 Vout1 R8 1 49.9 NC NC NC V- BUF634U/2K5 5 4 3 2 1 C VS+ 1 U1A J1 Vin1 4 C R21 DNP 49.9 GND VS- GND 3 4 1 GND 2 3 1 970 GND R2 DNP 1.0k R5 DNP 1.0k 3 4 1 DNP GND 971 GND J2 Vin2 50V 10pF DNPC4 50V 10pF R18 DNP 0 R12 0 U2 VS+ 1 BW V+ 7 3 VIN VO 6 2 5 8 NC NC NC U1B R22 DNP 49.9 6 1 R20 R9 DNP 0 5 R15 0 BDNP 7 OPA2810IDR 2 3 4 5 0 D SJ-3523-SMT GND VS- C3 J11 J12 R1 DNP 49.9 R16 0 R7 J4 Vout2 1 49.9 V- 4 5 4 3 2 J10 D BUF634U/2K5 VS- GND GND GND Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. 1 2 3 4 Orderable: BUF634ADEVM TID #: N/A Number: AMPS072 Rev: E1 SVN Rev: Not in version control Drawn By: Engineer: Sean Cashin 5 Designed for: Public Release Project Title: BUF634ADEVM Sheet Title: Assembly Variant: 001 File: AMPS072E1.SchDoc Contact: http://www.ti.com/support Mod. Date: 1/22/2019 Sheet: 1 of 2 Size: B http://www.ti.com © Texas Instruments 2019 6 Figure 1. BUF634ADEVM Schematic SBOU221 – February 2019 Submit Documentation Feedback BUF634AD Evaluation module Copyright © 2019, Texas Instruments Incorporated 3 Schematic, Layout, and Bill of Materials 2.2 www.ti.com Layout Figure 2 through Figure 7 illustrate the various layout silk screens for the BUF634ADEVM. 4 Figure 2. BUF634ADEVM Top Overlay Figure 3. BUF634ADEVM Top Solder Figure 4. BUF634ADEVM Top Layer Figure 5. BUF634ADEVM Bottom Layer BUF634AD Evaluation module SBOU221 – February 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Schematic, Layout, and Bill of Materials www.ti.com Figure 6. BUF634ADEVM Bottom Solder Figure 7. BUF634ADEVM Bottom Overlay SBOU221 – February 2019 Submit Documentation Feedback BUF634AD Evaluation module Copyright © 2019, Texas Instruments Incorporated 5 Schematic, Layout, and Bill of Materials 2.3 www.ti.com Bill of Materials Table 3 lists the bill of materials for the BUF634ADEVM. Table 3. Bill of Materials Designator 6 Qty Value Description Package Reference Part Number Manufacturer C5, C6 2 6.8µF CAP, TA, 6.8 uF, 50 V, +/- 10%, 0.3 ohm, SMD 7343-31 T495D685K050ATE300 Kemet C11, C12, C15, C16 4 1µF CAP, CERM, 1 uF, 50 V, +/- 10%, X5R, 0805 0805 C2012X5R1H105K125 AB TDK C13, C14, C17, C18 4 0.1µF CAP, CERM, 0.1 uF, 25 V, +80/-20%, Y5V, 0603 0603 C0603C104Z3VACTU Kemet C19, C21 2 0.01µF CAP, CERM, 0.01 uF, 100 V, +/- 10%, X7R, 0603 0603 06031C103KAT2A AVX H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead Screw NY PMS 440 0025 PH B&F Fastener Supply H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone J1, J2, J3, J4 4 Connector, End launch SMA, 50 ohm, SMT End Launch SMA 142-0701-801 Cinch Connectivity J5, J6, J7 3 Standard Banana Jack, Uninsulated Keystone_6095 6095 Keystone J8, J9 2 Power Jack, 2.1x5.5mm, R/A, TH Power Jack, 2.1x5.5mm, R/A, TH EJ508A Memory Protection Devices J10 1 RCA Jack, White, R/A, TH PC Mount Phono Jack-White, TH 970 Keystone J11 1 RCA Jack, Red, R/A, TH PC Mount Phono Jack-Red, TH 971 Keystone J12 1 Audio Jack, 3.5mm, Stereo, R/A, SMT Audio Jack SMD SJ-3523-SMT CUI Inc. L1, L2 2 Ferrite Bead, 80 ohm @ 100 MHz, 3 A, 1206 1206 HI1206N800R-10 Laird-Signal Integrity Products LBL1 1 Thermal Transfer Printable Labels, 0.650" W x 0.200" H - 10,000 per roll PCB Label 0.650 x 0.200 inch THT-14-423-10 Brady R7, R8 2 49.9Ω RES, 49.9, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 CRCW060349R9FKEA Vishay-Dale R11, R12, R13, R14, R15, R16, R19, R20 8 0Ω RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 CRCW06030000Z0EA Vishay-Dale TP1 1 Test Point, Miniature, Black, TH Black Miniature Testpoint 5001 Keystone U2, U3 2 High-Speed Buffer, D0008A (SOIC-8) D0008A BUF634AID Texas Instruments C1, C2, C3, C4 0 10pF CAP, CERM, 10 pF, 50 V, +/- 1%, C0G/NP0, 0603 0603 C0603C100F5GAC786 7 Kemet C7, C8 0 1µF CAP, CERM, 1 uF, 50 V, +/- 10%, X5R, 0805 0805 C2012X5R1H105K125 AB TDK C9, C10 0 0.1µF CAP, CERM, 0.1 uF, 25 V, +80/-20%, Y5V, 0603 0603 C0603C104Z3VACTU Kemet C20 0 0.01µF CAP, CERM, 0.01 uF, 100 V, +/- 10%, X7R, 0603 0603 06031C103KAT2A AVX R1, R4, R21, R22 0 49.9Ω RES, 49.9, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 CRCW060349R9FKEA Vishay-Dale R2, R3, R5, R6 0 1.0kΩ RES, 1.0 k, 5%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 CRCW06031K00JNEA Vishay-Dale R9, R10, R17, R18 0 0Ω RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 CRCW06030000Z0EA Vishay-Dale U1 0 High Performance Low Cost Rail-to-Rail Input/Output HV FET Op Amps, D0008A (SOIC8) D0008A OPA2810IDR Texas Instruments 80Ω BUF634AD Evaluation module SBOU221 – February 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated