C187EVK01/NOPB

User’s Guide SNLU102--May 2012 C187EVK01 User’s Guide CONTENTS 1. INTRODUCTION........................................................................................................ 2 2. SETUP ....................................................................................................................... 3 3. BOARD LAYOUT ...................................................................................................... 6 4. SCHEMATIC ............................................................................................................ 10 LIST OF FIGURES Figure 1: RFB Clock Strobe Settings............................................................................................................................3 Figure 2: Default Jumper Settings ................................................................................................................................4 Figure 3: LVDS Output Connections (OA-J3 and OB-J4) ............................................................................................4 Figure 4: LVCMOS Input Connections (INA-J5 and INB-J6)........................................................................................5 Figure 5: Top Assembly Layer ......................................................................................................................................7 Figure 6: Top Layer Routing .........................................................................................................................................8 Figure 7: Bottom Layer Routing ....................................................................................................................................9 Figure 8: C187EVK01 Schematic Page 1...................................................................................................................10 Figure 9: C187EVK01 Schematic Page 2...................................................................................................................12 Figure 10: C187EVK01 Schematic Page 3.................................................................................................................12 LIST OF TABLES Table 1: Device and Package Information....................................................................................................................2 Table 2: Device Configuration.......................................................................................................................................3 Table 3: C187EVK01 Bill of Materials.........................................................................................................................13 TRI-STATE is a registered trademark of Texas Instruments H SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 1 Introduction 1. Introduction The Texas Instruments C187EVK01 evaluation module (EVM) helps designers evaluate the performance of the DS90C187 Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer. The device operates off of a single 1.8V supply and supports input pixel clocks from 50 MHz to 185 MHz (Single In Dual Out) or 25 MHz to 105 MHz (Single/Dual In Single/Dual Out). The typical application, Single In Dual Out, is shown below. This EVM contains one Low Power 1.8V Dual Pixel FPD-Link (LVDS) Serializer (See Table 1). Table 1: Device and Package Information SERIALIZER U1 2 C187EVK01 User’s Guide IC DS90C187LF PACKAGE LFA92A SNLU102-May 2012 Submit Documentation Feedback Setup 2. Setup This section describes the jumpers and connectors on the EVK as well and how to properly connect, set up and use the C187EVK01. 2.1. Input/Output Connector Description JP1 – MODE1 is to be used in combination with JP2 (MODE0) to configure the DS90C187. Refer to Table 2. JP2 – MODE0 is to be used in combination with JP1 (MODE1) to configure the DS90C187. Refer to Table 2. Table 2: Device Configuration MODE1 0 0 1 1 MODE1 0 1 0 1 Configuration SISO – Single Pixel In Single Pixel Out SIDO – Single Pixel In Dual Pixel Out DIDO – Dual Pixel In Dual Pixel Out Reserved JP3 – RFB is the jumper that selects the clock edge that the input LVCMOS data will be sampled on. If RFB is logic HIGH, the input data is latched on the RISING EDGE of the pixel clock. If RFB is set to logic LOW, the input data is latched on the FALLING EDGE of the pixel clock. Falling Edge Data Strobe Rising Edge Data Strobe Figure 1: RFB Clock Strobe Settings JP4 – PDB is the jumper used to enable the Serializer. Power Down Bar (PDB) set to logic HIGH enables the device, while connecting this jumper to logic LOW will disable the device. JP5 – 18B is the jumper used to enable a power saving mode for 18-bit color applications. When this jumper is set to logic LOW, all data inputs will be sampled, serialized and driven out through the LVDS drivers to support 24-bit color applications or 28-bit generic data buses. If this jumper is set to logic HIGH, the device will enter a power saving mode that will power down the circuitry that feeds the 4th data LVDS driver and also the 8th data LVDS driver for dual pixel output configurations. In dual pixel outputs configurations the 4th data LVDS driver, OA_3+/-, and 8th data LVDS driver, OB_3+/- will be TRI-STATE®. JP6 – VODSEL is the jumper that controls the differential output voltage. When VODSEL is set to logic HIGH, the output launch amplitude of the LVDS drivers will be set to have a larger output swing. If this jumper is set to logic LOW, then the LVDS drivers will be configured to have a power saving smaller output swing. JP7 – LVDSSWAP is reserved for future use and should be tied LOW. H SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 3 Setup VDD GND Reserved for Future Use Falling Clock Edge MODE0: HIGH MODE1: LOW 24-Bit Low Enabled Operation VOD Single Pixel In Dual Pixel Out (SIDO) Figure 2: Default Jumper Settings J3, J4 – LVDS OUTPUTS are brought out to two 2 x10 bank of header pins. Outputs for channel A are brought out to J3 and outputs for channel B are brought out to J4. Note that each LVDS output is separated from adjacent LVDS signals by one ground pin. By default, 100 ohm termination resistors are soldered onto the EVM to allow for easy measuring and probing of the LVDS signals. If a cable is connected to J3 and/or J4, these termination resistors (R57, R58, R62, R63, R64 and/or R65, R66, R67, R68, R69) must be removed or the differential voltage swing will be reduced. Figure 3: LVDS Output Connections (OA-J3 and OB-J4) 4 C187EVK01 User’s Guide SNLU102-May 2012 Submit Documentation Feedback Setup J5, J6 – LVCMOS INPUTS for channel A are connected to the 2 x 30 bank of header pins, J5. LVCMOS inputs for channel B are connected to the 2 x 28 bank of header pins, J6. Note that each LVCMOS signal is paired with a ground signal. When attaching external test equipment or other hardware to this board it is important that there be sufficient ground connections to ensure good signal integrity for the input clock and data waveforms. 50 ohm terminations are provided for each LVCMOS input by default. On a normal PCB these types of terminations are not needed. These resistors are provided by default to improve signal quality for long trace lengths during evaluation. Figure 4: LVCMOS Input Connections (INA-J5 and INB-J6) J1 – VDD is the terminal where 1.8V power should be applied. J2 – GND is the terminal where ground should be applied. SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 5 Setup 2.2. System Setup The input power jack (J1) should receive a voltage within the range of 1.71 V to 1.89 V referenced to ground which should be applied at J2, with JP4 set to LOW. Once, power has been applied to the board, JP4 (PDB pin) can be set to logic HIGH. After setting the PDB pin to HIGH, 1.8V clock and data can be transmitted to the EVM. If a cable is connected to J3 and/or J4, the termination resistors (R57, R58, R62, R63, R64 and/or R65, R66, R67, R68, R69) should be removed. 2.3. Operation For proper operation of the DS90C187, JP1, JP2, JP3, JP4, JP5, JP6 and JP7 should be properly configured by using shorting blocks (jumpers); see Figure 3. JP1 and JP2 set to the desired device mode (SISO, SIDO or DIDO) JP3 to LOW for falling clock edge strobe or HIGH for rising clock edge strobe JP4 to HIGH, after power on JP5 to LOW for 24-bit color (28-bit data bus) or to HIGH for 18-bit color (21-bit data bus) JP6 to LOW for reduced VOD swing or HIGH for large VOD swing JP7 to LOW After applying power and setting JP4 to HIGH, clock and data can be sent to the DS90C187. When the clock signal is detected, the DS90C187 will power on and begin to transmit serialized LVDS data. 3. Board Layout Figure 5, Figure 6 and Figure 7 show the board layout for the C187EVK01 printed circuit board. The EVM offers jumpers to configure and power on/off the DS90C187. 50 ohm shunt terminations are populated by default. 100 ohm differential termination resistors are populated by default to allow for easy probing of the LVDS outputs at J3 and J4. 6 C187EVK01 User’s Guide SNLU102-May 2012 Submit Documentation Feedback Board Layout Figure 5: Top Assembly Layer H SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 7 Board Layout Figure 6: Top Layer Routing 8 C187EVK01 User’s Guide SNLU102-May 2012 Submit Documentation Feedback Board Layout Figure 7: Bottom Layer Routing SNLU102-May 2012 Submit Documentation Feedback C187EVK01 User’s Guide 9 2 GND 2 1 A52 93 OA_3OA_3+ OA_0+ OA_1- B30 OA_1+ A36 OA_2- B29 OA_2+ A35 OA_C- B28 OA_C+ A34 OA_3- B27 OA_3+ OA_1+ R62 100 0201 2 1 A37 OA_0+ R63 100 0201 OA_2+ OA_C+ 2 4 6 8 10 12 14 16 18 20 OA_0- VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD 1 2 3 VDD MODE1 GND MODE0 GND OA_1JP3 OA_2OA_C- RFB GND OA_3JP4 OA_3+ GND 2 1 OA_COA_C+ B31 1 2 3 JP2 J3 1 3 5 7 9 11 13 15 17 19 PDB GND JP5 R64 100 0201 1 OA_2+ A38 OA_0- 2 1 DAP GND A27 GND GND RSVD1 A15 A11 A12 RSVD VDD VDDP A13 GND VDDP VDD A51 A26 A14 VDD R58 100 0201 18B GND 2 JP6 IN_CLK R65 100 0201 OB_1OB_1+ OB_2OB_2+ OB_COB_C+ C187EVK01 User’s Guide OB_0+ A32 OB_1- B25 OB_1+ A31 OB_2- B24 OB_2+ A30 OB_C- B23 OB_C+ A28 OB_3- B21 OB_3+ J4 OB_0+ OB_1+ R67 100 0201 R68 100 0201 OB_2+ OB_C+ OB_3+ 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 OB_0OB_1OB_2OB_COB_3- GND R69 100 0201 N/C 1 OB_3+ B26 R66 100 0201 A39 LVDS SWAP LVDSSWAP A16 VODSEL A41 VODSEL 18B A29 18B PDB A40 PDB RFB OB_3- OB_02 1 OB_0+ A33 2 1 OB_0- LVDSSWAP GND 2 1 INB_0 INB_1 INB_2 INB_3 INB_4 INB_5 INB_6 INB_7 INB_8 INB_9 INB_10 INB_11 INB_12 INB_13 INB_14 INB_15 INB_16 INB_17 INB_21 INB_22 INB_23 INB_24 INB_25 INB_26 INB_27 VODSEL GND JP7 2 1 HS VS DE DS90C187 10 OA_2- A24 A42 A43 A44 A45 A46 A47 A48 A49 A50 A1 A2 A3 A4 A5 A7 A8 A9 A10 A17 A18 A19 A20 A21 A22 A23 OA_1+ RFB INB_0 INB_1 INB_2 INB_3 INB_4 INB_5 INB_6 INB_7 INB_8 INB_9 INB_10 INB_11 INB_12 INB_13 INB_14 INB_15 INB_16 INB_17 INB_21 INB_22 INB_23 INB_24 INB_25 INB_26 INB_27 OA_1- MODE0 B10 B11 B12 OA_0+ B20 INB_0 INB_1 INB_2 INB_3 INB_4 INB_5 INB_6 INB_7 INB_8 INB_9 INB_10 INB_11 INB_12 INB_13 INB_14 INB_15 INB_16 INB_17 INB_21 INB_22 INB_23 INB_24 INB_25 INB_26 INB_27 HS VS DE JP1 R57 100 0201 OA_0- MODE0 HS VS DE IN_CLK A6 INA_0 INA_1 INA_2 INA_3 INA_4 INA_5 INA_6 INA_7 INA_8 INA_9 INA_10 INA_11 INA_12 INA_13 INA_14 INA_15 INA_16 INA_17 INA_21 INA_22 INA_23 INA_24 INA_25 INA_26 INA_27 MODE1 IN_CLK B32 B33 B34 B35 B36 B37 B38 B39 B40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B13 B14 B15 B16 B17 B18 B19 A25 INA_0 INA_1 INA_2 INA_3 INA_4 INA_5 INA_6 INA_7 INA_8 INA_9 INA_10 INA_11 INA_12 INA_13 INA_14 INA_15 INA_16 INA_17 INA_21 INA_22 INA_23 INA_24 INA_25 INA_26 INA_27 INA_0 INA_1 INA_2 INA_3 INA_4 INA_5 INA_6 INA_7 INA_8 INA_9 INA_10 INA_11 INA_12 INA_13 INA_14 INA_15 INA_16 INA_17 INA_21 INA_22 INA_23 INA_24 INA_25 INA_26 INA_27 VDD U1 VDDTX Schematic MODE1 4. B22 VDDTX Schematic Figure 8: C187EVK01 Schematic Page 1 SNLU102-May 2012 Submit Documentation Feedback Schematic GND GND 1 201 R322 49.9ohm 1 201 R312 49.9ohm 1 201 R302 49.9ohm 1 201 R292 49.9ohm 1 201 R282 49.9ohm 1 201 R272 49.9ohm 1 201 R262 49.9ohm 1 201 R252 49.9ohm 1 201 R242 49.9ohm 1 201 R232 49.9ohm 1 201 R222 49.9ohm 1 201 R212 49.9ohm 1 201 R202 49.9ohm 1 201 R192 49.9ohm 1 201 R182 49.9ohm 1 201 R172 49.9ohm 1 201 R162 49.9ohm 1 201 R152 49.9ohm 1 201 R142 49.9ohm 1 201 R132 49.9ohm 1 201 R122 49.9ohm 1 201 R112 49.9ohm 1 201 R102 49.9ohm 1 201 R92 49.9ohm 1 201 R82 49.9ohm GND 1 201 R332 49.9ohm IN_CLK INA_0 INA_1 INA_2 INA_3 INA_4 INA_5 INA_6 INA_7 INA_8 INA_9 INA_10 INA_11 INA_12 INA_13 INA_14 INA_15 INA_16 INA_17 HS VS DE INA_21 INA_22 INA_23 INA_24 INA_25 INA_26 INA_27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 201 R72 49.9ohm 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 201 R62 49.9ohm 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 1 201 R562 49.9ohm 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 HEADER 30x2 J5 IN_CLK INA_0 INA_1 INA_2 INA_3 INA_4 INA_5 INA_6 INA_7 INA_8 INA_9 INA_10 INA_11 INA_12 INA_13 INA_14 INA_15 INA_16 INA_17 HS VS DE INA_21 INA_22 INA_23 INA_24 INA_25 INA_26 INA_27 GND INB_0 INB_1 INB_2 INB_3 INB_4 INB_5 INB_6 INB_7 INB_8 INB_9 INB_10 INB_11 INB_12 INB_13 INB_14 INB_15 INB_16 INB_17 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 SNLU102-May 2012 Submit Documentation Feedback 1 201 R382 49.9ohm 1 201 R372 49.9ohm 1 201 R362 49.9ohm 1 201 R352 49.9ohm 1 201 R612 49.9ohm 1 201 R602 49.9ohm 1 201 R592 49.9ohm 1 201 R552 49.9ohm 1 201 R542 49.9ohm 1 201 R532 49.9ohm 1 201 R522 49.9ohm 1 201 R512 49.9ohm 1 201 R502 49.9ohm 1 201 R492 49.9ohm 1 201 R482 49.9ohm 1 201 R472 49.9ohm 1 201 R462 49.9ohm 1 201 R452 49.9ohm 1 201 R442 49.9ohm 1 201 R432 49.9ohm 1 201 R422 49.9ohm 1 201 R412 49.9ohm 1 201 R402 49.9ohm 1 201 R392 49.9ohm GND INB_0 INB_1 INB_2 INB_3 INB_4 INB_5 INB_6 INB_7 INB_8 INB_9 INB_10 INB_11 INB_12 INB_13 INB_14 INB_15 INB_16 INB_17 INB_21 INB_22 INB_23 INB_24 INB_25 INB_26 INB_27 1 201 R342 49.9ohm 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 HEADER 28x2 J6 INB_21 INB_22 INB_23 INB_24 INB_25 INB_26 INB_27 GND C187EVK01 User’s Guide 11 Schematic VDD_b + 2 R1 1 0 Ohm,0402 C16 2 2 GND VDD C21 C24 C27 + C19 22uF 2 2 2 GND VDDP 1 2 R5 1 0 Ohm,0402 C29 1 VDD_b 2 0.01uF 0.1uF 0.1uF 0.1uF C36 0.1uF 1 C35 0.1uF 2 1 1 C34 0.1uF 2 1 C33 0.1uF 2 1 C32 0.1uF 2 1 2 GND 2 1 C20 1 2 R2 1 0 Ohm,0402 1 VDD_b VDD_b 1 BANANA C31 0.1uF C18 22uF + 0.01uF 0.1uF 2 GND 1 C17 0.1uF 2 1 2 J2 2.2uF 2 22uF VDDTX 1 C4 2 + 1 C5 1 + 1 C6 BANANA 1 VDD_b 1 1 1 1 J1 1 Figure 9: C187EVK01 Schematic Page 2 C30 + C28 22uF 2 2 2 0.01uF 0.1uF GND Figure 10: C187EVK01 Schematic Page 12 C187EVK01 User’s Guide SNLU102-May 2012 Submit Documentation Feedback Schematic Table 3: C187EVK01 Bill of Materials Quantity 1 1 1 3 5 3 6 7 2 2 1 1 3 Reference C4 C5 C6 C16,C20,C29 C17,C21,C24,C27,C30 C18,C19,C28 C31,C32,C33,C34,C35,C36 JP1,JP2,JP3,JP4,JP5,JP6,JP7 J1,J2 J3,J4 J5 J6 R1,R2,R5 R6,R7,R8,R9,R10,R11,R12,R13,R14,R 15,R16,R17,R18,R19,R20,R21,R22,R2 3,R24,R25,R26,R27,R28,R29,R30,R31, R32,R33,R34,R35,R36,R37,R38,R39,R 40,R41,R42,R43,R44,R45,R46,R47,R4 8,R49,R50,R51,R52,R53,R54,R55,R56, 54 R59,R60,R61 R57,R58,R62,R63,R64,R65,R66,R67,R 10 68,R69 1 U1 SNLU102-May 2012 Submit Documentation Feedback H Part 0.1uF 2.2uF 22uF 0.01uF 0.1uF 22uF 0.1uF 3-Pin Header BANANA 2X10-Pin Header HEADER 30x2 HEADER 28x2 0 Ohm,0402 Vendor KEMET KEMET nichicon KEMET Panasonic Kemet Murata AMP/Tyco Johnson 3M AMP/Tyco AMP/TYCO Panasonic Part Number C1206C104K5RACTU T491B225K020AT F931E226MNC C0603C103K1RACTU ECJ-1VB1E104K T494B226M016AT GCM155R71C104KA55D 87224-3 108-0740-001 N2520-6002RB 3-87215-0 3-87215-0 ERJ-2GEJ0R00X 49.9 ohm Panasonic ERJ-1GEF49R9C 100 ohm DS90C187 Susumu RR0306P-101-D Texas Instruments DS90C187LF C187EVK01 User’s Guide 13 FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general customer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. 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