CAPTIVATE-BSWP

Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 MSP430FR263x、 、MSP430FR253x 电容式触控感应混合信号微控制器 1 器件概述 1.1 特性 1 • CapTIvate ™技术 – 电容式触控 – 性能 – 四路同步快速电极扫描 – 支持点数高达 1024 的高分辨率滑块 – 接近感应 – 可靠性 – 提高了针对电力线、射频及其他环境噪声的抗 扰度 – 内置扩展频谱、自动调优、噪声滤除和消抖算 法 – 提供可靠的触控解决方案，具有 10V RMS 共 模噪声、4kV 电气快速瞬变以及 15kV 静电放 电，符合 IEC‑61000-4-6、IEC‑61000-4-4 和 IEC‑61000-4-2 标准 – 降低了射频辐射，简化了电气设计 – 支持金属触控和防水设计 – 灵活性 – 多达 16 个自电容式电极和 64 个互电容式电极 – 在同一设计中混合使用自电容式电极和互电容 式电极 – 支持多点触控功能 – 宽电容检测范围；0 至 300pF 宽电极范围 – 低功耗 – 四个传感器的触摸唤醒电流小于 5µA – 触摸唤醒状态机支持在 CPU 休眠过程中进行 电极扫描 – 用于环境补偿、滤波和阈值检测的硬件加速 – 易于使用 – CapTIvate 设计中心 PC GUI 允许工程师对电 容按钮进行实时设计和调试，无需编写代码 – 存储于 ROM 中的 CapTIvate 软件库为客户应 用提供充足的 FRAM • 嵌入式微控制器 – 16 位 RISC 架构 – 支持的时钟频率最高可达 16MHz – 3.6V 至 1.8V 的宽电源电压范围（最低电源电压 受限于 SVS 电平，请参阅 SVS 规格） • 优化的超低功耗模式 – 激活模式：126µA/MHz（典型值） – 待机模式：四个传感器的触摸唤醒电流小于 5µA – 采用 32768Hz 晶振的 LPM3.5 实时时钟 (RTC) 计数器：730nA（典型值） – 关断电流 (LPM4.5)：16nA（典型值） • 高性能模拟 – 8 通道 10 位模数转换器 (ADC) – 1.5V 的内部基准电压 – 采样与保持 200ksps • 增强型串行通信 – 两个增强型通用串行通信接口 (eUSCI_A) 支持 UART、IrDA 和 SPI – 一个 eUSCI (eUSCI_B) 支持 SPI 和 I2C • 智能数字外设 – 四个 16 位计时器 – 两个计时器，每个计时器具有三个捕捉/比较寄 存器 (Timer_A3) – 两个计时器，每个计时器具有两个捕捉/比较寄 存器 (Timer_A2) – 一个采用 CapTIvate 技术的 16 位计时器 – 一个仅用作计数器的 16 位 RTC – 16 位循环冗余校验 (CRC) • 低功耗铁电 RAM (FRAM) – 容量高达 15.5KB 的非易失性存储器 – 内置错误修正码 (ECC) – 可配置的写保护 – 对程序、常量和存储的统一存储 – 耐写次数达 1015 次 – 抗辐射和非磁性 – FRAM 与 SRAM 之比高达 4：1 1 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确 性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SLAS942 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 • 时钟系统 (CS) – 片上 32kHz RC 振荡器 (REFO) – 带有锁频环 (FLL) 的片上 16MHz 数控振荡器 (DCO) – 室温下的精度为 ±1%（具有片上基准） – 片上超低频 10kHz 振荡器 (VLO) – 片上高频调制振荡器 (MODOSC) – 外部 32kHz 晶振 (LFXT) – 可编程 MCLK 预分频器（1 至 128） – 通过可编程预分频器（1、2、4 或 8）从 MCLK 获得的 SMCLK • 通用输入/输出和引脚功能 – 共计 19 个 I/O（采用 TSSOP-32 封装） – 16 个中断引脚（P1 和 P2）可以将 MCU 从低功 耗模式下唤醒 • 开发工具和软件 – 开发工具 – MSP CapTIvate™ MCU 开发套件评估：与 CAPTIVATE-PGMR 编程器和电容式触控 MSP430FR2633 MCU 板 CAPTIVATE‑FR2633 配合使用 1.2 • • • • • • – 目标开发板 (MSP‑TS430RGE24A) – 易于使用的生态系统 – CapTIvate 设计中心 – 代码生成、可自定义 GUI、实时调优 • 系列成员（另请参阅 器件比较） – MSP430FR2633：15KB 程序 FRAM、512 字节 信息 FRAM、4KB RAM、多达 16 个自电容式传 感器或 64 个互电容式传感器 – MSP430FR2533：15KB 程序 FRAM、512 字节 信息 FRAM、2KB RAM、多达 16 个自电容式传 感器或 24 个互电容式传感器 – MSP430FR2632：8KB 程序 FRAM、512 字节 信息 FRAM、2KB RAM、多达 8 个自电容式传 感器或 16 个互电容式传感器 – MSP430FR2532：8KB 程序 FRAM、512 字节 信息 FRAM、1KB RAM、多达 8 个自电容式传 感器或 8 个互电容式传感器 • 封装选项 – 32 引脚：VQFN (RHB) – 32 引脚：TSSOP (DA) – 24 引脚：VQFN (RGE) – 24 引脚：DSBGA (YQW) 应用 电子智能锁、门键盘和读取器 车库门系统 入侵 HMI 键盘和控制面板 电动百叶窗 遥控器 个人电子产品 1.3 www.ti.com.cn • • • • • • 无线扬声器和耳机 手持式视频游戏控制器 A/V 接收器 白色家电 小型电器 园艺和电动工具 说明 MSP430FR263x 和 MSP430FR253x 是用于电容式触控检测的超低功耗 MSP430™ 微控制器，采用 CapTIvate™ 触控技术，适用于按钮、滑块、滚轮及接近传感 应用中的数字输入 D 类音频放大器。采用 CapTIvate 技术的 MSP430 MCU 提供市面上最高集成度和自主性的电容式触控解决方案，具有高可靠性和 抗噪能力以及最低功耗。TI 的电容式触控技术支持在同一设计方案中同时使用自电容式和互电容式电极，最 大限度地提高了灵活性。采用 CapTIvate 技术的 MSP430 MCU 可以穿透厚玻璃、塑料外壳、金属和木材， 在恶劣的环境（包括潮湿、油腻和脏污环境）中工作。 TI 电容式触控感应 MSP430 MCU 由一个由各种软、硬件资源组成的生态系统提供支持，并配套提供有参考 设计和代码示例，可帮助您快速开展设计。开发套件包括 MSP-CAPT-FR2633 CapTIvate 技术开发套件。 TI 还提供免费的软件，如 CapTIvate 设计中心，工程师可以在其中 借助 方便易用的 GUI 和 MSP430Ware™ 软件以及包括 CapTIvate 技术指南在内的综合性文档快速进行应用开发。 TI 的 MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相 结合，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术将 RAM 的低能耗快速写入、灵活 性和耐用性与闪存的非易失性相结合。 有关完整的模块说明，请参阅《MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南》。 2 器件概述 版权 © 2015–2019, Texas Instruments Incorporated MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 器件信息 (1) 器件型号 MSP430FR2633IRHB 封装 封装尺寸 (2) VQFN (32) 5mm x 5mm MSP430FR2533IRHB VQFN (32) 5mm × 5mm MSP430FR2633IDA TSSOP (32) 11mm × 6.2mm MSP430FR2533IDA TSSOP (32) 11mm × 6.2mm MSP430FR2632IRGE 超薄四方扁平无引线 (VQFN) (24) 4mm x 4mm MSP430FR2532IRGE 超薄四方扁平无引线 (VQFN) (24) 4mm x 4mm MSP430FR2633IYQW DSBGA (24) 2.29mm × 2.34mm MSP430FR2632IYQW DSBGA (24) 2.29mm × 2.34mm (1) (2) 要获得最新的产品、封装和订购信息，请参见封装选项附录（节 9），或者访问德州仪器 (TI) 网站 www.ti.com.cn。 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 9中）。 CAUTION 系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对 数据或代码存储器造成干扰。有关更多信息，请参阅《MSP430 系统级 ESD 注 意事项》。 版权 © 2015–2019, Texas Instruments Incorporated 器件概述 3 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 1.4 www.ti.com.cn 功能框图 图 1-1 给出了功能框图。 DVCC DVSS Power Management Module RST/NMI P1.x/P2.x P3.x I/O Ports P3 1×3 IOs 32-bit Hardware Multiplier I/O Ports P1, P2 2×8 IOs Interrupt and Wakeup PA 1×16 IOs 2×eUSCI_A eUSCI_B0 XOUT XIN LFXT ADC FRAM RAM Clock System Up to 8-ch single-ended 10 bit 200 ksps 15KB+512B 8KB+512B 4KB 2KB 2×TA 2×TA VREG MPY32 PB 1×3 IOs CapTIvate 16-channel 8-channel MAB 16-MHz CPU including 16 Registers MDB EEM CRC16 SYS TCK TMS TDI/TCLK TDO SBWTCK SBWTDIO JTAG Watchdog Timer_A3 3 CC Registers Timer_A2 2 CC Registers (UART, IrDA, SPI) 2 (SPI, I C) RTC Counter BAKMEM 16-bit Real-Time Clock 32-byte Backup Memory LPM3.5 Domain SBW • • • • • • 4 16-bit Cyclic Redundancy Check 图 1-1. 功能框图 MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为 4.7μF 至 10μF 和 0.1μF，精度为 ±5%。 VREG 是 CapTIvate 稳压器的去耦电容。所需去耦电容的建议值为 1µF，最大等效串联电阻 (ESR) ≤ 200mΩ。 P1 和 P2 特有引脚中断功能，可将 MCU 从所有低功耗模式 (LPM) 唤醒（包括 LPM3.5 和 LPM4）。 每个 Timer_A3 具有三个捕捉/比较寄存器。仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周 期时序和生成中断。 每个 Timer_A2 具有两个捕捉/比较寄存器。两个寄存器仅用于内部周期时序和生成中断。 在 LPM3 模式下，CapTIvate 可在其他外设停止工作的情况下继续工作。 器件概述 版权 © 2015–2019, Texas Instruments Incorporated MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 内容 1 器件概述 .................................................... 1 20 ............................................ ................................................. 6.3 Operating Modes .................................... 6.4 Interrupt Vector Addresses.......................... 6.5 Bootloader (BSL) .................................... 6.6 JTAG Standard Interface............................ 6.7 Spy-Bi-Wire Interface (SBW)........................ 6.8 FRAM................................................ 6.9 Memory Protection .................................. 6.10 Peripherals .......................................... 6.11 Input/Output Diagrams .............................. 6.12 Device Descriptors .................................. 6.13 Memory .............................................. 6.14 Identification ......................................... Applications, Implementation, and Layout........ 7.1 Device Connection and Layout Fundamentals ...... 20 7.2 77 Peripheral- and Interface-Specific Design Information .......................................... 80 7.3 CapTIvate Technology Evaluation .................. 83 1.1 特性 ................................................... 1 1.2 应用 ................................................... 2 1.3 说明 ................................................... 2 1.4 功能框图 .............................................. 4 2 3 修订历史记录............................................... 6 Device Comparison ..................................... 8 4 Terminal Configuration and Functions .............. 9 3.1 4.1 Pin Diagrams ......................................... 9 4.2 Pin Attributes ........................................ 13 4.3 Signal Descriptions .................................. 16 ..................................... 4.5 Buffer Types......................................... 4.6 Connection of Unused Pins ......................... Specifications ........................................... 5.1 Absolute Maximum Ratings ......................... 5.2 ESD Ratings ........................................ 5.3 Recommended Operating Conditions ............... 4.4 5 Pin Multiplexing 19 19 19 20 Active Mode Supply Current Into VCC Excluding External Current ..................................... 21 5.5 5.6 Active Mode Supply Current Per MHz .............. Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current.......................... Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current .... Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current .................... Typical Characteristics - Low-Power Mode Supply Currents ............................................. 5.8 5.9 7 Overview 6.2 CPU 20 5.4 5.7 6 Related Products ..................................... 8 6.1 8 21 21 22 23 24 5.10 Thermal Resistance Characteristics ................ 25 5.11 Timing and Switching Characteristics ............... 26 45 45 47 48 49 49 49 49 50 60 67 68 76 77 器件和文档支持 .......................................... 84 8.1 入门和后续步骤...................................... 84 8.2 器件命名规则 ........................................ 84 8.3 工具和软件 8.4 文档支持 ............................................. 87 8.5 相关链接 ............................................. 88 8.6 社区资源 ............................................. 88 8.7 商标.................................................. 88 8.8 静电放电警告 ........................................ 89 .......................................... ............................... 8.10 Glossary ............................................. 机械、封装和可订购信息................................ 8.9 9 45 Export Control Notice 85 89 89 90 Detailed Description ................................... 45 版权 © 2015–2019, Texas Instruments Incorporated 内容 5 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 2 修订历史记录 注：之前版本的页码可能与当前版本有所不同。 从修订版本 D 更改为修订版本 E Changes from August 20, 2019 to December 9, 2019 • • • • • • • • • • Page Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating Conditions ............................................................................. Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating Conditions ............................................................................. Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating Conditions ............................................................................................ Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4, XT1 Crystal Oscillator (Low Frequency) ........................................................................................................ Added the t(int) parameter in Table 5-10, Digital Inputs ........................................................................ Added the tTA,cap parameter in Table 5-13, Timer_A ............................................................................ Corrected the test conditions for the RI,MUX parameter in Table 5-20, ADC, Power Supply and Input Range Conditions ............................................................................................................................ Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing Parameters.................... Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical Characteristics ........................................................................................................... Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-22, Device Descriptors ..................... 20 20 20 28 32 34 40 40 42 67 从修订版本 C 更改为修订版本 D Changes from August 29, 2018 to August 19, 2019 • • • • • • • • • • • • • • • • • • • 6 Page 更新了节 1.1特性...................................................................................................................... 1 在 节 1.1，特性 中添加了“目标开发板”信息 ....................................................................................... 2 Changed "fCONVER = 2 MHz" to "fCONVER = 4 MHz" in the note that begins "CapTIvate technology works in LPM3 with 64 mutual-capacitance buttons" on Section 5.7, Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current .................................................................................................. 22 Added the tTA,cap parameter in Table 5-13, Timer_A ............................................................................ 34 Changed the parameter symbol from RI to RI,MUX in Table 5-20 , ADC, Power Supply and Input Range Conditions . 40 Added RI,Misc TYP value of 34 kΩ in Table 5-20 , ADC, Power Supply and Input Range Conditions ................... 40 Added formula for RI calculation in Table 5-21 , ADC, 10-Bit Timing Parameters ......................................... 40 Removed the description of "±3°C" in table note that starts "The device descriptor structure ..." of Table 5-22, ADC, 10-Bit Linearity Parameters ................................................................................................. 41 Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical Characteristics ........................................................................................................... 42 Added test condition for CELECTRODE in Table 5-23 , CapTIvate Electrical Characteristics ................................. 42 Changed the symbol and description of the DCCAPCLK parameter in Table 5-23, CapTIvate Electrical Characteristics ...................................................................................................................... 42 Moved the SNR parameter to Table 5-24, CapTIvate Signal-to-Noise Ratio Characteristics ............................ 42 Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8, Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2), in the description that starts "The interconnection of Timer0_A3 and ..." .................................... 56 Corrected the ADCINCHx column heading in Table 6-15, ADC Channel Connections ................................... 58 Corrected the ADCSHSx column heading in Table 6-16, ADC Trigger Signal Connections .............................. 58 Added P1SELC information in Table 6-32, Port P1, P2 Registers (Base Address: 0200h) .............................. 71 Added P2SELC information in Table 6-32, Port P1, P2 Registers (Base Address: 0200h) .............................. 71 Added P3SELC information in Table 6-33, Port P3 Registers (Base Address: 0220h) ................................... 71 Updated Section 7.2.2, CapTIvate Peripheral .................................................................................. 81 修订历史记录 版权 © 2015–2019, Texas Instruments Incorporated MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 从修订版本 B 更改为修订版本 C Changes from June 9, 2017 to August 28, 2018 • • • • • • • • • • • Page 删除了节 1.1，特性 中“接近感应”项的“30cm” .................................................................................... 1 Updated Section 3.1, Related Products ........................................................................................... 8 Corrected package type in VQFN row (changed from QFN to VQFN) in Table 4-2, Signal Descriptions .............. 18 Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2, ESD Ratings .................................. 20 Added note to VSVSH- and VSVSH+ parameters in Table 5-2, PMM, SVS and BOR .......................................... 26 Added the tTA,cap parameter in Table 5-13, Timer_A ............................................................................ 34 Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical Characteristics ........................................................................................................... 42 Added the SNR parameter in Table 5-23, CapTIvate Electrical Characteristics ........................................... 42 Moved "FRAM access time error" to "System Reset" row and added ACCTEIFG to interrupt flag column in Table 6-2, Interrupt Sources, Flags, and Vectors ............................................................................... 47 Corrected the offset for P2SEL1 in Table 6-32, Port P1, P2 Registers (Base Address: 0200h) ......................... 71 更新了节 8.2器件命名规则 中的文本和图 ........................................................................................ 84 从修订版本 A 更改为修订版本 B Changes from December 10, 2015 to June 8, 2017 • • • • • • • • • • • • • • • • • • • • • • Page 更改了 “特性” 列表的组织结构 ...................................................................................................... 1 在节 1.1，特性 中的“封装选项”列表中添加了 DSBGA (YQW) 封装 ............................................................ 2 更新了节 1.2，应用 中的列表 ....................................................................................................... 2 更新节 1.3，说明...................................................................................................................... 2 在器件信息 表（位于节 1.3“说明”中）中添加了 DSBGA (YQW) 封装选项 .................................................... 3 Added MSP430FR2633IYQW and MSP430FR2632IYQW to Table 3-1, Device Comparison ............................. 8 Added Section 3.1, Related Products .............................................................................................. 8 Added DSBGA (YQW) pinout ..................................................................................................... 12 Added DSBGA (YQW) package to Table 4-1, Pin Attributes .................................................................. 13 Added DSBGA (YQW) package to Table 4-2, Signal Descriptions ........................................................... 16 Added row for VQFN thermal pad in Table 4-2, Signal Descriptions......................................................... 18 Removed FRAM reflow note ....................................................................................................... 20 Updated the notes on ILPM3, CapTIvate, 16 buttons and ILPM3, CapTIvate, 64 buttons in Section 5.7, Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current ......................................................... 22 Added DSBGA (YQW) package and changed notes for Section 5.10, Thermal Resistance Characteristics ........... 25 Added the tTA,cap parameter in Table 5-13, Timer_A ............................................................................ 34 Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 521, ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division) ........................................ 40 Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical Characteristics ........................................................................................................... 42 Add description of blank device detection ....................................................................................... 48 Changed the paragraph that starts "Quickly switching digital signals and ..." in Section 7.2.1.2, Design Requirements ........................................................................................................................ 80 更新了图 8-1，器件命名规则 ...................................................................................................... 84 将先前的开发工具支持 部分替换为节 8.3“工具和软件” ......................................................................... 85 更新了节 8.4“文档支持”的格式和内容 ............................................................................................. 87 从初始发行版更改为修订版本 A Changes from November 6, 2015 to December 9, 2015 • • • • Page 将文档状态从“产品预览”更改为“生产数据” ......................................................................................... 1 更改了开头为“提供可靠的触控解决方案...”的列表项.............................................................................. 1 向开头为“宽电源电压范围...”的列表项添加了说明 ................................................................................ 1 In the note that starts "Low-power mode 3, VLO, excludes SVS test conditions...", changed "fXT1 = 0 Hz" to "fXT1 = 32768 Hz" .................................................................................................................... 22 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 修订历史记录 7 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 • • • • • • 8 www.ti.com.cn Added note that starts "The VLO clock frequency is reduced by 15%...".................................................... Added the tTA,cap parameter in Table 5-13, Timer_A ............................................................................ Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical Characteristics ........................................................................................................... Added note to "Clock" in Table 6-1, Operating Modes ......................................................................... Added note that starts "XT1CLK and VLOCLK can be active during LPM4..." ............................................. Corrected description in Section 6.10.10, Backup Memory (BKMEM) ....................................................... 修订历史记录 31 34 42 46 46 57 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 3 Device Comparison Table 3-1 summarizes the features of the available family members. Table 3-1. Device Comparison (1) (2) PROGRAM FRAM + INFORMATION FRAM (BYTES) SRAM (BYTES) TA0 TO TA3 eUSCI_A MSP430FR2633IRHB 15360 + 512 4096 MSP430FR2533IRHB 15360 + 512 MSP430FR2633IDA eUSCI_B 10-BIT ADC CHANNELS CapTIvate™ CHANNELS GPIOs PACKAGE TYPE up to 2 1 8 16 (4) 19 32 RHB (VQFN) up to 2 up to 2 1 8 16 (4) 19 32 RHB (VQFN) 2, 3 × CCR (3) 2, 2 × CCR up to 2 up to 2 1 8 16 (4) 19 32 DA (TSSOP) 2048 2, 3 × CCR (3) 2, 2 × CCR up to 2 up to 2 1 8 16 (4) 19 32 DA (TSSOP) 8192 + 512 2048 2, 3 × CCR (3) 2, 2 × CCR up to 2 1 1 8 8 (5) 15 24 RGE (VQFN) MSP430FR2532IRGE 8192 + 512 1024 2, 3 × CCR (3) 2, 2 × CCR up to 2 1 1 8 8 (5) 15 24 RGE (VQFN) MSP430FR2633IYQW 15360 + 512 4096 2, 3 × CCR (3) 2, 2 × CCR up to 2 1 1 8 8 (6) 17 24 YQW (DSBGA) up to 2 1 1 8 8 (6) 17 24 YQW (DSBGA) DEVICE UART SPI 2, 3 × CCR (3) 2, 2 × CCR up to 2 2048 2, 3 × CCR (3) 2, 2 × CCR 15360 + 512 4096 MSP430FR2533IDA 15360 + 512 MSP430FR2632IRGE (3) MSP430FR2632IYQW (1) (2) (3) (4) (5) (6) 3.1 8192 + 512 2048 2, 3 × CCR 2, 2 × CCR For the most current package and ordering information, see the Package Option Addendum in 节 9, or see the TI website at www.ti.com Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs. Eight dedicated CapTIvate channels are included. Four dedicated CapTIvate channels are included. Two dedicated CapTIvate channels are included. Related Products For information about other devices in this family of products or related products, see the following links. TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous future Products for MSP430 ultra-low-power sensing & measurement MCUs One platform. One ecosystem. Endless possibilities. Companion products for MSP430FR2633 Review products that are frequently purchased or used with this product. Reference designs for MSP430FR2633 Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors Device Comparison Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 9 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 4 Terminal Configuration and Functions 4.1 Pin Diagrams P2.7/CAP3.0 P3.2/CAP3.2 CAP3.1 CAP3.3 P2.1/XIN P2.0/XOUT DVSS DVCC Figure 4-1 shows the pinout for the 32-pin RHB package. RST/NMI/SBWTDIO 1 26 25 24 CAP2.3 TEST/SBWTCK 2 23 CAP2.2 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ 3 22 CAP2.1 P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 4 21 CAP2.0 P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 5 20 VREG P2.6/UCA1TXD/UCA1SIMO/CAP1.3 P2.5/UCA1RXD/UCA1SOMI/CAP1.2 32 31 30 29 28 27 MSP430FR2633IRHB MSP430FR2533IRHB P1.7/UCA0STE/SMCLK/TDO/A7 6 19 P1.0/UCB0STE/TA0CLK/A0/Veref+ 7 18 P1.1/UCB0CLK/TA0.1/A1 8 P2.4/UCA1CLK/CAP1.1 P3.1/UCA1STE/CAP1.0 CAP0.3 P2.3/CAP0.2 CAP0.1 P3.0/CAP0.0 P2.2/SYNC/ACLK 17 10 11 12 13 14 15 16 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- 9 Figure 4-1. 32-Pin RHB Package (Top View) 10 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Figure 4-2 shows the pinout for the 32-pin DA package. P2.0/XOUT 1 32 CAP3.3 P2.1/XIN 2 31 P3.2/CAP3.2 DVSS 3 30 CAP3.1 DVCC 4 29 P2.7/CAP3.0 RST/NMI/SBWTDIO 5 28 CAP2.3 TEST/SBWTCK 6 27 CAP2.2 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ 7 26 CAP2.1 P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 8 25 CAP2.0 MSP430FR2633IDA MSP430FR2533IDA P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 9 24 VREG P1.7/UCA0STE/SMCLK/TDO/A7 10 23 P2.6/UCA1TXD/UCA1SIMO/CAP1.3 P1.0/UCB0STE/TA0CLK/A0/Veref+ 11 22 P2.5/UCA1RXD/UCA1SOMI/CAP1.2 P1.1/UCB0CLK/TA0.1/A1 12 21 P2.4/UCA1CLK/CAP1.1 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- 13 20 P3.1/UCA1STE/CAP1.0 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 14 19 CAP0.3 P2.2/SYNC/ACLK 15 18 P2.3/CAP0.2 P3.0/CAP0.0 16 17 CAP0.1 Figure 4-2. 32-Pin DA Package (Top View) Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 11 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn CAP3.1 P2.7/CAP3.0 P2.0/XOUT DVSS P2.1/XIN DVCC Figure 4-3 shows the pinout for the 24-pin RGE package. 24 23 22 21 20 19 RST/NMI/SBWTDIO 1 18 CAP2.1 TEST/SBWTCK 2 17 CAP2.0 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ 3 16 VREG P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 4 15 P2.6/UCA1TXD/UCA1SIMO/CAP1.3 P1.6/UCA0CLK/TA1CLK/TDI/TCLKA6 5 14 P2.5/UCA1RXD/UCA1SOMI/CAP1.2 P1.7/UCA0STE/SMCLK/TDO/A7 6 13 CAP0.3 P1.1/UCB0CLK/TA0.1/A1 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- 10 11 12 P2.3/CAP0.2 9 P2.2/SYNC/ACLK 8 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 7 P1.0/UCB0STE/TA0CLK/A0/Veref+ MSP430FR2632IRGE MSP430FR2532IRGE Figure 4-3. 24-Pin RGE Package (Top View) 12 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Figure 4-4 shows the top view of the YQW package, and Figure 4-5 shows the bottom (ball-side) view. Top View SIGNAL NAME PIN NO. E5 D5 D C5 E4 D4 C4 E3 E2 D2 D3 E1 D1 C2 C3 B5 B4 B3 B2 A5 A4 A3 A2 B1 SIGNAL NAME PIN NO. A1 P1.1/UCB0CLK/TA0.1/A1 C4 CAP2.0 A2 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 C5 VREG A3 P2.2/SYNC/ACLK D1 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ A4 P3.0/CAP0.0 D2 TEST/SBWTCK A5 P2.3/CAP0.2 D3 DVSS B1 P1.0/UCB0STE/TA0CLK/A0/Veref+ D4 P3.2/CAP3.2 B2 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- D5 CAP2.2 B3 P1.7/UCA0STE/SMCLK/TDO/A7 E1 RST/NMI/SBWTDIO B4 P2.5/UCA1RXD/CAP1.2 E2 DVCC B5 P2.6/UCA1TXD/CAP1.3 E3 P2.1/XIN C2 P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 E4 P2.0/XOUT C3 P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 E5 P2.7/CAP3.0 A1 E Figure 4-4. 24-Pin YQW Package (Top View) Ball-SIde View SIGNAL NAME PIN NO. E1 E2 E3 E4 E5 D1 D2 D3 D4 D5 C2 D B1 A1 B2 A2 C3 B3 A3 C4 B4 A4 C5 B5 A5 SIGNAL NAME PIN NO. A1 P1.1/UCB0CLK/TA0.1/A1 C4 CAP2.0 A2 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 C5 VREG A3 P2.2/SYNC/ACLK D1 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ A4 P3.0/CAP0.0 D2 TEST/SBWTCK A5 P2.3/CAP0.2 D3 DVSS B1 P1.0/UCB0STE/TA0CLK/A0/Veref+ D4 P3.2/CAP3.2 B2 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- D5 CAP2.2 B3 P1.7/UCA0STE/SMCLK/TDO/A7 E1 RST/NMI/SBWTDIO B4 P2.5/UCA1RXD/CAP1.2 E2 DVCC B5 P2.6/UCA1TXD/CAP1.3 E3 P2.1/XIN C2 P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 E4 P2.0/XOUT C3 P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 E5 P2.7/CAP3.0 E Figure 4-5. 24-Pin YQW Package (Bottom View) Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 13 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 4.2 www.ti.com.cn Pin Attributes Table 4-1 lists the attributes of all pins. Table 4-1. Pin Attributes PIN NUMBER RHB DA RGE SIGNAL NAME (1) (2) YQW RST (RD) 1 2 3 4 5 6 5 6 7 8 9 10 1 2 3 4 5 6 E1 D2 D1 C2 C3 B3 NMI (1) (2) (3) (4) (5) (6) 14 11 7 B1 BUFFER TYPE (4) POWER SOURCE (5) RESET STATE AFTER BOR (6) I LVCMOS DVCC OFF – I LVCMOS DVCC SBWTDIO I/O LVCMOS DVCC – TEST (RD) I LVCMOS DVCC OFF SBWTCK I LVCMOS DVCC – P1.4 (RD) I/O LVCMOS DVCC OFF UCA0TXD O LVCMOS DVCC – UCA0SIMO I/O LVCMOS DVCC – TA1.2 I/O LVCMOS DVCC – TCK I LVCMOS DVCC – A4 I Analog DVCC – VREF+ O Power DVCC – P1.5 (RD) I/O LVCMOS DVCC OFF UCA0RXD I LVCMOS DVCC – UCA0SOMI I/O LVCMOS DVCC – TA1.1 I/O LVCMOS DVCC – TMS I LVCMOS DVCC – A5 I Analog DVCC – P1.6 (RD) I/O LVCMOS DVCC OFF UCA0CLK I/O LVCMOS DVCC – TA1CLK I LVCMOS DVCC – TDI I LVCMOS DVCC – TCLK I LVCMOS DVCC – A6 I Analog DVCC – P1.7 (RD) I/O LVCMOS DVCC OFF UCA0STE I/O LVCMOS DVCC – SMCLK O LVCMOS DVCC – TDO O LVCMOS DVCC – A7 7 SIGNAL TYPE (3) I Analog DVCC – P1.0 (RD) I/O LVCMOS DVCC OFF UCB0STE I/O LVCMOS DVCC – TA0CLK I LVCMOS DVCC – A0 I Analog DVCC – Veref+ I Power DVCC – Signals names with (RD) denote the reset default pin name. To determine the pin mux encodings for each pin, see Section 6.11, Input/Output Diagrams. Signal Types: I = Input, O = Output, I/O = Input or Output Buffer Types: LVCMOS, Analog, or Power (see Table 4-3) The power source shown in this table is the I/O power source, which may differ from the module power source. Reset States: OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled N/A = Not applicable Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 4-1. Pin Attributes (continued) PIN NUMBER RHB 8 DA 12 RGE 8 SIGNAL NAME (1) SIGNAL TYPE (3) BUFFER TYPE (4) POWER SOURCE (5) RESET STATE AFTER BOR (6) P1.1 (RD) I/O LVCMOS DVCC OFF UCB0CLK I/O LVCMOS DVCC – TA0.1 I/O LVCMOS DVCC – (2) YQW A1 A1 9 10 13 14 9 10 B2 A2 I Analog DVCC – P1.2 (RD) I/O LVCMOS DVCC OFF UCB0SIMO I/O LVCMOS DVCC – UCB0SDA I/O LVCMOS DVCC – TA0.2 I/O LVCMOS DVCC – A2 I Analog DVCC – Veref- I Power DVCC – P1.3 (RD) I/O LVCMOS DVCC OFF UCB0SOMI I/O LVCMOS DVCC – UCB0SCL I/O LVCMOS DVCC – MCLK O LVCMOS DVCC – A3 I Analog DVCC – I/O LVCMOS DVCC OFF SYNC I LVCMOS DVCC – ACLK O LVCMOS DVCC – P3.0 (RD) I/O LVCMOS DVCC OFF CAP0.0 I/O Analog VREG – CAP0.1 I/O Analog VREG OFF P2.3 (RD) I/O LVCMOS DVCC OFF CAP0.2 I/O Analog VREG – CAP0.3 I/O Analog VREG OFF P3.1 (RD) I/O LVCMOS DVCC OFF UCA1STE I/O LVCMOS DVCC – CAP1.0 I/O Analog VREG – P2.4 (RD) I/O LVCMOS DVCC OFF UCA1CLK I/O LVCMOS DVCC – CAP1.1 I/O Analog VREG – P2.5 (RD) I/O LVCMOS DVCC OFF UCA1RXD I LVCMOS DVCC – UCA1SOMI I/O LVCMOS DVCC – CAP1.2 I/O Analog VREG – P2.6 (RD) I/O LVCMOS DVCC OFF UCA1TXD O LVCMOS DVCC – UCA1SIMO I/O LVCMOS DVCC – CAP1.3 I/O Analog VREG – P Power VREG N/A P2.2 (RD) 11 15 11 A3 12 16 – A4 13 17 – – 14 18 12 A5 15 19 13 – 16 17 18 19 20 21 22 23 – – 14 15 – – B4 B5 20 24 16 C5 VREG 21 25 17 C4 CAP2.0 I/O Analog VREG OFF 22 26 18 – CAP2.1 I/O Analog VREG OFF 23 27 – D5 CAP2.2 I/O Analog VREG OFF 24 28 – – CAP2.3 I/O Analog VREG OFF 25 29 19 E5 P2.7 (RD) I/O LVCMOS DVCC OFF CAP3.0 I/O Analog VREG – 26 30 20 – CAP3.1 I/O Analog VREG OFF Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 15 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 4-1. Pin Attributes (continued) PIN NUMBER 16 SIGNAL NAME (1) RHB DA RGE YQW 27 31 – D4 28 32 – – 29 1 21 E4 SIGNAL TYPE (3) BUFFER TYPE (4) POWER SOURCE (5) RESET STATE AFTER BOR (6) P3.2 (RD) I/O LVCMOS DVCC OFF CAP3.2 I/O Analog VREG – CAP3.3 I/O Analog VREG OFF P2.0 (RD) I/O LVCMOS DVCC OFF XOUT O LVCMOS DVCC – P2.1 (RD) I/O LVCMOS DVCC OFF (2) 30 2 22 E3 XIN I LVCMOS DVCC – 31 3 23 D3 DVSS P Power DVCC N/A 32 4 24 E2 DVCC P Power DVCC N/A Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn 4.3 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Signal Descriptions Table 4-2 describes the signals for all device variants and package options. Table 4-2. Signal Descriptions FUNCTION ADC CapTIvate Clock Debug (1) SIGNAL NAME PIN NUMBER RGE YQW PIN TYPE (1) DESCRIPTION RHB DA A0 7 11 7 B1 I Analog input A0 A1 8 12 8 A1 I Analog input A1 A2 9 13 9 B2 I Analog input A2 A3 10 14 10 A2 I Analog input A3 A4 3 7 3 D1 I Analog input A4 A5 4 8 4 C2 I Analog input A5 A6 5 9 5 C3 I Analog input A6 A7 6 10 6 B3 I Analog input A7 Veref+ 7 11 7 B1 I ADC positive reference Veref- 9 13 9 B2 I ADC negative reference CAP0.0 12 16 – A4 I/O CapTIvate channel CAP0.1 13 17 – – I/O CapTIvate channel CAP0.2 14 18 12 A5 I/O CapTIvate channel CAP0.3 15 19 13 – I/O CapTIvate channel CAP1.0 16 20 – – I/O CapTIvate channel CAP1.1 17 21 – – I/O CapTIvate channel CAP1.2 18 22 14 B4 I/O CapTIvate channel CAP1.3 19 23 15 B5 I/O CapTIvate channel CAP2.0 21 25 17 C4 I/O CapTIvate channel CAP2.1 22 26 18 – I/O CapTIvate channel CAP2.2 23 27 – D5 I/O CapTIvate channel CAP2.3 24 28 – – I/O CapTIvate channel CAP3.0 25 29 19 E5 I/O CapTIvate channel CAP3.1 26 30 20 – I/O CapTIvate channel CAP3.2 27 31 – D4 I/O CapTIvate channel CAP3.3 28 32 – – I/O CapTIvate channel SYNC 11 15 11 A3 I CapTIvate synchronous trigger input for processing and conversion ACLK 11 15 11 A3 O ACLK output MCLK 10 14 10 A2 O MCLK output SMCLK 6 10 6 B3 O SMCLK output XIN 30 2 22 E3 I Input terminal for crystal oscillator XOUT 29 1 21 E4 O Output terminal for crystal oscillator SBWTCK 2 6 2 D2 I Spy-Bi-Wire input clock SBWTDIO 1 5 1 E1 I/O TCK 3 7 3 D1 I Test clock TCLK 5 9 5 C3 I Test clock input TDI 5 9 5 C3 I Test data input TDO 6 10 6 B3 O Test data output TEST 2 6 2 D2 I Test Mode pin – selected digital I/O on JTAG pins TMS 4 8 4 C2 I Test mode select Spy-Bi-Wire data input/output Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 17 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 4-2. Signal Descriptions (continued) FUNCTION GPIO I2C Power SPI System (2) 18 SIGNAL NAME PIN NUMBER RGE YQW PIN TYPE (1) DESCRIPTION RHB DA P1.0 7 11 7 B1 I/O General-purpose I/O P1.1 8 12 8 A1 I/O General-purpose I/O P1.2 9 13 9 B2 I/O General-purpose I/O P1.3 10 14 10 A2 I/O General-purpose I/O P1.4 3 7 3 D1 I/O General-purpose I/O (2) P1.5 4 8 4 C2 I/O General-purpose I/O (2) P1.6 5 9 5 C3 I/O General-purpose I/O (2) P1.7 6 10 6 B3 I/O General-purpose I/O (2) P2.0 29 1 21 E4 I/O General-purpose I/O P2.1 30 2 22 E3 I/O General-purpose I/O P2.2 11 15 11 A3 I/O General-purpose I/O P2.3 14 18 12 A5 I/O General-purpose I/O P2.4 17 21 – – I/O General-purpose I/O P2.5 18 22 14 B4 I/O General-purpose I/O P2.6 19 23 15 B5 I/O General-purpose I/O P2.7 25 29 19 E5 I/O General-purpose I/O P3.0 12 16 – A4 I/O General-purpose I/O P3.1 16 20 – – I/O General-purpose I/O P3.2 27 31 – D4 I/O General-purpose I/O UCB0SCL 10 14 10 A2 I/O eUSCI_B0 I2C clock UCB0SDA 9 13 9 B2 I/O eUSCI_B0 I2C data DVCC 32 4 24 E2 P Power supply DVSS 31 3 23 D3 P Power ground VREF+ 3 7 3 D1 P Output of positive reference voltage with ground as reference VREG 20 24 16 C5 O CapTIvate regulator external decoupling capacitor UCA0CLK 5 9 5 C3 I/O eUSCI_A0 SPI clock input/output UCA0SIMO 3 7 3 D1 I/O eUSCI_A0 SPI slave in/master out UCA0SOMI 4 8 4 C2 I/O eUSCI_A0 SPI slave out/master in UCA0STE 6 10 6 B3 I/O eUSCI_A0 SPI slave transmit enable UCA1CLK 17 21 – – I/O eUSCI_A1 SPI clock input/output UCA1SIMO 19 23 15 B5 I/O eUSCI_A1 SPI slave in/master out UCA1SOMI 18 22 14 B4 I/O eUSCI_A1 SPI slave out/master in UCA1STE 16 20 – – I/O eUSCI_A1 SPI slave transmit enable UCB0CLK 8 12 8 A1 I/O eUSCI_B0 clock input/output UCB0SIMO 9 13 9 B2 I/O eUSCI_B0 SPI slave in/master out UCB0SOMI 10 14 10 A2 I/O eUSCI_B0 SPI slave out/master in UCB0STE 7 11 7 B1 I/O eUSCI_B0 slave transmit enable NMI 1 5 1 E1 I Nonmaskable interrupt input RST 1 5 1 E1 I Active-low reset input Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions. Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 4-2. Signal Descriptions (continued) FUNCTION Timer_A UART VQFN Pad SIGNAL NAME PIN NUMBER DESCRIPTION DA TA0.1 8 12 8 A1 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs TA0.2 9 13 9 B2 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs TA0CLK 7 11 7 B1 I TA1.1 4 8 4 C2 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs TA1.2 3 7 3 D1 I/O Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs TA1CLK 5 9 5 C3 I Timer clock input TACLK for TA1 UCA0RXD 4 8 4 C2 I eUSCI_A0 UART receive data UCA0TXD 3 7 3 D1 O eUSCI_A0 UART transmit data UCA1RXD 18 22 14 B4 I eUSCI_A1 UART receive data UCA1TXD 19 23 15 B5 O eUSCI_A1 UART transmit data Pad N/A Pad N/A VQFN thermal pad RGE YQW PIN TYPE (1) RHB Timer clock input TACLK for TA0 VQFN package exposed thermal pad. TI recommends connecting to VSS. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 19 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 4.4 www.ti.com.cn Pin Multiplexing Pin multiplexing for these MCUs is controlled by both register settings and operating modes (for example, if the MCU is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 6.11. 4.5 Buffer Types Table 4-3 defines the pin buffer types that are listed in Table 4-1. Table 4-3. Buffer Types NOMINAL VOLTAGE HYSTERESIS PU OR PD NOMINAL PU OR PD STRENGTH (µA) OUTPUT DRIVE STRENGTH (mA) LVCMOS 3.0 V Y (1) Programmable See Section 5.11.4 See Section 5.11.4 Analog 3.0 V N N/A N/A N/A See analog modules in Section 5 for details. Power (DVCC) 3.0 V N N/A N/A N/A SVS enables hysteresis on DVCC. Power (AVCC) 3.0 V N N/A N/A N/A BUFFER TYPE (STANDARD) (1) OTHER CHARACTERISTICS Only for input pins. 4.6 Connection of Unused Pins Table 4-4 lists the correct termination of unused pins. Table 4-4. Connection of Unused Pins (1) PIN POTENTIAL COMMENT Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1) RST/NMI DVCC 47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown (2) TEST Open This pin always has an internal pulldown enabled. CAP2.x, CAPx.1, CAPx.3 Open These pins have internal pullup and pulldown resistors, and high impedance is their default setting. (1) (2) 20 Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection guidelines. The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like FET interfaces or GANG programmers. Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5 Specifications Absolute Maximum Ratings (1) 5.1 over operating free-air temperature range (unless otherwise noted) Voltage applied at DVCC pin to VSS Voltage applied to any dedicated CapTIvate pin or pin in CapTIvate mode Voltage applied to any other pin (2) (3) MIN MAX –0.3 4.1 V –0.3 VREG V –0.3 VCC + 0.3 (4.1 V Max) V Diode current at any device pin Maximum junction temperature, TJ Storage temperature, Tstg (4) (1) (2) (3) (4) –40 UNIT ±2 mA 85 °C 125 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This applies to dedicated CapTIvate I/Os only or I/Os worked in CapTIvate mode. All voltages referenced to VSS. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22‑C101 (2) Recommended Operating Conditions MIN VCC Supply voltage applied at DVCC pin (1) (2) (3) (4) VSS Supply voltage applied at DVSS pin TA Operating free-air temperature –40 TJ Operating junction temperature –40 CDVCC Recommended capacitor at DVCC (5) 4.7 fSYSTEM Processor frequency (maximum MCLK frequency) fACLK Maximum ACLK frequency fSMCLK Maximum SMCLK frequency (2) (3) (4) (5) (6) (7) (8) V ±250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. 5.3 (1) UNIT NOM 1.8 MAX V 85 °C 0 (6) UNIT 3.6 V 85 10 °C µF No FRAM wait states (NWAITSx = 0) 0 8 With FRAM wait states (NWAITSx = 1) (7) 0 16 (8) MHz 40 kHz 16 (8) MHz Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following the data sheet recommendation for capacitor CDVCC limits the slopes accordingly. Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet. TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM. The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in Table 5-2. A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as possible (within a few millimeters) to the respective pin pair. Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed without wait states. If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to comply with this operating condition. Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 21 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Active Mode Supply Current Into VCC Excluding External Current (1) 5.4 VCC = 3 V, TA = 25°C (unless otherwise noted) FREQUENCY (fMCLK = fSMCLK) EXECUTION MEMORY PARAMETER TEST CONDITION 1 MHz 0 WAIT STATES (NWAITSx = 0) TYP IAM, FRAM(0%) IAM, FRAM(100%) IAM, RAM (1) (2) (2) 8 MHz 0 WAIT STATES (NWAITSx = 0) MAX TYP 16 MHz 1 WAIT STATE (NWAITSx = 1) MAX TYP MAX 3480 FRAM 0% cache hit ratio 3 V, 25°C 504 2772 3047 3 V, 85°C 516 2491 2871 FRAM 100% cache hit ratio 3 V, 25°C 203 625 1000 3 V, 85°C 212 639 1016 RAM 3 V, 25°C 229 818 1377 UNIT µA 1215 µA µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data processing. fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency Program and data entirely reside in FRAM. All execution is from FRAM. Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM. 5.5 Active Mode Supply Current Per MHz VCC = 3 V, TA = 25°C (unless otherwise noted) PARAMETER dIAM,FRAM/df 5.6 TEST CONDITIONS Active mode current consumption per MHz, execution from FRAM, no wait states TYP UNIT 126 µA/MHz [IAM (75% cache hit rate) at 8 MHz – IAM (75% cache hit rate) at 1 MHz)] / 7 MHz Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current VCC = 3 V, TA = 25°C (unless otherwise noted) (1) (2) FREQUENCY (fSMCLK) PARAMETER VCC 1 MHz TYP ILPM0 (1) (2) 22 8 MHz MAX TYP 16 MHz MAX TYP 2V 156 328 420 3V 166 342 433 UNIT MAX µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Current for watchdog timer clocked by SMCLK included. fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency. Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn 5.7 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM3,XT1 Low-power mode 3, 12.5-pF crystal, includes SVS (2) (3) (4) ILPM3,VLO Low-power mode 3, VLO, excludes SVS (5) ILPM3, Low-power mode 3, RTC, excludes SVS (6) (see Figure 5-1) RTC ILPM3, CapTIvate, VCC –40°C TYP MAX 25°C (1) 85°C TYP MAX TYP 1.65 3.24 3V 0.98 1.18 2V 0.96 1.16 3V 0.78 0.98 2V 0.76 0.96 3.01 3V 0.93 1.13 3.19 MAX 3.21 1.40 3.04 UNIT µA µA µA Low-power mode 3, CapTIvate, excludes SVS (7) 3.3 V 5 µA Low-power mode 3, CapTIvate, excludes SVS (8) 3.3 V 3.4 µA Low-power mode 3, CapTIvate, excludes SVS (9) 3.3 V 3.6 µA Low-power mode 3, CapTIvate, excludes SVS (10) 3.3 V 27.2 µA Low-power mode 3, CapTIvate, excludes SVS (11) 3.3 V 109.2 µA 64 buttons ILPM4, Low-power mode 4, includes SVS 1 proximity, wake on touch ILPM3, CapTIvate, 1 button, wake on touch ILPM3, CapTIvate, 4 buttons, wake on touch ILPM3, CapTIvate, 16 buttons ILPM3, CapTIvate, SVS ILPM4 Low-power mode 4, excludes SVS ILPM4, CapTIvate, Low-power mode 4, CapTIvate, excludes SVS (12) 1 proximity, wake on touch 3V 0.51 0.65 2.65 2V 0.49 0.64 2.63 3V 0.35 0.49 2.49 2V 0.34 0.48 2.46 3V 4.4 µA µA µA (1) (2) (3) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Not applicable for MCUs with HF crystal oscillator only. Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5-pF load. (4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions: Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz (5) Low-power mode 3, VLO, excludes SVS test conditions: Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0). CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3) fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz (6) RTC periodically wakes up every second with external 32768-Hz input as source. (7) CapTIvate technology works in LPM3 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800 (8) CapTIvate technology works in LPM3 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay, Current for brownout included. SVS disabled (SVSHE = 0). fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250 (9) CapTIvate technology works in LPM3 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250 (10) CapTIvate technology works in LPM3 with 16 self-capacitance buttons. The CPU enters active mode between time cycles to configure the conversions and read the results. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250 (11) CapTIvate technology works in LPM3 with 64 mutual-capacitance buttons. The CPU enters active mode between time cycles to configure the conversions and read the results. TIDM-CAPTIVATE-64-BUTTON 64-Button Capacitive Touch Panel. Current for brownout included. SVS disabled (SVSHE = 0). fSCAN = 8 Hz, fCONVER = 4 MHz, COUNTS = 250 (12) CapTIvate technology works in LPM4 with one proximity sensor for wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal. fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 800 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 23 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM4, CapTIvate, 1 button, wake on touch ILPM4, CapTIvate, 4 buttons, wake on touch VCC –40°C TYP 25°C MAX TYP (1) 85°C MAX TYP MAX UNIT Low-power mode 4, CapTIvate, excludes SVS (13) 3V 2.7 µA Low-power mode 4, CapTIvate, excludes SVS (14) 3 V 3.0 µA (13) CapTIvate technology works in LPM4 with one button, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay, Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal. fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250 (14) CapTIvate technology works in LPM4 with four self-capacitance buttons, wake on touch. CapTIvate BSWP demonstration board with 1.5-mm overlay. Current for brownout included. SVS disabled (SVSHE = 0). VLO (10 kHz) sources to CapTIvate timer, no external crystal. fSCAN = 8 Hz, fCONVER = 2 MHz, COUNTS = 250 5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC –40°C TYP MAX 25°C MAX TYP MAX 0.95 0.99 1.42 ILPM3.5, Low-power mode 3.5, 12.5-pF crystal, includes SVS (1) (2) (3) (see Figure 5-2) 3V 0.65 0.73 XT1 2V 0.63 0.71 ILPM4.5, Low-power mode 4.5, includes SVS (4) (see Figure 53) 3V 0.22 0.24 SVS 2V 0.21 0.23 3V 0.012 0.016 2V 0.002 0.007 ILPM4.5 (1) (2) (3) (4) (5) 24 Low-power mode 4.5, excludes SVS (5) 85°C TYP 0.87 0.31 0.30 0.38 0.28 0.055 0.061 0.044 0.120 UNIT µA µA µA Not applicable for MCUs with HF crystal oscillator only. Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5-pF load. Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions: Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 32768 Hz, fACLK = 0, fMCLK = fSMCLK = 0 MHz Low-power mode 4.5, includes SVS test conditions: Current for brownout and SVS included (SVSHE = 1). Core regulator disabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz Low-power mode 4.5, excludes SVS test conditions: Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled. PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn 5.9 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Typical Characteristics - Low-Power Mode Supply Currents 3.0 10 LPM3.5 Supply Current (µA) LPM3 Supply Current (µA) 9 8 7 6 5 4 3 2 2.5 2.0 1.5 1.0 0.5 1 0.0 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 -40 80 -30 -20 -10 0 VCC = 3 V 10 20 30 40 50 60 70 80 Temperature (°C) Temperature (°C) RTC SVS Disabled VCC = 3 V Figure 5-1. LPM3 Supply Current vs Temperature XT1 SVS Enabled Figure 5-2. LPM3.5 Supply Current vs Temperature 0.50 LPM4.5 Supply Current (µA) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) VCC = 3 V SVS Enabled Figure 5-3. LPM4.5 Supply Current vs Temperature Table 5-1. Typical Characteristics – Current Consumption Per Module MODULE TEST CONDITIONS Timer_A REFERENCE CLOCK MIN TYP MAX UNIT Module input clock 5 µA/MHz eUSCI_A UART mode Module input clock 7 µA/MHz eUSCI_A SPI mode Module input clock 5 µA/MHz eUSCI_B SPI mode Module input clock 5 µA/MHz 5 µA/MHz eUSCI_B 2 I C mode, 100 kbaud RTC CRC From start to end of operation Module input clock 32 kHz 85 nA MCLK 8.5 µA/MHz Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 25 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 5.10 Thermal Resistance Characteristics THERMAL METRIC (1) RθJA Junction-to-ambient thermal resistance, still air RθJC(top) RθJB (1) (2) 26 Junction-to-case (top) thermal resistance Junction-to-board thermal resistance VALUE (2) VQFN 32 pin (RHB) 33.5 TSSOP 32 pin (DA) 69.4 VQFN 24 pin (RGE) 32.6 DSBGA 24 pin (YQW) 63.7 VQFN 32 pin (RHB) 25.7 TSSOP 32 pin (DA) 18.1 VQFN 24 pin (RGE) 32.4 DSBGA 24 pin (YQW) 0.3 VQFN 32 pin (RHB) 7.6 TSSOP 32 pin (DA) 33.1 VQFN 24 pin (RGE) 10.1 DSBGA 24 pin (YQW) 9.2 UNIT ºC/W ºC/W ºC/W For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5.11 Timing and Switching Characteristics 5.11.1 Power Supply Sequencing Table 5-2 lists the characteristics of the SVS and BOR. Table 5-2. PMM, SVS and BOR over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-4) PARAMETER TEST CONDITIONS (2) Safe BOR reset delay ISVSH,AM SVSH current consumption, active mode VCC = 3.6 V ISVSH,LPM SVSH current consumption, low-power modes VCC = 3.6 V VSVSH- SVSH power-down level (3) SVSH power-up level SVSH hysteresis tPD,SVSH, AM SVSH propagation delay, active mode tPD,SVSH, LPM SVSH propagation delay, low-power modes VREF, 1.2-V REF voltage (4) ms 240 µA nA 1.71 1.80 1.86 1.74 1.89 1.99 80 1.158 UNIT V 1.5 (3) VSVSH_hys (4) MAX 10 VSVSH+ 1.2V TYP 0.1 tBOR, safe (1) (2) (3) MIN Safe BOR power-down level (1) VBOR, safe V V mV 1.20 10 µs 100 µs 1.242 V A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises. When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+. For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference Design. This is a characterized result with external 1-mA load to ground from –40°C to 85°C. V Power Cycle Reset V SVS+ SVS Reset BOR Reset V SVS– V BOR t BOR t Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 27 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 5.11.2 Reset Timing Table 5-3 lists the wake-up times. Table 5-3. Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER VCC tWAKE-UP FRAM Additional wake-up time to activate the FRAM in AM if previously disabled by the FRAM controller or from a LPM if immediate activation is selected for wakeup (1) tWAKE-UP LPM0 Wake-up time from LPM0 to active mode (1) 3V tWAKE-UP LPM3 Wake-up time from LPM3 to active mode (2) 3V tWAKE-UP LPM4 Wake-up time from LPM4 to active mode tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode 3V (2) (2) SVSHE = 1 µs 200 + 2.5 / fDCO ns 10 µs 3V 350 µs 350 µs 1 ms 1 ms tWAKE-UP-RESET 3V tRESET Pulse duration required at RST/NMI pin to accept a reset 3V 28 10 UNIT 3V Wake-up time from RST or BOR event to active mode (2) (2) MAX µs Wake-up time from LPM4.5 to active mode SVSHE = 0 TYP 10 tWAKE-UP LPM4.5 (1) MIN 3V 2 µs The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable MCLK clock edge. The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed. Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5.11.3 Clock Specifications Table 5-4 lists the characteristics of XT1. Table 5-4. XT1 Crystal Oscillator (Low Frequency) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS fXT1, LF XT1 oscillator crystal, low frequency LFXTBYPASS = 0 DCXT1, LF XT1 oscillator LF duty cycle Measured at MCLK, fLFXT = 32768 Hz fXT1,SW XT1 oscillator logic-level squarewave input frequency LFXTBYPASS = 1 DCXT1, SW LFXT oscillator logic-level squareLFXTBYPASS = 1 wave input duty cycle OALFXT Oscillation allowance for LF crystals (4) LFXTBYPASS = 0, LFXTDRIVE = {3}, fLFXT = 32768 Hz, CL,eff = 12.5 pF CL,eff Integrated effective load capacitance (5) See tSTART,LFXT Start-up time fFault,LFXT (1) (2) (3) (4) (5) (6) (7) (8) (9) MIN TYP (8) MAX 32768 30% (2) (3) Hz 32.768 40% (6) XTS = 0 (9) UNIT 70% fOSC = 32768 Hz, LFXTBYPASS = 0, LFXTDRIVE = {3}, TA = 25°C, CL,eff = 12.5 pF (7) Oscillator fault frequency VCC kHz 60% 200 kΩ 1 pF 1000 ms 0 3500 Hz To improve EMI on the LFXT oscillator, observe the following guidelines: • Keep the trace between the device and the crystal as short as possible. • Design a good ground plane around the oscillator pins. • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins. • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins. When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW. Maximum frequency of operation of the entire device cannot be exceeded. Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: • For LFXTDRIVE = {0}, CL,eff = 3.7 pF • For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF • For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF • For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF Includes parasitic bond and package capacitance (approximately 2 pF per pin). Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met. Includes start-up counter of 1024 clock cycles. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the flag. A static condition or stuck at fault condition sets the flag. Measured with logic-level input frequency but also applies to operation with crystals. Table 5-5 lists the characteristics of the FLL. Table 5-5. DCO FLL, Frequency over recommended operating free-air temperature (unless otherwise noted) PARAMETER FLL lock frequency, 16 MHz, 25°C fDCO, FLL lock frequency, 16 MHz, –40°C to 85°C TEST CONDITIONS Measured at MCLK, Internal trimmed REFO as reference VCC MIN TYP MAX 3V –1.0% 1.0% 3V –2.0% 2.0% 3V –0.5% 0.5% UNIT FLL FLL lock frequency, 16 MHz, –40°C to 85°C Measured at MCLK, XT1 crystal as reference Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 29 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 5-5. DCO FLL, Frequency (continued) over recommended operating free-air temperature (unless otherwise noted) PARAMETER fDUTY Duty cycle Jittercc Cycle-to-cycle jitter, 16 MHz Jitterlong Long term jitter, 16 MHz tFLL, lock FLL lock time tstart-up DCO start-up time, 2 MHz TEST CONDITIONS Measured at MCLK, XT1 crystal as reference Measured at MCLK VCC MIN TYP MAX 3V 40% 50% 60% UNIT 3V 0.25% 3V 0.022% 3V 280 ms 3V 16 µs Table 5-6 lists the characteristics of the DCO. Table 5-6. DCO Frequency over recommended operating free-air temperature (unless otherwise noted) (also see Figure 5-5) PARAMETER TEST CONDITIONS VCC DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 0 fDCO, fDCO, fDCO, fDCO, fDCO, 16MHz 12MHz 8MHz 4MHz 2MHz DCO frequency, 16 MHz DCO frequency, 12 MHz DCO frequency, 8 MHz DCO frequency, 4 MHz DCO frequency, 2 MHz DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 511 DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 0 12.26 3V Specifications MHz 17.93 DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 511 29.1 DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 0 5.75 DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 511 DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 0 9.5 3V MHz 13.85 DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 511 22.5 DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 0 3.91 DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 511 DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 0 6.49 3V MHz 9.5 DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 511 15.6 DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 0 2.026 DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 511 DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 0 3.407 3V MHz 4.95 DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 511 8.26 DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 0 1.0225 DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 511 DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 0 UNIT 7.46 1.729 3V DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 511 30 TYP MHz 2.525 4.25 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 5-6. DCO Frequency (continued) over recommended operating free-air temperature (unless otherwise noted) (also see Figure 5-5) PARAMETER TEST CONDITIONS VCC DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 0 fDCO, 1MHz UNIT 0.5319 DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 000b, DCO = 511 DCO frequency, 1 MHz TYP 0.9029 3V DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 0 MHz 1.307 DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b, DCOFTRIM = 111b, DCO = 511 2.21 30 DCOFTRIM = 7 25 DCOFTRIM = 7 Frequency (MHz) 20 DCOFTRIM = 7 15 10 DCOFTRIM = 7 DCOFTRIM = 7 5 DCOFTRIM = 0 DCOFTRIM = 0 DCOFTRIM = 7 DCOFTRIM = 0 DCOFTRIM = 0 0 DCOFTRIM = 0 DCO 511 0 DCORSEL 0 DCOFTRIM = 0 511 0 511 0 1 VCC = 3 V 511 0 2 3 511 0 4 511 0 5 TA = –40°C to 85°C Figure 5-5. Typical DCO Frequency Table 5-7 lists the characteristics of the REFO. Table 5-7. REFO over recommended operating free-air temperature (unless otherwise noted) PARAMETER IREFO TEST CONDITIONS VCC REFO oscillator current consumption TA = 25°C REFO calibrated frequency Measured at MCLK REFO absolute calibrated tolerance –40°C to 85°C dfREFO/dT REFO frequency temperature drift Measured at MCLK (1) dfREFO/ dVCC REFO frequency supply voltage drift Measured at MCLK at 25°C (2) 1.8 V to 3.6 V fDC REFO duty cycle Measured at MCLK 1.8 V to 3.6 V tSTART REFO start-up time 40% to 60% duty cycle fREFO (1) (2) MIN 3V MAX 15 3V 1.8 V to 3.6 V TYP µA 32768 –3.5% 3V 40% UNIT Hz +3.5% 0.01 %/°C 1 %/V 50% 60% 50 µs Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 31 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 5-8 lists the characteristics of the VLO. NOTE The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO specifications (see Table 5-8). Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TYP UNIT fVLO VLO frequency Measured at MCLK 3V 10 kHz dfVLO/dT VLO frequency temperature drift Measured at MCLK (1) 3V 0.5 %/°C dfVLO/dVCC VLO frequency supply voltage drift Measured at MCLK (2) 2 V to 3.6 V 4 %/V fVLO,DC Duty cycle Measured at MCLK (1) (2) 3V 50% Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Table 5-9 lists the characteristics of the MODOSC. Table 5-9. Module Oscillator (MODOSC) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC MIN TYP MAX fMODOSC MODOSC frequency PARAMETER 3V 3.8 4.8 5.8 fMODOSC/dT MODOSC frequency temperature drift 3V 0.102 %/℃ fMODOSC/dVCC MODOSC frequency supply voltage drift 1.8 V to 3.6 V 1.02 %/V fMODOSC,DC Duty cycle 32 Specifications 3V 40% 50% UNIT MHz 60% Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5.11.4 Digital I/Os Table 5-10 lists the characteristics of the digital inputs. Table 5-10. Digital Inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX 2V 0.90 1.50 3V 1.35 2.25 2V 0.50 1.10 3V 0.75 1.65 2V 0.3 0.8 3V 0.4 1.2 UNIT VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = VCC CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF CI,ana Input capacitance, port pins with shared analog VIN = VSS or VCC functions 5 pF Ilkg(Px.y) High-impedance leakage current See External interrupt timing (external trigger pulse duration to set interrupt flag) (3) Ports with interrupt capability (see block diagram and terminal function descriptions) t(int) (1) (2) (3) (1) (2) 20 2 V, 3 V –20 2 V, 3 V 50 35 50 20 V V V kΩ nA ns The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Table 5-11 lists the characteristics of the digital outputs. Table 5-11. Digital Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (also see Figure 56, Figure 5-7, Figure 5-8, and Figure 5-9) PARAMETER VCC MIN I(OHmax) = –3 mA (1) TEST CONDITIONS 2V 1.4 2.0 I(OHmax) = –5 mA (1) 3V 2.4 3.0 I(OLmax) = 3 mA (1) 2V 0.0 0.60 I(OHmax) = 5 mA (1) 3V 0.0 0.60 2V 16 3V 16 VOH High-level output voltage VOL Low-level output voltage fPort_CLK Clock output frequency CL = 20 pF (2) trise,dig Port output rise time, digital only port pins CL = 20 pF tfall,dig Port output fall time, digital only port pins CL = 20 pF (1) (2) TYP MAX UNIT V V MHz 2V 10 3V 7 2V 10 3V 5 ns ns The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The port can output frequencies at least up to the specified limit and might support higher frequencies. Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 33 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 5.11.4.1 Typical Characteristics – Outputs at 3 V and 2 V 10 Low-Level Output Current (mA) Low-Level Output Current (mA) 25 20 15 10 5 85°C 0 25°C 0.5 1 1.5 2 Low-Level Output Voltage (V) 2.5 5 85°C 2.5 25°C –40°C –40°C 0 –5 0 7.5 0 3 DVCC = 3 V 0.75 1 1.25 1.5 Low-Level Output Voltage (V) 1.75 2 Figure 5-7. Typical Low-Level Output Current vs Low-Level Output Voltage 5 0 0 High-Level Output Current (mA) 85°C High-Level Output Current (mA) 0.5 DVCC = 2 V Figure 5-6. Typical Low-Level Output Current vs Low-Level Output Voltage 25°C –40°C –5 –10 –15 –20 –25 85°C 25°C –2.5 –40°C –5 –7.5 –10 –30 0 0.5 1 1.5 2 High-Level Output Voltage (V) 2.5 DVCC = 3 V Specifications 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 High-Level Output Voltage (V) DVCC = 2 V Figure 5-8. Typical High-Level Output Current vs High-Level Output Voltage 34 0.25 Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5.11.5 VREF+ Built-in Reference Table 5-12 lists the characteristics of VREF+. Table 5-12. VREF+ over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VREF+ Positive built-in reference voltage TCREF+ Temperature coefficient of built-in reference voltage EXTREFEN = 1 with 1-mA load current VCC MIN TYP MAX UNIT 2 V, 3 V 1.15 1.19 1.23 V 30 µV/°C 5.11.6 Timer_A Table 5-13 lists the characteristics of Timer_A. Table 5-13. Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10 and Figure 5-11) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, duty cycle = 50% ±10% 2 V, 3 V tTA,cap Timer_A capture timing All capture inputs, minimum pulse duration required for capture 2 V, 3 V MIN TYP MAX UNIT 16 MHz 20 ns tTIMR Timer Clock Timer CCR0-1 CCR0 0h CCR0-1 1h CCR0 0h tHD,PWM tVALID,PWM TAx.1 Figure 5-10. Timer PWM Mode Capture tTIMR Timer Clock tSU,CCIA t,HD,CCIA TAx.CCIA Figure 5-11. Timer Capture Mode Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 35 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 5.11.7 eUSCI Table 5-14 lists the supported frequencies of the eUSCI in UART mode. Table 5-14. eUSCI (UART Mode) Clock Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS feUSCI eUSCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in Mbaud) VCC Internal: SMCLK or MODCLK, External: UCLK, duty cycle = 50% ±10% MIN MAX UNIT 2 V, 3 V 16 MHz 2 V, 3 V 5 MHz Table 5-15 lists the characteristics of the eUSCI in UART mode. Table 5-15. eUSCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TYP UCGLITx = 0 tt UART receive deglitch time UCGLITx = 1 (1) 40 2 V, 3 V UCGLITx = 2 68 UCGLITx = 3 (1) UNIT 12 ns 110 Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. Table 5-16 lists the supported frequencies of the eUSCI in SPI master mode. Table 5-16. eUSCI (SPI Master Mode) Clock Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER feUSCI eUSCI input clock frequency TEST CONDITIONS MIN MAX UNIT 8 MHz Internal: SMCLK or MODCLK, duty cycle = 50% ±10% Table 5-17 lists the characteristics of the eUSCI in SPI master mode. Table 5-17. eUSCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS UCSTEM = 0, UCMODEx = 01 or 10 tSTE,LEAD STE lead time, STE active to clock tSTE,LAG STE lag time, last clock to STE inactive tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time (2) UCLK edge to SIMO valid, CL = 20 pF tHD,MO SIMO output data hold time (3) CL = 20 pF (1) (2) (3) 36 VCC UCSTEM = 1, UCMODEx = 01 or 10 UCSTEM = 0, UCMODEx = 01 or 10 UCSTEM = 1, UCMODEx = 01 or 10 MIN MAX UNIT 1 UCxCLK cycles 1 UCxCLK cycles 2V 45 3V 35 2V 0 3V 0 ns ns 2V 20 3V 20 2V 0 3V 0 ns ns fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)) For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-12 and Figure 5-13. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 512 and Figure 5-13. Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 5-12. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 5-13. SPI Master Mode, CKPH = 1 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 37 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 5-18 lists the characteristics of the eUSCI in SPI slave mode. Table 5-18. eUSCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER tSTE,LEAD STE lead time, STE active to clock tSTE,LAG STE lag time, Last clock to STE inactive tSTE,ACC STE access time, STE active to SOMI data out tSTE,DIS STE disable time, STE inactive to SOMI high impedance tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time (2) tHD,SO SOMI output data hold time (1) (2) (3) 38 (3) TEST CONDITIONS UCLK edge to SOMI valid, CL = 20 pF CL = 20 pF VCC MIN 2V 55 3V 45 2V 20 3V 20 MAX ns ns 2V 65 3V 40 2V 40 3V 35 2V 6 3V 4 2V 12 3V 12 65 40 3V 5 ns ns 3V 5 ns ns 2V 2V UNIT ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-14 and Figure 5-15. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-14 and Figure 5-15. Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SIMO tLOW/HIGH tHD,SIMO SIMO tACC tDIS tVALID,SOMI SOMI Figure 5-14. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tACC tVALID,SO tDIS SOMI Figure 5-15. SPI Slave Mode, CKPH = 1 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 39 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 5-19 lists the characteristics of the eUSCI in I2C mode. Table 5-19. eUSCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16) PARAMETER TEST CONDITIONS feUSCI eUSCI input clock frequency fSCL SCL clock frequency VCC MIN TYP Internal: SMCLK or MODCLK, External: UCLK Duty cycle = 50% ±10% 2 V, 3 V fSCL = 100 kHz UNIT 16 MHz 400 kHz 4.0 tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2 V, 3 V 0 ns tSU,DAT Data setup time 2 V, 3 V 250 ns tSU,STO tSP fSCL > 100 kHz fSCL = 100 kHz fSCL > 100 kHz fSCL = 100 kHz Setup time for STOP fSCL > 100 kHz Pulse duration of spikes suppressed by input filter 2 V, 3 V 0 MAX 2 V, 3 V 2 V, 3 V µs 0.6 4.7 µs 0.6 4.0 µs 0.6 UCGLITx = 0 50 600 UCGLITx = 1 25 300 12.5 150 UCGLITx = 2 2 V, 3 V UCGLITx = 3 6.3 75 UCCLTOx = 1 tTIMEOUT Clock low time-out UCCLTOx = 2 27 2 V, 3 V 30 UCCLTOx = 3 tSU,STA tHD,STA ns ms 33 tHD,STA tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-16. I2C Mode Timing 40 Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5.11.8 ADC Table 5-20 lists the input requirements of the ADC. Table 5-20. ADC, Power Supply and Input Range Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS DVCC ADC supply voltage V(Ax) Analog input voltage range IADC Operating supply current into DVCC terminal, reference current not included, repeat-single-channel mode fADCCLK = 5 MHz, ADCON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADCDIV = 0, ADCCONSEQx = 10b CI Input capacitance Only one terminal Ax can be selected at one time, from the pad to the ADC capacitor array, including wiring and pad RI,MUX Input MUX ON resistance DVCC = 2 V, 0 V ≤ VAx ≤ DVCC RI,Misc Input miscellaneous resistance VCC MIN All ADC pins TYP MAX UNIT 2.0 3.6 V 0 DVCC V 2V 185 3V 207 2.2 V 1.6 µA 2.0 pF 2 kΩ 34 kΩ Table 5-21 lists the timing parameters of the ADC. Table 5-21. ADC, 10-Bit Timing Parameters over operating free-air temperature range (unless otherwise noted) PARAMETER VCC MIN TYP MAX UNIT For specified performance of ADC linearity parameters 2 V to 3.6 V 0.45 5 5.5 MHz Internal ADC oscillator (MODOSC) ADCDIV = 0, fADCCLK = fADCOSC 2 V to 3.6 V 4.5 5.0 5.5 MHz 2 V to 3.6 V 2.18 Conversion time REFON = 0, Internal oscillator, 10 ADCCLK cycles, 10-bit mode, fADCOSC = 4.5 MHz to 5.5 MHz External fADCCLK from ACLK or SMCLK, ADCSSEL ≠ 0 2 V to 3.6 V fADCCLK fADCOSC tCONVERT TEST CONDITIONS tADCON Turnon settling time of the ADC The error in a conversion started after tADCON is less than ±0.5 LSB, Reference and input signal already settled tSample Sampling time RS = 1000 Ω, RI (1) = 36000 Ω, CI = 3.5 pF, Approximately 8 Tau (t) are required for an error of less than ±0.5 LSB (2) (1) (2) 2.67 µs 12 × 1 / fADCCLK 100 2V 1.5 3V 2.0 ns µs RI = RI,MUX + RI,Misc tSample = ln(2n+1) × τ, where n = ADC resolution, τ = (RI + RS) × CI Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 41 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 5-22 lists the linearity parameters of the ADC. Table 5-22. ADC, 10-Bit Linearity Parameters over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Integral linearity error (10-bit mode) EI Veref+ as reference Integral linearity error (8-bit mode) Differential linearity error (10-bit mode) ED Veref+ as reference Differential linearity error (8-bit mode) Offset error (10-bit mode) EO Veref+ as reference Offset error (8-bit mode) Gain error (10-bit mode) EG Gain error (8-bit mode) Total unadjusted error (10-bit mode) ET Total unadjusted error (8-bit mode) VSENSOR See (1) TCSENSOR See (2) tSENSOR (sample) (1) (2) (3) 42 Sample time required if channel 12 is selected (3) Veref+ as reference Internal 1.5-V reference Veref+ as reference Internal 1.5-V reference Veref+ as reference Internal 1.5-V reference Veref+ as reference Internal 1.5-V reference VCC MIN TYP MAX 2.4 V to 3.6 V –2 2 2 V to 3.6 V –2 2 2.4 V to 3.6 V –1 1 2 V to 3.6 V –1 1 2.4 V to 3.6 V –6.5 6.5 2 V to 3.6 V –6.5 6.5 LSB LSB mV 2.4 V to 3.6 V –2.0 2.0 –3.0% 3.0% 2 V to 3.6 V –2.0 2.0 –3.0% 3.0% 2.4 V to 3.6 V –2.0 2.0 –3.0% 3.0% –2.0 2.0 –3.0% 3.0% 2 V to 3.6 V UNIT LSB LSB LSB LSB ADCON = 1, INCH = 0Ch, TA = 0°C 3V 913 mV ADCON = 1, INCH = 0Ch 3V 3.35 mV/°C ADCON = 1, INCH = 0Ch, Error of conversion result ≤1 LSB, AM and all LPMs above LPM3 3V ADCON = 1, INCH = 0Ch, Error of conversion result ≤1 LSB, LPM3 3V 30 µs 100 The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The device descriptor structure contains calibration values for 30°C and 85°C for each available reference voltage level. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR , where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on). Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 5.11.9 CapTIvate Table 5-23 lists the characteristics of the CapTIvate module. Table 5-23. CapTIvate Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VREG Reference voltage output CREG External buffer capacitor ESR ≤ 200 mΩ CELECTRODE Maximum capacitance of all external electrodes on all CapTIvate blocks Running a conversion at 4 MHz tWAKEUP,COLD Voltage regulator wake-up time LDO completely off then turned on tWAKEUP,WARM Voltage regulator wake-up time LDO in low-power mode then turned on fCAPCLK Captivate oscillator frequency, nominal TA = 25ºC, CAPCLK0, FREQSHFT = 00b –3% DCCAPCLK CapTIvate oscillator duty cycle Excluding first clock cycle, DC = thigh × f 40% TYP MAX UNIT 1.5 1.55 1.6 V 0.8 1 1.2 µF 300 pF 1 ms 300 us 16 +3% MHz 50% 60% Table 5-24 lists the signal-to-noise ratio of the CapTIvate module. Table 5-24. CapTIvate Signal-to-Noise Ratio Characteristics over operating free-air temperature range from –40°C to 105°C ambient (TA), unless otherwise noted PARAMETER TEST CONDITIONS TA = 25°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in capacitance (2) Signal-to-noise ratio (1) SNR (1) (2) MIN TYP 5:1 36:1 TA = 0°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in capacitance (2) 28:1 TA = –40°C, Ct > 0.5 pF, Cp < 20 pF, >2.5% change in capacitance (2) 19:1 MAX UNIT SNR is defined as the ratio of the measured change in electrode capacitance due to a touch compared with the measured change in capacitance due to the device noise floor. For additional detail on SNR in capacitive sensing applications and how to measure it in your system, see Sensitivity, SNR, and Design Margin in Capacitive Touch Applications. Ct represents the increase or decrease in electrode capacitance due to a touch. Cp represents the inherent parasitic capacitance of the sensing electrode that is present when no touch is applied. Therefore, the touch signal is defined as Ct/Cp, expressed as a percent change in capacitance. Increasing Ct or decreasing Cp increases signal. 5.11.10 FRAM Table 5-25 lists the characteristics of the FRAM. Table 5-25. FRAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tRetention Data retention duration IWRITE Current to write into FRAM IERASE Erase current tWRITE tREAD (1) (2) (3) (4) MIN TYP 1015 Read and write endurance TJ = 25°C 100 TJ = 70°C 40 TJ = 85°C 10 Write time UNIT cycles years IREAD (1) nA N/A (2) nA (3) ns tREAD Read time MAX NWAITSx = 0 1/fSYSTEM (4) NWAITSx = 1 2/fSYSTEM (4) ns Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read current IREAD is included in the active mode current consumption parameter IAM,FRAM. FRAM does not require a special erase sequence. Writing into FRAM is as fast as reading. The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx). Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 43 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 5.11.11 Debug and Emulation Table 5-26 lists the characteristics of the Spy-Bi-Wire interface. Table 5-26. JTAG, Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17) PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2 V, 3 V 0 10 MHz tSBW,Low Spy-Bi-Wire low clock pulse duration 2 V, 3 V 0.028 15 µs tSU, SBWTDIO SBWTDIO setup time (before falling edge of SBWTCK in TMS and TDI slot, Spy-Bi-Wire) 2 V, 3 V 4 ns tHD, SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI slot, Spy-Bi-Wire) 2 V, 3 V 19 ns tValid, SBWTDIO SBWTDIO data valid time (after falling edge of SBWTCK in TDO slot, Spy-Bi-Wire) 2 V, 3 V 31 ns tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2 V, 3 V 110 µs tSBW,Ret Spy-Bi-Wire return to normal operation time (2) 2 V, 3 V 15 100 µs Rinternal Internal pulldown resistance on TEST 2 V, 3 V 20 50 kΩ (1) (2) SBWTDIO 35 Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. Maximum tSBW,Ret time after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function to their application function. This time applies only if the Spy-Bi-Wire mode is selected. tSBW,EN 1/fSBW tSBW,Low tSBW,High tSBW,Ret TEST/SBWTCK tEN,SBWTDIO tValid,SBWTDIO RST/NMI/SBWTDIO tSU,SBWTDIO tHD,SBWTDIO Figure 5-17. JTAG Spy-Bi-Wire Timing 44 Specifications Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 5-27 lists the characteristics of the 4-wire JTAG interface. Table 5-27. JTAG, 4-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18) PARAMETER VCC MIN TYP MAX UNIT 10 MHz fTCK TCK input frequency (1) 2 V, 3 V 0 tTCK,Low TCK low clock pulse duration 2 V, 3 V 15 ns tTCK,High TCK high clock pulse duration 2 V, 3 V 15 ns tSU,TMS TMS setup time (before rising edge of TCK) 2 V, 3 V 11 ns tHD,TMS TMS hold time (after rising edge of TCK) 2 V, 3 V 3 ns tSU,TDI TDI setup time (before rising edge of TCK) 2 V, 3 V 13 ns tHD,TDI TDI hold time (after rising edge of TCK) 2 V, 3 V 5 tZ-Valid,TDO TDO high impedance to valid output time (after falling edge of TCK) 2 V, 3 V 26 ns tValid,TDO TDO to new valid output time (after falling edge of TCK) 2 V, 3 V 26 ns tValid-Z,TDO TDO valid to high-impedance output time (after falling edge of TCK) 2 V, 3 V 26 ns tJTAG,Ret Spy-Bi-Wire return to normal operation time 100 µs Rinternal Internal pulldown resistance on TEST 50 kΩ (1) ns 15 2 V, 3 V 20 35 fTCK may be restricted to meet the timing requirements of the module selected. 1/fTCK tTCK,Low tTCK,High TCK TMS tSU,TMS tHD,TMS TDI (or TDO as TDI) tSU,TDI tHD,TDI TDO tZ-Valid,TDO tValid,TDO tValid-Z,TDO tJTAG,Ret TEST Figure 5-18. JTAG 4-Wire Timing Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Specifications 45 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6 Detailed Description 6.1 Overview The MSP430FR263x and MSP430FR253x ultra-low-power MCUs are the first FRAM-based MCUs with integrated high-performance charge-transfer CapTIvate technology in ultra-low-power high-reliability highflexibility MCUs. The MSP430FR263x and MSP430FR253x MCUs feature up to 16 self-capacitance or 64 mutual-capacitance electrodes, proximity sensing, and high accuracy up to 1-fF detection. The MCUs also include four 16-bit timers, eUSCIs that support UART, SPI, and I2C, a hardware multiplier, an RTC module with alarm capabilities, and a high-performance 10-bit ADC. 6.2 CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register (SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with all instructions. 6.3 Operating Modes The MSP430FR263x and MSP430FR253x MCUs have one active mode and several software-selectable low-power modes of operation (see Table 6-1). An interrupt event can wake the MCU from low-power mode (LPM0 or LPM3), service the request, and restore the MCU back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption. Table 6-1. Operating Modes MODE Maximum system clock Power consumption at 25°C, 3 V Wake-up time LPM3 LPM4 LPM3.5 LPM4.5 CPU OFF STANDBY OFF ONLY RTC SHUTDOWN 16 MHz 16 MHz 40 kHz 0 40 kHz 0 126 µA/MHz 40 µA/MHz 1.7 µA/button average with 8-Hz scan 0.49 µA without SVS 0.73 µA with RTC counter only in LFXT 16 nA without SVS N/A Instant 10 µs 10 µs 350 µs 350 µs RTC I/O I/O N/A All All Full Regulation Full Regulation Partial Power Down Partial Power Down Partial Power Down Power Down SVS On On Optional Optional Optional Optional Brownout On On On On On On Regulator 46 LPM0 CapTIvate I/O Wake-up events Power AM ACTIVE MODE (FRAM ON) Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-1. Operating Modes (continued) Clock (1) Core Peripherals I/O (1) (2) AM LPM0 LPM3 LPM4 LPM3.5 LPM4.5 MODE ACTIVE MODE (FRAM ON) CPU OFF STANDBY OFF ONLY RTC SHUTDOWN MCLK Active Off Off Off Off Off SMCLK Optional Optional Off Off Off Off FLL Optional Optional Off Off Off Off DCO Optional Optional Off Off Off Off MODCLK Optional Optional Off Off Off Off REFO Optional Optional Optional Off Off Off ACLK Optional Optional Optional Off Off Off XT1CLK Optional Optional Optional Off Optional Off VLOCLK Optional Optional Optional Off Optional Off CapTIvate MODCLK Optional Optional Optional Off Off Off CPU On Off Off Off Off Off FRAM On On Off Off Off Off RAM On On On On Off Off Backup memory (2) On On On On On Off Timer0_A3 Optional Optional Optional Off Off Off Timer1_A3 Optional Optional Optional Off Off Off Timer2_A2 Optional Optional Optional Off Off Off Timer3_A2 Optional Optional Optional Off Off Off WDT Optional Optional Optional Off Off Off eUSCI_A0 Optional Optional Off Off Off Off eUSCI_A1 Optional Optional Off Off Off Off eUSCI_B0 Optional Optional Off Off Off Off CRC Optional Optional Off Off Off Off ADC Optional Optional Optional Off Off Off RTC Optional Optional Optional Off Optional Off CapTIvate Optional Optional Optional Off Off Off On Optional State Held State Held State Held State Held General-purpose digital input/output The status shown for LPM4 applies to internal clocks only. Backup memory contains 32 bytes of register space in peripheral memory. See Table 6-24 and Table 6-43 for its memory allocation. NOTE XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals, such as RTC, WDT, or CapTIvate. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 47 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.4 www.ti.com.cn Interrupt Vector Addresses The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-2. Interrupt Sources, Flags, and Vectors 48 SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset FFFEh 63, Highest Nonmaskable FFFCh 62 NMIIFG OFIFG Nonmaskable FFFAh 61 Timer0_A3 TA0CCR0 CCIFG0 Maskable FFF8h 60 Timer0_A3 TA0CCR1 CCIFG1, TA0CCR2 CCIFG2, TA0IFG (TA0IV) Maskable FFF6h 59 Timer1_A3 TA1CCR0 CCIFG0 Maskable FFF4h 58 Timer1_A3 TA1CCR1 CCIFG1, TA1CCR2 CCIFG2, TA1IFG (TA1IV) Maskable FFF2h 57 Timer2_A2 TA2CCR0 CCIFG0 Maskable Timer2_A2 TA2CCR1 CCIFG1, TA2IFG (TA2IV) INTERRUPT SOURCE INTERRUPT FLAG System Reset Power up, Brownout, Supply supervisor External reset RST Watchdog time-out, Key violation FRAM access time error FRAM uncorrectable bit error detection Software POR, BOR FLL unlock error PMMPORIFG, PMMBORIFG, SVSHIFG PMMRSTIFG WDTIFG ACCTEIFG UBDIFG SYSRSTIV FLLUNLOCKIFG System NMI Vacant memory access JTAG mailbox FRAM bit error detection VMAIFG JMBINIFG, JMBOUTIFG CBDIFG, UBDIFG User NMI External NMI Oscillator fault Maskable FFF0h 56 FFEEh 55 FFECh 54 FFEAh 53 Timer3_A2 TA3CCR0 CCIFG0 Timer3_A2 TA3CCR1 CCIFG1, TA3IFG (TA3IV) RTC RTCIFG Maskable FFE8h 52 Watchdog timer interval mode WDTIFG Maskable FFE6h 51 eUSCI_A0 receive or transmit UCTXCPTIFG, UCSTTIFG, UCRXIFG, UCTXIFG (UART mode) UCRXIFG, UCTXIFG (SPI mode) (UCA0IV) Maskable FFE4h 50 eUSCI_A1 receive or transmit UCTXCPTIFG, UCSTTIFG, UCRXIFG, UCTXIFG (UART mode) UCRXIFG, UCTXIFG (SPI mode) (UCA1IV) Maskable FFE2h 49 eUSCI_B0 receive or transmit UCB0RXIFG, UCB0TXIFG (SPI mode) UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode) (UCB0IV) Maskable FFE0h 48 ADC ADCIFG0, ADCINIFG, ADCLOIFG, ADCHIIFG, ADCTOVIFG, ADCOVIFG (ADCIV) Maskable FFDEh 47 P1 P1IFG.0 to P1IFG.7 (P1IV) Maskable FFDCh 46 P2 P2IFG.0 to P2IFG.7 (P2IV) Maskable FFDAh 45 CapTIvate (See CapTivate Design Center for details) Maskable FFD8h 44, Lowest Reserved Reserved Maskable FFD6h to FF88h Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-2. Interrupt Sources, Flags, and Vectors (continued) INTERRUPT SOURCE Signatures 6.5 SYSTEM INTERRUPT INTERRUPT FLAG WORD ADDRESS BSL Signature 2 0FF86h BSL Signature 1 0FF84h JTAG Signature 2 0FF82h JTAG Signature 1 0FF80h PRIORITY Bootloader (BSL) The BSL lets users program the FRAM or RAM using either the UART serial interface or the I2C interface. Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins (see Table 6-3 and Table 6-4). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. This device supports the blank device detection to automatically invoke the BSL, skipping this special entry sequence, to save time and simplify onboard programming. For a complete description of the features of the BSL, see the MSP430 FRAM Device Bootloader (BSL) User's Guide. Table 6-3. UART BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal TEST/SBWTCK Entry sequence signal P1.4 Data transmit P1.5 Data receive VCC Power supply VSS Ground supply Table 6-4. I2C BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entry sequence signal TEST/SBWTCK Entry sequence signal P1.2 Data transmit and receive P1.3 Clock VCC Power supply VSS Ground supply Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 49 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.6 www.ti.com.cn JTAG Standard Interface The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-5 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For details on using the JTAG interface, see MSP430 Programming With the JTAG Interface. Table 6-5. JTAG Pin Requirements and Function 6.7 DEVICE SIGNAL DIRECTION P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ IN JTAG FUNCTION JTAG clock input P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 IN JTAG state control P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 IN JTAG data input, TCLK input P1.7/UCA0STE/SMCLK/TDO/A7 OUT JTAG data output TEST/SBWTCK IN Enable JTAG pins RST/NMI/SBWTDIO IN External reset DVCC – Power supply DVSS – Ground supply Spy-Bi-Wire Interface (SBW) The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface with MSP development tools and device programmers. Table 6-6 lists the SBW interface pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For details on using the SBW interface, see the MSP430 Programming With the JTAG Interface. Table 6-6. Spy-Bi-Wire Pin Requirements and Functions DEVICE SIGNAL 6.8 DIRECTION SBW FUNCTION TEST/SBWTCK IN Spy-Bi-Wire clock input RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input and output DVCC – Power supply DVSS – Ground supply FRAM The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features of the FRAM include: • Byte and word access capability • Programmable wait state generation • Error correction coding (ECC) 6.9 Memory Protection The device features memory protection for user access authority and write protection, including options to: • Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU. • Enable write protection to prevent unwanted write operation to FRAM contents by setting the control bits in the System Configuration 0 register. For detailed information, see the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MP430FR4xx and MP430FR2xx Family User's Guide. 50 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.10 Peripherals Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be handled by using all instructions in the memory map. For complete module description, see the MP430FR4xx and MP430FR2xx Family User's Guide. 6.10.1 Power-Management Module (PMM) The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR) is implemented to provide the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the primary supply. The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference. The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as Equation 1 by using ADC sampling 1.5-V reference without any external components support. DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result (1) A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when EXTREFEN = 1 in the PMMCTL1 register. ADC channel 4 can also be selected to monitor this voltage. For more detailed information, see the MP430FR4xx and MP430FR2xx Family User's Guide. 6.10.2 Clock System (CS) and Clock Distribution The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and an on-chip asynchronous high-speed clock (MODOSC). The clock system is designed for cost-effective designs with minimal external components. A fail-safe mechanism is included for XT1. The clock system module offers the following clock signals. • Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or 128. • Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK. • Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to 40 kHz. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 51 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn All peripherals may have one or several clock sources depending on specific functionality. Table 6-7 lists the clock distribution used in this device. Table 6-7. Clock Distribution CLOCK SOURCE SELECT BITS Frequency Range MCLK SMCLK ACLK MODCLK XT1CLK VLOCLK EXTERNAL PIN DC to 16 MHz DC to 16 MHz DC to 40 kHz 5 MHz ±10% DC to 40 kHz 10 kHz ±50% – CPU N/A Default – – – – – – FRAM N/A Default – – – – – – RAM N/A Default – – – – – – CRC N/A Default – – – – – – I/O N/A Default – – – – – – TA0 TASSEL – 10b 01b – – – 00b (TA0CLK pin) TA1 TASSEL – 10b 01b – – – 00b (TA1CLK pin) TA2 TASSEL – 10b 01b – – – – TA3 TASSEL – 10b 01b – – – – eUSCI_A0 UCSSEL – 10b or 11b – 01b – – 00b (UCA0CLK pin) eUSCI_A1 UCSSEL – 10b or 11b – 01b – – 00b (UCA1CLK pin) eUSCI_B0 UCSSEL – 10b or 11b – 01b – – 00b (UCB0CLK pin) WDT WDTSSEL – 00b 01b – – 10b or 11b – ADC ADCSSEL – 11b 01b 00b – – – CAPTSSEL – 00b – – 01b – CAPCLKSEL – 1b – – – – – RTCSS – 01b – – 10b 11b – CapTIvate RTC 6.10.3 General-Purpose Input/Output Port (I/O) Up to 19 I/O ports are implemented. • P1 and P2 are full 8-bit ports; P3 has 3 bits implemented. • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • All ports support programmable pullup or pulldown. • Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2. • Read and write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise or word-wise in pairs. • CapTIvate functionality is supported on all CAPx.y pins. NOTE Configuration of digital I/Os after BOR reset To prevent any cross currents during start-up of the device, all port pins are high-impedance with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, see the Configuration After Reset section in the Digital I/O chapter of the MP430FR4xx and MP430FR2xx Family User's Guide. 52 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.10.4 Watchdog Timer (WDT) The primary function of the WDT module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as interval timer and can generate interrupts at selected time intervals. Table 6-8 lists the system clocks that can be used to source the WDT. Table 6-8. WDT Clocks WDTSSEL NORMAL OPERATION (WATCHDOG AND INTERVAL TIMER MODE) 00 SMCLK 01 ACLK 10 VLOCLK 11 Reserved Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 53 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.10.5 System (SYS) Module The SYS module handles many of the system functions within the device. These features include poweron reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism through SBW called a JTAG mailbox mail box that can be used in the application. Table 6-9 summarizes the interrupts that are managed by the SYS module. Table 6-9. System Module Interrupt Vector Registers INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset SYSSNIV, System NMI SYSUNIV, User NMI 54 Detailed Description ADDRESS 015Eh 015Ch 015Ah INTERRUPT EVENT VALUE No interrupt pending 00h Brownout (BOR) 02h RSTIFG RST/NMI (BOR) 04h PMMSWBOR software BOR (BOR) 06h LPMx.5 wake up (BOR) 08h Security violation (BOR) 0Ah Reserved 0Ch SVSHIFG SVSH event (BOR) 0Eh Reserved 10h Reserved 12h PMMSWPOR software POR (POR) 14h WDTIFG watchdog time-out (PUC) 16h WDTPW password violation (PUC) 18h FRCTLPW password violation (PUC) 1Ah Uncorrectable FRAM bit error detection 1Ch Peripheral area fetch (PUC) 1Eh PMMPW PMM password violation (PUC) 20h FLL unlock (PUC) 24h Reserved 22h, 26h to 3Eh No interrupt pending 00h SVS low-power reset entry 02h Uncorrectable FRAM bit error detection 04h Reserved 06h Reserved 08h Reserved 0Ah Reserved 0Ch Reserved 0Eh Reserved 10h VMAIFG Vacant memory access 12h JMBINIFG JTAG mailbox input 14h JMBOUTIFG JTAG mailbox output 16h Correctable FRAM bit error detection 18h Reserved 1Ah to 1Eh No interrupt pending 00h NMIIFG NMI pin or SVSH event 02h OFIFG oscillator fault 04h Reserved 06h to 1Eh PRIORITY Highest Lowest Highest Lowest Highest Lowest Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.10.6 Cyclic Redundancy Check (CRC) The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data values and can be used for data checking purposes. The CRC generation polynomial is compliant with CRC-16-CCITT standard of x16 + x12 + x5 + 1. 6.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0) The eUSCI modules are used for serial data communications. The eUSCI_A module supports either UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications. Additionally, eUSCI_A supports automatic baud-rate detection and IrDA. Table 6-10 lists the pin configurations that are required for each eUSCI mode. Table 6-10. eUSCI Pin Configurations eUSCI_A0 eUSCI_A1 eUSCI_B0 PIN UART SPI P1.4 TXD SIMO P1.5 RXD SOMI P1.6 – SCLK P1.7 – STE P2.6 TXD SIMO P2.5 RXD SOMI P2.4 – SCLK P3.1 – STE PIN 2 I C SPI P1.0 – STE P1.1 – SCLK P1.2 SDA SIMO P1.3 SCL SOMI Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 55 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.10.8 Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2) The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers each. Both timers support multiple captures or compares, PWM outputs, and interval timing (see Table 6-11 and Table 6-12). Both timers have extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture/compare register. The CCR0 registers on Timer0_A3 and Timer1_A3 are not externally connected and can be used only for hardware period timing and interrupt generation. In Up mode, these CCR0 registers can be used to set the overflow value of the counter. Table 6-11. Timer0_A3 Signal Connections PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME TA0CLK TACLK P1.0 ACLK (internal) ACLK SMCLK (internal) SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL Timer N/A CCR0 TA0 Timer1_A3 CCI0B input CCI0A CCI0B DVSS VCC TA0.1 CCI1A TA0.1 from RTC (internal) CCI1B TA1 Timer1_A3 CCI1B input DVSS GND DVCC VCC TA0.2 CCI2A TA0.2 CCI2B TA2 Timer1_A3 CCI2B input, IR Input P1.1 P1.2 56 GND DVCC Detailed Description DVSS GND DVCC VCC CCR1 CCR2 Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-12. Timer1_A3 Signal Connections PORT PIN P1.6 DEVICE INPUT SIGNAL MODULE INPUT NAME TA1CLK TACLK ACLK (internal) ACLK SMCLK (internal) SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer N/A CCR0 TA0 DEVICE OUTPUT SIGNAL CCI0A Timer0_A3 CCR0B output (internal) CCI0B DVSS GND DVCC VCC TA1.1 CCI1A Timer0_A3 CCR1B output (internal) CCI1B DVSS GND P1.5 DVCC VCC TA1.2 CCI2A Timer0_A3 CCR2B output (internal) CCI2B DVSS GND DVCC VCC P1.4 TA1.1 CCR1 TA1 to ADC trigger TA1.2 CCR2 TA2 IR Input The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MP430FR4xx and MP430FR2xx Family User's Guide. The Timer2_A2 and Timer3_A2 modules are 16-bit timers and counters with two capture/compare registers each. Both timers support multiple captures or compares and interval timing (see Table 6-13 and Table 6-14). Both timers have extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each capture register. The CCR0 registers on Timer2_TA2 and Timer3_TA2 are not externally connected and can be used only for hardware period timing and interrupt generation. In Up mode, these CCR0 registers can be used to set the overflow value of the counter. Timer2_A2 and Timer3_A2 are only internally connected and do not support PWM output. Table 6-13. Timer2_A2 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME ACLK (internal) ACLK SMCLK (internal) SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer N/A CCR0 TA0 CCR1 CCR1 DEVICE OUTPUT SIGNAL CCI0A CCI0B DVSS GND DVCC VCC Timer3_A3 CCI0B input CCI1A CCI1B DVSS GND DVCC VCC Timer3_A3 CCI1B input Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 57 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 6-14. Timer3_A2 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT NAME ACLK (internal) ACLK SMCLK (internal) SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer N/A CCR0 TA0 CCR1 CCR1 DEVICE OUTPUT SIGNAL CCI0A Timer3_A3 CCI0B input CCI0B DVSS GND DVCC VCC CCI1A Timer3_A3 CCI1B input CCI1B DVSS GND DVCC VCC 6.10.9 Hardware Multiplier (MPY) The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication, unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations. 6.10.10 Backup Memory (BAKMEM) The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are retained during LPM3.5. 6.10.11 Real-Time Clock (RTC) The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module may periodically wake up the CPU from LPM0, LPM3, and LPM3.5 based on timing from a low-power clock source such as the XT1 and VLO clocks. In AM, SMCLK can drive the RTC to generate high-frequency timing events and interrupts. The RTC overflow events trigger: • Timer0_A3 CCR1B • ADC conversion trigger when ADCSHSx bits are set as 01b 58 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.10.12 10-Bit Analog-to-Digital Converter (ADC) The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The module implements a 10-bit SAR core, sample select control, reference generator and a conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags. The ADC supports 10 external inputs and 4 internal inputs (see Table 6-15). Table 6-15. ADC Channel Connections ADCINCHx ADC CHANNELS EXTERNAL PINOUT 0 A0/Veref+ P1.0 1 A1 P1.1 2 A2/Veref- P1.2 3 A3 P1.3 4 (1) A4 (1) P1.4 5 A5 P1.5 6 A6 P1.6 7 A7 P1.7 8 A8 NA 9 A9 NA 10 Not used N/A 11 Not used N/A 12 On-chip temperature sensor N/A 13 Reference voltage (1.5 V) N/A 14 DVSS N/A 15 DVCC N/A When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM control register. The 1.2-V voltage can be directly measured by A4 channel. Software or a hardware trigger can start the analog-to-digital conversion. Table 6-16 lists the trigger sources that are available. Table 6-16. ADC Trigger Signal Connections ADCSHSx TRIGGER SOURCE BINARY DECIMAL 00 0 ADCSC bit (software trigger) 01 1 RTC event 10 2 TA1.1B 11 3 -- Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 59 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.10.13 CapTIvate Technology The CapTIvate module detects the capacitance changed with a charge-transfer method and is functional in AM, LPM0, LPM3, and LPM4. The CapTIvate module can periodically wake the CPU from LPM0, LPM3, or LPM4 based on a CapTIvate timer source such as ACLK or VLO clock. The CapTIvate module supports the following touch-sensing capability: • Up to 64 CapTIvate buttons composed of 4 CapTIvate blocks. Each block consists of 4 I/Os, and these blocks scan in parallel of 4 electrodes. • Each block can be individually configured in self or mutual mode. Each CapTIvate I/O can be used for either self or mutual electrodes. • Supports a wake-on-touch state machine. • Supports synchronized conversion on a zero-crossing event trigger. • Processing logic to perform filter calculation and threshold detection. To learn more about MSP MCUs featuring CapTIvate technology, see the CapTIvate™ Technology Guide. 6.10.14 Embedded Emulation Module (EEM) The EEM supports real-time in-system debugging. The EEM on these devices has the following features: • Three hardware triggers or breakpoints on memory access • One hardware trigger or breakpoint on CPU register write access • Up to four hardware triggers that can be combined to form complex triggers or breakpoints • One cycle counter • Clock control on module level • EEM version: S 60 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.11 Input/Output Diagrams 6.11.1 Port P1 Input/Output With Schmitt Trigger Figure 6-1 shows the port diagram. Table 6-17 summarizes the selection of pin function. A0..A7 From SYS (ADCPCTLx) P1REN.x P1DIR.x From Module1 00 01 10 11 2 bit DVSS 0 DVCC 1 00 01 10 11 P1OUT.x From Module1 From Module2 DVSS 2 bit P1SEL.x EN To module D P1IN.x P1IE.x P1 Interrupt Q D S P1IFG.x P1IES.x From JTAG Edge Select Bus Keeper P1.0/UCB0STE/TA0CLK/A0/Veref+ P1.1/UCB0CLK/TA0.1/A1 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VerefP1.3/UCB0SOMI/UCB0SCL/MCLK/A3 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 P1.7/UCA0STE/SMCLK/TDO/A7 To JTAG Figure 6-1. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 61 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 6-17. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) x P1.0/UCB0STE/ TA0CLK/A0 0 P1.1/UCB0CLK/TA0.1/ A1 1 FUNCTION P1DIR.x P1SELx ADCPCTLx (2) JTAG P1.0 (I/O) I: 0; O: 1 00 0 N/A UCB0STE X 01 0 N/A TA0CLK 0 10 0 N/A A0/Veref+ X X 1 (x = 0) N/A P1.1 (I/O) I: 0; O: 1 00 0 N/A UCB0CLK X 01 0 N/A TA0.CCI1A 0 TA0.1 1 10 0 N/A A1 X X 1 (x = 1) N/A I: 0; O: 1 00 0 N/A UCB0SIMO/UCB0SDA X 01 0 N/A TA0.CCI2A 0 TA0.2 1 10 0 N/A P1.2 (I/O) P1.2/UCB0SIMO/ UCB0SDA/TA0.2/A2 2 P1.3/UCB0SOMI/ UCB0SCL/MCLK/A3 3 A2/Veref- X X 1 (x = 2) N/A P1.3 (I/O) I: 0; O: 1 00 0 N/A UCB0SOMI/UCB0SCL X 01 0 N/A MCLK 1 10 0 N/A A3 X X 1 (x = 3) N/A P1.4 (I/O) P1.4/UCA0TXD/ UCA0SIMO/TA1.2/TCK/ A4 /VREF+ P1.5/UCA0RXD/ UCA0SOMI/TA1.1/TMS/ A5 P1.6/UCA0CLK/ TA1CLK/TDI/TCLK/A6 62 5 6 P1.7/UCA0STE/SMCLK/ TDO/A7 (1) (2) 4 7 CONTROL BITS AND SIGNALS (1) I: 0; O: 1 00 0 Disabled UCA0TXD/UCA0SIMO X 01 0 Disabled TA1.CCI2A 0 TA1.2 1 10 0 Disabled A4, VREF+ X X 1 (x = 4) Disabled JTAG TCK X X X TCK P1.5 (I/O) I: 0; O: 1 00 0 Disabled UCA0RXD/UCA0SOMI X 01 0 Disabled TA1.CCI1A 0 TA1.1 1 10 0 Disabled A5 X X 1 (x = 5) Disabled JTAG TMS X X X TMS P1.6 (I/O) I: 0; O: 1 00 0 Disabled UCA0CLK X 01 TA1CLK 0 10 0 A6 X X 1 (x = 6) Disabled JTAG TDI/TCLK X X X TDI/TCLK P1.7 (I/O) I: 0; O: 1 00 0 Disabled UCA0STE X 01 0 Disabled SMCLK 1 10 0 Disabled A7 X X 1 (x = 7) Disabled JTAG TDO X X X TDO Disabled Disabled X = don't care Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied. Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger Figure 6-2 shows the port diagram. Table 6-18 summarizes the selection of pin function. P2REN.x P2DIR.x 00 01 10 11 2 bit DVSS 0 DVCC 1 00 01 10 11 P2OUT.x From Module1 DVSS DVSS 2 bit P2SEL.x EN D To module P2IN.x P2IE.x P2 Interrupt Q D S P2IFG.x Bus Keeper P2.0/XOUT P2.1/XIN P2.2/SYNC/ACLK Edge Select P2IES.x Figure 6-2. Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger Table 6-18. Port P2 (P2.0 to P2.2) Pin Functions PIN NAME (P2.x) x P2.0/XOUT 0 P2.1/XIN 1 FUNCTION P2DIR.x P2SELx I: 0; O: 1 00 X 01 I: 0; O: 1 00 X 01 I: 0; O: 1 00 SYNC 0 01 ACLK 1 10 P2.0 (I/O) XOUT P2.1 (I/O) XIN P2.2 (I/O) P2.2/SYNC/ACLK (1) 2 CONTROL BITS AND SIGNALS (1) X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 63 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger Figure 6-3 shows the port diagram. Table 6-19 summarizes the selection of pin function. CAP0.2, CAP1.1, CAP1.2 CAP1.3, CAP3.0 From CapTIvate P2REN.x P2DIR.x From Module1 00 01 10 11 2 bit DVSS 0 DVCC 1 00 01 10 11 P2OUT.x From Module1 DVSS DVSS 2 bit P2SEL.x EN To module D P2IN.x P2IE.x P2 Interrupt Q D S P2IFG.x P2IES.x Edge Select Bus Keeper P2.3/CAP0.2 P2.4/UCA1CLK/CAP1.1 P2.5/UCA1RXD/UCA1SOMI/CAP1.2 P2.6/UCA1TXD/UCA1SIMO/CAP1.3 P2.7/CAP3.0 Figure 6-3. Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger 64 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-19. Port P2 (P2.3 to P2.7) Pin Functions CONTROL BITS AND SIGNALS (1) PIN NAME (P2.x) P2.3/CAP0.2 P2.4/UCA1CLK/ CAP1.1 x 3 FUNCTION P2.3 (I/O) CAP0.2 4 P2.7/CAP3.0 (1) 6 7 I: 0; O: 1 00 0 X X 1 00 0 UCA1CLK X 01 0 X X 1 I: 0; O: 1 00 0 UCA1RXD/UCA1SOMI X 01 0 CAP1.2 X X 1 P2.6 (I/O) P2.6/UCA1TXD/ UCA1SIMO/CAP1.3 ANALOG FUNCTION I: 0; O: 1 P2.5 (I/O) 5 P2SELx P2.4 (I/O) CAP1.1 P2.5/UCA1RXD/ UCA1SOMI/CAP1.2 P2DIR.x I: 0; O: 1 00 0 UCA1TXD/UCA1SIMO X 01 0 CAP1.3 X X 1 I: 0; O: 1 0 0 X X 1 P2.7 (I/O) CAP3.0 X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 65 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger Figure 6-4 shows the port diagram. Table 6-20 summarizes the selection of pin function. CAP0.0, CAP1.0, CAP3.2 From CapTIvate P3REN.x P3DIR.x From Module1 00 01 10 11 2 bit DVSS 0 DVCC 1 00 01 10 11 P3OUT.x From Module1 DVSS DVSS 2 bit P3SEL.x EN To module D P3IN.x Bus Keeper P3.0/CAP0.0 P3.1/UCA1STE/CAP1.0 P3.2/CAP3.2 Figure 6-4. Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger NOTE CapTIvate shared with I/Os configuration The CapTIvate function and GPIOs are powered by different power supplies (1.5 V and 3.3 V, respectively). To prevent pad damage when changing the function, TI recommends checking the external application circuit of each pad before enabling the alternate function. 66 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-20. Port P3 (P3.0 to P3.2) Pin Functions CONTROL BITS AND SIGNALS (1) PIN NAME (P3.x) P3.0/CAP0.0 P3.1/UCA1STE/ CAP1.0 x 0 1 FUNCTION P3.0 (I/O) CAP0.0 (1) 2 P3SEL.x ANALOG FUNCTION I: 0; O: 1 00 0 X X 1 P3.1 (I/O) I: 0; O: 1 00 0 UCA1STE X 01 0 CAP1.0 P3.2/CAP3.2 P3DIR.x P3.2 (I/O) CAP3.2 X X 1 I: 0; O: 1 00 0 X X 1 X = don't care Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 67 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.12 Device Descriptors Table 6-21 lists the Device IDs of the devices. Table 6-22 lists the contents of the device descriptor taglength-value (TLV) structure for the devices. Table 6-21. Device IDs DEVICE ID DEVICE 1A05h 1A04h MSP430FR2633 82h 3Ch MSP430FR2533 82h 3Dh MSP430FR2632 82h 3Eh MSP430FR2532 82h 3Fh Table 6-22. Device Descriptors DESCRIPTION ADDRESS VALUE Info length 1A00h 06h CRC length 1A01h 06h 1A02h Per unit 1A03h Per unit CRC value (1) Information Block Device ID See Table 6-21. 1A06h Per unit 1A07h Per unit Die record tag 1A08h 08h Die Record Die X position Die Y position Test result 1A09h 0Ah 1A0Ah Per unit 1A0Bh Per unit 1A0Ch Per unit 1A0Dh Per unit 1A0Eh Per unit 1A0Fh Per unit 1A10h Per unit 1A11h Per unit 1A12h Per unit 1A13h Per unit ADC calibration tag 1A14h Per unit ADC calibration length 1A15h Per unit 1A16h Per unit 1A17h Per unit 1A18h Per unit ADC gain factor ADC offset ADC 1.5-V reference temperature 30°C ADC 1.5-V reference temperature 85°C 68 1A05h Firmware revision Lot wafer ID (1) 1A04h Hardware revision Die record length ADC Calibration MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 1A19h Per unit 1A1Ah Per unit 1A1Bh Per unit 1A1Ch Per unit 1A1Dh Per unit The CRC value covers the checksum from 0x1A04h to 0x1AF5h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1. Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-22. Device Descriptors (continued) MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 DESCRIPTION ADDRESS VALUE Calibration tag 1A1Eh 12h Calibration length 1A1Fh 04h 1A20h Per unit 1A21h Per unit 1A22h Per unit 1A23h Per unit Reference and DCO Calibration 1.5-V reference factor DCO tap setting for 16 MHz, temperature 30°C (2) (2) This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature, especially when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature drift might result an overshoot beyond 16 MHz. 6.13 Memory 6.13.1 Memory Organization Table 6-23 summarizes the memory map of the devices. Table 6-23. Memory Organization ACCESS MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Read/Write (Optional Write Protect) (1) 15KB FFFFh to FF80h FFFFh to C400h 8KB FFFFh to FF80h FFFFh to E000h 15KB FFFFh to FF80h FFFFh to C400h 8KB FFFFh to FF80h FFFFh to E000h Read/Write 4KB 2FFFh to 2000h 2KB 27FFh to 2000h 2KB 27FFh to 2000h 1KB 23FFh to 2000h Read/Write (Optional Write Protect) (2) 512 bytes 19FFh to 1800h 512 bytes 19FFh to 1800h 512 bytes 19FFh to 1800h 512 bytes 19FFh to 1800h Bootstrap loader (BSL1) Memory (ROM) Read only 2KB 17FFh to 1000h 2KB 17FFh to 1000h 2KB 17FFh to 1000h 2KB 17FFh to 1000h Bootstrap loader (BSL2) Memory (ROM) Read only 1KB FFFFFh to FFC00h 1KB FFFFFh to FFC00h 1KB FFFFFh to FFC00h 1KB FFFFFh to FFC00h CapTIvate Libraries and Driver Libraries (ROM) Read only 12KB 6FFFh to 4000h 12KB 6FFFh to 4000h 12KB 6FFFh to 4000h 12KB 6FFFh to 4000h Peripherals Read/Write 4KB 0FFFh to 0000h 4KB 0FFFh to 0000h 4KB 0FFFh to 0000h 4KB 0FFFh to 0000h Memory (FRAM) Main: interrupt vectors and signatures Main: code memory RAM Information Memory (FRAM) (1) (2) The Program FRAM can be write protected by setting the PFWP bit in the SYSCFG0 register. See the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide for more details. The Information FRAM can be write protected by setting the DFWP bit in the SYSCFG0 register. See the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide for more details. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 69 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 6.13.2 Peripheral File Map Table 6-24 lists the available peripherals and the register base address for each. Table 6-25 to list the registers and address offsets for each peripheral. Table 6-24. Peripherals Summary BASE ADDRESS SIZE Special Functions (See Table 6-25) MODULE NAME 0100h 0010h PMM (See Table 6-26) 0120h 0020h SYS (See Table 6-27) 0140h 0040h CS (See Table 6-28) 0180h 0020h FRAM (See Table 6-29) 01A0h 0010h CRC (See Table 6-30) 01C0h 0008h WDT (See Table 6-31) 01CCh 0002h Port P1, P2 (See Table 6-32) 0200h 0020h Port P3 (See Table 6-33) 0220h 0020h RTC (See Table 6-34) 0300h 0010h Timer0_A3 (See Table 6-35) 0380h 0030h Timer1_A3 (See Table 6-36) 03C0h 0030h Timer2_A2 (See Table 6-37) 0400h 0030h Timer3_A2 (See Table 6-38) 0440h 0030h MPY32 (See Table 6-39) 04C0h 0030h eUSCI_A0 (See Table 6-40) 0500h 0020h eUSCI_A1 (See Table 6-41) 0520h 0020h eUSCI_B0 (See Table 6-42) 0540h 0030h Backup Memory (See Table 6-43) 0660h 0020h ADC (See Table 6-44) 0700h 0040h CapTIvate (See CapTivate Design Center for details) 0A00h 0200h Table 6-25. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION SFR interrupt enable SFR interrupt flag SFR reset pin control ACRONYM OFFSET SFRIE1 00h SFRIFG1 02h SFRRPCR 04h Table 6-26. PMM Registers (Base Address: 0120h) ACRONYM OFFSET PMM control 0 REGISTER DESCRIPTION PMMCTL0 00h PMM control 1 PMMCTL1 02h PMM control 2 PMMCTL2 04h PMM interrupt flags PMMIFG 0Ah PM5 control 0 PM5CTL0 10h 70 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-27. SYS Registers (Base Address: 0140h) REGISTER DESCRIPTION ACRONYM OFFSET SYSCTL 00h Bootloader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System control System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh System configuration 0 SYSCFG0 20h System configuration 1 SYSCFG1 22h System configuration 2 SYSCFG2 24h Table 6-28. CS Registers (Base Address: 0180h) ACRONYM OFFSET CS control 0 REGISTER DESCRIPTION CSCTL0 00h CS control 1 CSCTL1 02h CS control 2 CSCTL2 04h CS control 3 CSCTL3 06h CS control 4 CSCTL4 08h CS control 5 CSCTL5 0Ah CS control 6 CSCTL6 0Ch CS control 7 CSCTL7 0Eh CS control 8 CSCTL8 10h Table 6-29. FRAM Registers (Base Address: 01A0h) REGISTER DESCRIPTION ACRONYM OFFSET FRAM control 0 FRCTL0 00h General control 0 GCCTL0 04h General control 1 GCCTL1 06h Table 6-30. CRC Registers (Base Address: 01C0h) REGISTER DESCRIPTION ACRONYM OFFSET CRC16DI 00h CRC data input reverse byte CRCDIRB 02h CRC initialization and result CRCINIRES 04h CRC result reverse byte CRCRESR 06h CRC data input Table 6-31. WDT Registers (Base Address: 01CCh) REGISTER DESCRIPTION Watchdog timer control ACRONYM OFFSET WDTCTL 00h Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 71 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 6-32. Port P1, P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION ACRONYM OFFSET P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 input Port P1 pulling enable P1REN 06h Port P1 selection 0 P1SEL0 0Ah Port P1 selection 1 P1SEL1 0Ch Port P1 interrupt vector word P1IV 0Eh Port P1 complement selection P1SELC 16h Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable Port P1 interrupt flag Port P2 input P1IE 1Ah P1IFG 1Ch P2IN 01h P2OUT 03h Port P2 direction P2DIR 05h Port P2 pulling enable P2REN 07h Port P2 selection 0 P2SEL0 0Bh Port P2 selection 1 Port P2 output P2SEL1 0Dh Port P2 interrupt vector word P2IV 1Eh Port P2 complement selection P2SELC 17h Port P2 interrupt edge select P2IES 19h P2IE 1Bh P2IFG 1Dh Port P2 interrupt enable Port P2 interrupt flag Table 6-33. Port P3 Registers (Base Address: 0220h) REGISTER DESCRIPTION ACRONYM OFFSET P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 pulling enable P3REN 06h Port P3 selection 0 P3SEL0 0Ah Port P3 selection 1 P3SEL1 0 Port P3 complement selection P3SELC 16h Port P3 input Table 6-34. RTC Registers (Base Address: 0300h) REGISTER DESCRIPTION RTC control RTC interrupt vector ACRONYM OFFSET RTCCTL 00h RTCIV 04h RTC modulo RTCMOD 08h RTC counter RTCCNT 0Ch 72 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-35. Timer0_A3 Registers (Base Address: 0380h) REGISTER DESCRIPTION ACRONYM OFFSET TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h TA0R 10h Capture/compare 0 TA0CCR0 12h Capture/compare 1 TA0CCR1 14h Capture/compare 2 TA0CCR2 16h TA0EX0 20h TA0IV 2Eh TA0 control TA0 counter TA0 expansion 0 TA0 interrupt vector Table 6-36. Timer1_A3 Registers (Base Address: 03C0h) REGISTER DESCRIPTION TA1 control ACRONYM OFFSET TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1R 10h Capture/compare 0 TA1CCR0 12h Capture/compare 1 TA1CCR1 14h Capture/compare 2 TA1CCR2 16h TA1 counter TA1 expansion 0 TA1 interrupt vector TA1EX0 20h TA1IV 2Eh Table 6-37. Timer2_A2 Registers (Base Address: 0400h) REGISTER DESCRIPTION TA2 control ACRONYM OFFSET TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h TA2 counter TA2R 10h Capture/compare 0 TA2CCR0 12h Capture/compare 1 TA2CCR1 14h TA2EX0 20h TA2IV 2Eh TA2 expansion 0 TA2 interrupt vector Table 6-38. Timer3_A2 Registers (Base Address: 0440h) REGISTER DESCRIPTION ACRONYM OFFSET TA3CTL 00h Capture/compare control 0 TA3CCTL0 02h Capture/compare control 1 TA3CCTL1 04h TA3R 10h Capture/compare 0 TA3CCR0 12h Capture/compare 1 TA3CCR1 14h TA3 control TA3 counter TA3 expansion 0 TA3 interrupt vector TA3EX0 20h TA3IV 2Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 73 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 6-39. MPY32 Registers (Base Address: 04C0h) REGISTER DESCRIPTION 16-bit operand 1 – multiply 16-bit operand 1 – signed multiply 16-bit operand 1 – multiply accumulate 16-bit operand 1 – signed multiply accumulate 16-bit operand 2 16 × 16 result low word 16 × 16 result high word ACRONYM OFFSET MPY 00h MPYS 02h MAC 04h MACS 06h OP2 08h RESLO 0Ah RESHI 0Ch 16 × 16 sum extension SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h MAC32L 18h 32-bit operand 1 – multiply accumulate low word 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32CTL0 2Ch MPY32 control 0 Table 6-40. eUSCI_A0 Registers (Base Address: 0500h) REGISTER DESCRIPTION ACRONYM OFFSET eUSCI_A control word 0 UCA0CTLW0 00h eUSCI_A control word 1 UCA0CTLW1 02h eUSCI_A control rate 0 UCA0BR0 06h UCA0BR1 07h eUSCI_A control rate 1 eUSCI_A modulation control UCA0MCTLW 08h UCA0STAT 0Ah eUSCI_A receive buffer UCA0RXBUF 0Ch eUSCI_A transmit buffer UCA0TXBUF 0Eh eUSCI_A LIN control UCA0ABCTL 10h eUSCI_A IrDA transmit control lUCA0IRTCTL 12h eUSCI_A IrDA receive control IUCA0IRRCTL 13h UCA0IE 1Ah UCA0IFG 1Ch UCA0IV 1Eh eUSCI_A status eUSCI_A interrupt enable eUSCI_A interrupt flags eUSCI_A interrupt vector word 74 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Table 6-41. eUSCI_A1 Registers (Base Address: 0520h) ACRONYM OFFSET eUSCI_A control word 0 REGISTER DESCRIPTION UCA1CTLW0 00h eUSCI_A control word 1 UCA1CTLW1 02h eUSCI_A control rate 0 UCA1BR0 06h UCA1BR1 07h eUSCI_A control rate 1 eUSCI_A modulation control UCA1MCTLW 08h UCA1STAT 0Ah eUSCI_A receive buffer UCA1RXBUF 0Ch eUSCI_A transmit buffer UCA1TXBUF 0Eh eUSCI_A LIN control UCA1ABCTL 10h eUSCI_A IrDA transmit control lUCA1IRTCTL 12h eUSCI_A IrDA receive control IUCA1IRRCTL 13h UCA1IE 1Ah UCA1IFG 1Ch UCA1IV 1Eh eUSCI_A status eUSCI_A interrupt enable eUSCI_A interrupt flags eUSCI_A interrupt vector word Table 6-42. eUSCI_B0 Registers (Base Address: 0540h) ACRONYM OFFSET eUSCI_B control word 0 REGISTER DESCRIPTION UCB0CTLW0 00h eUSCI_B control word 1 UCB0CTLW1 02h eUSCI_B bit rate 0 UCB0BR0 06h eUSCI_B bit rate 1 UCB0BR1 07h eUSCI_B status word UCB0STATW 08h eUSCI_B byte counter threshold UCB0TBCNT 0Ah eUSCI_B receive buffer UCB0RXBUF 0Ch eUSCI_B transmit buffer UCB0TXBUF 0Eh eUSCI_B I2C own address 0 UCB0I2COA0 14h eUSCI_B I2C own address 1 UCB0I2COA1 16h eUSCI_B I2C own address 2 UCB0I2COA2 18h eUSCI_B I2C own address 3 UCB0I2COA3 1Ah UCB0ADDRX 1Ch UCB0ADDMASK 1Eh eUSCI_B receive address eUSCI_B address mask eUSCI_B I2C slave address eUSCI_B interrupt enable eUSCI_B interrupt flags eUSCI_B interrupt vector word UCB0I2CSA 20h UCB0IE 2Ah UCB0IFG 2Ch UCB0IV 2Eh Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 75 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 6-43. Backup Memory Registers (Base Address: 0660h) ACRONYM OFFSET Backup memory 0 REGISTER DESCRIPTION BAKMEM0 00h Backup memory 1 BAKMEM1 02h Backup memory 2 BAKMEM2 04h Backup memory 3 BAKMEM3 06h Backup memory 4 BAKMEM4 08h Backup memory 5 BAKMEM5 0Ah Backup memory 6 BAKMEM6 0Ch Backup memory 7 BAKMEM7 0Eh Backup memory 8 BAKMEM8 10h Backup memory 9 BAKMEM9 12h Backup memory 10 BAKMEM10 14h Backup memory 11 BAKMEM11 16h Backup memory 12 BAKMEM12 18h Backup memory 13 BAKMEM13 1Ah Backup memory 14 BAKMEM14 1Ch Backup memory 15 BAKMEM15 1Eh Table 6-44. ADC Registers (Base Address: 0700h) REGISTER DESCRIPTION ACRONYM OFFSET ADC control 0 ADCCTL0 00h ADC control 1 ADCCTL1 02h ADC control 2 ADCCTL2 04h ADCLO 06h ADC window comparator low threshold ADC window comparator high threshold ADCHI 08h ADC memory control 0 ADCMCTL0 0Ah ADC conversion memory ADCMEM0 12h ADC interrupt enable ADC interrupt flags ADC interrupt vector word 76 Detailed Description ADCIE 1Ah ADCIFG 1Ch ADCIV 1Eh Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 6.14 Identification 6.14.1 Revision Identification The device revision information is included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see 节 8.4). The hardware revision is also stored in the Device Descriptor structure in the Information Block section. For details on this value, see the Hardware Revision entries in Table 6-22. 6.14.2 Device Identification The device type can be identified from the top-side marking on the device package. The device-specific errata sheet describes these markings (see 节 8.4). A device identification value is also stored in the Device Descriptor structure in the Information Block section. For details on this value, see the Device ID entries in Table 6-22. 6.14.3 JTAG Identification Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in MSP430 Programming With the JTAG Interface. Detailed Description Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 77 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn 7 Applications, Implementation, and Layout NOTE Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 7.1 Device Connection and Layout Fundamentals This section discusses the recommended guidelines when designing with the MSP430 devices. These guidelines are to make sure that the device has proper connections for powering, programming, debugging, and optimum analog performance. 7.1.1 Power Supply Decoupling and Bulk Capacitors TI recommends connecting a combination of a 10-µF and a 100-nF low-ESR ceramic decoupling capacitor to the DVCC and DVSS pins (see Figure 7-1). Higher-value capacitors may be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). Additionally, TI recommends separated grounds with a single-point connection for better noise isolation from digital-to-analog circuits on the board and to achieve high analog accuracy. DVCC Digital Power Supply Decoupling + 10 µF 100 nF DVSS Figure 7-1. Power Supply Decoupling 7.1.2 External Oscillator This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass capacitors for the crystal oscillator pins are required. It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT pin can be used for other purposes. If the XIN and XOUT pins are not used, they must be terminated according to Section 4.6. Figure 7-2 shows a typical connection diagram. XIN CL1 XOUT CL2 Figure 7-2. Typical Crystal Connection 78 Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal oscillator with the MSP430 devices. 7.1.3 JTAG With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the connections also support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG connector and the target device required to support in-system programming and debugging for 4-wire JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire). The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). The VCC sense feature detects the local VCC present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same time. For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's Guide. VCC Important to connect MSP430FRxxx J1 (see Note A) DVCC J2 (see Note A) R1 47 kW JTAG VCC TOOL VCC TARGET TEST 2 RST/NMI/SBWTDIO 1 4 3 6 5 8 7 10 9 12 11 14 13 TDO/TDI TDI TDO/TDI TDI TMS TMS TCK TCK GND RST TEST/SBWTCK C1 1 nF (see Note B) A. B. DVSS If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2. The upper limit for C1 is 1.1 nF when using current TI tools. Figure 7-3. Signal Connections for 4-Wire JTAG Communication Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 79 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn VCC Important to connect MSP430FRxxx J1 (see Note A) DVCC J2 (see Note A) R1 47 kΩ (see Note B) JTAG VCC TOOL VCC TARGET 2 1 4 3 6 5 8 7 10 9 12 11 14 13 TDO/TDI RST/NMI/SBWTDIO TCK GND TEST/SBWTCK C1 1 nF (see Note B) A. B. DVSS Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or programming adapter. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 1.1 nF when using current TI tools. Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) 7.1.4 Reset The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function Register (SFR), SFRRPCR. In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing specifications generates a BOR-type device reset. Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI. When an external NMI event occurs, the NMIIFG is set. The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩ pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers. See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced control registers and bits. 7.1.5 Unused Pins For details on the connection of unused pins, see Section 4.6. 80 Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn 7.1.6 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 General Layout Recommendations • • • • 7.1.7 Proper grounding and short traces for external crystal to reduce parasitic capacitance. For recommended layout guidelines, see MSP430 32-kHz Crystal Oscillators. Proper bypass capacitors on DVCC and reference pins, if used. Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals. Proper ESD level protection should be considered to protect the device from unintended high-voltage electrostatic discharge. For guidelines see MSP430 System-Level ESD Considerations. Do's and Don'ts During power up, power down, and device operation, DVCC must not exceed the limits specified in Section 5.1. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM. 7.2 Peripheral- and Interface-Specific Design Information 7.2.1 ADC Peripheral 7.2.1.1 Partial Schematic Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. DVSS Using an external positive reference VREF+/VEREF+ + 10 µF 100 nF Using an external negative reference VEREF+ 10 µF 100 nF Figure 7-5. ADC Grounding and Noise Considerations 7.2.1.2 Design Requirements As with any high-resolution ADC, appropriate PCB layout and grounding techniques must be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the ADC flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the ADC. The general guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this. Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep the ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power mode during the ADC conversion improves the ADC performance in a noisy environment. If the device includes the analog power pair inputs (AVCC and AVSS), TI recommends a noise-free design using separate analog and digital ground planes with a single-point connection to achieve high accuracy. Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The internal reference module has a maximum drive current as described in the sections ADC Pin Enable and 1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 81 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency ripple. A bypass capacitor of 100 nF filters out any high-frequency noise. 7.2.1.3 Layout Guidelines Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as possible to the respective device pins to avoid long traces, because they add additional parasitic capacitance, inductance, and resistance on the signal. Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because the high-frequency switching can be coupled into the analog signal. 7.2.2 CapTIvate Peripheral This section provides a brief introduction to the CapTIvate technology with examples of PCB layout and performance from the design kit. A more detailed description of the CapTIvate technology and the tools needed to be successful, application development tools, hardware design guides, and software library, can be found in the CapTIvate™ Technology Guide. 7.2.2.1 Device Connection and Layout Fundamentals To learn more on how to design the CapTIvate Technology, see the Capacitive Touch Design Flow for MSP430™ MCUs With CapTIvate™ Technology application report. 82 Applications, Implementation, and Layout Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn 7.2.2.2 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 Measurements The following measurements are taken from the CapTIvate Technology Design Center, using the CAPTIVATE-PHONE and CAPTIVATE-BSWP panels. Unless otherwise stated, the settings used are the out-of-box settings, which can be found in the example projects. The intent of these measurements is to show performance in a configuration that is readily available and reproducible. Figure 7-6. CAPTIVATE-PHONE and CAPTIVATE-BSWP Panels 7.2.2.2.1 SNR The Sensitivity, SNR, and Design Margin in Capacitive Touch Applications application report provides a specific view for analyzing the signal-to-noise ratio of each element. 7.2.2.2.2 Sensitivity To show sensitivity, in terms of farads, the internal reference capacitor is used as the change in capacitance. In the mutual-capacitance case, the 0.1-pF capacitor is used. In the self-capacitance case, the 1-pF reference capacitor is used. For simplicity, the results for only button 1 on both the CAPTIVATEPHONE and CAPTIVATE-BSWP panels are reported in Table 7-1. Table 7-1. Button Sensitivity CAPTIVATE-PHONE BUTTON 1 CAPTIVATE-BSWP BUTTON 1 CONVERSION COUNT CONVERSION GAIN 100 100 25 6 50 8 200 200 50 10 100 16 200 100 50 21 100 31 800 400 200 70 400 112 800 200 200 140 400 202 800 100 200 257 400 333 CONVERSION TIME (µs) COUNTS FOR 0.1-pF CHANGE CONVERSION TIME (µs) COUNTS FOR 1-pF CHANGE An alternative measure in sensitivity is the ability to resolve capacitance change over a wide range of base capacitance. Table 7-2 shows example conversion times (for a self-mode measurement of discrete capacitors) that can be used to achieve the desired resolution for a given parasitic load capacitance. Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 Copyright © 2015–2019, Texas Instruments Incorporated 83 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 www.ti.com.cn Table 7-2. Button Sensitivity CAPACITANCE, Cp (pF) (1) CONVERSION COUNT/GAIN CONVERSION TIME (µs) COUNTS FOR 0.130-pF CHANGE COUNTS FOR 0.260-pF CHANGE COUNTS FOR 0.520-pF CHANGE 23 400/100 200 10 23 35 50 550/100 275 11 24 37 78 650/100 325 11 23 36 150 850/100 425 11 22 35 150 (2) 1200/200 600 11 23 37 (2) 1200/150 600 13 26 41 200 (1) (2) These measurements were taken with the CapTIvate MCU processor board with the 470-Ω series resistors replaced with 0-Ω resistors. 0-V discharge voltage is used. 7.2.2.2.3 Power The low-power mode LPM3 specifications in Section 5.7 are derived from the CapTIvate technology design kit as indicated in the notes. 7.3 CapTIvate Technology Evaluation Table 7-3 lists tools that demonstrate the use of the MSP430FR263x devices. See CapTIvate Evaluation Tools to get started with evaluating the CapTIvate technology in various real-world application scenarios. Consult these evaluation tool designs for additional guidance regarding schematics, layout, and software implementation. Table 7-3. Evaluation Tools NAME LINK MSP CapTIvate MCU Development Kit http://www.ti.com/tool/msp-capt-fr2633 Capacitive Touch Thermostat User Interface Reference Design http://www.ti.com/tool/tidm-captivate-thermostat-ui 84 Applications, Implementation, and Layout 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 8 器件和文档支持 8.1 入门和后续步骤 更过有关 MSP 低功耗微控制器以及开发协助工具和库的信息，请访问《MSP430™ 超低功耗传感和测量 MCU 概述》。 8.2 器件命名规则 为了标示产品开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用 系列产品成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了产品开发的发展阶段，即从工程原 型 (XMS) 直到完全合格的生产器件 (MSP)。 XMS - 实验器件，不一定代表最终器件的电气规格 MSP - 完全合格的生产器件 XMS 器件在供货时附带如下免责声明： “开发中的产品用于内部评估用途。” MSP 用。 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适 预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，德 州仪器 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。 TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。图 81 提供了解读完整器件名称的图例。 MSP 430 FR 2 633 I RHB R Distribution Format Processor Family MCU Platform Packaging Memory Type Series Processor Family Temperature Range Feature Set MSP = Mixed-signal processor XMS = Experimental silicon MCU Platform 430 = MSP430 16-bit low-power platform Memory Type Series FR = FRAM Feature Set (see note) CapTIvate Performance 633 = 4 CapTIvate blocks, 16KB of FRAM, 4KB of SRAM, up to 16 CapTIvate I/Os 533 = 4 CapTIvate blocks, 16KB of FRAM, 2KB of SRAM, up to 16 CapTIvate I/Os 632 = 4 CapTIvate blocks, 8KB of FRAM, 2KB of SRAM, up to 8 CapTIvate I/Os 532 = 4 CapTIvate blocks, 8KB of FRAM, 1KB of SRAM, up to 8 CapTIvate I/Os Temperature Range I = –40°C to 85°C 2 = Up to 16 MHz without LCD Packaging www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray NOTE: 有关采用 CapTIvate 触控技术的器件的更多指导，请参阅《CapTIvate 技术指南》中的器件选择基准。 图 8-1. 器件命名规则 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 器件和文档支持 85 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 8.3 www.ti.com.cn 工具和软件 所有 MSP 微控制器均受多种软件和硬件开发工具的支持。相关工具由 TI 以及多家第三方供应商提供。可从 低功耗 MCU 开发套件和软件获取全部信息。 表 8-1 列 调试 的调试功能。请参阅《适用于 MSP430 MCU 的 Code Composer Studio IDE 用户指南》， 以了解有关可用 功能）的详细信息。 表 8-1. 硬件调试 特性 MSP430 架构 四线制 JTAG 两线制 JTAG 断点 (N) 范围断点 时钟控制 状态序列发生器 跟踪缓冲器 LPMx.5 调试支 持 EEM 版本 MSP430Xv2 有 有 3 有 是 否 否 否 S 设计套件与评估模块 MSP CapTIvate MCU 开发套件 MSP CapTIvate MCU 开发套件是一种用于评估采用电容式触控技术的 MSP430FR2633 微控制器的易用综 合性平台。此套件包含基于 MSP430FR2633 的处理器板、采用 EnergyTrace 技术的编程器和调试器板（用 于通过 Code Composer Studio IDE 测量能耗），以及用于评估自电容、互电容、手势和接近传感的传感器 板。 软件 MSP430Ware 软件 MSP430Ware 是一套设计资源集，可帮助用户高效地创建和构建 MSP430 代码。MSP430Ware 包括各种 高度抽象的软件库，范围涵盖 MSP 驱动程序库或 USB 等特定于器件和外设的库，以及图形库和电容式触 控库等特定于应用的库。MSP430 驱动程序库是一个尤为重要的库，可以帮助软件开发人员利用便捷的 API 来控制错综复杂的低级别硬件外设，从而使生成的代码更易于读取和维护。 MSP430FR243x、MSP430FR253x、MSP430FR263x 代码示例 根据不同应用需求配置各集成外设的每个 MSP 器件均具备相应的 C 代码示例。 MSP 驱动程序库 MSP 驱动程序库的抽象 API 提供易用的函数调用，无需直接操纵 MSP430 硬件的位与字节。完整的文档通 过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证的参数的详细信息。开发人员可以 使用驱动程序库功能，以最低开销编写完整项目。 MSP EnergyTrace™ 技术 适用于 MSP430 微控制器的 EnergyTrace 技术是基于电能的代码分析工具，适用于测量和显示应用的电能 系统配置并帮助优化应用以实现超低功耗。 ULP（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，从而充分利用 MSP430 和 MSP432 微控制器 独特 功能。ULP Advisor 的目标人群是微控制器的资深开发者和开发新手，可以根据详 尽的 ULP 检验表检查代码，以便最大限度地减少应用程序的能耗。在编译时，ULP Advisor 会提供通知和 备注以突出显示代码中可以进一步优化的区域，进而实现更低功耗。 86 器件和文档支持 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 IEC60730 软件包 IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用及类似用途的自动化 电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、电弧检测器、电源转换器、电动工 具、电动自行车及其他诸多产品。IEC60730 MSP430 软件包可以嵌入在 MSP430 MCU 中 运行的客户应 用， 从而帮助客户简化其消费类器件在功能安全方面遵循 IEC 60730-1:2010 B 类规范的认证工作。 适用于 MSP 的定点数学库 MSP IQmath 和 Qmath 库是为 C 语言编程器提供的经过高度优化的高精度数学运算函数集合，能够将浮点 算法无缝嵌入 MSP430 和 MSP432 器件的定点代码中。这些例程通常用于计算密集型实时 应用， 而优化 的执行速度、高精度以及超低能耗通常是影响这些实时应用的关键因素。与使用浮点数学算法编写的同等代 码相比，使用 IQmath 和 Qmath 库可以大幅提高执行速度并显著降低能耗。 适用于 MSP430 的浮点数学库 TI 在低功耗和低成本微控制器领域锐意创新，为您提供 MSPMATHLIB。此标量函数的浮点数学库，能够充 分利用器件的智能外设，使速度最高达到标准 MSP430 数学函数的 26 倍。Mathlib 能够轻松集成到您的设 计中。该运算库免费使用并集成在 Code Composer Studio IDE 和 IAR Embedded Workbench IDE 中。 开发工具 适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio (CCS) 集成开发环境 (IDE) 支持所有 MSP 微控制器器件。CCS 包含一整套用于开 发和调试嵌入式 应用的工具。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环境、调试器、描 述器以及其他多种 功能。 命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过 FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或 .hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。 MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可让用户在 MSP 低功耗微控制器 (MCU) 上 快速进行应用开发。创建 MCU 软件通常需要将生成的二进制程序下载到 MSP 器件，以进行验证和调试。 MSP-FET 在主机和目标 MSP 间提供调试通信通道。此外，MSP-FET 还在计算机的 USB 接口和 MSP UART 之间提供反向通道 UART 连接。这为 MSP 编程器提供了一种便捷方法，实现了 MSP 和在计算机上 运行的终端之间的串行通信。 MSP-GANG 生产编程器 MSP Gang 编程器可同时对多达八个完全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定 义流程。MSP Gang 编程器配有扩展板“Gang 分离器”，可在 MSP Gang 编程器和多个目标器件间实现互 连。 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 器件和文档支持 87 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 8.4 www.ti.com.cn 文档支持 以下文档对 MSP430FR263x 和 MSP430FR253x MCU 进行了介绍。www.ti.com.cn 网站上提供了这些文档 的副本。 接收文档更新通知 如需接收文档更新通知（包括器件勘误表），请转至 ti.com.cn 上相关器件的产品文件夹（关于这些产品文 件夹的链接，请参阅节 8.5）。单击右上角的“提醒我”(Alert me) 按钮。点击注册后，即可收到产品信息更改 每周摘要（如有）。有关更改的详细信息，请查阅已修订文档的修订历史记录。 勘误 《MSP430FR2633 器件勘误表》 说明了功能规格的已知例外情况。 《MSP430FR2533 器件勘误表》 说明了功能规格的已知例外情况。 《MSP430FR2632 器件勘误表》 说明了功能规格的已知例外情况。 《MSP430FR2532 器件勘误表》 说明了功能规格的已知例外情况。 用户指南 《MSP430FR4xx 和 MSP430FR2xx 系列用户指南》 详细介绍了该器件系列提供的模块和外设。 《MSP430 FRAM 器件引导加载程序 (BSL) 用户指南》 在 MSP430 MCU 项目开发和更新阶段，引导加载程序 (BSL) 提供存储器的编程方法。该程序可由使用串行 协议发送命令的工具激活。BSL 支持用户控制 MSP430 MCU 的活动，可与个人计算机或其他设备进行数据 交换。 《MSP430 硬件工具用户指南》 此手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对 MSP430 超低功耗微控制器的程 序开发工具。 应用报告 MSP430 FRAM 技术 – 操作方法和最佳实践 FRAM 采用非易失性存储器技术，行为与 SRAM 类似，支持大量新 应用，还改变了固件的设计方式。该应 用程序报告从嵌入式软件开发方面概述了 FRAM 技术在 MSP430 中的使用方法和最佳实践。其中介绍了如 何按照应用程序特定的代码、常量、数据空间要求实施存储器布局以及如何使用 FRAM 优化应用程序的能 耗。 MSP430FR4xx 和 MSP430FR2xx 系列的 VLO 校准 MSP430FR4xx 和 MSP430FR2xx (FR4xx/FR2xx) 系列微控制器 (MCU) 提供了各种时钟源，包括一些高 速、高精度时钟以及一些低功耗、低系统成本时钟。用户可以选择以最佳方式权衡了性能、功耗和系统成本 的时钟。片上超低频振荡器 (VLO) 是 FR4xx/FR2xx 系列 MCU 中包含的频率为 10kHz（典型值）的时钟 源。VLO 具有超低的功耗， 因而 广泛适用于各种应用。 88 器件和文档支持 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 《MSP430 32kHz 晶体振荡器》 选择合适的晶体、正确的负载电路和适当的电路板布局是实现稳定的晶体振荡器的关键。该应用报告总结了 晶体振荡器的功能，介绍了用于选择合适的晶体以实现 MSP430 超低功耗运行的参数。此外，还给出了正 确电路板布局的提示和示例。此外，为了确保振荡器在大规模生产后能够稳定运行，还可能需要进行一些振 荡器测试，该文档中提供了有关这些测试的详细信息。 《MSP430 系统级 ESD 注意事项》 随着芯片技术向更低电压方向发展以及设计具有成本效益的超低功耗组件的需求的出现，系统级 ESD 要求 变得越来越苛刻。该应用报告介绍了不同的 ESD 主题，旨在帮助电路板设计人员和 OEM 理解并设计出稳 健耐用的系统级设计。 8.5 相关链接 表 8-2 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。 表 8-2. 相关链接 器件 产品文件夹 立即订购 技术文档 工具和软件 支持和社区 MSP430FR2633 单击此处 单击此处 单击此处 单击此处 单击此处 MSP430FR2632 单击此处 单击此处 单击此处 单击此处 单击此处 MSP430FR2533 单击此处 单击此处 单击此处 单击此处 单击此处 MSP430FR2532 单击此处 单击此处 单击此处 单击此处 单击此处 8.6 社区资源 下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术 规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。 TI E2E™ 社区 TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提 问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。 TI 嵌入式处理器维基网页 德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理 器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。 8.7 商标 CapTIvate, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 器件和文档支持 89 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 8.8 www.ti.com.cn 静电放电警告 ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可 能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可 能会导致器件与其发布的规格不相符。 8.9 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 8.10 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 90 器件和文档支持 版权 © 2015–2019, Texas Instruments Incorporated 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 MSP430FR2633, MSP430FR2632, MSP430FR2533, MSP430FR2532 www.ti.com.cn ZHCSET6E – NOVEMBER 2015 – REVISED DECEMBER 2019 9 机械、封装和可订购信息 以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据会在无通知且不对 本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。 机械、封装和可订购信息 提交文档反馈意见 产品主页链接: MSP430FR2633 MSP430FR2632 MSP430FR2533 MSP430FR2532 版权 © 2015–2019, Texas Instruments Incorporated 91 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) MSP430FR2532IRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2532 MSP430FR2532IRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2532 MSP430FR2533IDA ACTIVE TSSOP DA 32 46 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533 MSP430FR2533IDAR ACTIVE TSSOP DA 32 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533 MSP430FR2533IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533 MSP430FR2533IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2533 MSP430FR2632IRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2632 MSP430FR2632IRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2632 MSP430FR2632IYQWR ACTIVE DSBGA YQW 24 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2632 MSP430FR2632IYQWT ACTIVE DSBGA YQW 24 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2632 MSP430FR2633IDA ACTIVE TSSOP DA 32 46 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633 MSP430FR2633IDAR ACTIVE TSSOP DA 32 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633 MSP430FR2633IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633 MSP430FR2633IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FR2633 MSP430FR2633IYQWR ACTIVE DSBGA YQW 24 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2633 MSP430FR2633IYQWT ACTIVE DSBGA YQW 24 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 430FR2633 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of