CC1020
CC1020
Low-Power RF Transceiver for Narrowband Systems
Applications
Narrowband low power UHF wireless
data transmitters and receivers with
channel spacing as low as 12.5 and 25
kHz
402 / 424 / 426 / 429 / 433 / 447 / 449 /
469 / 868 / 915 / 960 MHz ISM/SRD
band systems
AMR - Automatic Meter Reading
Wireless alarm and security systems
Home automation
Low power telemetry
Product Description
CC1020 is a true single-chip UHF transceiver designed for very low power and
very low voltage wireless applications. The
circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 402, 424, 426, 429, 433, 447,
449, 469, 868, 915, and 960 MHz, but can
easily be programmed for multi-channel
operation at other frequencies in the 402 470 and 804 - 960 MHz range.
The CC1020 main operating parameters
can be programmed via a serial bus, thus
making CC1020 a very flexible and easy to
use transceiver.
In a typical system CC1020 will be used
together with a microcontroller and a few
external passive components.
The CC1020 is especially suited for narrowband systems with channel spacing of
12.5 or 25 kHz complying with ARIB STDT67 and EN 300 220.
Features
True single chip UHF RF transceiver
Frequency range 402 MHz - 470 MHz
and 804 MHz - 960 MHz
High sensitivity (up to -118 dBm for a
12.5 kHz channel)
Programmable output power
Low current consumption (RX: 19.9
mA)
Low supply voltage (2.3 V to 3.6 V)
No external IF filter needed
Low-IF receiver
Very few external components required
Small size (QFN 32 package)
Pb-free package
Digital RSSI and carrier sense indicator
Data rate up to 153.6 kBaud
OOK, FSK and GFSK data modulation
Integrated bit synchronizer
Image rejection mixer
Programmable frequency and AFC
make
crystal
temperature
drift
compensation possible without TCXO
Suitable for frequency hopping systems
Suited
for
systems
targeting
compliance with EN 300 220, FCC
CFR47 part 15, ARIB STD-T67, and
ARIB STD-T96
Development kit available
Easy-to-use software for generating the
CC1020 configuration data
TI recommends using the latest RF performance line device CC1120 as successor of
CC1020: www.ti.com/rfperformanceline”
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CC1020
Table of Contents
1.
Abbreviations ................................................................................................................ 4
2.
Absolute Maximum Ratings......................................................................................... 5
3.
Operating Conditions ................................................................................................... 5
4.
Electrical Specifications .............................................................................................. 5
4.1.
RF Transmit Section ............................................................................................ 6
4.2.
RF Receive Section ............................................................................................. 8
4.3.
RSSI / Carrier Sense Section ............................................................................ 11
4.4.
IF Section ........................................................................................................... 11
4.5.
Crystal Oscillator Section ................................................................................... 12
4.6.
Frequency Synthesizer Section ......................................................................... 13
4.7.
Digital Inputs / Outputs....................................................................................... 14
4.8.
Current Consumption ......................................................................................... 15
5.
Pin Assignment ........................................................................................................... 15
6.
Circuit Description ...................................................................................................... 17
7.
Application Circuit ...................................................................................................... 18
8.
Configuration Overview ............................................................................................. 21
8.1.
9.
Configuration Software ...................................................................................... 21
Microcontroller Interface ............................................................................................ 22
9.1.
4-wire Serial Configuration Interface ................................................................. 23
9.2.
Signal Interface .................................................................................................. 25
10.
Data Rate Programming ............................................................................................. 27
11.
Frequency Programming ........................................................................................... 28
11.1.
12.
Dithering ......................................................................................................... 29
Receiver ....................................................................................................................... 30
12.1.
IF Frequency .................................................................................................. 30
12.2.
Receiver Channel Filter Bandwidth ................................................................ 30
12.3.
Demodulator, Bit Synchronizer and Data Decision ........................................ 31
12.4.
Receiver Sensitivity versus Data Rate and Frequency Separation ............... 32
12.5.
RSSI ............................................................................................................... 33
12.6.
Image Rejection Calibration ........................................................................... 35
12.7.
Blocking and Selectivity ................................................................................. 36
12.8.
Linear IF Chain and AGC Settings ................................................................. 37
12.9.
AGC Settling ................................................................................................... 38
12.10.
Preamble Length and Sync Word .................................................................. 39
12.11.
Carrier Sense ................................................................................................. 39
12.12.
Automatic Power-up Sequencing ................................................................... 40
12.13.
Automatic Frequency Control ......................................................................... 41
12.14.
Digital FM ....................................................................................................... 42
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CC1020
13.
Transmitter .................................................................................................................. 43
13.1.
FSK Modulation Formats ............................................................................... 43
13.2.
Output Power Programming ........................................................................... 45
13.3.
TX Data Latency............................................................................................. 46
13.4.
Reducing Spurious Emission and Modulation Bandwidth .............................. 46
14.
Input / Output Matching and Filtering ....................................................................... 46
15.
Frequency Synthesizer .............................................................................................. 50
15.1.
VCO, Charge Pump and PLL Loop Filter ....................................................... 50
15.2.
VCO and PLL Self-Calibration ....................................................................... 51
15.3.
PLL Turn-on Time versus Loop Filter Bandwidth ........................................... 52
15.4.
PLL Lock Time versus Loop Filter Bandwidth ................................................ 53
16.
VCO and LNA Current Control .................................................................................. 53
17.
Power Management .................................................................................................... 54
18.
On-Off Keying (OOK) .................................................................................................. 57
19.
Crystal Oscillator ........................................................................................................ 58
20.
Built-in Test Pattern Generator ................................................................................. 59
21.
Interrupt on Pin DCLK ................................................................................................ 60
22.
21.1.
Interrupt upon PLL Lock ................................................................................. 60
21.2.
Interrupt upon Received Signal Carrier Sense .............................................. 60
PA_EN and LNA_EN Digital Output Pins ................................................................. 61
22.1.
Interfacing an External LNA or PA ................................................................. 61
22.2.
General Purpose Output Control Pins............................................................ 61
22.3.
PA_EN and LNA_EN Pin Drive ...................................................................... 61
23.
System Considerations and Guidelines ................................................................... 62
24.
PCB Layout Recommendations ................................................................................ 64
25.
Antenna Considerations ............................................................................................ 65
26.
Configuration Registers ............................................................................................. 65
26.1.
CC1020 Register Overview ............................................................................ 66
27.
Package Marking ........................................................................................................ 86
28.
Soldering Information ................................................................................................ 86
29.
Plastic Tube Specification ......................................................................................... 86
30.
Ordering Information .................................................................................................. 87
31.
General Information .................................................................................................... 88
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CC1020
1.
ACP
ACR
ADC
AFC
AGC
AMR
ASK
BER
BOM
bps
BT
ChBW
CW
DAC
DNM
ESR
FHSS
FM
FS
FSK
GFSK
IC
IF
IP3
ISM
kbps
LNA
LO
MCU
NRZ
OOK
PA
PD
PER
PCB
PN9
PLL
PSEL
RF
RSSI
RX
SBW
SPI
SRD
TBD
T/R
TX
UHF
VCO
VGA
XOSC
XTAL
Abbreviations
Adjacent Channel Power
Adjacent Channel Rejection
Analog-to-Digital Converter
Automatic Frequency Control
Automatic Gain Control
Automatic Meter Reading
Amplitude Shift Keying
Bit Error Rate
Bill Of Materials
bits per second
Bandwidth-Time product (for GFSK)
Receiver Channel Filter Bandwidth
Continuous Wave
Digital-to-Analog Converter
Do Not Mount
Equivalent Series Resistance
Frequency Hopping Spread Spectrum
Frequency Modulation
Frequency Synthesizer
Frequency Shift Keying
Gaussian Frequency Shift Keying
Integrated Circuit
Intermediate Frequency
Third Order Intercept Point
Industrial Scientific Medical
kilo bits per second
Low Noise Amplifier
Local Oscillator (in receive mode)
Micro Controller Unit
Non Return to Zero
On-Off Keying
Power Amplifier
Phase Detector / Power Down
Packet Error Rate
Printed Circuit Board
Pseudo-random Bit Sequence (9-bit)
Phase Locked Loop
Program Select
Radio Frequency
Received Signal Strength Indicator
Receive (mode)
Signal Bandwidth
Serial Peripheral Interface
Short Range Device
To Be Decided/Defined
Transmit/Receive (switch)
Transmit (mode)
Ultra High Frequency
Voltage Controlled Oscillator
Variable Gain Amplifier
Crystal oscillator
Crystal
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CC1020
2.
Absolute Maximum Ratings
The absolute maximum ratings given Table 1 should under no circumstances be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Min
Max
Unit
Supply voltage, VDD
Parameter
-0.3
5.0
V
Voltage on any pin
Input RF level
Storage temperature range
Package body temperature
Humidity non-condensing
ESD
(Human Body Model)
-0.3
VDD+0.3, max 5.0
10
150
260
85
±1
±0.4
V
dBm
C
C
%
kV
kV
-50
5
Condition
All supply pins must have the
same voltage
Norm: IPC/JEDEC J-STD-020 1
All pads except RF
RF Pads
Table 1. Absolute maximum ratings
1
The reflow peak soldering temperature (body temperature) is specified according to
IPC/JEDEC J-STD_020“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices”.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
3.
Operating Conditions
The operating conditions for CC1020 are listed in Table 2.
Parameter
Min
Typ
Max
Unit
RF Frequency Range
402
804
470
960
MHz
MHz
Operating ambient temperature
range
-40
85
C
Supply voltage
2.3
3.6
V
3.0
Condition / Note
Programmable in 0 then
set DG = ROUND( 7·DX·(2·(Y0-Y4)+Y1Y3) / (10·AG) )
else
if Y0+Y1 > Y3+Y4 then
set DG = DX
else
set DG = -DX.
31. If DG > DX then
set DG = DX
else
if DG < -DX then set DG = -DX.
32. Set XG = XG+DG.
33. If DX > 1 then go to step 2.
34.
Write XP to PHASE_COMP register and
XG to GAIN_COMP register.
If repeated calibration gives varying
results, try to change the input level or
increase the number of RSSI reads N. A
good starting point is N=8. As accuracy is
more important in the last fine-calibration
steps, it can be worthwhile to increase N
for each loop iteration.
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CC1020
For high frequency deviation and high data
rates (typically ≥ 76.8 kBaud) the analog
filter succeeding the mixer must be
bypassed by setting FILTER_BYPASS = 1
in the FILTER register. In this case the
image rejection is degraded.
The image rejection is reduced for low
supply voltages (typically 10. Otherwise, write 45h to VGA2.
Modify AGC_AVG in the above VGA2 value if
faster carrier sense and AGC settling is desired.
RSSI Level
Note that the AGC works with "raw" filter output signal
strength, while the RSSI readout value is compensated for
VGA gain changes by the AGC.
The AGC keeps the signal strength in this range. Minimize
VGA_DOWN for best selectivity, but leave some margin to
avoid frequent VGA gain changes during reception.
The AGC keeps the signal strength above carrier sense level
+ VGA_UP. Minimize VGA_UP for best selectivity, but
increase if first VGA gain reduction occurs too close to the
noise floor.
(signal strength, 1.5dB/step)
AGC decreases gain if above
this level (unless at minimum).
VGA_DOWN+3
AGC increases gain if below this
level (unless at maximum).
VGA_UP
Carrier sense is turned on here.
To set CS_LEVEL, subtract 8 from RSSI readout with RF
input signal at desired carrier sense level.
CS_LEVEL+8
Zero level depends on front-end settings and VGA_SETTING
value.
0
Figure 18. Relationship between RSSI, carrier sense level, and AGC settings CS_LEVEL,
VGA_UP and VGA_DOWN
12.9. AGC Settling
After turning on the RX chain, the following
occurs:
A) The AGC waits 16-128 ADC_CLK
(1.2288 MHz) periods, depending on the
VGA_FREEZE setting in the VGA1
register, for settling in the analog parts.
B) The AGC waits 16-48 FILTER_CLK
periods, depending on the VGA_WAIT
setting in the VGA1 register, for settling in
the analog parts and the digital channel
filter.
C) The AGC calculates the RSSI value as
the average magnitude over the next 2-16
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CC1020
FILTER_CLK periods, depending on the
AGC_AVG setting in the VGA2 register.
2-3 VGA gain changes should be
expected before the AGC has settled.
Increasing AGC_AVG increases the
settling time, but may be worthwhile if
there is the time in the protocol, and for
reducing false wake-up events when
setting the carrier sense close to the noise
floor.
D) If the RSSI value is higher than
CS_LEVEL+8, then the carrier sense
indicator is set (if CS_SET = 0). If the
RSSI value is too high according to the
CS_LEVEL, VGA_UP and VGA_DOWN
settings, and the VGA gain is not already
at minimum, then the VGA gain is reduced
and the AGC continues from B).
The AGC settling time depends on the
FILTER_CLK (= 2∙ChBW). Thus, there is a
trade off between AGC settling time and
receiver sensitivity because the AGC
settling time can be reduced for data rates
lower than 76.8 kBaud by using a wider
receiver channel filter bandwidth (i.e.
larger ChBW).
E) If the RSSI value is too low according to
the CS_LEVEL and VGA_UP settings, and
the VGA gain is not already at maximum
(given by VGA_SETTING), then the VGA
gain is increased and the AGC continues
from B).
12.10. Preamble Length and Sync Word
The rules for choosing a good sync word
are as follows:
1. The sync word should be significantly
different from the preamble
2. A large number of transitions is good for
the bit synchronization or clock recovery.
Equal bits reduce the number of
transitions. The recommended sync word
has at most 3 equal bits in a row.
3. Autocorrelation. The sync word should
not repeat itself, as this will increase the
likelihood for errors.
4. In general the first bit of sync should be
opposite of last bit in preamble, to achieve
one more transition.
The recommended sync words for CC1020
are 2 bytes (0xD391), 3 bytes (0xD391DA)
or 4 bytes (0xD391DA26) and are selected
as the best compromise of the above
criteria.
Using the register settings provided by the
SmartRF Studio software, packet error
rates (PER) less than 0.5% can be
achieved when using 24 bits of preamble
and a 16 bit sync word (0xD391). Using a
preamble longer than 24 bits will improve
the PER.
When performing the PER measurements
described above the packet format
consisted of 10 bytes of random data, 2
bytes CRC and 1 dummy byte in addition
to the sync word and preamble at the start
of each package.
For the test 1000 packets were sent 10
times. The transmitter was put in power
down between each packet. Any bit error
in the packet, either in the sync word, in
the data or in the CRC caused the packet
to be counted as a failed packet.
12.11. Carrier Sense
The carrier sense signal is based on the
RSSI value and a programmable
threshold. The carrier sense function can
be used to simplify the implementation of a
CSMA (Carrier Sense Multiple Access)
medium access protocol.
Carrier
sense
threshold
level
is
programmed by CS_LEVEL[4:0] in the
VGA4 register and VGA_SETTING[4:0] in
the VGA3 register.
VGA_SETTING[4:0] sets the maximum
gain in the VGA. This value must be set so
that the ADC works with optimum dynamic
range for a certain channel filter
bandwidth. The detected signal strength
(after the ADC) will therefore depend on
this setting.
CS_LEVEL[4:0] sets the threshold for this
specific VGA_SETTING[4:0] value. If the
VGA_SETTING[4:0] is changed, the
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CC1020
CS_LEVEL[4:0]
must
be
changed
accordingly to maintain the same absolute
carrier sense threshold. See Figure 18 for
an explanation of the relationship between
RSSI, AGC and carrier sense settings.
The carrier sense signal can also be made
available at the LOCK pin by setting
LOCK_SELECT[3:0] = 0100 in the LOCK
register.
The carrier sense signal can be read as
the CARRIER_SENSE bit in the STATUS
register.
12.12. Automatic Power-up Sequencing
CC1020 has a built-in automatic power-up
sequencing state machine. By setting the
CC1020 into this mode, the receiver can be
powered-up automatically by a wake-up
signal and will then check for a carrier
signal (carrier sense). If carrier sense is
not detected, it returns to power-down
mode. A flow chart for automatic power-up
sequencing is shown in Figure 19.
The automatic power-up sequencing mode
is selected when PD_MODE[1:0] = 11 in
the MAIN register. When the automatic
power-up sequencing mode is selected,
the functionality of the MAIN register is
changed and used to control the
sequencing.
By setting SEQ_PD = 1 in the MAIN
register, CC1020 is set in power down
mode. If SEQ_PSEL = 1 in the
SEQUENCING register the automatic
power-up sequence is initiated by a
negative transition on the PSEL pin.
If SEQ_PSEL = 0 in the SEQUENCING
register, then the automatic power-up
sequence is initiated by a negative
transition on the DIO pin (as long as
SEP_DI_DO = 1 in the INTERFACE
register).
Sequence timing is controlled through
RX_WAIT[2:0] and CS_WAIT[3:0] in the
SEQUENCING register.
VCO and PLL calibration can also be done
automatically as a part of the sequence.
This is controlled through SEQ_CAL[1:0]
in the MAIN register. Calibration can be
th
done every time, every 16 sequence,
th
every 256 sequence, or never. See the
register description for details. A
description of when to do, and how the
VCO and PLL self-calibration is done, is
given in section 15.2 on page 51.
See also Application Note AN070 CC1020
Automatic Power-Up Sequencing available
from the TI web site.
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CC1020
Turn on crystal oscillator/bias
Frequency synthesizer off
Receive chain off
Sequencing wake-up event
(negative transition on
PSEL pin or DIO pin)
Power down
Crystal oscillator and bias off
Frequency synthesizer off
Receive chain off
Crystal oscillator and bias on
Turn on frequency synthesizer
Receive chain off
Wait for PLL
lock or timeout,
127 filter clocks
PLL timeout
Set
SEQ_ERROR
flag in STATUS
register
Optional calibration
Programmable: each time,
once in 16, or once in 256
Receive chain off
PLL in lock
Optional waiting time before
turning on receive chain
Programmable:
32-256 ADC clocks
Crystal oscillator and bias on
Frequency synthesizer on
Turn on receive chain
Wait for
carrier sense or timeout
Programmable: 20-72
filter clocks
Carrier sense timeout
Carrier sense
Receive mode
Sequencing power-down event
Crystal oscillator and bias on
Frequency synthesizer on
(Positive transition on SEQ_PD in MAIN register)
Receive chain on
Figure 19. Automatic power-up sequencing flow chart
Notes to Figure 19:
Filter clock (FILTER_CLK):
ADC clock (ADC_CLK):
f ADC
f filter _ clock 2 ChBW
where ChBW is defined on page 30.
f xoscx
2 ( ADC _ DIV 2 : 0 1)
where ADC_DIV[2:0] is set in the MODEM
register.
12.13. Automatic Frequency Control
CC1020 has a built-in feature called AFC
The frequency offset is given by:
(Automatic Frequency Control) that can be
used to compensate for frequency drift.
The average frequency offset of the
received signal (from the nominal IF
frequency) can be read in the AFC
register. The signed (2’s-complement) 8bit value AFC[7:0] can be used to
compensate for frequency offset between
transmitter and receiver.
F = AFC∙Baud rate / 16
The receiver can be calibrated against the
transmitter by changing the operating
frequency according to the measured
offset. The new frequency must be
calculated and written to the FREQ
register by the microcontroller. The AFC
can be used for an FSK/GFSK signal, but
not for OOK. Application Note AN029
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CC1020
CC1020/1021 AFC provides the procedure
and equations necessary to implement
AFC.
The AFC feature reduces the crystal
accuracy requirement.
12.14. Digital FM
It is possible to read back the
instantaneous IF from the FM demodulator
as a frequency offset from the nominal IF
frequency. This digital value can be used
to perform a pseudo analog FM
demodulation.
The frequency offset can be read from the
GAUSS_FILTER register and is a signed
8-bit value coded as 2-complement.
kHz (Nyquist) and is determined by the
MODEM_CLK. The MODEM_CLK, which
is the sampling rate, equals 8 times the
baud rate. That is, the minimum baud rate,
which can be programmed, is 1 kBaud.
However, the incoming data will be filtered
in the digital domain and the 3-dB cut-off
frequency is 0.6 times the programmed
Baud rate. Thus, for audio the minimum
programmed Baud rate should be
approximately 7.2 kBaud.
The instantaneous deviation is given by:
F = GAUSS_FILTER∙Baud rate / 8
The digital value should be read from the
register and sent to a DAC and filtered in
order to get an analog audio signal. The
internal register value is updated at the
MODEM_CLK rate. MODEM_CLK is
available at the LOCK pin when
LOCK_SELECT[3:0] = 1101 in the LOCK
register, and can be used to synchronize
the reading.
For audio (300 – 4000 Hz) the sampling
rate should be higher than or equal to 8
The
GAUSS_FILTER
resolution
decreases with increasing baud rate. A
accumulate and dump filter can be
implemented in the uC to improve the
resolution.
Note
that
each
GAUSS_FILTER reading should be
synchronized to the MODEM_CLK. As an
example, accumulating 4 readings and
dividing the total by 4 will improve the
resolution by 2 bits.
Furthermore,
to
fully
utilize
the
GAUSS_FILTER dynamic range the
frequency deviation must be 16 times the
programmed baud rate.
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CC1020
13.
Transmitter
13.1. FSK Modulation Formats
The data modulator can modulate FSK,
which is a two level FSK (Frequency Shift
Keying), or GFSK, which is a Gaussian
filtered FSK with BT = 0.5. The purpose of
the GFSK is to make a more bandwidth
efficient system as shown in Figure 20.
The modulation and the Gaussian filtering
are done internally in the chip. The
TX_SHAPING bit in the DEVIATION
register enables the GFSK. GFSK is
recommended for narrowband operation.
Figure 21 and Figure 22 show typical eye
diagrams for 434 MHz and 868 MHz
operation respectively.
Figure 20. FSK vs. GFSK spectrum plot. 2.4 kBaud, NRZ, ±2.025 kHz frequency deviation
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CC1020
Figure 21. FSK vs. GFSK eye diagram. 2.4 kBaud, NRZ, ±2.025 kHz frequency deviation
Figure 22. GFSK eye diagram. 153.6 kBaud, NRZ, ±79.2 kHz frequency deviation
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CC1020
13.2. Output Power Programming
The RF output power from the device is
programmable by the 8-bit PA_POWER
register. Figure 23 and Figure 24 shows
the output power and total current
consumption as a function of the
PA_POWER register setting. It is more
efficient in terms of current consumption to
use either the lower or upper 4-bits in the
register to control the power, as shown in
the figures. However, the output power
can be controlled in finer steps using all
the available bits in the PA_POWER
register.
35.0
Current [mA] / Output power [dBm]
30.0
25.0
20.0
15.0
10.0
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
0
1
2
3
4
5
6
7
8
9 0A 0B 0C 0D 0E 0F 50 60 70 80 90 A0 B0 C0 D0 E0 F0 FF
PA_POWER [hex]
Current Consumption
Output Power
Figure 23. Typical output power and current consumption, 433 MHz
35.0
Current [mA] / Output power [dBm]
30.0
25.0
20.0
15.0
10.0
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
0
1
2
3
4
5
6
7
8
9 0A 0B 0C 0D 0E 0F 50 60 70 80 90 A0 B0 C0 D0 E0 F0 FF
PA_POWER [hex]
Current Consumption
Output Power
Figure 24. Typical output power and current consumption, 868 MHz
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CC1020
13.3. TX Data Latency
The transmitter will add a delay due to the
synchronization of the data with DCLK and
further clocking into the modulator. The
user should therefore add a delay
equivalent to at least 2 bits after the data
payload has been transmitted before
switching off the PA (i.e. before stopping
the transmission).
13.4. Reducing Spurious Emission and Modulation Bandwidth
Modulation bandwidth and spurious
emission are normally measured with the
PA continuously on and a repeated test
sequence.
In cases where the modulation bandwidth
and spurious emission are measured with
the CC1020 switching from power down
mode to TX mode, a PA ramping
sequence could be used to minimize
modulation bandwidth and spurious
emission.
14.
PA ramping should then be used both
when switching the PA on and off. A linear
PA ramping sequence can be used where
register PA_POWER is changed from 00h
to 0Fh and then from 50h to the register
setting that gives the desired output power
(e.g. F0h for +10 dBm output power at 433
MHz operation). The longer the time per
PA ramping step the better, but setting the
total PA ramping time equal to 2 bit
periods is a good compromise between
performance and PA ramping time.
Input / Output Matching and Filtering
When designing the impedance matching
network for the CC1020 the circuit must be
matched correctly at the harmonic
frequencies as well as at the fundamental
tone. A recommended matching network is
shown in Figure 25. Component values for
various frequencies are given in Table 21.
Component values for other frequencies
can be found using the SmartRF Studio
software.
As can be seen from Figure 25 and Table
21, the 433 MHz network utilizes a T-type
filter, while the 868/915 MHz network has
a -type filter topology.
It is important to remember that the
physical layout and the components used
contribute significantly to the reflection
coefficient, especially at the higher
harmonics. For this reason, the frequency
response of the matching network should
be measured and compared to the
response of the TI reference design. Refer
to Figure 27 and Table 22 as well as
Figure 28 and Table 23.
The use of an external T/R switch reduces
current consumption in TX for high output
power levels and improves the sensitivity
in RX. A recommended application circuit
is available from the TI web site
(CC1020EMX). The external T/R switch
can be omitted in certain applications, but
performance will then be degraded.
The match can also be tuned by a shunt
capacitor array at the PA output
(RF_OUT). The capacitance can be set in
0.4 pF steps and used either in RX mode
or TX mode. The RX_MATCH[3:0] and
TX_MATCH[3:0] bits in the MATCH
register control the capacitor array.
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Page 46 of 89
CC1020
AVDD=3V
R10
ANTENNA
L2
C60
CC1020
L70
C3
RF_OUT
RF_IN
C71
L71
C72
C1
L1
T/R SWITCH
Figure 25. Input/output matching network
Item
C1
C3
C60
C71
C72
L1
L2
L70
L71
R10
433 MHz
10 pF, 5%, NP0, 0402
5.6 pF, 5%, NP0, 0402
220 pF, 5%, NP0, 0402
DNM
4.7 pF, 5%, NP0, 0402
33 nH, 5%, 0402
22 nH, 5%, 0402
47 nH, 5%, 0402
39 nH, 5%, 0402
82 , 5%, 0402
868 MHz
47 pF, 5%, NP0, 0402
10 pF, 5%, NP0, 0402
220 pF, 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
82 nH, 5%, 0402
3.6 nH, 5%, 0402
5.1 nH, 5%, 0402
0 resistor, 0402
82 , 5%, 0402
915 MHz
47 pF, 5%, NP0, 0402
10 pF, 5%, NP0, 0402
220 pF, 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
82 nH, 5%, 0402
3.6 nH, 5%, 0402
5.1 nH, 5%, 0402
0 resistor, 0402
82 , 5%, 0402
Table 21. Component values for the matching network described in Figure 25 (DNM = Do
Not Mount).
Figure 26. Typical LNA input impedance, 200 – 1000 MHz
SWRS046F
Page 47 of 89
CC1020
433 MHz
Figure 27. Typical optimum PA load impedance, 433 MHz. The frequency is swept from
300 MHz to 2500 MHz. Values are listed in Table 22
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
433
54
44
866
20
173
1299
288
-563
1732
14
-123
2165
5
-66
Table 22. Impedances at the first 5 harmonics (433 MHz matching network)
SWRS046F
Page 48 of 89
CC1020
868 MHz
Figure 28: Typical optimum PA load impedance, 868/915 MHz. The frequency is swept
from 300 MHz to 2800 MHz. Values are listed in Table 23
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
868
15
24
915
20
35
1736
1.5
18
1830
1.7
22
2604
3.2
44
2745
3.6
45
Table 23. Impedances at the first 3 harmonics (868/915 MHz matching network)
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CC1020
15.
Frequency Synthesizer
15.1. VCO, Charge Pump and PLL Loop Filter
The VCO is completely integrated and
operates in the 1608 – 1920 MHz range. A
frequency divider is used to get a
frequency in the UHF range (402 – 470
and 804 – 960 MHz). The BANDSELECT
bit in the ANALOG register selects the
frequency band.
The VCO frequency is given by:
FREQ 0.5 DITHER
f VCO f ref 3
8192
The VCO frequency is divided by 2 and by
4 to generate frequencies in the two
bands, respectively.
The VCO sensitivity (sometimes referred
to as VCO gain) varies over frequency and
operating conditions. Typically the VCO
sensitivity varies between 12 and 36
MHz/V. For calculations the geometrical
mean at 21 MHz/V can be used. The PLL
calibration (explained below) measures
the actual VCO sensitivity and adjusts the
charge pump current accordingly to
achieve correct PLL loop gain and
bandwidth (higher charge pump current
when VCO sensitivity is lower).
The following equations can be used for
calculating PLL loop filter component
values, see Figure 3, for a desired PLL
loop bandwidth, BW:
2
C7 = 3037 (fref / BW ) -7
R2 = 7126 (BW / fref)
2
C6 = 80.75 (fref / BW )
R3 = 21823 (BW / fref)
2
C8 = 839 (fref / BW ) -6
[pF]
[kΩ]
[nF]
[kΩ]
[pF]
Define a minimum PLL loop bandwidth as
BW min =
1
C6 = 220 nF
C7 = 8200 pF
C8 = 2200 pF
R2 = 1.5 kΩ
R3 = 4.7 kΩ
2) If the data rate is 4.8 kBaud or below
and the channel spacing is different from
12.5 kHz the following loop filter
components are recommended:
C6 = 100 nF
C7 = 3900 pF
C8 = 1000 pF
R2 = 2.2 kΩ
R3 = 6.8 kΩ
After calibration the PLL bandwidth is set
by the PLL_BW register in combination
with the external loop filter components
calculated above. The PLL_BW can be
found from
PLL_BW = 174 + 16 log2(fref /7.126)
where fref is the reference frequency (in
MHz). The PLL loop filter bandwidth
increases with increasing PLL_BW setting.
Note that in SmartRF Studio PLL_BW is
fixed to 9E hex when the channel spacing
is set up for 12.5 kHz, optimized
selectivity.
After calibration the applied charge pump
current (CHP_CURRENT[3:0]) can be
read in the STATUS1 register. The charge
pump current is approximately given by:
80.75 f ref 220 . If BW min >
Baud rate/3 then set BW = BW min and if
BW min < Baud rate/3 then set BW = Baud
rate/3 in the above equations.
There are two special cases when using
the recommended 14.7456 MHz crystal:
If the data rate is 4.8 kBaud or
below and the channel spacing is
12.5 kHz the following loop filter
components are recommended:
I CHP 16 2 CHP _ CURRENT
4
uA
The combined charge pump and phase
detector gain (in A/rad) is given by the
charge pump current divided by 2.
The PLL bandwidth will limit the maximum
modulation frequency and hence data
rate.
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Page 50 of 89
CC1020
15.2. VCO and PLL Self-Calibration
To compensate for supply voltage,
temperature and process variations, the
VCO and PLL must be calibrated. The
calibration is performed automatically and
sets the maximum VCO tuning range and
optimum charge pump current for PLL
stability. After setting up the device at the
operating frequency, the self-calibration
can be initiated by setting the
CAL_START bit in the CALIBRATE
register. The calibration result is stored
internally in the chip, and is valid as long
as power is not turned off. If large supply
voltage drops (typically more than 0.25 V)
or temperature variations (typically more
o
than 40 C) occur after calibration, a new
calibration should be performed.
To check that the PLL is in lock the user
should monitor the LOCK_CONTINUOUS
bit in the STATUS register. The
LOCK_CONTINUOUS bit can also be
monitored at the LOCK pin, configured by
LOCK_SELECT[3:0] = 0010.
There are separate calibration values for
the two frequency registers. However, dual
calibration is possible if all of the below
conditions apply:
The nominal VCO control voltage is set by
the CAL_ITERATE[2:0] bits in the
CALIBRATE register.
The CAL_COMPLETE bit in the STATUS
register indicates that calibration has
finished. The calibration wait time
(CAL_WAIT) is programmable and is
inverse proportional to the internal PLL
reference frequency. The highest possible
reference frequency should be used to get
the minimum calibration time. It is
recommended to use CAL_WAIT[1:0] = 11
in order to get the most accurate loop
bandwidth.
Calibration
time [ms]
CAL_WAIT
00
01
10
11
Reference frequency [MHz]
1.8432
49 ms
60 ms
71 ms
109 ms
7.3728
12 ms
15 ms
18 ms
27 ms
9.8304
10 ms
11 ms
13 ms
20 ms
Table 24. Typical calibration times
The CAL_COMPLETE bit can also be
monitored at the LOCK pin, configured by
LOCK_SELECT[3:0] = 0101, and used as
an interrupt input to the microcontroller.
The two frequencies A and B differ by
less than 1 MHz
Reference frequencies are equal
(REF_DIV_A[2:0] = REF_DIV_B[2:0]
in the CLOCK_A/CLOCK_B registers)
VCO
currents
are
equal
(VCO_CURRENT_A[3:0]
=
VCO_CURRENT_B[3:0] in the VCO
register).
The CAL_DUAL bit in the CALIBRATE
register controls dual or separate
calibration.
The
single
calibration
algorithm
(CAL_DUAL=0) using separate calibration
for RX and TX frequency is illustrated in
Figure 29. The same algorithm is
applicable
for
dual
calibration
if
CAL_DUAL=1. Application Note AN023
CC1020 MCU Interfacing, available from
the TI web site, includes example source
code for single calibration.
TI recommends that single calibration be
used for more robust operation.
There is a small, but finite, possibility that
the PLL self-calibration will fail. The
calibration routine in the source code
should include a loop so that the PLL is recalibrated until PLL lock is achieved if the
PLL does not lock the first time. Refer to
CC1020 Errata Note 004.
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Page 51 of 89
CC1020
Start single calibration
fref is the reference frequency (in
MHz)
Write FREQ_A, FREQ_B, VCO,
CLOCK_A and CLOCK_B registers.
PLL_BW = 174 + 16log2(fref/7.126)
Calibrate RX frequency register A
(to calibrate TX frequency register
B write MAIN register = D1h).
Register CALIBRATE = 34h
Write MAIN register = 11h:
RXTX=0, F_REG=0, PD_MODE=1,
FS_PD=0, CORE_PD=0, BIAS_PD=0,
RESET_N=1
Write CALIBRATE register = B4h
Start calibration
Wait for T100 us
Read STATUS register and wait until
CAL_COMPLETE=1
Read STATUS register and wait until
LOCK_CONTINUOUS=1
Calibration OK?
No
Yes
End of calibration
Figure 29. Single calibration algorithm for RX and TX
15.3. PLL Turn-on Time versus Loop Filter Bandwidth
If calibration has been performed the PLL
turn-on time is the time needed for the PLL
to lock to the desired frequency when
going from power down mode (with the
crystal oscillator running) to TX or RX
mode. The PLL turn-on time depends on
the PLL loop filter bandwidth. Table 25
gives the PLL turn-on time for different
PLL loop filter bandwidths.
SWRS046F
Page 52 of 89
CC1020
C6
[nF]
220
C7
[pF]
8200
C8
[pF]
2200
R2
[kΩ]
1.5
R3
[kΩ]
4.7
PLL turn-on time
[us]
3200
100
56
15
3900
2200
560
1000
560
150
2.2
3.3
5.6
6.8
10
18
2500
1400
1300
3.9
120
33
12
39
1080
1.0
27
3.3
27
82
950
0.2
1.5
-
47
150
700
Comment
Up to 4.8 kBaud data rate, 12.5 kHz channel
spacing
Up to 4.8 kBaud data rate, 25 kHz channel spacing
Up to 9.6 kBaud data rate, 50 kHz channel spacing
Up to 19.2 kBaud data rate, 100 kHz channel
spacing
Up to 38.4 kBaud data rate, 150 kHz channel
spacing
Up to 76.8 kBaud data rate, 200 kHz channel
spacing
Up to 153.6 kBaud data rate, 500 kHz channel
spacing
Table 25. Typical PLL turn-on time to within ±10% of channel spacing for different loop
filter bandwidths
15.4. PLL Lock Time versus Loop Filter Bandwidth
If calibration has been performed the PLL
lock time is the time needed for the PLL to
lock to the desired frequency when going
from RX to TX mode or vice versa. The
PLL lock time depends on the PLL loop
filter bandwidth. Table 26 gives the PLL
lock time for different PLL loop filter
bandwidths.
C6
[nF]
C7
[pF]
C8
[pF]
R2
[kΩ]
R3
[kΩ]
220
8200
2200
1.5
4.7
PLL lock time
[us]
1
2
3
900
180
1300
100
3900
1000
2.2
6.8
640
270
830
56
2200
560
3.3
10
400
140
490
15
560
150
5.6
18
140
70
230
3.9
120
33
12
39
75
50
180
1.0
27
3.3
27
82
30
15
55
0.2
1.5
-
47
150
14
14
28
Comment
Up to 4.8 kBaud data rate, 12.5 kHz channel
spacing
Up to 4.8 kBaud data rate, 25 kHz channel
spacing
Up to 9.6 kBaud data rate, 50 kHz channel
spacing
Up to 19.2 kBaud data rate, 100 kHz channel
spacing
Up to 38.4 kBaud data rate, 150 kHz channel
spacing
Up to 76.8 kBaud data rate, 200 kHz channel
spacing
Up to 153.6 kBaud data rate, 500 kHz channel
spacing
Table 26. Typical PLL lock time to within ±10% of channel spacing for different loop filter
bandwidths. 1) 307.2 kHz step, 2) 1 channel step, 3) 1 MHz step
16.
VCO and LNA Current Control
The VCO current is programmable and
should be set according to operating
frequency, RX/TX mode and output power.
Recommended
settings
for
the
VCO_CURRENT bits in the VCO register
are shown in the register overview and
also given by SmartRF Studio. The VCO
current for frequency FREQ_A and
FREQ_B
can
independently.
be
programmed
The bias currents for the LNA, mixer and
the LO and PA buffers are also
programmable. The FRONTEND and the
BUFF_CURRENT registers control these
currents.
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CC1020
17.
Power Management
CC1020 offers great flexibility for power
management in order to meet strict power
consumption requirements in batteryoperated applications. Power down mode
is controlled through the MAIN register.
There are separate bits to control the RX
part, the TX part, the frequency
synthesizer and the crystal oscillator in the
MAIN register. This individual control can
be used to optimize for lowest possible
current consumption in each application.
Figure 30 shows a typical power-on and
initializing sequence for minimum power
consumption.
Figure 31 shows a typical sequence for
activating RX and TX mode from power
down
mode
for
minimum
power
consumption.
Note that PSEL should be tri-stated or set
to a high level during power down mode in
order to prevent a trickle current from
flowing in the internal pull-up resistor.
Application Note AN023 CC1020 MCU
Interfacing includes example source code
and is available from the TI web site.
TI recommends resetting the CC1020 (by
clearing the RESET_N bit in the MAIN
register) when the chip is powered up
initially. All registers that need to be
configured should then be programmed
(those which differ from their default
values). Registers can be programmed
freely in any order. The CC1020 should
then be calibrated in both RX and TX
mode. After this is completed, the CC1020
is ready for use. See the detailed
procedure flowcharts in Figure 29 – Figure
31.
With reference to Application Note AN023
CC1020 MCU Interfacing TI recommends
the following sequence:
After power up:
1) ResetCC1020
2) Initialize
3) WakeUpCC1020ToRX
4) Calibrate
5) WakeUpCC1020ToTX
6) Calibrate
After calibration is completed, enter TX
mode (SetupCC1020TX), RX mode
(SetupCC1020RX) or power down mode
(SetupCC1020PD)
From power-down mode to RX:
1) WakeUpCC1020ToRX
2) SetupCC1020RX
From power-down mode to TX:
1) WakeUpCC1020ToTX
2) SetupCC1020TX
Switching from RX to TX mode:
1) SetupCC1020TX
Switching from TX to RX mode:
1
SetupCC1020RX
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Page 54 of 89
CC1020
Power Off
ResetCC1020
Turn on power
Reset CC1020
MAIN: RX_TX=0, F_REG=0,
PD_MODE=1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
RESET_N=0
RESET_N=1
WakeupCC1020ToRx/
WakeupCC1020ToTx
Program all necessary registers
except MAIN and RESET
Turn on crystal oscillator, bias
generator and synthesizer
successively
SetupCC1020PD
Calibrate VCO and PLL
MAIN: PD_MODE=1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
PA_POWER=00h
Power Down mode
Figure 30. Initialising sequence
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Page 55 of 89
CC1020
Turn on bias generator. MAIN: BIAS_PD=0
Wait 150 us
RX or TX?
TX
Turn on frequency synthesizer
MAIN: RXTX=0, F_REG=0, FS_PD=0
Turn on frequency synthesizer
MAIN: RXTX=1, F_REG=1, FS_PD=0
Wait until lock detected from LOCK pin
or STATUS register
Turn on RX: MAIN: PD_MODE = 0
Wait until lock detected from LOCK pin
or STATUS register
Turn on TX: MAIN: PD_MODE = 0
Set PA_POWER
RX mode
TX mode
Turn off RX/TX:
MAIN: PD_MODE = 1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
PA_POWER=00h
SetupCC1020Tx
SetupCC1020Rx
WakeupCC1020ToTx
Turn on crystal oscillator core
MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=0, BIAS_PD=1
Wait 1.2 ms*
RX
SetupCC1020PD
*Time to wait depends
on the crystal frequency
and the load capacitance
SetupCC1020PD
WakeupCC1020ToRx
Power Down mode
Power Down mode
Figure 31. Sequence for activating RX or TX mode
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CC1020
18.
On-Off Keying (OOK)
The data modulator can also provide OOK
(On-Off Keying) modulation. OOK is an
ASK (Amplitude Shift Keying) modulation
using 100% modulation depth. OOK
modulation is enabled in RX and in TX by
setting TXDEV_M[3:0] = 0000 in the
DEVIATION register. An OOK eye
diagram is shown in Figure 32.
The data demodulator can also perform
OOK demodulation. The demodulation is
done by comparing the signal level with
the “carrier sense” level (programmed as
CS_LEVEL in the VGA4 register). The
signal is then decimated and filtered in the
data filter. Data decision and bit
synchronization are as for FSK reception.
In this mode AGC_AVG in the VGA2
register must be set to 3. The channel
bandwidth must be 4 times the Baud rate
for data rates up to 9.6 kBaud. For the
highest data rates the channel bandwidth
must be 2 times the Baud rate (see Table
27). Manchester coding must always be
used for OOK.
Note that the automatic frequency control
(AFC) cannot be used when receiving
OOK, as it requires a frequency shift.
The AGC has a certain time-constant
determined by FILTER_CLK, which
depends on the IF filter bandwidth. There
is a lower limit on FILTER_CLK and hence
the AGC time constant. For very low data
rates the minimum time constant is too
fast and the AGC will increase the gain
when a “0” is received and decrease the
gain when a “1” is received. For this
reason the minimum data rate in OOK is
2.4 kBaud.
Typical figures for the receiver sensitivity
-3
(BER = 10 ) are shown in Table 27 for
OOK.
Figure 32. OOK eye diagram. 9.6 kBaud
SWRS046F
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CC1020
Data rate
[kBaud]
Filter BW
[kHz]
2.4
4.8
9.6
19.2
38.4
76.8
153.6
9.6
19.2
38.4
51.2
102.4
153.6
307.2
Sensitivity [dBm]
433 MHz
868 MHz
Manchester mode Manchester mode
-116
-113
-103
-102
-95
-92
-81
-107
-104
-101
-97
-94
-87
Table 27. Typical receiver sensitivity as a function of data rate at 433 and 868 MHz, OOK
-3
modulation, BER = 10 , pseudo-random data (PN9 sequence)
19.
Crystal Oscillator
The recommended crystal frequency is
14.7456 MHz, but any crystal frequency in
the range 4 – 20 MHz can be used. Using
a crystal frequency different from 14.7456
MHz might in some applications give
degraded
performance.
Refer
to
Application
Note
AN022
Crystal
Frequency Selection for more details on
the use of other crystal frequencies than
14.7456 MHz. The crystal frequency is
used as reference for the data rate (as
well as other internal functions) and in the
4 – 20 MHz range the frequencies 4.9152,
7.3728,
9.8304,
12.2880,
14.7456,
17.2032, 19.6608 MHz will give accurate
data rates as shown in Table 17 and an IF
frequency of 307.2 kHz. The crystal
frequency will influence the programming
of the CLOCK_A, CLOCK_B and MODEM
registers.
An external clock signal or the internal
crystal oscillator can be used as main
frequency reference. An external clock
signal should be connected to XOSC_Q1,
while XOSC_Q2 should be left open. The
XOSC_BYPASS bit in the INTERFACE
register should be set to ‘1’ when an
external digital rail-to-rail clock signal is
used. No DC block should be used then. A
sine with smaller amplitude can also be
used. A DC blocking capacitor must then
be used (10 nF) and the XOSC_BYPASS
bit in the INTERFACE register should be
set to ‘0’. For input signal amplitude, see
section 4.5 on page 12.
Using the internal crystal oscillator, the
crystal must be connected between the
XOSC_Q1 and XOSC_Q2 pins. The
oscillator is designed for parallel mode
operation of the crystal. In addition,
loading capacitors (C4 and C5) for the
crystal are required. The loading capacitor
values depend on the total load
capacitance, CL, specified for the crystal.
The total load capacitance seen between
the crystal terminals should equal CL for
the crystal to oscillate at the specified
frequency.
CL
1
1
1
C 4 C5
C parasitic
The parasitic capacitance is constituted by
pin input capacitance and PCB stray
capacitance. Total parasitic capacitance is
typically 8 pF. A trimming capacitor may
be placed across C5 for initial tuning if
necessary.
The crystal oscillator circuit is shown in
Figure 33. Typical component values for
different values of CL are given in Table
28.
The crystal oscillator is amplitude
regulated. This means that a high current
is required to initiate the oscillations. When
the amplitude builds up, the current is
reduced to what is necessary to maintain
approximately 600 mVpp amplitude. This
ensures a fast start-up, keeps the drive
level to a minimum and makes the
oscillator insensitive to ESR variations. As
long
as
the
recommended
load
capacitance values are used, the ESR is
not critical.
The initial tolerance, temperature drift,
aging and load pulling should be carefully
specified in order to meet the required
frequency
accuracy
in
a
certain
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CC1020
application. By specifying the total
expected frequency accuracy in SmartRF
Studio together with data rate and
frequency separation, the software will
estimate the total bandwidth and compare
to the available receiver channel filter
bandwidth. The software will report any
contradictions and a more accurate crystal
will be recommended if required.
XOSC_Q2
XOSC_Q1
XTAL
C4
C5
Figure 33. Crystal oscillator circuit
Item
C4
C5
CL= 12 pF
6.8 pF
6.8 pF
CL= 16 pF
15 pF
15 pF
CL= 22 pF
27 pF
27 pF
Table 28. Crystal oscillator component values
20.
Built-in Test Pattern Generator
The CC1020 has a built-in test pattern
generator that generates a PN9 pseudo
random sequence. The PN9_ENABLE bit
in the MODEM register enables the PN9
generator. A transition on the DIO pin is
required after enabling the PN9 pseudo
random sequence.
The PN9 pseudo random sequence is
9
5
defined by the polynomial x + x + 1.
The PN9 sequence is ‘XOR’ed with the
DIO signal in both TX and RX mode as
shown in Figure 34. Hence, by transmitting
only zeros (DIO = 0), the BER (Bit Error
Rate) can be tested by counting the
number of received ones. Note that the 9
first received bits should be discarded in
this case. Also note that one bit error will
generate 3 received ones.
Transmitting only ones (DIO = 1), the BER
can be tested by counting the number of
received zeroes.
The PN9 generator can also be used for
transmission of ‘real-life’ data when
measuring narrowband ACP (Adjacent
Channel Power), modulation bandwidth or
occupied bandwidth.
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CC1020
Tx pseudo random sequence
Tx out (modulating signal)
Tx data (DIO pin)
XOR
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
XOR
Rx pseudo random sequence
Rx in (Demodulated Rx data)
8
7
6
XOR
XOR
Rx out (DIO pin)
Figure 34. PN9 pseudo random sequence generator in TX and RX mode
21.
Interrupt on Pin DCLK
21.1. Interrupt upon PLL Lock
In synchronous mode the DCLK pin on
CC1020 can be used to give an interrupt
signal to wake the microcontroller when
the PLL is locked.
PD_MODE[1:0] in the MAIN register
should be set to 01. If DCLK_LOCK in the
INTERFACE register is set to 1 the DCLK
signal is always logic high if the PLL is not
in lock. When the PLL locks to the desired
frequency the DCLK signal changes to
logic 0. When this interrupt has been
detected write PD_MODE[1:0] = 00. This
will enable the DCLK signal.
This function can be used to wait for the
PLL to be locked before the PA is ramped
up in transmit mode. In receive mode, it
can be used to wait until the PLL is locked
before searching for preamble.
21.2. Interrupt upon Received Signal Carrier Sense
In synchronous mode the DCLK pin on
CC1020 can also be used to give an
interrupt signal to the microcontroller when
the RSSI level exceeds a certain threshold
(carrier sense threshold). This function can
be used to wake or interrupt the
microcontroller when a strong signal is
received.
Gating the DCLK signal with the carrier
sense signal makes the interrupt signal.
This function should only be used in
receive mode and is enabled by setting
DCLK_CS = 1 in the INTERFACE register.
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CC1020
The DCLK signal is always logic high
unless carrier sense is indicated. When
carrier sense is indicated the DCLK starts
running. When gating the DCLK signal
with the carrier sense signal at least 2
dummy bits should be added after the data
payload in TX mode. The reason being
that the carrier sense signal is generated
earlier in the receive chain (i.e. before the
22.
demodulator), causing it to be updated 2
bits before the corresponding data is
available on the DIO pin.
In transmit mode DCLK_CS must be set to
0. Refer to CC1020 Errata Note 002.
PA_EN and LNA_EN Digital Output Pins
22.1. Interfacing an External LNA or PA
CC1020 has two digital output pins, PA_EN
internal PA is turned on. Otherwise, the
EXT_PA_POL bit controls the PA_EN pin
directly. If EXT_LNA = 1, then the
LNA_EN pin will be activated when the
internal LNA is turned on. Otherwise, the
EXT_LNA_POL bit controls the LNA_EN
pin directly.
and LNA_EN, which can be used to
control an external LNA or PA. The
functionality of these pins are controlled
through the INTERFACE register. The
outputs can also be used as general digital
output control signals.
These two pins can therefore also be used
as two general control signals, see section
22.2. In the TI reference design LNA_EN
and PA_EN are used to control the
external T/R switch.
EXT_PA_POL and EXT_LNA_POL control
the active polarity of the signals.
EXT_PA and EXT_LNA control the
function of the pins. If EXT_PA = 1, then
the PA_EN pin will be activated when the
22.2. General Purpose Output Control Pins
is controlled by LOCK_SELECT[3:0] in the
LOCK register. The LOCK pin is low when
LOCK_SELECT[3:0] = 0000, and high
when LOCK_SELECT[3:0] = 0001.
The two digital output pins, PA_EN and
LNA_EN, can be used as two general
control signals by setting EXT_PA = 0 and
EXT_LNA = 0. The output value is then
set directly by the value written to
EXT_PA_POL and EXT_LNA_POL.
These features can be used to save I/O
pins on the microcontroller when the other
functions associated with these pins are
not used.
The LOCK pin can also be used as a
general-purpose output pin. The LOCK pin
22.3. PA_EN and LNA_EN Pin Drive
Figure 35 shows the PA_EN and LNA_EN
pin drive currents. The sink and source
currents have opposite signs but absolute
values are used in Figure 35.
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CC1020
1400
1200
Current [uA]
1000
800
600
400
200
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
Voltage on PA_EN/LNA_EN pin [V]
source current, 3 V
sink current, 3V
source current, 2.3 V
sink current, 2.3 V
source current, 3.6 V
sink current, 3.6 V
Figure 35. Typical PA_EN and LNA_EN pin drive
23.
System Considerations and Guidelines
SRD regulations
International regulations and national laws
regulate the use of radio receivers and
transmitters. SRDs (Short Range Devices)
for license free operation are allowed to
operate in the 433 and 868 – 870 MHz
bands in most European countries. In the
United States, such devices operate in the
260 – 470 and 902 – 928 MHz bands.
CC1020 is also applicable for use in the 950
– 960 MHz frequency band in Japan. A
summary of the most important aspects of
these regulations can be found in
Application Note AN001 SRD regulations
for license free transceiver operation,
available from the TI web site.
Narrowband systems
CC1020 is specifically designed for
narrowband systems complying with ARIB
STD-T67 and EN 300 220. The CC1020
meets the strict requirements to ACP
(Adjacent Channel Power) and occupied
bandwidth for a narrowband transmitter.
To meet the ARIB STD-T67 requirements
a 3.0 V regulated voltage supply should be
used.
For the receiver side, CC1020 gives very
good ACR (Adjacent Channel Rejection),
image frequency suppression and blocking
properties for channel spacings down to
12.5 kHz.
Such narrowband performance normally
requires the use of external ceramic filters.
The CC1020 provides this performance as
a true single-chip solution with integrated
IF filters.
Japan and Korea have allocated several
frequency bands at 424, 426, 429, 447,
449 and 469 MHz for narrowband license
free operation. CC1020 is designed to
meet the requirements for operation in all
these
bands,
including
the
strict
requirements for narrowband operation
down to 12.5 kHz channel spacing.
Due to on-chip complex filtering, the image
frequency is removed. An on-chip
calibration circuit is used to get the best
possible image rejection. A narrowband
preselector filter is not necessary to
achieve image rejection.
A unique feature in CC1020 is the very fine
frequency resolution. This can be used for
temperature compensation of the crystal if
the temperature drift curve is known and a
temperature sensor is included in the
system. Even initial adjustment can be
performed
using
the
frequency
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CC1020
programmability. This eliminates the need
for an expensive TCXO and trimming in
some applications. For more details refer
to Application Note AN027 Temperature
Compensation available from the TI web
site.
In less demanding applications, a crystal
with low temperature drift and low aging
could
be
used
without
further
compensation. A trimmer capacitor in the
crystal oscillator circuit (in parallel with C5)
could be used to set the initial frequency
accurately.
The
frequency
offset
between
a
transmitter and receiver is measured in the
CC1020 and can be read back from the
AFC register. The measured frequency
offset can be used to calibrate the receiver
frequency using the transmitter as the
reference. For more details refer to
Application Note AN029 CC1020/1021
AFC available from the TI web site.
CC1020 also has the possibility to use
Gaussian shaped FSK (GFSK). This
spectrum-shaping
feature
improves
adjacent channel power (ACP) and
occupied bandwidth. In ‘true’ FSK systems
with abrupt frequency shifting, the
spectrum is inherently broad. By making
the frequency shift ‘softer’, the spectrum
can be made significantly narrower. Thus,
higher data rates can be transmitted in the
same bandwidth using GFSK.
Low cost systems
As the CC1020 provides true narrowband
multi-channel performance without any
external filters, a very low cost high
performance system can be achieved. The
oscillator crystal can then be a low cost
crystal with 50 ppm frequency tolerance
using the on-chip frequency tuning
possibilities.
Battery operated systems
In low power applications, the power down
mode should be used when CC1020 is not
being active. Depending on the start-up
time requirement, the oscillator core can
be powered during power down. See
section 17 on page 54 for information on
how effective power management can be
implemented.
High reliability systems
Using a SAW filter as a preselector will
improve the communication reliability in
harsh environments by reducing the
probability of blocking. The receiver
sensitivity and the output power will be
reduced due to the filter insertion loss. By
inserting the filter in the RX path only,
together with an external RX/TX switch,
only the receiver sensitivity is reduced and
output power is remained. The PA_EN
and LNA_EN pin can be configured to
control an external LNA, RX/TX switch or
power amplifier. This is controlled by the
INTERFACE register.
Frequency hopping spread spectrum
systems (FHSS)
Due to the very fast locking properties of
the PLL, the CC1020 is also very suitable
for frequency hopping systems. Hop rates
of 1-100 hops/s are commonly used
depending on the bit rate and the amount
of data to be sent during each
transmission. The two frequency registers
(FREQ_A and FREQ_B) are designed
such that the ‘next’ frequency can be
programmed while the ‘present’ frequency
is used. The switching between the two
frequencies is done through the MAIN
register. Several features have been
included to do the hopping without a need
to re-synchronize the receiver. For more
details refer to Application Note AN014
Frequency Hopping Systems available
from the TI web site.
In order to implement a frequency hopping
system with CC1020 do the following:
Set the desired frequency, calibrate and
store the following register settings in nonvolatile memory:
STATUS1[3:0]: CHP_CURRENT[3:0]
STATUS2[4:0]: VCO_ARRAY[4:0]
STATUS3[5:0]:VCO_CAL_CURRENT[5:0]
Repeat the calibration for each desired
frequency. VCO_CAL_CURRENT[5:0] is
not dependent on the RF frequency and
the same value can be used for all
frequencies.
When performing frequency hopping, write
the stored values to the corresponding
TEST1, TEST2 and TEST3 registers, and
enable override:
TEST1[3:0]: CHP_CO[3:0]
TEST2[4:0]: VCO_AO[4:0]
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CC1020
TEST2[5]: VCO_OVERRIDE
TEST2[6]: CHP_OVERRIDE
TEST3[5:0]: VCO_CO[5:0]
TEST3[6]: VCO_CAL_OVERRIDE
set by register FREQ_B which can be
written to while operating on channel 1.
The calibration data must be written to the
TEST1-3 registers after switching to the
next frequency. That is, when hopping to a
new channel write to register MAIN[6] first
and the test registers next. The PA should
be switched off between each hop and the
PLL should be checked for lock before
switching the PA back on after a hop has
been performed.
CHP_CO[3:0] is the register setting read
from CHP_CURRENT[3:0], VCO_AO[4:0]
is
the register setting read from
VCO_ARRAY[4:0] and VCO_CO[5:0] is
the
register
setting
read
from
VCO_CAL_CURRENT[5:0].
Assume channel 1 defined by register
FREQ_A is currently being used and that
CC1020 should operate on channel 2 next
(to change channel simply write to register
MAIN[6]). The channel 2 frequency can be
24.
Note
that
the
override
bits
VCO_OVERRIDE, CHP_OVERRIDE and
VCO_CAL_OVERRIDE must be disabled
when performing a re-calibration.
PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be
filled with metallization connected to
ground using several vias.
decoupling capacitor and then to the
CC1020 supply pin. Supply power filtering is
very important, especially for pins 23, 22,
20 and 18.
The area under the chip is used for
grounding and must be connected to the
bottom ground plane with several vias. In
the TI reference designs we have placed 9
vias inside the exposed die attached pad.
These vias should be “tented” (covered
with solder mask) on the component side
of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
Each decoupling capacitor ground pad
should be connected to the ground plane
using a separate via. Direct connections
between neighboring power pins will
increase noise coupling and should be
avoided unless absolutely necessary.
Do not place a via underneath CC1020 at
“pin #1 corner” as this pin is internally
connected to the exposed die attached
pad, which is the main ground connection
for the chip.
Each decoupling capacitor should be
placed as close as possible to the supply
pin it is supposed to decouple. Each
decoupling capacitor should be connected
to the power line (or power plane) by
separate vias. The best routing is from the
power line (or power plane) to the
The external components should ideally
be as small as possible and surface mount
devices are highly recommended.
Precaution should be used when placing
the microcontroller in order to avoid noise
interfering with the RF circuitry.
A CC1020/1070DK Development Kit with
a fully assembled CC1020EMX Evaluation
Module is available. It is strongly advised
that this reference layout is followed very
closely in order to get the best
performance. The layout Gerber files are
available from the TI web site.
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CC1020
25.
Antenna Considerations
CC1020 can be used together with various
types of antennas. The most common
antennas for short-range communication
are monopole, helical and loop antennas.
Monopole
antennas
are
resonant
antennas with a length corresponding to
one quarter of the electrical wavelength
(/4). They are very easy to design and
can be implemented simply as a “piece of
wire” or even integrated onto the PCB.
Non-resonant monopole antennas shorter
than /4 can also be used, but at the
expense of range. In size and cost critical
applications such an antenna may very
well be integrated onto the PCB.
Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in
size critical applications. But helical
antennas tend to be more difficult to
optimize than the simple monopole.
Loop antennas are easy to integrate into
the PCB, but are less effective due to
26.
difficult impedance matching because of
their very low radiation resistance.
For low power applications the /4monopole antenna is recommended due
to its simplicity as well as providing the
best range.
The length of the /4-monopole antenna is
given by:
L = 7125 / f
where f is in MHz, giving the length in cm.
An antenna for 868 MHz should be 8.2
cm, and 16.4 cm for 433 MHz.
The antenna should be connected as
close as possible to the IC. If the antenna
is located away from the input pin the
antenna should be matched to the feeding
transmission line (50 ).
For a more thorough background on
antennas, please refer to Application Note
AN003 SRD Antennas available from the
TI web site.
Configuration Registers
The configuration of CC1020 is done by
programming the 8-bit configuration
registers. The configuration data based on
selected system parameters are most
easily found by using the SmartRF Studio
software. Complete descriptions of the
registers are given in the following tables.
After a RESET is programmed, all the
registers have default values. The TEST
registers also get default values after a
RESET, and should not be altered by the
user.
TI recommends using the register settings
found using the SmartRF Studio
software. These are the register settings
that TI specifies across temperature,
voltage and process. Please check the TI
web site for regularly updates to the
SmartRF Studio software.
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CC1020
26.1. CC1020 Register Overview
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
Byte Name
MAIN
INTERFACE
RESET
SEQUENCING
FREQ_2A
FREQ_1A
FREQ_0A
CLOCK_A
FREQ_2B
FREQ_1B
FREQ_0B
CLOCK_B
VCO
MODEM
DEVIATION
AFC_CONTROL
FILTER
VGA1
VGA2
VGA3
VGA4
LOCK
FRONTEND
ANALOG
BUFF_SWING
BUFF_CURRENT
PLL_BW
CALIBRATE
PA_POWER
MATCH
PHASE_COMP
GAIN_COMP
POWERDOWN
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
STATUS
RESET_DONE
RSSI
AFC
GAUSS_FILTER
STATUS1
STATUS2
STATUS3
STATUS4
STATUS5
STATUS6
STATUS7
Description
Main control register
Interface control register
Digital module reset register
Automatic power-up sequencing control register
Frequency register 2A
Frequency register 1A
Frequency register 0A
Clock generation register A
Frequency register 2B
Frequency register 1B
Frequency register 0B
Clock generation register B
VCO current control register
Modem control register
TX frequency deviation register
RX AFC control register
Channel filter / RSSI control register
VGA control register 1
VGA control register 2
VGA control register 3
VGA control register 4
Lock control register
Front end bias current control register
Analog modules control register
LO buffer and prescaler swing control register
LO buffer and prescaler bias current control register
PLL loop bandwidth / charge pump current control register
PLL calibration control register
Power amplifier output power register
Match capacitor array control register, for RX and TX impedance matching
Phase error compensation control register for LO I/Q
Gain error compensation control register for mixer I/Q
Power-down control register
Test register for overriding PLL calibration
Test register for overriding PLL calibration
Test register for overriding PLL calibration
Test register for charge pump and IF chain testing
Test register for ADC testing
Test register for VGA testing
Test register for VGA testing
Status information register (PLL lock, RSSI, calibration ready, etc.)
Status register for digital module reset
Received signal strength register
Average received frequency deviation from IF (can be used for AFC)
Digital FM demodulator register
Status of PLL calibration results etc. (test only)
Status of PLL calibration results etc. (test only)
Status of PLL calibration results etc. (test only)
Status of ADC signals (test only)
Status of channel filter “I” signal (test only)
Status of channel filter “Q” signal (test only)
Status of AGC (test only)
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CC1020
MAIN Register (00h)
REGISTER
NAME
Active
RXTX
F_REG
Default
value
-
MAIN[7]
MAIN[6]
MAIN[5:4]
PD_MODE[1 :0]
-
-
MAIN[3]
MAIN[2]
MAIN[1]
FS_PD
XOSC_PD
BIAS_PD
-
H
H
H
MAIN[0]
RESET_N
-
L
-
Description
RX/TX switch, 0: RX , 1: TX
Selection of Frequency Register,
0: Register A, 1: Register B
Power down mode
0 (00): Receive Chain in power-down in TX, PA in power-down in
RX
1 (01): Receive Chain and PA in power-down in both TX and RX
2 (10): Individual modules can be put in power-down by
programming the POWERDOWN register
3 (11): Automatic power-up sequencing is activated (see below)
Power Down of Frequency Synthesizer
Power Down of Crystal Oscillator Core
Power Down of BIAS (Global Current Generator) and Crystal
Oscillator Buffer
Reset, active low. Writing RESET_N low will write default values to
all other registers than MAIN. Bits in MAIN do not have a default
value and will be written directly through the configuration
interface. Must be set high to complete reset.
MAIN Register (00h) when using automatic power-up sequencing (RXTX = 0, PD_MODE[1:0] =11)
REGISTER
NAME
Active
RXTX
F_REG
PD_MODE[1 :0]
SEQ_CAL[1:0]
Default
value
-
MAIN[7]
MAIN[6]
MAIN[5 :4]
MAIN[3:2]
MAIN[1]
SEQ_PD
-
MAIN[0]
RESET_N
-
L
H
-
Description
Automatic power-up sequencing only works in RX (RXTX=0)
Selection of Frequency Register, 0: Register A, 1: Register B
Set PD_MODE[1:0]=3 (11) to enable sequencing
Controls PLL calibration before re-entering power-down
0: Never perform PLL calibration as part of sequence
1: Always perform PLL calibration at end of sequence
2: Perform PLL calibration at end of every 16th sequence
3: Perform PLL calibration at end of every 256th sequence
1: Put the chip in power down and wait for start of new power-up
sequence
Reset, active low. Writing RESET_N low will write default values to
all other registers than MAIN. Bits in MAIN do not have a default
value and will be written directly through the configuration
interface. Must be set high to complete reset.
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CC1020
INTERFACE Register (01h)
REGISTER
NAME
Active
XOSC_BYPASS
Default
value
0
INTERFACE[7]
INTERFACE[6]
SEP_DI_DO
0
H
H
INTERFACE[5]
DCLK_LOCK
0
H
INTERFACE[4]
DCLK_CS
0
H
INTERFACE[3]
EXT_PA
0
H
INTERFACE[2]
EXT_LNA
0
H
INTERFACE[1]
EXT_PA_POL
0
H
INTERFACE[0]
EXT_LNA_POL
0
H
Description
Bypass internal crystal oscillator, use external clock
0: Internal crystal oscillator is used, or external sine wave fed
through a coupling capacitor
1: Internal crystal oscillator in power down, external clock
with rail-to-rail swing is used
Use separate pin for RX data output
0: DIO is data output in RX and data input in TX. LOCK pin
is available (Normal operation).
1: DIO is always input, and a separate pin is used for RX
data output (synchronous mode: LOCK pin, asynchronous
mode: DCLK pin).
If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING
register then negative transitions on DIO is used to start
power-up sequencing when PD_MODE=3 (power-up
sequencing is enabled).
Gate DCLK signal with PLL lock signal in synchronous mode
Only applies when PD_MODE = “01”
0: DCLK is always 1
1: DCLK is always 1 unless PLL is in lock
Gate DCLK signal with carrier sense indicator in
synchronous mode
Use when receive chain is active (in power-up)
Always set to 0 in TX mode.
0: DCLK is independent of carrier sense indicator.
1: DCLK is always 1 unless carrier sense is indicated
Use PA_EN pin to control external PA
0: PA_EN pin always equals EXT_PA_POL bit
1: PA_EN pin is asserted when internal PA is turned on
Use LNA_EN pin to control external LNA
0: LNA_EN pin always equals EXT_LNA_POL bit
1: LNA_EN pin is asserted when internal LNA is turned on
Polarity of external PA control
0: PA_EN pin is “0” when activating external PA
1: PA_EN pin is “1” when activating external PA
Polarity of external LNA control
0: LNA_EN pin is “0” when activating external LNA
1: LNA_EN pin is “1” when activating external LNA
Note: If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test
module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1
and TEST_MODE[2:0]=001.
RESET Register (02h)
REGISTER
NAME
Active
ADC_RESET_N
AGC_RESET_N
GAUSS_RESET_N
AFC_RESET_N
BITSYNC_RESET_N
Default
value
0
0
0
0
0
RESET[7]
RESET[6]
RESET[5]
RESET[4]
RESET[3]
RESET[2]
RESET[1]
RESET[0]
SYNTH_RESET_N
SEQ_RESET_N
CAL_LOCK_RESET_N
0
0
0
L
L
L
L
L
L
L
L
Description
Reset ADC control logic
Reset AGC (VGA control) logic
Reset Gaussian data filter
Reset AFC / FSK decision level logic
Reset modulator, bit synchronization logic and PN9
PRBS generator
Reset digital part of frequency synthesizer
Reset power-up sequencing logic
Reset calibration logic and lock detector
Note: For reset of CC1020 write RESET_N=0 in the MAIN register. The reset register should not be
used during normal operation.
Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant
digital clocks must be running for the resetting to complete. After writing to the RESET register, the user
should verify that all reset operations have been completed, by reading the RESET_DONE status
register (41h) until all bits equal 1.
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CC1020
SEQUENCING Register (03h)
REGISTER
NAME
Active
SEQ_PSEL
Default
value
1
SEQUENCING[7]
SEQUENCING[6:4]
RX_WAIT[2:0]
0
-
SEQUENCING[3:0]
CS_WAIT[3:0]
10
-
H
Description
Use PSEL pin to start sequencing
0: PSEL pin does not start sequencing. Negative
transitions on DIO starts power-up sequencing if
SEP_DI_DO=1.
1: Negative transitions on the PSEL pin will start powerup sequencing
Waiting time from PLL enters lock until RX power-up
0: Wait for approx. 32 ADC_CLK periods (26 μs)
1: Wait for approx. 44 ADC_CLK periods (36 μs)
2: Wait for approx. 64 ADC_CLK periods (52 μs)
3: Wait for approx. 88 ADC_CLK periods (72 μs)
4: Wait for approx. 128 ADC_CLK periods (104 μs)
5: Wait for approx. 176 ADC_CLK periods (143 μs)
6: Wait for approx. 256 ADC_CLK periods (208 μs)
7: No additional waiting time before RX power-up
Waiting time for carrier sense from RX power-up
0: Wait 20 FILTER_CLK periods before power down
1: Wait 22 FILTER_CLK periods before power down
2: Wait 24 FILTER_CLK periods before power down
3: Wait 26 FILTER_CLK periods before power down
4: Wait 28 FILTER_CLK periods before power down
5: Wait 30 FILTER_CLK periods before power down
6: Wait 32 FILTER_CLK periods before power down
7: Wait 36 FILTER_CLK periods before power down
8: Wait 40 FILTER_CLK periods before power down
9: Wait 44 FILTER_CLK periods before power down
10: Wait 48 FILTER_CLK periods before power down
11: Wait 52 FILTER_CLK periods before power down
12: Wait 56 FILTER_CLK periods before power down
13: Wait 60 FILTER_CLK periods before power down
14: Wait 64 FILTER_CLK periods before power down
15: Wait 72 FILTER_CLK periods before power down
FREQ_2A Register (04h)
REGISTER
NAME
FREQ_2A[7:0]
FREQ_A[22:15]
Default
value
131
Active
Default
value
177
Active
Default
value
124
1
Active
-
Description
8 MSB of frequency control word A
FREQ_1A Register (05h)
REGISTER
NAME
FREQ_1A[7:0]
FREQ_A[14:7]
-
Description
Bit 15 to 8 of frequency control word A
FREQ_0A Register (06h)
REGISTER
NAME
FREQ_0A[7:1]
FREQ_0A[0]
FREQ_A[6:0]
DITHER_A
H
SWRS046F
Description
7 LSB of frequency control word A
Enable dithering for frequency A
Page 69 of 89
CC1020
CLOCK_A Register (07h)
REGISTER
NAME
CLOCK_A[7:5]
REF_DIV_A[2:0]
Default
value
2
Active
-
CLOCK_A[4:2]
MCLK_DIV1_A[2:0]
4
-
CLOCK_A[1:0]
MCLK_DIV2_A[1:0]
0
-
Description
Reference frequency divisor (A):
0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
It is recommended to use the highest possible reference
clock frequency that allows the desired Baud rate.
Modem clock divider 1 (A):
0: Divide by 2.5
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5·3)
4: Divide by 12.5 (2.5·5)
5: Divide by 40 (2.5·16)
6: Divide by 48 (3·16)
7: Divide by 64 (4·16)
Modem clock divider 2 (A):
0: Divide by 1
1: Divide by 2
2: Divide by 4
3: Divide by 8
MODEM_CLK frequency is FREF frequency divided by
the product of divider 1 and divider 2.
Baud rate is MODEM_CLK frequency divided by 8.
FREQ_2B Register (08h)
REGISTER
NAME
FREQ_2B[7:0]
FREQ_B[22:15]
Default
value
131
Active
Default
value
189
Active
Default
value
124
1
Active
-
Description
8 MSB of frequency control word B
FREQ_1B Register (09h)
REGISTER
NAME
FREQ_1B[7:0]
FREQ_B[14:7]
-
Description
Bit 15 to 8 of frequency control word B
FREQ_0B Register (0Ah)
REGISTER
NAME
FREQ_0B[7:1]
FREQ_0B[0]
FREQ_B[6:0]
DITHER_B
H
SWRS046F
Description
7 LSB of frequency control word B
Enable dithering for frequency B
Page 70 of 89
CC1020
CLOCK_B Register (0Bh)
REGISTER
NAME
Active
REF_DIV_B[2:0]
Default
value
2
CLOCK_B[7:5]
CLOCK_B[4:2]
MCLK_DIV1_B[2:0]
4
-
CLOCK_B[1:0]
MCLK_DIV2_B[1:0]
0
-
-
Description
Reference frequency divisor (B):
0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
Modem clock divider 1 (B):
0: Divide by 2.5
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5·3)
4: Divide by 12.5 (2.5·5)
5: Divide by 40 (2.5·16)
6: Divide by 48 (3·16)
7: Divide by 64 (4·16)
Modem clock divider 2 (B):
0: Divide by 1
1: Divide by 2
2: Divide by 4
3: Divide by 8
MODEM_CLK frequency is FREF frequency divided by
the product of divider 1 and divider 2.
Baud rate is MODEM_CLK frequency divided by 8.
VCO Register (0Ch)
REGISTER
NAME
Active
VCO_CURRENT_A[3:0]
Default
value
8
VCO[7 :4]
VCO[3:0]
VCO_CURRENT_B[3:0]
8
-
-
Description
Control of current in VCO core for frequency A
0 : 1.4 mA current in VCO core
1 : 1.8 mA current in VCO core
2 : 2.1 mA current in VCO core
3 : 2.5 mA current in VCO core
4 : 2.8 mA current in VCO core
5 : 3.2 mA current in VCO core
6 : 3.5 mA current in VCO core
7 : 3.9 mA current in VCO core
8 : 4.2 mA current in VCO core
9 : 4.6 mA current in VCO core
10 : 4.9 mA current in VCO core
11 : 5.3 mA current in VCO core
12 : 5.6 mA current in VCO core
13 : 6.0 mA current in VCO core
14 : 6.4 mA current in VCO core
15 : 6.7 mA current in VCO core
Recommended setting: VCO_CURRENT_A=4
Control of current in VCO core for frequency B
The current steps are the same as for
VCO_CURRENT_A
Recommended setting: VCO_CURRENT_B=4
SWRS046F
Page 71 of 89
CC1020
MODEM Register (0Dh)
REGISTER
NAME
MODEM[7]
MODEM[6:4]
ADC_DIV[2:0]
MODEM[3]
MODEM[2]
MODEM[1:0]
Default
value
0
3
PN9_ENABLE
Active
-
0
0
DATA_FORMAT[1:0]
Reserved, write 0
ADC clock divisor
0: Not supported
1: ADC frequency = XOSC frequency / 4
2: ADC frequency = XOSC frequency / 6
3: ADC frequency = XOSC frequency / 8
4: ADC frequency = XOSC frequency / 10
5: ADC frequency = XOSC frequency / 12
6: ADC frequency = XOSC frequency / 14
7: ADC frequency = XOSC frequency / 16
Note that the intermediate frequency should be as close
to 307.2 kHz as possible. ADC clock frequency is always
4 times the intermediate frequency and should therefore
be as close to 1.2288 MHz as possible.
Reserved, write 0
Enable scrambling of TX and RX with PN9 pseudorandom bit sequence
0: PN9 scrambling is disabled
1: PN9 scrambling is enabled (x9+x5+1)
H
0
Description
The PN9 pseudo-random bit sequence can be used for
BER testing by only transmitting zeros, and then
counting the number of received ones.
Modem data format
0 (00): NRZ operation
1 (01): Manchester operation
2 (10): Transparent asynchronous UART operation, set
DCLK=0
3 (11): Transparent asynchronous UART operation, set
DCLK=1
-
DEVIATION Register (0Eh)
REGISTER
NAME
Active
TX_SHAPING
Default
value
1
DEVIATION[7]
DEVIATION[6 :4]
DEVIATION [3 :0]
TXDEV_X[2 :0]
TXDEV_M[3 :0]
6
8
-
H
Description
Enable Gaussian shaping of transmitted data
Recommended setting: TX_SHAPING=1
Transmit frequency deviation exponent
Transmit frequency deviation mantissa
Deviation in 402-470 MHz band:
FREF ·TXDEV_M ·2(TXDEV_X−16)
Deviation in 804-960 MHz band:
FREF ·TXDEV_M ·2(TXDEV_X−15)
On-off-keying (OOK) is used in RX/TX if TXDEV_M[3:0]=0
To find TXDEV_M given the deviation and TXDEV_X:
TXDEV_M = deviation·2(16−TXDEV_X)/FREF
in 402-470 MHz band,
TXDEV_M = deviation·2(15−TXDEV_X)/FREF
in 804-960 MHz band.
Decrease TXDEV_X and try again if TXDEV_M 8.
Increase TXDEV_X and try again if TXDEV_M 16.
SWRS046F
Page 72 of 89
CC1020
AFC_CONTROL Register (0Fh)
REGISTER
NAME
AFC_CONTROL[7:6]
SETTLING[1:0]
AFC_CONTROL[5:4]
AFC_CONTROL[3:0]
Default
value
2
RXDEV_X[1:0]
RXDEV_M[3:0]
Active
-
1
12
Description
Controls AFC settling time versus accuracy
0: AFC off; zero average frequency is used in demodulator
1: Fastest settling; frequency averaged over 1 0/1 bit pair
2: Medium settling; frequency averaged over 2 0/1 bit pairs
3: Slowest settling; frequency averaged over 4 0/1 bit pairs
Recommended setting: AFC_CONTROL=3 for higher
accuracy unless it is essential to have the fastest settling
time when transmission starts after RX is activated.
RX frequency deviation exponent
RX frequency deviation mantissa
-
Expected RX deviation should be:
Baud rate · RXDEV_M ·2(RXDEV_X−3) / 3
To find RXDEV_M given the deviation and RXDEV_X:
RXDEV_M = 3 · deviation ·2(3−RXDEV_X) / Baud rate
Decrease RXDEV_X and try again if RXDEV_M8.
Increase RXDEV_X and try again if RXDEV_M16.
Note: The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100
kBaud data rate and below. The RX frequency deviation should be close to the TX frequency deviation
for FSK and for GFSK at 100 kBaud data rate and above.
FILTER Register (10h)
REGISTER
NAME
FILTER[7]
FILTER_BYPASS
FILTER[6:5]
FILTER[4:0]
DEC_SHIFT[1:0]
DEC_DIV[4:0]
Default
value
0
0
0
Active
H
-
-
Description
Bypass analog image rejection / anti-alias filter. Set to 1 for
increased dynamic range at high Baud rates.
Recommended setting:
FILTER_BYPASS=0 below 76.8 kBaud,
FILTER_BYPASS=1 for 76.8 kBaud and up.
Number of extra bits to shift decimator input
(may improve filter accuracy and lower power consumption).
Recommended settings:
DEC_SHIFT=0 when DEC_DIV ≤1 (receiver channel bandwidth
≥ 153.6 kHz),
DEC_SHIFT=1 when optimized sensitivity and 1< DEC_DIV
24 (12.29 kHz < receiver channel bandwidth < 153.6 kHz),
DEC_SHIFT=2 when optimized selectivity and DEC_DIV 24
(receiver channel bandwidth ≤12.29 kHz)
Decimation clock divisor
0: Decimation clock divisor = 1, 307.2 kHz channel filter BW.
1: Decimation clock divisor = 2, 153.6 kHz channel filter BW.
…
30: Decimation clock divisor = 31, 9.91 kHz channel filter BW.
31: Decimation clock divisor = 32, 9.6 kHz channel filter BW.
Channel filter bandwidth is 307.2 kHz divided by the decimation
clock divisor.
SWRS046F
Page 73 of 89
CC1020
VGA1 Register (11h)
REGISTER
NAME
VGA1[7 :6]
CS_SET[1:0]
VGA1[5]
CS_RESET
Default
value
1
1
Active
-
-
VGA1[4 :2]
VGA_WAIT[2 :0]
1
-
VGA1[1:0]
VGA_FREEZE[1:0]
1
-
Description
Sets the number of consecutive samples at or above carrier
sense level before carrier sense is indicated (e.g. on LOCK
pin)
0: Set carrier sense after first sample at or above carrier sense
level
1: Set carrier sense after second sample at or above carrier
sense level
2: Set carrier sense after third sample at or above carrier
sense level
3: Set carrier sense after fourth sample at or above carrier
sense level
Increasing CS_SET reduces the number of “false” carrier
sense events due to noise at the expense of increased carrier
sense response time.
Sets the number of consecutive samples below carrier sense
level before carrier sense indication (e.g. on lock pin) is reset
0: Carrier sense is reset after first sample below carrier sense
level
1: Carrier sense is reset after second sample below carrier
sense level
Recommended setting: CS_RESET=1 in order to reduce the
chance of losing carrier sense due to noise.
Controls how long AGC, bit synchronization, AFC and RSSI
levels are frozen after VGA gain is changed when frequency is
changed between A and B or PLL has been out of lock or after
RX power-up
0: Freeze operation for 16 filter clocks, 8/(filter BW) seconds
1: Freeze operation for 20 filter clocks, 10/(filter BW) seconds
2: Freeze operation for 24 filter clocks, 12/(filter BW) seconds
3: Freeze operation for 28 filter clocks, 14/(filter BW) seconds
4: Freeze operation for 32 filter clocks, 16/(filter BW) seconds
5: Freeze operation for 40 filter clocks, 20/(filter BW) seconds
6: Freeze operation for 48 filter clocks, 24/(filter BW) seconds
7: Freeze present levels unconditionally
Controls the additional time AGC, bit synchronization, AFC
and RSSI levels are frozen when frequency is changed
between A and B or PLL has been out of lock or after RX
power-up
0: Freeze levels for approx. 16 ADC_CLK periods (13 μs)
1: Freeze levels for approx. 32 ADC_CLK periods (26 μs)
2: Freeze levels for approx. 64 ADC_CLK periods (52 μs)
3: Freeze levels for approx. 128 ADC_CLK periods (104 μs)
SWRS046F
Page 74 of 89
CC1020
VGA2 Register (12h)
REGISTER
NAME
Active
LNA2_MIN
Default
value
0
VGA2[7]
VGA2[6]
LNA2_MAX
1
-
VGA2[5:4]
LNA2_SETTING[1:0]
3
-
-
Description
Minimum LNA2 setting used in VGA
0: Minimum LNA2 gain
1: Medium LNA2 gain
Recommended setting: LNA2_MIN=0 for best selectivity.
Maximum LNA2 setting used in VGA
0: Medium LNA2 gain
1: Maximum LNA2 gain
Recommended setting: LNA2_MAX=1 for best sensitivity.
Selects at what VGA setting the LNA gain should be
changed
0: Apply LNA2 change below min. VGA setting.
1: Apply LNA2 change at approx. 1/3 VGA setting (around
VGA setting 10).
2: Apply LNA2 change at approx. 2/3 VGA setting (around
VGA setting 19).
3: Apply LNA2 change above max. VGA setting.
Recommended setting:
LNA2_SETTING=0 if VGA_SETTING
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