CC1110EMK868-915

CC1110Fx / CC1111Fx Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller Applications Low-power SoC wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands Wireless alarm and security systems Industrial monitoring and control Wireless sensor networks AMR - Automatic Meter Reading Home and building automation Low power telemetry CC1111Fx: USB dongles Product Description ON-CHIP VOLTAGE REGULATOR 26 / 48 MHz CRYSTAL OSC HIGH SPEED RCOSC POWER ON RESET 32.768 kHz CRYSTAL OSC LOW POWER RC-OSC SLEEP TIMER DEBUG INTERFACE CLOCK MUX & CALIBRATION SLEEP MODE CONTROLLER DMA 8051 CPU CORE DCOUPL RESET_N XOSC_Q2 XOSC_Q1 32 KB FLASH P2_4 P2_3 P2_2 MEMORY ARBITRATOR 4 KB SRAM P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 AES ENCRYPTION & DECRYPTION ADC AUDIO / DC 8 CHANNELS IRQ CTRL FLASH WRITE RADIO REGISTERS RADIO DATA INTERFACE P1_0 CC1110Fx P0_7 DEMODULATOR USART 2 P0_6 AGC MODULATOR P0_5 TIMER 1 (16-bit) + P0_4 Noise Shaper P0_3 TIMER 2 (MAC TIMER) P0_2 P0_1 P0_0 RECEIVE CHAIN TIMER 3 (8-bit) TIMER 4 (8-bit) FRAME CONTROL USART 1 FREQUENCY SYNTHESIZER The CC1110Fx/CC1111Fx is highly suited for systems where very low power consumption is required. This is ensured by several advanced low-power operating modes. The CC1111Fx adds a full-speed USB 2.0 interface to the feature set of the CC1110Fx. Interfacing to a PC using the USB interface is quick and easy, and the high data rate (12 Mbps) of the USB interface avoids the bottlenecks of RS-232 or low-speed USB interfaces. WATCHDOG TIMER ANALOG MIXED VDD (2.0 - 3.6 V) RESET DIGITAL I/O CONTROLLER The CC1110Fx/CC1111Fx is a true low-power sub1 GHz system-on-chip (SoC) designed for lowpower wireless applications. The CC1110Fx/CC1111Fx combines the excellent performance of the state-of-the-art RF transceiver CC1101 with an industry-standard enhanced 8051 MCU, up to 32 kB of in-system programmable flash memory and up to 4 kB of RAM, and many other powerful features. The small 6x6 mm package makes it very suited for applications with size limitations. TRANSMIT CHAIN I2S DP DM CC1111Fx USB PHY USB 1 KB FIFO SRAM RF_P RF_N Key Features Radio o o o o o o o o High-performance RF transceiver based on the market-leading CC1101 Excellent receiver selectivity and blocking performance High sensitivity (−110 dBm at 1.2 kBaud) Programmable data rate up to 500 kBaud Programmable output power up to 10 dBm for all supported frequencies Frequency range: 300 - 348 MHz, 391 - 464 MHz and 782 - 928 MHz Digital RSSI / LQI support Low Power o o o Low current consumption (RX: 16.2 mA @ 1.2 kBaud, TX: 15.2 mA @ −6 dBm output power) 0.3 μA in PM3 (the operating mode with the lowest power consumption) 0.5 µA in PM2 (operating mode with the second lowest power consumption, timer or external interrupt wakeup) SWRS033H MCU, Memory, and Peripherals o o o o o o o o o o o o o High performance and low power 8051 microcontroller core. Powerful DMA functionality 8/16/32 KB in-system programmable flash, and 1/2/4 KB RAM Full-Speed USB Controller with 1 KB FIFO (CC1111Fx ) 128-bit AES security coprocessor 7 - 12 bit ADC with up to eight inputs 2 I S interface Two USARTs 16-bit timer with DSM mode Three 8-bit timers Hardware debug support 21 (CC1110Fx ) or 19 (CC1111Fx ) GPIO pins SW compatible with CC2510Fx/CC2511Fx General o o Wide supply voltage range (2.0V - 3.6V) RoHS compliant 6x6 mm QFN 36 package Page 1 of 246 CC1110Fx / CC1111Fx Table of Contents ABBREVIATION .................................................................................................................................................. 4 1 REGISTER CONVENTIONS .................................................................................................................. 5 2 KEY FEATURES (IN MORE DETAILS) .............................................................................................. 5 2.1 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER....................................... 5 2.2 8/16/32 KB NON-VOLATILE PROGRAM MEMORY AND 1/2/4 KB DATA MEMORY ........................................ 5 2.3 FULL-SPEED USB CONTROLLER (CC1111FX )................................................................................................. 5 2.4 I2S INTERFACE .............................................................................................................................................. 5 2.5 HARDWARE AES ENCRYPTION/DECRYPTION ............................................................................................... 6 2.6 PERIPHERAL FEATURES ................................................................................................................................ 6 2.7 LOW POWER ................................................................................................................................................. 6 2.8 SUB-1 GHZ RADIO WITH BASEBAND MODEM .............................................................................................. 6 3 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 7 4 OPERATING CONDITIONS .................................................................................................................. 8 4.1 CC1110FX OPERATING CONDITIONS ............................................................................................................... 8 4.2 CC1111FX OPERATING CONDITIONS ............................................................................................................... 8 5 GENERAL CHARACTERISTICS .......................................................................................................... 8 6 ELECTRICAL SPECIFICATIONS ........................................................................................................ 9 6.1 CURRENT CONSUMPTION ............................................................................................................................. 9 6.2 RF RECEIVE SECTION ................................................................................................................................. 13 6.3 RF TRANSMIT SECTION .............................................................................................................................. 17 6.4 CRYSTAL OSCILLATORS ............................................................................................................................. 19 6.5 32.768 KHZ CRYSTAL OSCILLATOR ........................................................................................................... 20 6.6 LOW POWER RC OSCILLATOR .................................................................................................................... 20 6.7 HIGH SPEED RC OSCILLATOR .................................................................................................................... 21 6.8 FREQUENCY SYNTHESIZER CHARACTERISTICS ........................................................................................... 21 6.9 ANALOG TEMPERATURE SENSOR ............................................................................................................... 22 6.10 7 - 12 BIT ADC ........................................................................................................................................... 23 6.11 CONTROL AC CHARACTERISTICS ............................................................................................................... 25 6.12 SPI AC CHARACTERISTICS ......................................................................................................................... 26 6.13 DEBUG INTERFACE AC CHARACTERISTICS ................................................................................................ 27 6.14 PORT OUTPUTS AC CHARACTERISTICS ...................................................................................................... 27 6.15 TIMER INPUTS AC CHARACTERISTICS ........................................................................................................ 28 6.16 DC CHARACTERISTICS ............................................................................................................................... 28 7 PIN AND I/O PORT CONFIGURATION ............................................................................................ 29 8 CIRCUIT DESCRIPTION ..................................................................................................................... 33 8.1 CPU AND PERIPHERALS ............................................................................................................................. 34 8.2 RADIO ........................................................................................................................................................ 36 9 APPLICATION CIRCUIT ..................................................................................................................... 36 9.1 BIAS RESISTOR ........................................................................................................................................... 36 9.2 BALUN AND RF MATCHING ........................................................................................................................ 36 9.3 CRYSTAL .................................................................................................................................................... 36 9.4 REFERENCE SIGNAL ................................................................................................................................... 37 9.5 USB (CC1111FX) .......................................................................................................................................... 37 9.6 POWER SUPPLY DECOUPLING ..................................................................................................................... 37 9.7 PCB LAYOUT RECOMMENDATIONS ............................................................................................................ 41 10 8051 CPU .................................................................................................................................................. 41 10.1 8051 INTRODUCTION .................................................................................................................................. 41 10.2 MEMORY .................................................................................................................................................... 42 10.3 CPU REGISTERS ......................................................................................................................................... 54 10.4 INSTRUCTION SET SUMMARY ..................................................................................................................... 56 10.5 INTERRUPTS................................................................................................................................................ 60 11 DEBUG INTERFACE............................................................................................................................. 70 11.1 DEBUG MODE ............................................................................................................................................. 70 11.2 DEBUG COMMUNICATION........................................................................................................................... 70 11.3 DEBUG LOCK BIT ....................................................................................................................................... 71 SWRS033H Page 2 of 246 CC1110Fx / CC1111Fx 11.4 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 13.15 13.16 13.17 13.18 13.19 14 14.1 15 16 17 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 21 22 DEBUG COMMANDS.................................................................................................................................... 72 PERIPHERALS ....................................................................................................................................... 76 POWER MANAGEMENT AND CLOCKS.......................................................................................................... 76 RESET ......................................................................................................................................................... 83 FLASH CONTROLLER .................................................................................................................................. 84 I/O PORTS................................................................................................................................................... 90 DMA CONTROLLER ................................................................................................................................. 101 16-BIT TIMER, TIMER 1............................................................................................................................. 112 MAC TIMER (TIMER 2) ............................................................................................................................ 124 SLEEP TIMER ............................................................................................................................................ 126 8-BIT TIMERS, TIMER 3 AND TIMER 4 ....................................................................................................... 130 ADC ......................................................................................................................................................... 141 RANDOM NUMBER GENERATOR ............................................................................................................... 147 AES COPROCESSOR .................................................................................................................................. 148 WATCHDOG TIMER................................................................................................................................... 151 USART .................................................................................................................................................... 153 I2S ............................................................................................................................................................ 162 USB CONTROLLER ................................................................................................................................... 170 RADIO .................................................................................................................................................... 186 COMMAND STROBES ................................................................................................................................ 186 RADIO REGISTERS .................................................................................................................................... 188 INTERRUPTS.............................................................................................................................................. 188 TX/RX DATA TRANSFER ......................................................................................................................... 190 DATA RATE PROGRAMMING ..................................................................................................................... 191 RECEIVER CHANNEL FILTER BANDWIDTH ................................................................................................ 191 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION ............................................................ 192 PACKET HANDLING HARDWARE SUPPORT ............................................................................................... 193 MODULATION FORMATS........................................................................................................................... 196 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ......................................................... 197 FORWARD ERROR CORRECTION WITH INTERLEAVING .............................................................................. 201 RADIO CONTROL ...................................................................................................................................... 202 FREQUENCY PROGRAMMING .................................................................................................................... 205 VCO ......................................................................................................................................................... 206 OUTPUT POWER PROGRAMMING .............................................................................................................. 206 SHAPING AND PA RAMPING ..................................................................................................................... 207 SELECTIVITY ............................................................................................................................................ 208 SYSTEM CONSIDERATIONS AND GUIDELINES ........................................................................................... 209 RADIO REGISTERS .................................................................................................................................... 212 VOLTAGE REGULATORS ................................................................................................................ 230 VOLTAGE REGULATOR POWER-ON ........................................................................................................... 230 RADIO TEST OUTPUT SIGNALS ..................................................................................................... 230 REGISTER OVERVIEW ..................................................................................................................... 232 PACKAGE DESCRIPTION (QFN 36) ................................................................................................ 236 RECOMMENDED PCB LAYOUT FOR PACKAGE (QFN 36) .......................................................................... 238 SOLDERING INFORMATION ........................................................................................................................ 238 TRAY SPECIFICATION ............................................................................................................................... 238 CARRIER TAPE AND REEL SPECIFICATION ................................................................................................ 239 ORDERING INFORMATION ............................................................................................................. 239 REFERENCES ...................................................................................................................................... 240 GENERAL INFORMATION ............................................................................................................... 241 DOCUMENT HISTORY ............................................................................................................................... 241 PRODUCT STATUS DEFINITIONS ............................................................................................................... 244 ADDRESS INFORMATION ................................................................................................................ 245 TI WORLDWIDE TECHNICAL SUPPORT ..................................................................................... 245 SWRS033H Page 3 of 246 CC1110Fx / CC1111Fx Abbreviation Delta-Sigma LFSR Linear Feedback Shift Register Analog to Digital Converter LNA Low-Noise Amplifier AES Advanced Encryption Standard LO Local Oscillator AGC Automatic Gain Control LQI Link Quality Indication ARIB Association of Radio Industries and Businesses LSB Least Significant Bit / Byte MAC Medium Access Control ASK Amplitude Shift Keying MCU Microcontroller Unit BCD Binary Coded Decimal MISO Master In Slave Out BER Bit Error Rate MOSI Master Out Slave In BOD Brown Out Detector MSB Most Significant Bit / Byte CBC Cipher Block Chaining NA Not Applicable CBC-MAC Cipher Block Chaining Message Authentication Code OFB Output Feedback (encryption) OOK On-Off Keying PA Power Amplifier PCB Printed Circuit Board PER Packet Error Rate PLL Phase Locked Loop PM{0 - 3} Power Mode 0 -3 PMC Power Management Controller POR Power On Reset PQI Preamble Quality Indicator PWM Pulse Width Modulator QLP Quad Leadless Package RAM Random Access Memory RCOSC RC Oscillator RF Radio Frequency RoHS Restriction on Hazardous Substances RSSI Receive Signal Strength Indicator RX Receive SCK Serial Clock SFD Start of Frame Delimiter Federal Communications Commission SFR Special Function Register FIFO First In First Out SINAD Signal-to-noise and distortion ratio GPIO General Purpose Input / Output SPI Serial Peripheral Interface HSSD High Speed Serial Debug SRAM Static Random Access Memory HW Hardware SW Software I/O Input / Output T/R Transmit / Receive I/Q In-phase / Quadrature-phase TX Transmit Inter-IC Sound UART Universal Asynchronous Receiver/Transmitter IF Intermediate Frequency USART IOC I/O Controller Universal Synchronous/Asynchronous Receiver/Transmitter ISM Industrial, Scientific and Medical USB Universal Serial Bus VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier WDT Watchdog Timer XOSC Crystal Oscillator ADC CCA Clear Channel Assessment CCM Counter mode + CBC-MAC CFB Cipher Feedback CFR Code of Federal Regulations CMOS Complementary Metal Oxide Semiconductor CPU CRC Central Processing Unit Cyclic Redundancy Check CTR Counter mode (encryption) DAC Digital to Analog Converter DMA Direct Memory Access DSM Delta-Sigma Modulator ECB Electronic Code Book EM Evaluation Module ENOB Effective Number of Bits EP{0 - 5} USB Endpoints 0 - 5 ESD ESR ETSI FCC 2 IS Electro Static Discharge Equivalent Series Resistance European Telecommunications Standard Institute ISR Interrupt Service Routine IV Initialization Vector JEDEC Joint Electron Device Engineering Council KB Kilo Bytes (1024 bytes) kbps kilo bits per second SWRS033H Page 4 of 246 CC1110Fx / CC1111Fx 1 Register Conventions Each SFR is described in a separate table. The table heading is given in the following format: REGISTER NAME (SFR Address) - Register Description. Each RF register is described in a separate table. The table heading is given in the following format: XDATA Address: REGISTER NAME - Register Description All register descriptions include a symbol denoted R/W describing the accessibility of each bit in the register. The register values are always given in binary notation unless prefixed by ‘0x’, which indicates hexadecimal notation. Symbol Access Mode R/W Read/write R Read only R0 Read as 0 R1 Read as 1 W Write only W0 Write as 0 W1 Write as 1 H0 Hardware clear H1 Hardware set Table 1: Register Bit Conventions 2 Key Features (in more details) 2.1 High-Performance and Low-Power 8051-Compatible Microcontroller 2.3 5 bi-directional endpoints in addition to control endpoint 0 Optimized 8051 core which typically gives 8x the performance of a standard 8051 Full-Speed, 12 Mbps transfer rate Two data pointers Support for Bulk, Interrupt, Isochronous endpoints In-circuit interactive debugging is supported by the IAR Embedded Workbench through a simple two-wire serial interface 1024 bytes of dedicated endpoint FIFO memory and 8 - 512 byte data packet size supported SW compatible with CC2510Fx/CC2511Fx 2.2 Full-Speed USB Controller (CC1111Fx ) Configurable FIFO size for IN and OUT direction of endpoint 8/16/32 KB Non-volatile Program Memory and 1/2/4 kB Data Memory 2.4 2 I S Interface 2 8, 16, or 32 KB of non-volatile flash memory, in-system programmable through a simple two-wire interface or by the 8051 core Industry standard I S interface transfer of digital audio data Minimum flash memory 1000 write/erase cycles Mono and stereo support endurance: Programmable read and write lock of portions of flash memory for software security for Full duplex Configurable sample rate and sample size Support for expansion -law compression and 1, 2, or 4 kB of internal SRAM SWRS033H Page 5 of 246 CC1110Fx / CC1111Fx The high speed crystal oscillator must be used when the radio is active. Typically used to connect to external DAC or ADC 2.5 Clock source for ultra-low power operation can be either a low-power RC oscillator or an optional 32.768 kHz crystal oscillator Hardware AES Encryption/Decryption 128-bit AES supported in hardware coprocessor 2.6 Very fast transition to active mode from power modes enables ultra low average power consumption in low duty-cycle systems Peripheral Features Powerful DMA Controller Power On Reset/Brown-Out Detection ADC with eight individual input channels, single-ended or differential (CC1111Fx has six channels) and configurable resolution 2.8 Programmable watchdog timer Five timers: one general 16-bit timer with DSM mode, two general 8-bit timers, one MAC timer, and one sleep timer Two programmable USARTs for master/slave SPI or UART operation 21 configurable general-purpose digital I/O-pins (CC1111Fx has 19) Random number generator Sub-1 GHz Radio with Baseband Modem Based on the industry leading CC1101 radio core Few external components: On-chip frequency synthesizer, no external filters or RF switch needed Flexible support for packet oriented systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling Supports use of DMA for both RX and TX resulting in minimal CPU intervention even on high data rates Programmable channel filter bandwidth 2.7 Low Power Four flexible power modes for reduced power consumption System can wake up on external interrupt or when the Sleep Timer expires 0.5 µA current consumption in PM2, where external interrupts or the Sleep Timer can wake up the system 0.3 µA current consumption in PM3, where external interrupts can wake up the system Low-power fully static CMOS design System clock source is either a high speed crystal oscillator (26 - 27 MHz for CC1110Fx and 48 MHz for CC1111Fx) or a high speed RC oscillator (13 - 13.5 MHz for CC1110Fx and 12 MHz for CC1111Fx). SWRS033H 2-FSK, GFSK, MSK, ASK, and OOK modulation formats supported Optional automatic whitening and dewhitening of data Programmable indicator Carrier Sense (CS) Programmable Preamble Quality Indicator (PQI) for detecting preambles and improved protection against sync word detection in random noise Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) Support for per-package Link Quality Indication (LQI) Page 6 of 246 CC1110Fx / CC1111Fx 3 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Min Max Units Supply voltage (VDD) −0.3 3.9 V Voltage on any digital pin −0.3 VDD + 0.3, max 3.9 V Voltage on the pins RF_P, RF_N and DCOUPL −0.3 2.0 V Voltage ramp-up rate 120 kV/µs Input RF level 10 dBm 150 C Device not programmed Solder reflow temperature 260 C According to IPC/JEDEC J-STD-020D ESD CC1110Fx 1000 V According to JEDEC STD 22, method A114, Human Body Model (HBM) ESD CC1110Fx 750 V According to JEDEC STD 22, C101C, Charged Device Model (CDM) ESD CC1111x 750 V According to JEDEC STD 22, method A114, Human Body Model (HBM) ESD CC1111x 750 V According to JEDEC STD 22, C101C, Charged Device Model (CDM) Storage temperature range −50 Condition All supply pins must have the same voltage Table 2: Absolute Maximum Ratings Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. SWRS033H Page 7 of 246 CC1110Fx / CC1111Fx 4 Operating Conditions 4.1 CC1110Fx Operating Conditions The operating conditions for CC1110Fx are listed in Table 3 below. Parameter Min Max Unit Operating ambient temperature, TA −40 85 C Operating supply voltage (VDD) 2.0 3.6 V Condition All supply pins must have the same voltage Table 3: Operating Conditions for CC1110Fx 4.2 CC1111Fx Operating Conditions The operating conditions for CC1111Fx are listed in Table 4 below. Parameter Min Max Unit 0 85 C 3.0 3.6 V Operating ambient temperature, TA Operating supply voltage (VDD) Condition All supply pins must have the same voltage Table 4: Operating Conditions for CC1111Fx 5 General Characteristics TA = 25 C, VDD = 3.0 V if nothing else stated Parameter Min Typ Max Unit 300 348 MHz 391 464 MHz 782 928 MHz 1.2 500 kBaud 1.2 250 kBaud 26 500 kBaud Condition/Note Radio part Frequency range Data rate 2-FSK (500 kBaud only characterized @ 915 MHz on CC1110Fx) GFSK, OOK, and ASK (Shaped) MSK (also known as differential offset QPSK) 500 kBaud only characterized @ 915 MHz Optional Manchester encoding (the data rate in kbps will be half the baud rate) Wake-Up Timing PM1  Active Mode 4 µs Digital regulator on. HS RCOSC and high speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running. SLEEP.OSC_PD=1 and CLKCON.OSC=1 PM2/3 Active Mode 100 µs Digital regulator off. HS RCOSC and high speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running (PM2). No crystal oscillators or RC oscillators are running in PM3 SLEEP.OSC_PD=1 and CLKCON.OSC=1 Table 5: General Characteristics SWRS033H Page 8 of 246 CC1110Fx / CC1111Fx 6 Electrical Specifications 6.1 Current Consumption TA = 25 C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference design ([1]). Parameter Active mode, full speed (high speed crystal oscillator)1. Min Typ Max Unit Condition 5.0 mA System clock running at 26 MHz. 4.8 mA System clock running at 24 MHz. Digital regulator on. High speed crystal oscillator and low power RCOSC running. No peripherals running. Low CPU activity. Low CPU activity: No flash access (i.e. only cache hit), no RAM access Active mode, full speed (HS RCOSC)1. 2.5 mA System clock running at 13 MHz. Digital regulator on. HS RCOSC and low power RCOSC running. No peripherals running. Low CPU activity. Low CPU activity: No flash access (i.e. only cache hit), no RAM access Active mode with radio in RX, 315 MHz Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=0) 19 mA 1.2 kBaud, input at sensitivity limit, system clock running at 26 MHz. 19.5 mA 1.2 kBaud, input at sensitivity limit, system clock running at 24 MHz 16.2 mA 1.2 kBaud, input at sensitivity limit, system clock running at 203 kHz. 19 mA 1.2 kBaud, input well above sensitivity limit, system clock running at 26 MHz 19.4 mA 1.2 kBaud, input well above sensitivity limit, system clock running at 24 MHz 19 mA 38.4 kBaud, input at sensitivity limit, system clock running at 26 MHz. 16.2 mA 38.4 kBaud, input at sensitivity limit, system clock running at 203 kHz. 19 mA 38.4 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 20 mA 250 kBaud, input at sensitivity limit, system clock running at 26 MHz 21 mA 250 kBaud, input at sensitivity limit, system clock running at 24 MHz. 17.2 mA 250 kBaud, input at sensitivity limit, system clock running at 1.625 MHz. 20 mA 20 mA 250 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 250 kBaud, input well above sensitivity limit, system clock running at 24 MHz. 1 Note: In order to reduce the current consumption in active mode, the clock speed can be reduced by setting CLKCON.CLKSPD≠000 (see section 12.1 for details).Figure 1 shows typical current consumption in active mode for different clock speeds SWRS033H Page 9 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=0) Active mode with radio in RX, 433 MHz 19.8 mA 1.2 kBaud, input at sensitivity limit, system clock running at 26 MHz. 19.7 mA 1.2 kBaud, input at sensitivity limit, system clock running at 24 MHz. 17.1 mA 1.2 kBaud, input at sensitivity limit, system clock running at 203 kHz. 19.8 mA 1.2 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 19.7 mA 1.2 kBaud, input well above sensitivity limit, system clock running at 24 MHz. 19.8 mA 38.4 kBaud, input at sensitivity limit, system clock running at 26 MHz. 17.1 mA 38.4 kBaud, input at sensitivity limit, system clock running at 203 kHz 19.8 mA 38.4 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 20.5 mA 250 kBaud, input at sensitivity limit, system clock running at 26 MHz. 21.5 mA 250 kBaud, input at sensitivity limit, system clock running at 24 MHz. 18.1 mA 250 kBaud, input at sensitivity limit, system clock running at 1.625 MHz. 20.5 mA 250 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 20.2 mA 250 kBaud, input well above sensitivity limit, system clock running at 24 MHz See Figure 2 for typical variation over operating conditions Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=0). 24 MHz system clock not measured Active mode with radio in RX, 868, 915 MHz 19.7 mA 1.2 kBaud, input at sensitivity limit, system clock running at 26 MHz. 17.0 mA 1.2 kBaud, input at sensitivity limit, system clock running at 203 kHz. 18.7 mA 1.2 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 19.7 mA 38.4 kBaud, input at sensitivity limit, system clock running at 26 MHz. 17.0 mA 38.4 kBaud, input at sensitivity limit, system clock running at 203 kHz. 18.7 mA 38.4 kBaud, input well above sensitivity limit, system clock running at 26 MHz. 20.4 mA 250 kBaud, input at sensitivity limit, system clock running at 26 MHz. 18.0 mA 250 kBaud, input at sensitivity limit, system clock running at 1.625 MHz. 19.1 mA 250 kBaud, input well above sensitivity limit, system clock running at 26 MHz. System clock running at 26 MHz or 24 MHz. Active mode with radio in TX, 315 MHz Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode 31.5 mA 10 dBm output power (PA_TABLE0=0xC2) 19 mA 0 dBm output power (PA_TABLE0=0x51) 18 mA −6 dBm output power (PA_TABLE0=0x2A) SWRS033H Page 10 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition System clock running at 26 MHz or 24 MHz. Active mode with radio in TX, 433 MHz Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode 33.5 mA 10 dBm output power (PA_TABLE0=0xC0) 20 mA 0 dBm output power (PA_TABLE0=0x60) 19 mA −6 dBm output power (PA_TABLE0=0x2A) System clock running at 26 MHz or 24 MHz. Active mode with radio in TX, 868, 915 MHz Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode 36.2 mA 10 dBm output power (PA_TABLE0=0xC2). See Table 7 for typical variation over operating conditions 21 mA 0 dBm output power (PA_TABLE0=0x50) 20 mA −6 dBm output power (PA_TABLE0=0x2B) Power mode 0 4.3 mA Same as active mode, but the CPU is not running (see 12.1.2.2 for details). System clock at 26 MHz or 24 MHz Power mode 1 220 A Digital regulator on. HS RCOSC and high speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running (see 12.1.2.3 for details) Power mode 2 0.5 µA Digital regulator off. HS RCOSC and high speed crystal oscillator off. Low power RCOSC running (see 12.1.2.4 for details) Power mode 3 0.3 µA Digital regulator off. No crystal oscillators or RC oscillators are running (see 12.1.2.5 for details) 1.0 Peripheral Current Consumption Add to the figures above if the peripheral unit is activated Timer 1 2.7 A/MHz When running Timer 2 1.3 A/MHz When running Timer 3 1.6 A/MHz When running Timer 4 2 A/MHz When running 1.2 mA ADC During conversion Table 6: Current Consumption SWRS033H Page 11 of 246 CC1110Fx / CC1111Fx Current Consumption Active Mode. No Peripherals Running. fxosc = 26 MHz 6,0 5,0 Current [mA] 4,0 HS XOSC 3,0 HS RCOSC 2,0 1,0 0,0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 Clock Speed [MHz] Measurements done for all valid CLKCON.CLKSPD settings (000 - 111 for HS XOSC, 001 - 111 for HS RCOSC) Figure 1: Current Consumption (Active Mode) vs. Clock Speed Typical Variation in RX Current Consumption over Temperature and Input Power Level Data Rate = 250 kBaud, Frequency Band = 433 MHz Current [mA] 25 Avg −40°C 23 Avg 25°C Avg 85°C 21 19 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Input Power Level [dBm] Figure 2: Typical Variation in RX Current Consumption over Temperature and Input Power Level. Data Rate = 250 kBaud, Frequency Band = 433 MHz Supply Voltage, VDD = 2 V Supply Voltage, VDD = 3 V Supply Voltage, VDD = 3.6 V Temperature [°C] −40 25 85 −40 25 85 −40 25 85 Current [mA] 37 36 35.4 37.2 36.2 35.6 37.5 36.4 35.8 Table 7: Typical Variation in TX Current Consumption over Temperature and Supply Voltage, @ 868 MHz and 10 dBm Output Power. SWRS033H Page 12 of 246 CC1110Fx / CC1111Fx 6.2 RF Receive Section TA = 25 C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference design ([1]) if nothing else is stated. Parameter Min Digital channel filter bandwidth 58 Typ Max Unit Condition/Note 812 kHz User programmable (see Section 13.6). The bandwidth limits are proportional to crystal frequency (given values assume a 26 MHz system clock). 315 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity −110 dBm System clock running at 26 MHz −112 dBm System clock running at 24 MHz The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −107 dBm. 315 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity −102 dBm System clock running at 26 MHz −103 dBm System clock running at 24 MHz The RX current consumption can be reduced by approximately 2.1 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −99 dBm. 315 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity −94 dBm System clock running at 26 MHz −94 dBm System clock running at 24 MHz 433 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity −110 dBm System clock running at 26 MHz −110 dBm System clock running at 24 MHz The RX current consumption can be reduced by approximately 2.6 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −107 dBm. 433 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity −102 dBm System clock running at 26 MHz −101 dBm System clock running at 24 MHz The RX current consumption can be reduced by approximately 2.7 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −99 dBm. Parameter Min Typ Max Unit Condition/Note 433 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity −95 dBm System clock running at 26 MHz −93 dBm System clock running at 24 MHz See Table 9 for typical variation over operating conditions SWRS033H Page 13 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition/Note 868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity −110 dBm System clock running at 26 MHz −110 dBm Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −107 dBm. Saturation −14 dBm MCSM0.CLOSE_IN_RX=00 Adjacent channel rejection 38 dB Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing Alternate channel rejection 35 dB Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing See Figure 58 for plot of selectivity versus frequency offset Image channel rejection, 868 MHz 33 dB IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit. 868 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity −102 dBm System clock running at 26 MHz −101 dBm Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock The RX current consumption can be reduced by approximately 2.2 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −100 dBm. Saturation −14 dBm Adjacent channel rejection 19 dB Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing Alternate channel rejection 32 dB Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing MCSM0.CLOSE_IN_RX=00 See Figure 59 for plot of selectivity versus frequency offset Image channel rejection, 868 MHz 28 dB IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit. SWRS033H Page 14 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition/Note 868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity −94 dBm System clock running at 26 MHz −91 dBm Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock MCSM0.CLOSE_IN_RX=00 Saturation −16 dBm Adjacent channel rejection 27 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing Alternate channel rejection 36 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing Image channel rejection, 868 MHz 17 dB See Figure 60 for plot of selectivity versus frequency offset IF frequency 304 kHz Desired channel 3 dB above the sensitivity limit. 915 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 5.2 kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth) Receiver sensitivity −108 dBm System clock running at 26 MHz −110 dBm Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −107 dBm. 915 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 100 kHz digital channel filter bandwidth) Receiver sensitivity −100 dBm System clock running at 26 MHz −100 dBm Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock The RX current consumption can be reduced by approximately 2.1 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then −99 dBm. 915 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –93 dBm System clock running at 26 MHz –91 dBm Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock 915 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –86 dBm System clock running at 26 MHz. Not tested on [4] CC1111 USB-Dongle Reference Design, 24 MHz clock SWRS033H Page 15 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition/Note Blocking Blocking at ±2 MHz offset, 1.2 kBaud, 868 MHz −45 dBm Desired channel 3 dB above the sensitivity limit. Blocking at ±2 MHz offset, 250 kBaud, 868 MHz −50 dBm Desired channel 3 dB above the sensitivity limit Blocking at ±10 MHz offset, 1.2 kBaud, 868 MHz −33 dBm Desired channel 3 dB above the sensitivity limit. Blocking at ±10 MHz offset, 250 kBaud, 868 MHz −40 dBm Desired channel 3 dB above the sensitivity limit. General Spurious emissions Conducted measurement in a 50 single ended load. Complies with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66. Numbers are from CC1101 (same radio on CC1110 and CC1111) Typical radiated spurious emission is −49 dB measured at the VCO frequency. 25 MHz 1 GHz −68 −57 dBm Maximum figure is the ETSI EN 300 220 limit Above 1 GHz −66 −47 dBm Maximum figure is the ETSI EN 300 220 limit Table 8: RF Receive Section Supply Voltage, VDD = 2 V Supply Voltage, VDD = 3 V Supply Voltage, VDD = 3.6 V Temperature [°C] −40 25 85 −40 25 85 −40 25 85 Sensitivity [dBm] −96.4 −94.9 −92.6 −96.1 −95.0 −92.2 −96.1 −94.5 −92.2 Table 9: Typical Variation in Sensitivity over Temperature and Supply Voltage @ 433 MHz and 250 kBaud Data Rate SWRS033H Page 16 of 246 CC1110Fx / CC1111Fx 6.3 RF Transmit Section TA = 25 C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference designs ([1]) if nothing else is stated. Parameter Min Typ Max Unit Differential load impedance 315 MHz Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1110EM reference designs ([1], [2] and [3]) available from the TI website. 122 + j31 433 MHz 116 + j41 868/915 MHz 86.5 + j43 Output power, highest setting 10 Condition/Note dBm Output power is programmable, and full range is available in all frequency bands Output power may be restricted by regulatory limits. See AN050 [13]. Note that this application note is for CC1101 but the same limitations apply to CC1110Fx and CC1111Fx as well. For CC1111Fx see in addition DN016 [14] for information on antenna solution and additional regulatory restrictions See Figure 3 for typical variation over operating conditions Delivered to 50 single-ended load via CC1110EM reference design [3] RF matching network. Output power, lowest setting −30 dBm Output power is programmable and is available across the entire frequency band Delivered to 50 single-ended load via CC1110EM reference design [3] RF matching network. Harmonics, radiated nd 2 Harm, 433 MHz 3rd Harm, 433 MHz nd 2 Harm, 868 MHz 3rd Harm, 868 MHz −51 −42 dBm dBm −37 −43 dBm dBm Harmonics, radiated nd 2 Harm, 868 MHz 3rd Harm, 868 MHz −55 dBm −55 dBm Harmonics, conducted Measured on CC1110EM reference designs ([2] and [3]) with CW, 10 dBm output power The antennas used during the radiated measurements (SMAFF-433 from R.W. Badland and Nearson S331 868/915) play a part in attenuating the harmonics Measured on [4] CC1111 USB-Dongle Reference Design, with CW, 10 dBm output power. The chip antenna used during the radiated measurements play a part in attenuating the harmonics Measured on CC1110EM reference designs ([1], [2] and [3]) with CW, 10 dBm output power, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz, or 915.00 MHz 315 MHz < −35 < −52 dBm Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz < −44 < −35 dBm Frequencies below 1 GHz Frequencies above 1 GHz 868 MHz < −35 dBm Frequencies above 1 GHz 915 MHz < −34 dBm Frequencies above 1 GHz SWRS033H Page 17 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Spurious emissions radiated, Harmonics not included Condition/Note Measured on CC1110EM reference designs ([1], [2] and [3]) with 10 dBm CW, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 or 915.00 MH. For CC1111Fx see DN016 [14] Please refer to register TEST1 on Page 226 for required settings in RX and TX 315 MHz < −58 < −53 dBm Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz < −50 < −54 < −56 dBm Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47 - 74, 87.5 - 118, 174 - 230, 470 - 862 MHz 868 MHz < −56 < −54 < −56 dBm Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47 - 74, 87.5 - 118, 174 - 230, 470 - 862 MHz. 915 MHz < −51 < −60 dBm Frequencies below 960 MHz Frequencies above 960 MHz Table 10: RF Transmit Section Typical Variation in Output Power (10dBm) over Frequency and Temperature Output Power [dBm] 12 11 10 Avg −40°C 9 Avg 25°C 8 Avg 85°C 7 6 750 800 850 900 950 Frequency [MHz] Figure 3: Typical Variation in Output Power over Frequency and Temperature (10 dBm output power) SWRS033H Page 18 of 246 CC1110Fx / CC1111Fx 6.4 6.4.1 Crystal Oscillators CC1110Fx Crystal Oscillator TA = 25 C, VDD = 3.0 V if nothing else is stated. Parameter Min Typ Max Unit Condition/Note Crystal frequency 26 26 27 MHz Referred to as fXOSC. ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. Crystal frequency accuracy requirement ±40 The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. C0 1 5 Load capacitance 10 13 ESR 7 pF Simulated over operating conditions 20 pF Simulated over operating conditions 100 Start-up time Simulated over operating conditions μs 250 fXOSC = 26 MHz Note: A Ripple counter of 12 bit is included to ensure duty-cycle requirements. Start-up time includes ripple counter delay until SLEEP.XOSC_STB is asserted Power Down Guard Time 3 ms The crystal oscillator must be in power down for a guard time before it is used again. This requirement is valid for all modes of operation. The need for power down guard time can vary with crystal type and load. Minimum figure is valid for reference crystal NDK, AT-41CD2 and load capacitance according to Table 29. If power down guard time is violated, one of the consequences can be increased PER when using the radio immediately after the crystal oscillator has been reported stable. Table 11: CC1110Fx Crystal Oscillator Parameters 6.4.2 CC1111Fx Crystal Oscillator TA = 25 C, VDD = 3.0 V if nothing else is stated. Parameter Min Crystal frequency Typ Max 48 Unit Condition/Note MHz Referred to as fXOSC. 48 MHz crystal gives a system clock of 24 MHz. Please note that there is restricted usage in the frequency bands 863 870 MHz (due to spurious emission). See DN016 Compact Antenna Solutions for 868/915 MHz [14] Crystal frequency accuracy requirement ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. C0 Fundamental Load capacitance 0.85 1 1.15 pF Simulated over operating conditions. Variation given by reference crystal NX2520SA from NDK (fundamental). 15 16 17 pF Simulated over operating conditions ESR 60 Simulated over operating conditions Start-up time Fundamental Note: A Ripple counter of 14 bit is included to ensure duty-cycle requirements. Start-up time includes ripple counter delay until SLEEP.XOSC_STB is asserted 650 μs Table 12: CC1111Fx Crystal Oscillator Parameters SWRS033H Page 19 of 246 CC1110Fx / CC1111Fx 6.5 32.768 kHz Crystal Oscillator TA = 25 C, VDD = 3.0V if nothing else is stated. Parameter Min Crystal frequency Typ Max 32.768 Unit Condition/Note kHz C0 0.9 2.0 pF Simulated over operating conditions Load capacitance 12 16 pF Simulated over operating conditions ESR 40 130 k Simulated over operating conditions Start-up time 400 ms Value is simulated Table 13: 32.768 kHz Crystal Oscillator Parameters 6.6 Low Power RC Oscillator TA = 25 C, VDD = 3.0 V if nothing else is stated. Parameter 2 Calibrated frequency Min Typ Max Unit Condition/Note 34.7 34.7 36.0 kHz CC1110Fx 32.0 32.0 32.0 CC1111Fx Calibrated low power RC oscillator frequency is fRef / 750 Frequency accuracy after calibration Temperature coefficient ±1 % +0.5 %/ C Frequency drift when temperature changes after calibration Supply voltage coefficient +3 %/V Frequency drift when supply voltage changes after calibration Initial calibration time 2 ms When the low power RC oscillator is enabled, calibration is continuously done in the background as long as the high speed crystal oscillator is running. Table 14: Low Power RC Oscillator Parameters fRef = fXOSC for CC1110Fx and fRef = fXOSC /2 for CC1111Fx For CC1110Fx Min figures are given using fXOSC = 26 MHz. Typ figures are given using fXOSC = 26 MHz, and Max figures are given using fXOSC = 27 MHz. For CC1111Fx, fXOSC = 48 MHz 2 SWRS033H Page 20 of 246 CC1110Fx / CC1111Fx 6.7 High Speed RC Oscillator TA = 25 C, VDD = 3.0 V if nothing else is stated. Parameter 2 Calibrated frequency Min Typ Max Unit Condition/Note 12 13 13.5 MHz Calibrated HS RCOSC frequency is fXOSC / 2 Uncalibrated frequency accuracy % 15 Calibrated frequency accuracy Start-up time Temperature coefficient Supply voltage coefficient Calibration time 1 % 10 µs −325 ppm/ C Frequency drift when temperature changes after calibration 28 ppm/V Frequency drift when supply voltage changes after calibration 65 µs The HS RCOSC will be calibrated once when the high speed crystal oscillator is selected as system clock source (CLKCON.OSC is set to 0), and also when the system wakes up from PM{1 - 3} if CLKCON.OSC was set to 0 when entering PM{1 - 3}. See 12.1.5.1 for details). Table 15: High Speed RC Oscillator Parameters 6.8 Frequency Synthesizer Characteristics TA = 25 C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference designs ([1]). Parameter Min Typ Max Unit Programmed frequency resolution3 397 397 412 Hz 366 366 366 Condition/Note CC1110Fx CC1111Fx Frequency resolution = fRef/ 216 Synthesizer frequency tolerance ±40 ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. RF carrier phase noise −92 dBc/Hz @ 50 kHz offset from carrier RF carrier phase noise −93 dBc/Hz @ 100 kHz offset from carrier RF carrier phase noise −93 dBc/Hz @ 200 kHz offset from carrier RF carrier phase noise −98 dBc/Hz @ 500 kHz offset from carrier RF carrier phase noise −107 dBc/Hz @ 1 MHz offset from carrier RF carrier phase noise −113 dBc/Hz @ 2 MHz offset from carrier RF carrier phase noise −119 dBc/Hz @ 5 MHz offset from carrier RF carrier phase noise −129 dBc/Hz @ 10 MHz offset from carrier fRef = fXOSC for CC1110Fx and fRef = fXOSC /2 for CC1111Fx For CC1110Fx Min figures are given using fXOSC = 26 MHz. Typ figures are given using fXOSC = 26 MHz, and Max figures are given using fXOSC = 27 MHz. For CC1111Fx, fXOSC = 48 MHz 3 SWRS033H Page 21 of 246 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit PLL turn-on / hop time4 72.4 75.2 75.2 s 81.4 81.4 81.4 Condition/Note CC1110Fx CC1111Fx Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration. Crystal oscillator running. RX to TX switch 4 29.0 30.1 30.1 32.6 32.6 32.6 CC1110Fx s CC1111Fx Settling time for the 1∙IF frequency step from RX to TX TX to RX switch 4 30.0 31.1 31.1 33.6 33.6 33.6 CC1110Fx s CC1111Fx Settling time for the 1∙IF frequency step from TX to RX PLL calibration time 4 707 735 735 796 796 796 CC1110Fx s CC1111Fx Calibration can be initiated manually or automatically before entering or after leaving RX/TX. Note: This is the PLL calibration time given that TEST0=0x0B and FSCAL3.CHP_CURR_CAL_EN=10 (max calibration time). Please see DN110 [15] for more details Table 16: Frequency Synthesizer Parameters 6.9 Analog Temperature Sensor TA= 25 C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1110EM reference designs ([1]). Parameter Min Typ Max Unit Output voltage at −0 C 0.660 V Output voltage at 0 C 0.755 V Output voltage at 40 C 0.859 V Output voltage at 80 C 0.958 V Temperature coefficient Error in calculated temperature, calibrated 2.47 −2 * 0 mV/ C 2 * C Condition/Note Fitted from −20 C to 80 C From –20 C to 80 C when using 2.47 mV/ C, after 1-point calibration at room temperature * The indicated minimum and maximum error with 1-point calibration is based on measured values for typical process parameters Current consumption increase when enabled 0.3 mA Table 17: Analog Temperature Sensor Parameters fRef = fXOSC for CC1110Fx and fRef = fXOSC /2 for CC1111Fx For CC1110Fx Min figures are given using fXOSC = 27 MHz. Typ figures are given using fXOSC = 26 MHz, and Max figures are given using fXOSC = 26 MHz. For CC1111Fx, fXOSC = 48 MHz The system clock frequency is equal to fRef and the data rate is 250 kBaud. No PA ramping is used. See DN110 [15] for more details. 4 SWRS033H Page 22 of 246 CC1110Fx / CC1111Fx 6.10 7 - 12 bit ADC TA = 25 C, VDD = 3.0 V if nothing else stated. The numbers given here are based on tests performed in accordance with IEEE Std 1241-2000 [8]. The ADC data are from CC2430 characterization. As the CC1110Fx/C1111Fx uses the same ADC, the numbers listed in Table 18 should be good indicators of the performance to be expected from CC1110Fx and CC1111Fx. Note that these numbers will apply for 24 MHz operated systems (CC1111Fx using a 48 MHz crystal). Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz). Parameter Min Typ Max Unit Condition/Note Input voltage 0 VDD V VDD is the voltage on the AVDD pin (2.0 - 3.6 V) External reference voltage 0 VDD V VDD is the voltage on the AVDD pin (2.0 - 3.6 V) External reference voltage differential 0 VDD V VDD is the voltage on the AVDD pin (2.0 - 3.6 V) Input resistance, signal 197 k Simulated using 4 MHz clock speed (see Section 12.10.2.7) Full-Scale Signal5 2.97 V Peak-to-peak, defines 0 dBFS 5.7 bits ENOB 5 Single ended input ENOB 5 7.5 9-bits setting 9.3 10-bits setting 10.8 12-bits setting 6.5 Differential input Useful Power Bandwidth 7-bits setting bits 7-bits setting 8.3 9-bits setting 10.0 10-bits setting 11.5 12-bits setting 0 - 20 kHz 7-bits setting, both single and differential -Single ended input −75.2 dB 12-bits setting, −6 dBFS -Differential input −86.6 5 THD Signal To Non-Harmonic Ratio -Single ended input 70.2 -Differential input Spurious Free Dynamic Range -Single ended input 12-bits setting, −6 dBFS 5 dB 79.3 12-bits setting 5 78.8 dB 12-bits setting, -6 dBFS -Differential input 88.9 CMRR, differential input 8; // Set EVENT0, high byte WOREVT0 = desired event0; // Set EVENT0, low byte // Alignment of both updating EVENT0 // on the 32 kHz clock source char temp = WORTIME0; while(temp == WORTIME0); WOREVT1 = desired event0 >> 8; WOREVT0 = desired event0; PCON |= 0x01; and entering PM{0 - 2}to a positive edge // // // // Wait until a positive 32 kHz edge Set EVENT0, high byte Set EVENT0, low byte Enter PM{0 – 2} If EVENT0 is changed to a value lower than the current counter value, WORCTRL.WOR_RESET has to be asserted first to reset the timer. The assertion of WORCTRL.WOR_RESET must be // Reset timer and enter PM{0 – 2} WORCTRL |= 0x04; char temp = WORTIME0; while(temp == WORTIME0); temp = WORTIME0; while(temp == WORTIME0); PCON |= 0x01; // Reset timer and update EVENT0 WORCTRL |= 0x04; char temp = WORTIME0; while(temp == WORTIME0); temp = WORTIME0; while(temp == WORTIME0); WOREVT1 = desired event0 >> 8; WOREVT0 = desired event0; followed by two positive edges on the 32 kHz clock source. The code below shows how to reset the Sleep Timer in combination with updating EVENT0 and/or entering PM{0 - 2}. // Reset Sleep Timer // Wait until a positive 32 kHz edge // Wait until a positive 32 kHz edge // Enter PM{0 – 2} // Reset Sleep Timer // Wait until a positive 32 kHz edge // Wait until a positive 32 kHz edge // Set EVENT0, high byte // Set EVENT0, low byte // Reset timer, update EVENT0, and enter PM{0 – 2} WORCTRL |= 0x04; // Reset Sleep Timer char temp = WORTIME0; while(temp == WORTIME0); // Wait until a positive 32 kHz edge temp = WORTIME0; while(temp == WORTIME0); // Wait until a positive 32 kHz edge WOREVT1 = desired event0 >> 8; // Set EVENT0, high byte WOREVT0 = desired event0; // Set EVENT0, low byte PCON |= 0x01; // Enter PM{0 – 2} 12.8.3 Low Power RC Oscillator and Timing This section applies to using the low power RC oscillator as clock source for the Sleep Timer. The frequency of the low-power RC oscillator, which can be used as clock source for the Sleep Timer, varies with temperature and supply voltage. In order to keep the frequency as accurate as possible, the RC oscillator will be calibrated whenever possible, which is when the high speed crystal oscillator is running and the chip is in active mode or PM0. When the chip goes to PM1 or PM2, the RC oscillator will use the last valid calibration result. The frequency of the low power RC oscillator is therefore locked to fref / 750. 12.8.4 Sleep Timer Interrupt When Event 0 occurs, the WORIRQ.EVENT0_FLAG bit will be asserted. If the corresponding mask bit, EVENT0_MASK, is set in the WORIRQ register, the CPU interrupt flag IRCON.STIF will also be asserted in addition to the interrupt flag in WORIRQ. If IEN0.STIE=1 when IRCON.STIF is asserted, and ST interrupt request will be generated. SWRS033H Page 127 of 246 CC1110Fx / CC1111Fx 12.8.6 Note: All port interrupts are blocked when SLEEP.MODE≠00 12.8.5 Sleep Timer Registers This section describes the SFRs associated with the Sleep Timer. Sleep Timer DMA Trigger There is one DMA trigger associated with the Sleep Timer. This is the DMA trigger ST, which is generated when Event 0 occurs. WORTIME0 (0xA5) - Sleep Timer Low Byte Bit Field Name Reset R/W Description 7:0 WORTIME[7:0] 0x00 R 8 LSB of the16 bits selected from the 31-bit Sleep Timer according to the setting of WORCTRL.WOR_RES[1:0] WORTIME1 (0xA6) - Sleep Timer High Byte Bit Field Name Reset R/W Description 7:0 WORTIME[15:8] 0x00 R 8 MSB of the16 bits selected from the 31-bit Sleep Timer according to the setting of WORCTRL.WOR_RES[1:0] WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High Bit Field Name Reset R/W Description 7:0 EVENT0[15:8] 0x87 R/W High byte of Event 0 timeout register Sleep Timer clocked by low power RCOSC t Event0 750 EVENT 0 25 WOR _ RES f ref Sleep Timer clocked by 32.768 kHz crystal oscillator t Event0 1 EVENT 0 2 5 WOR _ RES 32768 WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low Bit Field Name Reset R/W Description 7:0 EVENT0[7:0] 0x6B R/W Low byte of Event 0 timeout register SWRS033H Page 128 of 246 CC1110Fx / CC1111Fx WORCTRL (0xA2) - Sleep Timer Control Bit Field Name Reset R/W Description 7 - R0 Not used 6:4 111 R/W Reserved. Always write 000 3 - R0 Not used 2 WOR_RESET 0 R0/W1 Reset timer. The timer will be reset to 4. 1:0 WOR_RES[1:0] 00 R/W Sleep Timer resolution Controls the resolution and maximum timeout for the Sleep Timer. Adjusting the resolution does not affect the clock cycle counter: Setting Resolution (1 LSB) Bits selected from the 31-bit Sleep Timer 00 1 period 15:0 5 01 2 periods 20:5 10 210 periods 25:10 15 11 2 periods 30:15 WORIRQ (0xA1) - Sleep Timer Interrupt Control Bit Reset R/W 7:6 00 R0 5 0 R/W Reserved. Always write 0 0 R/W Event 0 interrupt mask 4 Field Name EVENT0_MASK Description 0 Interrupt is disabled 1 Interrupt is enabled 3:2 00 R0 1 0 R/W0 Reserved 0 R/W0 Event 0 interrupt flag 0 EVENT0_FLAG 0 No interrupt is pending 1 Interrupt is pending SWRS033H Page 129 of 246 CC1110Fx / CC1111Fx 12.9 8-bit Timers, Timer 3 and Timer 4 Timer 3 and Timer 4 are two 8-bit timers which supports typical timer/counter functions such as output compare and PWM functions. The timers have two independent compare channels each and use one I/O pin per channel. highest is 24 MHz for CC1111Fx. When the high speed RC oscillator is used as system clock source, the highest clock frequency used by Timer 3/4 is fXOSC/2 for CC1110Fx and 12 MHz for CC1111Fx, given that the HS RCOSC has been calibrated. The features of Timer 3/4 are as follows: The counter operates as either a free-running counter, a modulo counter, a down counter, or as an up/down counter for use in centrealigned PWM. Two compare channels Set, clear, or toggle output compare or It is possible to read the 8-bit counter value through the SFR TxCNT. Clock prescaler for divide by 1, 2, 4, 8, 16, 32, 64, 128 Writing a 1 to TxCTL.CLR will reset the 8-bit counter. Interrupt request generation on compare and when reaching the terminal count value The counter may produce an interrupt request when the terminal count value (overflow) is reached (see Section 12.9.3 - 12.9.3.3). It is possible to start and halt the counter with the TxCTL.START bit. The counter is started when a 1 is written to TxCTL.START. If a 0 is written to TxCTL.START, the counter halts at its present value. Free-running, modulo, down, up/down counter operation DMA trigger function Note: In the following sections, an n in the register name represent the channel number 0 or 1 if nothing else is stated. An x in the register name refers to the timer number, 3 or 4 12.9.1 12.9.2 8-bit Timer Counter Both timers consist of an 8-bit counter that increments or decrements at each active clock edge. The frequency of the active clock edges is given by CLKCON.TICKSPD and TxCTL.DIV. CLKCON.TICKSPD is used to set the timer tick speed. The timer tick speed will vary from 203.125 kHz to 26 MHz for CC1110Fx and 187.5 kHz to 24 MHz for CC1111Fx (given the use of a 26 MHz or 48 MHz crystal respectively). Note that the clock speed of the system clock is not affected by the TICKSPD setting. The timer tick speed is further divided in Timer 3/4 by the prescaler value set by TxCTL.DIV. This prescaler value can be 1, 2, 4, 8, 16, 32, 64, or 128. Thus the lowest clock frequency used by Timer 3/4 is 1.587 kHz and the highest is 26 MHz when a 26 MHz crystal oscillator is used as system clock source (CC1110Fx). The lowest clock frequency used by Timer 3/4 is 1.465 kHz and the Timer 3/4 Operation In general, the control register TxCTL is used to control the timer operation. The timer modes are described in the following four sections. 12.9.3 Free-running Mode In free-running mode the counter starts from 0x00 and increments at each active clock edge. When the counter reaches the terminal count value 0xFF (overflow), the counter is loaded with 0x00 on the next timer tick and continues incrementing its value as shown in Figure 35. When 0xFF is reached, the TIMIF.TxOVFIF flag is set. The IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. The free-running mode can be used to generate independent time intervals and output signal frequencies. SWRS033H Page 130 of 246 CC1110Fx / CC1111Fx 0xFF 0x00 OVFIF = 1 OVFIF = 1 Figure 35: Free-running Mode 12.9.3.1 TIMIF.TxOVFIF flag is set. The IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. Modulo mode can be used for applications where a period other than 0xFF is required. Modulo Mode In modulo mode the counter starts from 0x00 and increments at each active clock edge. When the counter reaches the terminal count value TxCC0 (overflow), the counter is loaded with 0x00 on the next timer tick and continues incrementing its value as shown in Figure 36. When TxCC0 is reached, the TxCC0 0x00 OVFIF = 1 OVFIF = 1 Figure 36: Modulo Mode 12.9.3.2 IRCON.TxIF is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. The timer down mode can generally be used in applications where an event timeout interval is required. Down Mode In down mode, after the timer has been started, the counter is loaded with the contents in TxCC0. The counter then counts down to 0x00 (terminal count value) and remains at 0x00 as shown in Figure 37. The flag TIMIF.TxOVFIF is set when 0x00 is reached. TxCC0 0x00 OVFIF = 1 Figure 37: Down Mode 12.9.3.3 Up/Down Mode In up/down mode the counter starts from 0x00 and increments at each active clock edge. When the counter value matches the terminal count value TxCC0, the counter counts down until 0x00 is reached and it starts counting up again as shown in Figure 38. When 0x00 is reached, the TIMIF.TxOVFIF flag is set. The IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. The up/down mode can be used when symmetrical output pulses are required with a period other than 0xFF, and therefore allows implementation of centrealigned PWM output applications. SWRS033H Page 131 of 246 CC1110Fx / CC1111Fx TxCC0 0x00 OVFIF = 1 OVFIF = 1 Figure 38: Up/Down Mode 12.9.4 Channel Mode Control The channel mode is set with each channel’s control and status register TxCCTLn. Note: before an I/O pin can be used by the timer, the required I/O pin must be configured as a Timer 3/4 peripheral pin as described in section 12.4.6 on Page 91. 12.9.5 may generate an interrupt Counter reaches terminal count value (overflow) or turns around on zero / reach zero Output compare event Output Compare Mode In output compare mode the I/O pin associated with a channel is set as an output. After the timer has been started, the contents of the counter are compared with the contents of the channel compare register TxCCn. If the compare register equals the counter contents, the output pin is set, reset, or toggled according to the compare output mode setting of TxCCTLn.CMP. Note that all edges on output pins are glitch-free when operating in a given compare output mode. Writing to the compare register TxCC0 does not take effect on the output compare value until the counter value is 0x00. Writing to the compare register TxCC1 takes effect immediately. When a compare occurs, the interrupt flag for the appropriate channel (TIMIF.TxCHnIF) is asserted. The IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCCTLn.IM is set to 1. An interrupt request is generated if the corresponding interrupt mask bit is set together with IEN1.TxEN. When operating in up-down mode, the interrupt flag for channel 0 is set when the counter reaches 0x00 instead of when a compare occurs. For simple PWM use, output compare modes 3 and 4 are preferred. 12.9.6 timer events request: The register bits TIMIF.T3OVFIF, TIMIF.T4OVFIF, TIMIF.T3CH0IF, TIMIF.T3CH1IF, TIMIF.T4CH0IF, and TIMIF.T4CH1IF contains the interrupt flags for the two terminal count value event (overflow), and the four channel compare events, respectively. These flags will be asserted regardless off the channel n interrupt mask bit (TxCCTLn.IM). The CPU interrupt flag, IRCON.TxIF will only be asserted if one or more of the channel n interrupt mask bits are set to 1. An interrupt request is only generated when the corresponding interrupt mask bit is set together with IEN1.TxEN. The interrupt mask bits are T3CCTL0.IM, T3CCTL1.IM, T4CCTL0.IM, T4CCTL1.IM, T3CTL.OVFIM, and T4CTL.OVFIM. Note that enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. When the timer is used in Free-running Mode or Modulo Mode the interrupt flags are set as follows: TIMIF.TxCH0IF and TIMIF.TxCH1IF are set on compare event TIMIF.TxOVFIF is set when counter reaches terminal count value (overflow) When the timer is used in Down Mode the interrupt flags are set as follows: Timer 3 and 4 Interrupts There is one interrupt vector assigned to each of the timers. These are T3 and T4 (interrupt #11 and #12, see Table 39). The following SWRS033H TIMIF.TxCH0IF and TIMIF.TxCH1IF are set on compare event TIMIF.TxOVFIF is set when counter reaches zero Page 132 of 246 CC1110Fx / CC1111Fx When the timer is used in Up/Down Mode the interrupt flags are set as follows: TIMIF.TxCH0IF and TIMIF.TxOVFIF are set when the counter turns around on zero TIMIF.TxCH1IF is set on compare event 12.9.8 Timer 3 and 4 Registers This section describes the following Timer 3 and Timer 4 registers: In addition, the CPU interrupt flag, IRCON.TxIF will be asserted if the channel n interrupt mask bit (TxCCTLn.IM) is set to 1. T3CNT - Timer 3 Counter T3CTL - Timer 3 Control T3CCTLn - Timer 3 Channel n Compare Control T3CCn - Timer 3 Channel n Compare Value T4CNT - Timer 4 Counter 12.9.7 Timer 3 and Timer 4 DMA Triggers There are two DMA triggers associated with Timer 3 and two DMA triggers associated with Timer 4. These are DMA triggers T3_CH0, T3_CH1, T4_CH0, and T4_CH1, which are generated on timer compare events as follows: T3_CH0: Timer 3 channel 0 compare T4CTL - Timer 4 Control T4CCTLn - Timer 4 Channel n Compare Control T4CCn - Timer 4 Channel n Compare Value TIMIF - Timer 1/3/4 Interrupt Mask/Flag T3_CH1: Timer 3 channel 1 compare T4_CH0: Timer 4 channel 0 compare T4_CH1: Timer 4 channel 1 compare T3CNT (0xCA) - Timer 3 Counter Bit Field Name Reset R/W Description 7:0 CNT[7:0] 0x00 R Timer count byte. Contains the current value of the 8-bit counter SWRS033H Page 133 of 246 CC1110Fx / CC1111Fx T3CTL (0xCB) - Timer 3 Control Bit Field Name Reset R/W Description 7:5 DIV[2:0] 000 R/W Prescaler divider value. Generates the active clock edge used to update the counter as follows: 000 Tick frequency /1 001 Tick frequency /2 010 Tick frequency /4 011 Tick frequency /8 100 Tick frequency /16 101 Tick frequency /32 110 Tick frequency /64 111 Tick frequency /128 Note: Changes to these bits has immediate effect on the frequency of the active clock edges. 4 3 2 START OVFIM CLR 0 1 0 R/W R/W0 R0/W1 Start timer 0 Suspended 1 Normal operation Overflow interrupt mask 0 Interrupt disabled 1 Interrupt enabled Clear counter. Writing a 1 resets the counter to 0x00. This bit will be 0 when returning from PM2 and PM3 1:0 MODE[1:0] 00 R/W Timer 3 mode select. The timer operating mode is selected as follows: 00 Free running, repeatedly count from 0x00 to 0xFF 01 Down, count from T3CC0 to 0x00 10 Modulo, repeatedly count from 0x00 to T3CC0 11 Up/down, repeatedly count from 0x00 to T3CC0 and from T3CC0 down to 0x00 SWRS033H Page 134 of 246 CC1110Fx / CC1111Fx T3CCTL0 (0xCC) - Timer 3 Channel 0 Compare Control Bit Field Name 7 6 5:3 2 IM CMP[2:0] MODE 1:0 Reset R/W Description - R0 Not used 1 R/W Channel 0 interrupt mask 000 0 00 R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T3CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) 100 Clear output on compare-up, set on 0 (set on compare-down in up/down mode) 101 Set output on compare, clear on 0xFF 110 Clear output on compare, set on 0x00 111 Not used Timer 3 channel 0 compare mode enable 0 Disable 1 Enable Reserved. Always write 00 T3CC0(0xCD) - Timer 3 Channel 0 Compare Value Bit Field Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer 3 channel 0 compare value SWRS033H Page 135 of 246 CC1110Fx / CC1111Fx T3CCTL1 (0xCE) - Timer 3 Channel 1 Compare Control Bit Field Name 7 6 5:3 2 IM CMP[2:0] MODE 1:0 Reset R/W Description - R0 Not used 1 R/W Channel 1 interrupt mask 000 0 00 R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled Channel 1 compare output mode select. Specified action on output when timer value equals compare value in T3CC1 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) 100 Clear output on compare-up, set on 0 (set on compare-down in up/down mode) 101 Set output on compare, clear on T3CC0 110 Clear output on compare, set on T3CC0 111 Not used Timer 3 channel 1 compare mode enable 0 Disable 1 Enable Reserved. Always write 00 T3CC1 (0xCF) - Timer 3 Channel 1 Compare Value Bit Field Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer 3 channel 1 compare value T4CNT (0xEA) - Timer 4 Counter Bit Field Name Reset R/W Description 7:0 CNT[7:0] 0x00 R Timer count byte. Contains the current value of the 8-bit counter SWRS033H Page 136 of 246 CC1110Fx / CC1111Fx T4CTL (0xEB) - Timer 4 Control Bit Field Name Reset R/W Description 7:5 DIV[2:0] 000 R/W Prescaler divider value. Generates the active clock edge used to update the counter as follows: 000 Tick frequency /1 001 Tick frequency /2 010 Tick frequency /4 011 Tick frequency /8 100 Tick frequency /16 101 Tick frequency /32 110 Tick frequency /64 111 Tick frequency /128 Note: Changes to these bits has immediate effect on the frequency of the active clock edges. 4 3 2 START OVFIM CLR 0 1 0 R/W R/W0 R0/W1 Start timer 0 Suspended 1 Normal operation Overflow interrupt mask 0 Interrupt disabled 1 Interrupt enabled Clear counter. Writing a 1 resets the counter to 0x00. This bit will be 0 when returning from PM2 and PM3 1:0 MODE[1:0] 00 R/W Timer 4 mode select. The timer operating mode is selected as follows: 00 Free running, repeatedly count from 0x00 to 0xFF 01 Down, count from T4CC0 to 0x00 10 Modulo, repeatedly count from 0x00 to T4CC0 11 Up/down, repeatedly count from 0x00 to T4CC0 and from T4CC0 down to 0x00 SWRS033H Page 137 of 246 CC1110Fx / CC1111Fx T4CCTL0 (0xEC) - Timer 4 Channel 0 Compare Control Bit Field Name 7 6 5:3 2 IM CMP[2:0] MODE 1:0 Reset R/W Description - R0 Not used 1 R/W Channel 0 interrupt mask 000 0 00 R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T4CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) 100 Clear output on compare-up, set on 0 (set on compare-down in up/down mode) 101 Set output on compare, clear on 0xFF 110 Clear output on compare, set on 0x00 111 Not used Timer 4 channel 0 compare mode enable 0 Disable 1 Enable Reserved. Always write 00 T4CC0 (0xED) - Timer 4 Channel 0 Compare Value Bit Field Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer 4 channel 0 compare value SWRS033H Page 138 of 246 CC1110Fx / CC1111Fx T4CCTL1 (0xEE) - Timer 4 Channel 1 Compare Control Bit Field Name 7 6 5:3 2 IM CMP[2:0] MODE 1:0 Reset R/W Description - R0 Not used 1 R/W Channel 0 interrupt mask 000 0 00 R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T4CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) 100 Clear output on compare-up, set on 0 (set on compare-down in up/down mode) 101 Set output on compare, clear on T4CC0 110 Clear output on compare, set on T4CC0 111 Not used Timer 4 channel 1 compare mode enable 0 Disable 1 Enable Reserved. Always write 00 T4CC1 (0xEF) - Timer 4 Channel 1 Compare Value Bit Field Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer 4 channel 1 compare value SWRS033H Page 139 of 246 CC1110Fx / CC1111Fx TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag Bit Field Name 7 6 5 4 3 2 1 0 OVFIM T4CH1IF T4CH0IF T4OVFIF T3CH1IF T3CH0IF T3OVFIF Reset R/W Description - R0 Not used 1 R/W Timer 1 overflow interrupt mask 0 0 0 0 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 Interrupt disabled 1 Interrupt enabled Timer 4 channel 1 interrupt flag. Writing a 1 has no effect 0 No interrupt is pending 1 Interrupt is pending Timer 4 channel 0 interrupt flag. Writing a 1 has no effect 0 No interrupt is pending 1 Interrupt is pending Timer 4 overflow interrupt flag. Writing a 1 has no effect 0 No interrupt is pending 1 Interrupt is pending Timer 3 channel 1 interrupt flag. Writing a 1 has no effect 0 No interrupt is pending 1 Interrupt is pending Timer 3 channel 0 interrupt flag. Writing a 1 has no effect 0 No interrupt is pending 1 Interrupt is pending Timer 3 overflow interrupt flag. Writing a 1 has no effect 0 No interrupt is pending 1 Interrupt is pending SWRS033H Page 140 of 246 CC1110Fx / CC1111Fx 12.10 ADC 12.10.1 ADC Introduction Eight individual input channels, singleended or differential (CC1111Fx has only six channels) The ADC supports up to 12-bit analog-todigital conversion. The ADC includes an analog multiplexer with up to eight individually configurable channels, reference voltage generator, and conversion results written to memory through DMA. Several modes of operation are available. All references to VDD applies to voltage on the pin AVDD. Reference voltage selectable as internal, external single ended, external differential, or VDD. Interrupt request generation DMA triggers at end of conversions The main features of the ADC are as follows: Temperature sensor input Selectable decimation rates which also sets the resolution (7 to 12 bits). AIN7 ... AIN0 Battery measurement capability VDD/3 input mux TMP_SENSOR Delta-Sigma Modulator Decimation Filter Int 1.25V AIN7 AVDD ref mux Clock Generation and Control AIN6-AIN7 Figure 39: ADC Block Diagram 12.10.2 ADC Operation This section describes the general setup and operation of the ADC and describes the usage of the ADC control and status registers accessed by the CPU. 12.10.2.1 ADC Core The ADC is capable of converting an analog input into a digital representation with up to 12 bits resolution. The ADC uses a selectable positive reference voltage. 12.10.2.2 ADC Inputs The signals on the P0 port pins can be used as ADC inputs. Note: P0_6 and P0_7 do not exist on CC1111Fx, hence only six input channels are available (AIN0 - AIN5) To configure a P0 pin to be used as an ADC input the corresponding bit in the ADCCFG register must be set to 1. The default value in this register disables the ADC inputs. Please see Section 12.4.6.7 on Page 94 for more details on how to configure the ADC input pins. In the following these port pin will be referred to as the AIN0 - AIN7 pins. The ADC can be set up to automatically perform a sequence of conversions and optionally perform an extra conversion. It is possible to configure the inputs as singleended or differential inputs. In the case where differential inputs are selected, the differential inputs consist of the input pairs AIN0 - AIN1, AIN2 - AIN3, AIN4 - AIN5, and AIN6 - AIN7. Note that neither a negative supply, nor a supply larger than VDD (unregulated power) can be applied to these pins. It is the difference between the pairs that are converted in differential mode. In addition to the input pins AIN0 - AIN7, the output of an on-chip temperature sensor can SWRS033H Page 141 of 246 CC1110Fx / CC1111Fx be selected as an input to the ADC for temperature measurements. It is also possible to select a voltage corresponding to VDD/3 as an ADC input. This input allows the implementation of e.g. a battery monitor in applications where this feature is required. 12.10.2.3 ADC Conversion Sequences The ADC will perform a sequence of conversions, and the results can be moved to memory (through DMA) without any interaction from the CPU. The ADCCON2.SCH register bits are used to define an ADC conversion sequence from the ADC inputs. If some of the inputs in this sequence are not configured to be analog input signals in the ADCCFG register, these will be skipped. For differential inputs both input pins must be configured to be analog input signals. 0000 ≤ ADCCON2.SCH ≤ 0111: Singleended inputs 1000 ≤ ADCCON2.SCH Differential inputs ≤ 1011: 1100 ≤ ADCCON2.SCH ≤ 1111: GND, internal voltage reference, temp. sensor, and VDD/3 When ADCCON2.SCH is set to a value less than 1000 a conversion sequence will contain a conversion from each ADC input, starting at AIN0 and ending at the input programmed in ADCCON2.SCH. When ADCCON2.SCH is set to a value ranging from 1000 to 1011, the sequence will start at the differential input pair (AIN0 - AIN1) and stop at the input pair given by ADCCON2.SCH. For even higher settings, only single conversions are performed. In addition to this sequence of conversions, the ADC can be programmed to perform a single conversion (see next section). The ADCCON1.ST bit is used to start a sequence of conversions. A sequence will start when this bit is set high, ADCCON1.STSEL=11, and no conversion is currently running. When the sequence is completed, this bit is automatically cleared. The ADCCON1.STSEL bits select which event that will start a new sequence of conversions. The options which can be selected are rising edge on external pin P2_0, end of previous sequence, a Timer 1 channel 0 compare event, or ADCCON1.ST is 1. ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed when no conversion is running. The ADCCON2.SDIV bits select the decimation rate (and thereby also the resolution and time required to complete a conversion and sample rate). The decimation rate should only be changed when no conversion is running. The ADCCON2.SCH register bits are used to define an ADC conversion sequence. The ADC can be programmed to perform a single conversion (single-ended, differential, GND, internal voltage reference, temperature sensor, or VDD/3). This is called an extra conversion and is controlled with the ADCCON3 register. This conversion is triggered by writing to ADCCON3. If this register is written while the ADC is running, the conversion will take place as soon as the sequence has completed. If the register is written while the ADC is not running, the conversion will take place immediately after the ADCCON3 register is updated. The ADCCON3 register controls which input to use, reference voltage, and decimation rate for the extra conversion. The coding of the register bits is exactly as for ADCCON2. Note: If a sequence of conversions is started without setting any of the P0 pins as analog inputs, ADCCON2.SCH and ADCCON1.EOC will still be updated, as if the conversions had taken place. 12.10.2.4 ADC Operating Modes This section describes the operating modes and initialization of conversions. The ADC has three control registers: ADCCON1, ADCCON2, and ADCCON3. These registers are used to configure the ADC and to report status. The ADCCON1.EOC bit is a status bit that is set high when a conversion ends and cleared when ADCH is read. 12.10.2.5 ADC Reference Voltage The positive reference voltage for analog-todigital conversions is selectable as either an internally generated 1.25 V voltage, VDD on the AVDD pin, an external voltage applied to the AIN7 input pin, or a differential voltage applied to the AIN6 - AIN7 inputs (AIN6 must have the highest input voltage). It is possible to select the reference voltage as the input to the SWRS033H Page 142 of 246 CC1110Fx / CC1111Fx ADC in order to perform a conversion of the reference voltage e.g. for calibration purposes. Similarly, it is possible to select the ground terminal GND as an input. calculations. Using other frequencies will affect the results, and conversion time. All data presented within this data sheet assume the use of the high speed crystal oscillator. Note: P0_6 and P0_7 do not exist on CC1111Fx, hence it is not possible to use external voltage reference for the ADC on the CC1111Fx. The time required to perform a conversion depends on the selected decimation rate. When, for instance, the decimation rate is set to 128, the decimation filter uses exactly 128 ADC clock periods to calculate the result. When a conversion is started, the input multiplexer is allowed 16 ADC clock periods to settle in case the channel has been changed since the previous conversion. The 16 clock cycles settling time applies to all decimation rates. This means that the conversion time, Tconv, is given by: 12.10.2.6 ADC Conversion Results The digital conversion result is represented in two's complement form. For single ended configurations the result is always positive (the result is the difference between ground and the input signal AINn, where n is 0, 1, 2, …, 7) and will be a value between 0 and 2047. The maximum value is reached when the input amplitude is equal VREF, the selected voltage reference. For differential configurations the difference between two pin pairs are converted and this difference can be negatively signed. For 12-bit resolution the digital conversion result is 2047 when the analog input is equal to VREF, and the conversion result is –2048 when the analog input is equal to –VREF. The digital conversion result is available in ADCH and ADCL when ADCCON1.EOC is set to 1. Note that the conversion result always resides in MSB section of ADCH:ADCL. When reading the ADCCON2.SCH bits, the number returned will indicate what the last conversion was. Notice that when the value written to ADCCON2.SCH is less than 1100, the number returned will be the number written + 1. For example, after a sequence of conversions from AIN0 to AIN4 has completed, ADCCON2.SCH will be read as 0101, while after a single conversion of the temperature sensor has completed, the register field will be read as 1110 (same as the value written to it). If an extra conversion has been initiated by writing to ADCCON3.ECH, ADCCON2.SCH will be updated, after the conversion has completed, with the same value as written to ADCCON3.ECH, even if this value was less than 1100. Tconv = (decimation rate + 16) x T where 0.22 μs ≤ T ≤ 0.23 μs for CC1110Fx, depending on the frequency of the high speed crystal oscillator T = 0.25 μs for CC1111Fx 12.10.2.8 ADC Interrupts The ADC will only generate an interrupt when an extra conversion has completed. 12.10.2.9 ADC DMA Triggers DMA triggers 20 - 28 are associated with single-ended or differential conversion sequences (ADCCON2.SCH ≤ 1100). The ADC will generate a DMA trigger event when a new sample is ready from a conversion in the sequence. The same is the case if a single conversion is completed (ADCCON2.SCH ≥ 1100). Be aware that DMA trigger number 27 2 and 28 are shared with the I S module. In addition there is one DMA trigger, ADC_CHALL, which is active when new data is ready from any of the conversions in the ADC conversion sequence and from the single conversion defined by ADCCON2.SCH. A completion of an extra conversion will not generate a trigger event. The DMA triggers are listed in Table 51 on age 107. 12.10.2.7 ADC Conversion Timing The high speed crystal oscillator should be selected as system clock when the ADC is used and CLKCON.CLKSPD should be 000. The ADC runs on a clock which is the system clock divided by 6 to give a 4.33/4 MHz ADC clock. Both the delta-sigma modulator and the decimation filter use the ADC clock for their 12.10.3 ADC Registers This section describes the ADC registers. SWRS033H Page 143 of 246 CC1110Fx / CC1111Fx ADCL (0xBA) - ADC Data Low Bit Field Name Reset R/W Description 7:4 ADC[3:0] 0000 R Least significant part of ADC conversion result. The decimation rate configures through ADCCON2.SDIV determines how many of these bits are relevant to use. 0000 R 3:0 ADCH (0xBB) - ADC Data High Bit Field Name Reset R/W Description 7:0 ADC[11:4] 0x00 R Most significant part of ADC conversion result. The decimation rate configures through ADCCON2.SDIV determines how many of these bits are relevant to use. ADCCON1 (0xB4) - ADC Control 1 Bit Field Name Reset R/W Description 7 EOC 0 R H0 End of conversion. Cleared when ADCH has been read. If a new conversion is completed before the previous data has been read, the EOC bit will remain high. 6 5:4 3:2 1:0 ST STSEL[1:0] RCTRL[1:0] 0 11 00 11 R/W1 R/W R/W R/W 0 Conversion not complete 1 Conversion completed Start conversion. Read as 1 until conversion has completed 0 No conversion in progress 1 Start a conversion sequence if ADCCON1.STSEL=11 and no sequence is running. Start select. Selects which event that will start a new conversion sequence. 00 External trigger on P2_0 pin. 01 Full speed. Do not wait for triggers. 10 Timer 1 channel 0 compare event 11 ADCCON1.ST=1 Controls the 16 bit random generator. When set to 01, the setting will automatically return to 00 when operation has completed. 00 Operation completed 01 Clock the LFSR once (13x unrolling) 10 Reserved 11 Reserved Reserved. Always write 11 SWRS033H Page 144 of 246 CC1110Fx / CC1111Fx ADCCON2 (0xB5) - ADC Control 2 Bit Field Name Reset R/W Description 7:6 SREF[1:0] 00 R/W Selects reference voltage used for the sequence of conversions 5:4 3:0 SDIV[1:0] SCH[3:0] 01 00 R/W R/W 00 Internal 1.25V reference 01 External reference on AIN7 pin (only CC1110Fx) 10 VDD on the AVDD pin 11 External reference on AIN6 - AIN7 differential input (only CC1110Fx) Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00 64 dec rate (7 bits resolution) 01 128 dec rate (9 bits resolution) 10 256 dec rate (10 bits resolution) 11 512 dec rate (12 bits resolution) Sequence Channel Select. Selects the end of the sequence. SCH ≤ 0111: A conversion sequence will contain a conversion from each ADC input, starting at AIN0 and ending at the input programmed in ADCCON2.SCH. 1000 ≤ SCH ≤ 1011: The sequence will start at the differential input pair (AIN0 AIN1) and stop at the input pair given by ADCCON2.SCH. SCH ≥ 1100: Only single conversions are performed. When reading the ADCCON2.SCH bits, the number returned will indicate what the last conversion was. Please see Section 12.10.2.6 for details. 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 AIN0 - AIN1 1001 AIN2 - AIN3 1010 AIN4 - AIN5 1011 AIN6 - AIN7 1100 GND 1101 Positive voltage reference 1110 Temperature sensor 1111 VDD/3 SWRS033H Page 145 of 246 CC1110Fx / CC1111Fx ADCCON3 (0xB6) - ADC Control 3 Bit Field Name Reset R/W Description 7:6 EREF[1:0] 00 R/W Selects reference voltage used for the extra conversion 5:4 3:0 EDIV[1:0] ECH[3:0] 00 0000 R/W R/W 00 Internal 1.25V reference 01 External reference on AIN7 pin (only CC1110Fx) 10 VDD on the AVDD pin 11 External reference on AIN6 - AIN7 differential input (only CC1110Fx) Sets the decimation rate used for the extra conversion. The decimation rate also determines the resolution and time required to complete the conversion. 00 64 dec rate (7 bits resolution) 01 128 dec rate (9 bits resolution) 10 256 dec rate (10 bits resolution) 11 512 dec rate (12 bits resolution) Extra channel select. An extra conversion will be triggered by writing to these bits. If they are written while the ADC is running, the conversion will take place as soon as the sequence has completed. If the bits are written while the ADC is not running, the conversion will take place immediately after this register has been updated. The bits are automatically cleared when the extra conversion has finished. 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 AIN0 - AIN1 1001 AIN2 - AIN3 1010 AIN4 - AIN5 1011 AIN6 - AIN7 1100 GND 1101 Positive voltage reference 1110 Temperature sensor 1111 VDD/3 SWRS033H Page 146 of 246 CC1110Fx / CC1111Fx 12.11 Random Number Generator 12.11.1 Introduction The random number following features. generator has The random number generator is a 16-bit Linear Feedback Shift Register (LFSR) with the 16 15 2 Generate pseudo-random bytes which can be read by the CPU. polynomial X X X 1 (i.e. CRC16). It uses different levels of unrolling depending on the operation it performs. The basic version (no unrolling) is shown below. Calculate CRC16 of bytes that are written to RNDH. The random number generator is turned off when ADCCON1.RCTRL=11. Seeded by value written to RNDL. 15 in_bit + 14 13 12 11 10 9 8 7 6 5 4 3 2 + 1 0 + Figure 40: Basic Structure of the Random Number Generator 12.11.2 Random Operation Number Generator The operation of the random number generator is controlled by the ADCCON1.RCTRL bits. The current value of the 16-bit shift register in the LFSR can be read from the RNDH and RNDL registers. 12.11.2.1 Semi Random Sequence Generation To generate pseudo-random bytes, ADCCON1.RCTRL should be set to 01. This will clock the LFSR once (13x unrolling) and the ADCCON1.RCTRL bits will automatically be cleared when the operation has completed. 12.11.2.3 CRC16 The LFSR can also be used to calculate the CRC value of a sequence of bytes. Writing to the RNDH register will trigger a CRC calculation. The new byte is processed from the MSB end and an 8x unrolling is used, so that a new byte can be written to RNDH every clock cycle. Note that the LFSR must be properly seeded by writing to RNDL twice, before the CRC calculations start. Usually the seed value should be 0x0000 or 0xFFFF. Using 0xFFFF as seed value will give the CRC used by the radio. For the following byte sequence: 0x03, 0x41, 0x42, 0x43 12.11.2.2 Seeding The LFSR can be seeded by writing to the RNDL register twice. Each time the RNDL register is written, the 8 LSB of the LFSR is copied to the 8 MSB and the 8 LSBs are replaced with the new data byte that was written to RNDL. The CRC will be 0xB4BC when using 0xFFFF as seed value. 12.11.3 Registers The random number generator registers are described in this section. SWRS033H Page 147 of 246 CC1110Fx / CC1111Fx RNDL (0xBC) - Random Number Generator Data Low Byte Bit Field Name Reset R/W Description [7:0] RNDL[7:0] 0xFF R/W Random value/seed or CRC result, low byte When used for random number generation writing this register twice will seed the random number generator. Writing to this register copies the 8 LSBs of the LFSR to the 8 MSBs and replaces the 8 LSBs with the data value written. The value returned when reading from this register is the 8 LSBs of the LFSR. When used for random number generation, reading this register returns the 8 LSBs of the random number. When used for CRC calculations, reading this register returns the 8 LSBs of the CRC result. RNDH (0xBD) - Random Number Generator Data High Byte Bit Field Name Reset R/W Description [7:0] RNDH[7:0] 0xFF R/W Random value or CRC result/input data, high byte When written, a CRC16 calculation will be triggered, and the data value written is processed starting with the MSB bit. The value returned when reading from this register is the 8 MSBs of the LFSR. When used for random number generation, reading this register returns the 8 MSBs of the random number. When used for CRC calculations, reading this register returns the 8 MSBs of the CRC result. 12.12 AES Coprocessor The CC1110Fx/CC1111Fx data encryption is performed using a dedicated coprocessor which supports the Advanced Encryption Standard, AES. The coprocessor allows encryption/decryption to be performed with minimal CPU usage. The coprocessor has the following features: ECB, CBC, CFB, OFB, CTR, and CBC- MAC modes. Hardware support for CCM mode 12.12.2 Key and IV Before a key or IV/nonce load starts, an appropriate load key or IV/nonce command must be issued to the coprocessor. When loading the IV it is important to also set the correct mode. A key load or IV load operation aborts any processing that could be running. The key, once loaded, stays valid until a key reload takes place. The IV must be downloaded before the beginning of each message (not block). 128-bits key and IV/Nonce DMA transfer trigger capability Both key and IV are cleared by a reset of the device and when PM2 or PM3 are entered. 12.12.1 AES Operation To encrypt a message, procedure must be followed: the following AES works on blocks of 128 bits. If a block contains less than 128 bits, it must be padded with zeros when written to the coprocessor. Load key Load initialization vector (IV)/nonce Download and upload encryption/decryption. data 12.12.3 Padding of Input Data for The AES coprocessor works on blocks of 128 bits. A block of data is loaded into the coprocessor, encryption is performed, and the result must be read out before the next block can be processed. Before each block load, a dedicated start command must be sent to the coprocessor. 12.12.4 Interface to CPU The CPU communicates coprocessor using three SFRs: with the ENCCS, Encryption control and status register ENCDI, Encryption input register ENCDO, Encryption output register SWRS033H Page 148 of 246 CC1110Fx / CC1111Fx Read/write to the control and status register is done by the CPU, while read/write the output/input registers is intended for use together with direct memory access (DMA). When using DMA, one channel is used for input data and one for output data. The DMA channels must be initialized before a start command is written to the ENCCS. Writing a start command generates a DMA trigger and the transfer is started. After each block is processed, the interrupt flag, S0CON.ENCIF, is asserted, and an interrupt request generated if IEN0.ENCIE is set to 1. The interrupt is used to issue a new start command to the ENCCS. ECB and CBC modes are performed as described in Section 12.12.1 When using CFB, OFB, and CTR mode, the 128 bits blocks are divided into four 32 bit blocks. 32 bits are loaded into the AES coprocessor and the resulting 32 bits are read out. This continues until all 128 bits have been encrypted. The only time one has to consider this is if data is loaded/read directly using the CPU. When using DMA, this is handled automatically by the DMA triggers generated by the AES coprocessor, thus DMA is preferred. decryption 12.12.6 AES Interrupts The AES interrupt flag, S0CON.ENCIF, is asserted when encryption or decryption of a block is completed. An interrupt request is generated if IEN0.ENCIE is set to 1 12.12.7 AES DMA Triggers 12.12.5 Modes of Operation Both encryption and performed similarly. block at a time, except for the last block. Before the last block is loaded, the mode must be changed to CBC. The last block is then downloaded and the block uploaded will be the MAC value. CBC-MAC decryption is similar to encryption. The message MAC uploaded must be compared with the MAC to be verified. are The CBC-MAC mode is a variant of the CBC mode. When performing CBC-MAC, data is downloaded to the coprocessor one 128 bits There are two DMA triggers associated with the AES coprocessor. These are ENC_DW, which is active when input data needs to be downloaded to the ENCDI register, and ENC_UP, which is active when output data needs to be uploaded from the ENCDO register. The ENCDI and ENCDO registers should be set as destination and source locations for DMA channels used to transfer data to or from the AES coprocessor. 12.12.8 AES Registers The AES coprocessor registers are described below. These registers will be in their reset state when returning to active mode from PM2 and PM3. SWRS033H Page 149 of 246 CC1110Fx / CC1111Fx ENCCS (0xB3) - Encryption Control and Status Bit Field Name 7 6:4 3 2:1 0 MODE[2:0] RDY CMD[1:0] ST Reset R/W Description 0 R0 Not used 000 R/W Encryption/decryption mode 1 0 0 R R/W R/W1 H0 000 CBC 001 CFB 010 OFB 011 CTR 100 ECB 101 CBC MAC 110 Reserved 111 Reserved Encryption/decryption ready status 0 Encryption/decryption in progress 1 Encryption/decryption is completed Command to be performed when a 1 is written to ST. 00 encrypt block 01 decrypt block 10 load key 11 load IV/nonce Start processing command set by CMD. Must be issued for each command or 128 bits block of data. Cleared by hardware ENCDI (0xB1) - Encryption Input Data Bit Field Name Reset R/W Description 7:0 DIN[7:0] 0x00 R/W Encryption input data. ENCDO (0xB2) - Encryption Output Data Bit Field Name Reset R/W Description 7:0 DOUT[7:0] 0x00 R/W Encryption output data. SWRS033H Page 150 of 246 CC1110Fx / CC1111Fx 12.13 Watchdog Timer The watchdog timer (WDT) is intended as a recovery method in situations where the software hangs. The WDT shall reset the system when software fails to clear the WDT within a selected time interval. The watchdog can be used in applications where high reliability is required. If the watchdog function is not needed in an application, it is possible to configure the watchdog timer to be used as an interval timer that can be used to generate interrupts at selected time intervals. The features of the watchdog timer are as follows: Four selectable timer intervals Watchdog mode Timer mode Interrupt request generation in timer mode Clock independent from system clock The operation of the WDT module is controlled by the WDCTL register. The watchdog timer consists of a 15-bit counter clocked by the one of the low speed oscillators. Note that the content of the 15-bit counter is not user-accessible. The content of the 15-bit counter is reset to 0x0000 when a PM2 or PM3 is entered. 12.13.1 Watchdog Mode The watchdog timer is disabled after a system reset. To set the WDT in watchdog mode the WDCTL.MODE bit must be set to 0. The watchdog timer counter starts incrementing when the enable bit WDCTL.EN is set to 1. When the timer is enabled in watchdog mode it is not possible to disable the timer. Therefore, writing a 0 to WDCTL.EN has no effect if a 1 was already written to this bit when WDCTL.MODE was 0. The WDT operates with a watchdog timer clock frequency of 32.768 kHz (low speed crystal oscillator) or 32 - 36 kHz (calibrated low power RC oscillator). The timer interval depend on the count value settings (64, 512, 8192, and 32768 respectively) configured in WDCTL.INT. If the counter reaches the selected timer interval value (watchdog timeout), the watchdog timer generates a reset signal for the system. If a watchdog clear sequence is performed before the counter reaches the selected timer interval value, the counter is reset to 0x0000 and continues incrementing its value. The watchdog clear sequence consists of writing 1010 to WDCTL.CLR[3:0] followed by writing 0101 to the same register bits within one half of a watchdog clock period. If this complete sequence is not performed, the watchdog timer generates a reset signal for the system. Note that as long as a correct watchdog clear sequence begins within the selected timer interval, the counter is reset when the complete sequence has been received. When the watchdog timer has been enabled in watchdog mode, it is not possible to change the mode by writing to the WDCTL.MODE bit. The timer interval value can be changed by writing to the WDCTL.INT[1:0] bits. Note that a change in the timer interval value should be followed by a clearing of the watchdog timer to avoid an unwanted watchdog reset. In watchdog mode, the WDT does not produce an interrupt request. 12.13.2 Timer Mode To set the WDT in normal timer mode, the WDCTL.MODE bit is set to 1. When register bit WDCTL.EN is set to 1, the timer is started and the counter starts incrementing. When the counter reaches the selected interval value, the IRCON2.WDTIF flag is asserted and an interrupt request is generated if watchdog timer interrupt is enabled (IEN2.WDTIE=1). In timer mode, it is possible to clear the timer contents by writing a 1 to WDCTL.CLR[0]. When the timer is cleared the contents of the counter is set to 0x0000. The timer is stopped by setting WDCTL.EN=0 and restarted from 0x000 by setting WDCTL.EN=1. The timer interval is set by the WDCTL.INT[1:0] bits. In timer mode, a reset will not be produced when the timer interval value is reached. 12.13.3 Watchdog Mode and Power Modes In active mode and PM0 the WDT runs and resets the chip upon timeout. To avoid reset, SWRS033H Page 151 of 246 CC1110Fx / CC1111Fx the watchdog timer must be cleared before the counter expires. Power Mode Comments PM1 The WDT runs but does not reset the chip upon timeout. If active mode is entered just as the timer expires, the chip will be reset immediately, hence the WDT needs to be cleared regularly (before timeout) also when in PM1. PM2 and PM3 The WDT is disabled and reset, and the configuration is retained. The counter will start from 0x0000 when active mode is entered from PM2 or PM3 Table 54: Watchdog Mode and Power Modes 12.13.4 Watchdog Timer Register WDCTL (0xC9) - Watchdog Timer Control Bit Field Name Reset R/W Description 7:4 CLR[3:0] 0000 R/W Clear timer. When 1010 followed by 0101 is written to these bits, the counter is reset to 0x0000. Note that the watchdog will only be cleared when 0101 is written within 0.5 watchdog clock period after 1010 was written. Writing to these bits when EN is 0 has no effect. 3 EN 0 R/W Enable timer. When a 1 is written to this bit the timer is enabled and starts incrementing. Writing a 0 to this bit in timer mode stops the timer. Writing a 0 to this bit in watchdog mode has no effect. 2 1:0 MODE INT[1:0] 0 00 R/W R/W 0 Timer disabled 1 Timer enabled Mode select. 0 Watchdog mode 1 Timer mode Timer interval select. These bits select the timer interval defined as a given number of low speed oscillator periods. Timer interval # of periods 32.768 kHz crystal oscillator 32 kHz RCOSC 34.667 kHz RCOSC (calibrated, CC1111Fx) (calibrated, CC1110Fx running @ 26 MHz) 00 32768 1s 1.024 s 0.945 s 01 8192 0.25 s 0.256 s 0.236 s 10 512 15.625 ms 16 ms 14.769 ms 11 64 1.953 ms 2 ms 1.846 ms SWRS033H Page 152 of 246 CC1110Fx / CC1111Fx 12.14 USART USART0 and USART1 are serial communications interfaces that can be operated separately in either asynchronous UART mode or in synchronous SPI mode. The two USARTs are identical in functionality but are assigned to separate I/O pins. Refer to Section 12.4 on Page 90 for I/O configuration. 12.14.1 UART Mode For asynchronous serial interfaces, the UART mode is provided. In UART mode the interface uses a two-wire or four-wire interface consisting of the pins RXD and TXD, and optionally RTS and CTS. The UART mode includes the following features: 8 or 9 data bits Odd, even, or no parity Configurable start and stop bit level Configurable LSB or MSB first transfer Independent interrupts receive and transmit Independent receive and transmit DMA triggers Parity and framing error status The UART mode provides full duplex asynchronous transfers and the synchronization of bits in the receiver does not interfere with the transmit function. A UART byte transfer consists of a start bit, eight data bits, an optional ninth data or parity bit, and one or two stop bits. Note that the data transferred is referred to as a byte, although the data can actually consist of eight or nine bits. The UART operation is controlled by the USART x Control and Status registers, UxCSR, and the USART x UART Control register, UxUCR, where x is the USART number, 0 or 1. The UART mode is UxCSR.MODE is set to 1. selected when 12.14.1.1 UART Transmit A UART transmission is initiated when the USART Receive/Transmit Data Buffer, UxDBUF register is written. The byte is transmitted on the TXDx output pin. The UxDBUF register is double-buffered. The UxCSR.ACTIVE bit goes high when the byte transmission starts and low when it ends. When the transmission ends, the UxCSR.TX_BYTE bit is set to 1. The USARTx TX complete CPU interrupt flag (IRCON2.UTXxIF) is asserted when the UxDBUF register is ready to accept new transmit data, and an interrupt request is generated if IEN2.UTXxIE=1. This happens immediately after the transmission has been started, hence a new data byte value can be loaded into the data buffer while the byte is being transmitted. 12.14.1.2 UART Receive Data reception on the UART is initiated when a 1 is written to the UxCSR.RE bit. The UART will then search for a valid start bit on the RXDx input pin and set the UxCSR.ACTIVE bit high. When a valid start bit has been detected the received byte is shifted into the receive register. The UxCSR.RX_BYTE bit and the CPU interrupt flag, TCON.URXxIF, is set to 1 when the operation has completed and an interrupt request is generated if IEN0.URXxIE=1. At the same time UxCSR.ACTIVE will go low. The received data byte is available through the UxDBUF register. When UxDBUF is read, UxCSR.RX_BYTE is cleared by hardware. 12.14.1.3 UART Hardware Flow Control Hardware flow control is enabled when the UxUCR.FLOW bit is set to 1. The RTS output will then be driven low when the receive register is empty and reception is enabled. Transmission of a byte will not occur before the CTS input go low. 12.14.1.4 UART Character Format If the BIT9 and PARITY bits in register UxUCR are set high, parity generation and detection is enabled. The parity is computed and transmitted as the ninth bit, and during reception, the parity is computed and compared to the received ninth bit. If there is a parity error, the UxCSR.ERR bit is set high. This bit is cleared when UxCSR is read. The number of stop bits to be transmitted is set to one or two bits determined by the register bit UxUCR.SPB. The receiver will always check for one stop bit. If the first stop bit received during reception is not at the expected stop bit level, a framing error is signaled by setting register bit UxCSR.FE high. UxCSR.FE is cleared when SWRS033H Page 153 of 246 CC1110Fx / CC1111Fx UxCSR is read. The receiver will check both stop bits when UxUCR.SPB=1. Note that the USARTx RX complete CPU interrupt flag, TCON.URXxIF, and the UxCSR.RX_BYTE bit will be asserted when the first stop bit is checked OK. If the second stop bit is not OK, the framing error bit, UxCSR.FE, will be asserted. This means that this bit is updated 1 bit duration later than the 2 other above mentioned bits. The UxCSR.ACTIVE bit will be de-asserted after the second stop bit (if UxUCR.SPB=1). 12.14.2 SPI Mode This section describes the SPI mode of operation for synchronous communication. In SPI mode, the USART communicates with an external system through a 3-wire or 4-wire interface. The interface consists of the pins MOSI, MISO, SCK and SSN. Refer to Section 12.4 on Page 90 for I/O configuration. The SPI mode includes the following features: 3-wire (master) and 4-wire SPI interface Master and slave modes asserted and the received data byte is available in UxDBUF. An interrupt request is generated if IEN0.URXxIE=1 Since UxDBUF is double-buffered, the assertion of the USARTx TX complete CPU interrupt flag (IRCON2.UTXxIF) happens just after a transmission has been initiated, and is therefore not safe to use. Instead, the assertion of the UxCSR.TX_BYTE bit should be used as an indication on when new data can be written to UxDBUF. For DMA transfers this is handled automatically, but with the limitation that the UxGCR.CPHA bit must be set to zero. For systems requiring setting UxGCR.CPHA=1, the DMA can not be used. Also note that the USARTx TX complete interrupt occurs approximately 1 byte period prior to the USARTx RX complete interrupt. In SPI master mode, only the MOSI, MISO, and SCK should be configured as peripherals (see Section 12.4.6.1 and 12.4.6.2). If the external slave requires a slave select signal (SSN) this can be implemented by using a general-purpose I/O pin and control from SW. Configurable SCK polarity and phase 12.14.2.2 SPI Slave Operation Configurable LSB or MSB first transfer An SPI byte transfer in slave mode is controlled by the external system. The data on the MOSI input is shifted into the receive register controlled by the serial clock SCK, which is an input in slave mode. At the same time the byte in the transmit register is shifted out onto the MISO output. The SPI mode is selected when UxCSR.MODE is set to 0. In SPI mode, the USART can be configured to operate either as an SPI master or as an SPI slave by setting UxCSR.SLAVE to 0 or 1, respectively. 12.14.2.1 SPI Master Operation An SPI byte transfer in master mode is initiated when the UxDBUF register is written. The USART generates the SCK signal using the baud rate generator (see Section 12.14.3) and shifts the provided byte from the transmit register onto the MOSI output. At the same time the receive register shifts in the received byte from the MISO input pin. The polarity and clock phase of the serial clock SCK is selected by UxGCR.CPOL and UxGCR.CPHA. The order of the byte transfer is selected by the UxGCR.ORDER bit. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. When the transfer ends, the UxCSR.TX_BYTE bit is set to 1. The UxCSR.ACTIVE bit is set to 1 when SNN is asserted and cleared when SNN is deasserted. The UxCSR.RX_BYTE bit is set to 1 when a byte transfer ends. At the end of the transfer, the USARTx RX complete CPU interrupt flag, TCON.URXxIF, is asserted and the received data byte is available in UxDBUF. An interrupt request is generated if IEN0.URXxIE=1. The USARTx TX complete CPU interrupt flag, IRCON2.UTXxIF, is asserted at the start of the operation and an interrupt request is generated if IEN2.UTXxIE=1. The expected polarity and clock phase of SCK is selected by UxGCR.CPOL and UxGCR.CPHA as shown in Figure 41. The expected order of the byte transfer is selected by the UxGCR.ORDER bit. At the end of the transfer, the USARTx RX complete CPU interrupt flag, TCON.URXxIF, is SWRS033H Page 154 of 246 CC1110Fx / CC1111Fx 12.14.2.3 Slave Select pin (SSN) When the USART is operating in SPI slave mode, a 4-wire interface is used with the Slave Select (SSN) pin as an input to the SPI (edge controlled). The SPI slave becomes active after a falling edge on SSN and will receive data on the MOSI input and send data on the MISO output. After a rising edge on SSN, the SPI slave is inactive and will not receive data. Note that the MISO output is not tri-stated when the SPI slave is inactive. Also note that the rising edge on SSN must be aligned to the end of the byte sent / received. If this is not the case, the next received byte will be corrupted. If there is a rising edge on SSN in the middle of a byte, this should be followed by a USART flush to avoid corruption of the following byte. In SPI master mode, the SSN pin is not used. When the USART operates as an SPI master and a slave select signal is needed by an external SPI slave device, a general purpose I/O pin should be used to implement the slave select signal function in software. Figure 41: SPI Dataflow 12.14.3 Baud Rate Generation An internal baud rate generator set up the UART baud rate when operating in UART mode and the SPI master clock frequency when operating in SPI mode. The UxBAUD.BAUD_M[7:0] and UxGCR.BAUD_E[4:0] registers define the baud rate used for UART transfers and the rate of the serial clock (SCK) for SPI transfers. The baud rate is given by the following equation: Baudrate (256 BAUD _ M ) 2 2 28 BAUD _ E F where F is the system clock frequency set by the selected system clock source. The register values required for standard baud rates are shown in Table 55 (F = 26 MHz) and Table 56 (24 MHz). The tables also give the difference in actual baud rate to standard baud rate value as a percentage error. The maximum baud rate for UART mode is F/16 (UxGCR.BAUD_E[4:0]=16 and UxBAUD.BAUD_M[7:0]=0). The maximum baud rate for SPI master mode and thus SCK frequency is F/8 (UxGCR.BAUD_E[4:0]=17 and UxBAUD.BAUD_M[7:0]=0). If SPI master mode does not need to receive data, the SWRS033H Page 155 of 246 CC1110Fx / CC1111Fx maximum SPI rate is F/2 (UxGCR.BAUD_E[4:0]=19 and UxBAUD.BAUD_M[7:0]=0). Setting higher baud rates than this will give erroneous results. For SPI slave mode the maximum baud rate is always F/8. Note that the baud rate must be configured before any other UART or SPI operations take place (the baud rate should never be changed when UxCSR.ACTIVE is asserted). Baud Rate [bps] UxBAUD.BAUD_M UxGCR.BAUD_E Error (%) 2400 131 6 0.04 4800 131 7 0.04 9600 131 8 0.04 14400 34 9 0.13 19200 131 9 0.04 28800 34 10 0.13 38400 131 10 0.04 57600 34 11 0.13 76800 131 11 0.04 115200 34 12 0.13 230400 34 13 0.13 Table 55: Commonly used Baud Rate Settings for 26 MHz System Clock Baud Rate [bps] UxBAUD.BAUD_M UxGCR.BAUD_E Error (%) 2400 163 6 0.08 4800 163 7 0.08 9600 163 8 0.09 14400 59 9 0.13 19200 163 9 0.10 28800 59 10 0.14 38400 163 10 0.10 57600 59 11 0.14 76800 163 11 0.10 115200 59 12 0.14 230400 59 13 0.14 Table 56: Commonly used Baud Rate Settings for 24 MHz System Clock 12.14.4 USART Flushing 12.14.5 USART Interrupts The current operation can be aborted (operation stopped and all data buffers cleared) by setting UxUCR.FLUSH=1.Asserting the FLUSH bit should either be aligned with USART interrupts or a wait time of one bit duration (at current baud rate) should be added after setting the bit to 1 before accessing the USART registers. Each USART has two interrupts. These are the USART x RX complete interrupt (TCON.URXxIF) and the USART x TX complete interrupt (IRCON2.UTXxIF). The interrupts are enabled by setting IEN0.URXxIE=1 and IEN2.UTXxIE=1, respectively. Please see the previous sections on how the interrupt flags are asserted in the different modes of operation (UART RX, UART TX, SPI master, and SPI Slave). SWRS033H Page 156 of 246 CC1110Fx / CC1111Fx The interrupt enables summarized below. and flags are Interrupt enable bits: configured using a USART Receive/transmit buffer, UxDBUF, as source or destination address. Note: For systems requiring setting UxGCR.CPHA=1, the DMA can not be used. USART0 RX : IEN0.URX0IE USART1 RX : IEN0.URX1IE USART0 TX : IEN2.UTX0IE Refer to Table 51 on Page 107 for an overview of the DMA triggers. USART1 TX : IEN2.UTX1IE Interrupt flags: USART0 RX : TCON.URX0IF 12.14.7 USART Registers USART1 RX : TCON.URX1IF The registers for the USART are described in this section. For each USART there are five registers consisting of the following (x refers to USART number i.e. 0 or 1): USART0 TX : IRCON2.UTX0IF USART1 TX : IRCON2.UTX1IF UxCSR USART x Control and Status 12.14.6 USART DMA Triggers UxUCR USART x UART Control There are two DMA triggers associated with each USART (URX0, UTX0, URX1, and UTX1). The DMA triggers are activated by RX complete and TX complete events i.e. the same events that might generate USART interrupt requests. A DMA channel can be UxGCR USART x Generic Control SWRS033H UxDBUF USART x Receive/Transmit Data Buffer UxBAUD USART x Baud Rate Control Page 157 of 246 CC1110Fx / CC1111Fx U0CSR (0x86) - USART 0 Control and Status Bit Field Name Reset R/W Description 7 MODE 0 R/W USART 0 mode select 0 SPI mode 1 UART mode 6 RE 0 R/W UART 0 receiver enable 0 Receiver disabled 1 Receiver enabled 5 SLAVE 0 R/W SPI 0 master or slave mode select 0 SPI master 1 SPI slave 4 FE 0 R/W 0 UART 0 framing error status 0 No framing error detected 1 Byte received with incorrect stop bit level Note: TCON.URX0IF and U0CSR.RX_BYTE bit will be asserted when the first stop bit is checked OK, meaning that if two stop bits are sent and the second stop bit is not OK, this bit is asserted 1 bit duration later than the 2 other above mentioned bits. 3 ERR 0 R/W 0 UART 0 parity error status 0 No parity error detected 1 Byte received with parity error 2 RX_BYTE 0 R/W 0 Receive byte status 0 No byte received 1 Received byte ready 1 TX_BYTE 0 R/W 0 Transmit byte status 0 Byte not transmitted 1 Last byte written to Data Buffer register transmitted 0 ACTIVE 0 R USART 0 transmit/receive active status 0 USART 0 idle 1 USART 0 busy in transmit or receive mode SWRS033H Page 158 of 246 CC1110Fx / CC1111Fx U0UCR (0xC4) - USART 0 UART Control Bit Field Name Reset R/W Description 7 FLUSH 0 R0/ W1 Flush unit. When set to 1, this event will immediately stop the current operation and return the unit to idle state. This bit will be 0 when returning from PM2 and PM3 6 5 FLOW D9 0 0 R/W R/W UART 0 hardware flow control enable. Selects use of hardware flow control with RTS and CTS pins 0 Flow control disabled 1 Flow control enabled UART 0 data bit 9 contents. This value is used when 9 bit transfer is enabled. When parity is disabled the value written to D9 is transmitted as the 9th bit when BIT9=1. If parity is enabled then this bit sets the parity level as follows. 4 3 2 1 0 BIT9 PARITY SPB STOP START 0 0 0 1 0 R/W R/W R/W R/W R/W 0 Even parity 1 Odd parity UART 0 9-bit data enable 0 8 bits transfer 1 9 bits transfer (content of the 9th bit is given by D9 and PARITY.) UART 0 parity enable 0 Parity disabled 1 Parity enabled UART 0 number of stop bits 0 1 stop bit 1 2 stop bits UART 0 stop bit level 0 Low stop bit 1 High stop bit UART 0 start bit level. The polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 Low start bit 1 High start bit U0GCR (0xC5) - USART 0 Generic Control Bit Field Name Reset R/W Description 7 CPOL 0 R/W SPI 0 clock polarity 6 5 4:0 CPHA ORDER BAUD_E[4:0] 0 0 00000 R/W R/W R/W 0 Negative clock polarity (SCK low when idle) 1 Positive clock polarity (SCK high when idle) SPI 0 clock phase 0 Data centered on first edge of SCK period 1 Data centered on second edge of SCK period Bit order for transfers 0 LSB first 1 MSB first Baud rate exponent value. BAUD_E along with BAUD_M decides the UART 0 baud rate and the SPI 0 clock (SCK) frequency SWRS033H Page 159 of 246 CC1110Fx / CC1111Fx U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer Bit Field Name Reset R/W Description 7:0 DATA[7:0] 0x00 R/W USART 0 receive and transmit data buffer. Writing data to U0DBUF places the data into the internal transmit buffer. Reading U0DBUF returns the contents of the receive buffer. U0BAUD (0xC2) - USART 0 Baud Rate Control Bit Field Name Reset R/W Description 7:0 BAUD_M[7:0] 0x00 R/W Baud rate mantissa value. BAUD_M along with BAUD_E decides the UART 0 baud rate and the SPI 0 clock (SCK) frequency U1CSR (0xF8) - USART 1 Control and Status Bit Field Name Reset R/W Description 7 MODE 0 R/W USART 1 mode select 0 SPI mode 1 UART mode 6 RE 0 R/W UART 1 receiver enable 0 Receiver disabled 1 Receiver enabled 5 SLAVE 0 R/W SPI 1 master or slave mode select 0 SPI master 1 SPI slave 4 FE 0 R/W 0 UART 1 framing error status 0 No framing error detected 1 Byte received with incorrect stop bit level Note that TCON.URX1IF and U1CSR.RX_BYTE bit will be asserted when the first stop bit is checked OK, meaning that if two stop bits are sent and the second stop bit is not OK, this bit is asserted 1 bit duration later than the 2 other above mentioned bits. 3 ERR 0 R/W 0 UART 1 parity error status 0 No parity error detected 1 Byte received with parity error 2 RX_BYTE 0 R/W 0 Receive byte status 0 No byte received 1 Received byte ready 1 TX_BYTE 0 R/W 0 Transmit byte status 0 Byte not transmitted 1 Last byte written to Data Buffer register transmitted 0 ACTIVE 0 R USART 1 transmit/receive active status 0 USART 1 idle 1 USART 1 busy in transmit or receive mode SWRS033H Page 160 of 246 CC1110Fx / CC1111Fx U1UCR (0xFB) - USART 1 UART Control Bit Field Name Reset R/W Description 7 FLUSH 0 R0/ W1 Flush unit. When set to 1, this event will immediately stop the current operation and return the unit to idle state. This bit will be 0 when returning from PM2 and PM3 6 5 FLOW D9 0 0 R/W R/W UART 1 hardware flow control enable. Selects use of hardware flow control with RTS and CTS pins 0 Flow control disabled 1 Flow control enabled UART 1 data bit 9 contents. This value is used when 9 bit transfer is enabled. When parity is disabled the value written to D9 is transmitted as the 9th bit when BIT9=1 If parity is enabled then this bit sets the parity level as follows. 4 3 2 1 0 BIT9 PARITY SPB STOP START 0 0 0 1 0 R/W R/W R/W R/W R/W 0 Even parity 1 Odd parity UART 1 9-bit data enable 0 8 bits transfer 1 9 bits transfer (content of the 9th bit is given by D9 and PARITY.) UART 1 parity enable 0 Parity disabled 1 Parity enabled UART 1 number of stop bits 0 1 stop bit 1 2 stop bits UART 1 stop bit level 0 Low stop bit 1 High stop bit UART 1 start bit level. The polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 Low start bit 1 High start bit U1GCR (0xFC) - USART 1 Generic Control Bit Field Name Reset R/W Description 7 CPOL 0 R/W SPI 1 clock polarity 6 5 4:0 CPHA ORDER BAUD_E[4:0] 0 0 00000 R/W R/W R/W 0 Negative clock polarity (SCK low when idle) 1 Positive clock polarity (SCK high when idle) SPI 1 clock phase 0 Data centered on first edge of SCK period 1 Data centered on second edge of SCK period Bit order for transfers 0 LSB first 1 MSB first Baud rate exponent value. BAUD_E along with BAUD_M decides the UART 1 baud rate and the SPI 1 clock (SCK) frequency SWRS033H Page 161 of 246 CC1110Fx / CC1111Fx U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer Bit Field Name Reset R/W Description 7:0 DATA[7:0] 0x00 R/W USART 1 receive and transmit data buffer. Writing data to U1DBUF places the data into the internal transmit buffer. Reading U1DBUF returns the contents of the receive buffer. U1BAUD (0xFA) - USART 1 Baud Rate Control Bit Field Name Reset R/W Description 7:0 BAUD_M[7:0] 0x00 R/W Baud rate mantissa value. BAUD_M along with BAUD_E decides the UART 1 baud rate and the SPI 1 clock (SCK) frequency 2 12.15 I S The CC1110Fx/CC1111Fx provides an industry 2 2 standard I S interface. The I S interface can be used to transfer digital audio samples between the CC1110Fx/CC1111Fx and an external audio device. Please see Section 12.4.6.6 for details on I/O 2 pin mapping for the I S interface. When the module is in master mode, it drives the SCK 2 and WS lines. When the I S interface is in slave mode, these lines are driven by an external master. The data on the serial data lines is transferred one bit per SCK cycle, most significant bit first. The WS signal selects the channel of the current word transfer (left = 0, right = 1). It also determines the length of each word. There is a transition on the WS line one bit time before the first word is transferred and before the last bit of each word. Figure 42 2 shows the I S signaling. Only a single serial data signal is shown in this figure. The SD signal could be the RX or TX signal depending on the direction of the data. 2 The I S interface can be configured to operate as master or slave and may use mono as well as stereo samples. When mono mode is enabled, the same audio sample will be used for both channels. Both full and half duplex is supported and automatic µ-Law compression and expansion can be used. 2 The I S interface consists of 4 signals: Continuous Serial Clock (SCK) Word Select (WS) Serial Data In (RX) Serial Data Out (TX) SCK WS MSB SD SAMPLE n-1, RIGHT CHANNEL LSB MSB LSB SAMPLE n, LEFT CHANNEL MSB SAMPLE n+1, RIGHT CHANNEL 2 Figure 42: I S Digital Audio Signaling 2 2 12.15.1 Enabling I S 12.15.2 I S Interrupts The I2SCFG0.ENAB bit must be set to 1 to 2 enable the I S transmitter/receiver. However, 2 when I2SCFG0.ENAB is 0, the I S can still be used as a stand-alone µ-Law compression/expansion engine. Refer to Section 12.15.12 on Page 165 for more details about this. The I S has two interrupts: 2 2 I S RX complete interrupt (I2SRX) 2 I S TX complete interrupt (I2STX) 2 The I S interrupt enable bits are found in the I2SCFG0 register. The interrupt flags are SWRS033H Page 162 of 246 CC1110Fx / CC1111Fx located in the I2SSTAT register. The interrupt enables and flags are summarized below. Interrupt enable bits: 2 I S RX: I2SCFG0.RXIEN 2 I S TX: I2SCFG0.TXIEN Interrupt flags: 2 I S RX: I2SSTAT.RXIRQ Notice that the DMA triggers I2SRX and ADC_CH6 share the same DMA trigger number (# 27) in the same way as I2STX and ADC_CH7 share DMA trigger number 28. This means that I2SRX can not be used together with ADC_CH6 and I2STX can not be used together with ADC_CH7. On the CC1111Fx ADC channels 6 and 7 cannot be used since P0_6 and P0_7 I/O pins are not available. Refer to Table 51 on Page 107 for an overview of the DMA triggers. 2 I S TX: I2SSTAT.TXIRQ The TX interrupt flag I2SSTAT.TXIRQ is asserted together with IRCON2.I2STXIF when the internal TX buffer is empty and the 2 I S fetches the new data previously written to the I2SDATH:I2SDATL registers. The TX interrupt flag, I2SSTAT.TXIRQ, is cleared when I2SDATH register is written. An interrupt request is only generated when I2SCFG0.TXIEN and IEN2.I2STXIE are both set to 1. The RX interrupt flag I2SSTAT.RXIRQ is asserted together with TCON.I2SRXIF when the internal RX buffer is full and the contents of the RX buffer is copied to the pair of internal data registers that can be read from the I2SDATH:I2SDATL registers. The RX interrupt flag, I2SSTAT.RXIRQ, is cleared when the I2SDATH register is read. An interrupt request is only generated when I2SCFG0.RXIEN and IEN0.I2SRXIE are both set to 1. Notice that interrupts will also be generated if the corresponding RXIRQ or TXIRQ flags are set from software, given that the interrupts are enabled. 2 The I S shares interrupt vector with USART 1, and the ISR must take this into account if both modules are used. Refer to 10.5 on Page 60 for more details about interrupts. 12.15.4 Underflow/Overflow 2 If the I S attempts to read from the internal TX buffer when it is empty, an underflow condition 2 occurs. The I S will then continue to read from the data in the TX buffer, and I2SSTAT.TXUNF will be asserted. 2 If the I S attempts to write to the internal RX buffer while it is full, an overflow condition occurs. The contents of the RX buffer will be overwritten and the I2SSTAT.RXOVF flag will be asserted. Thus, when debugging an application, software may check for underflow/overflow when an interrupt is generated or when the application completes. The TXUNF / RXOVF flags should be cleared in software. 12.15.5 Writing a Word (TX) When each sample fits into a single byte or µLaw compressed samples (always 8 bits) are written, i.e. µ-Law expansion is enabled (I2SCFG0.ULAWE=1), only the I2SDATH register needs to be written. When each sample is more than 8 bits the low byte must be written to the I2SDATL register before the high byte is written to the I2SDATH register, hence writing the I2SDATH register indicates the completion of the write operation. 2 2 12.15.3 I S DMA Triggers There are two DMA triggers associated with 2 the I S interface, I2SRX and I2STX. The DMA triggers are activated by RX complete and TX complete events, i.e. the same events that can 2 generated the I S interrupt requests. The DMA triggers are not masked by the interrupt enable bits, I2SCFG0.RXIEN and I2SCFG0.TXIEN, hence a DMA channel can be configured to 2 use the I S receive/transmit data registers, I2SDATH:I2SDATL, as source or destination address and let RX and TX complete trigger the DMA. When the I S is configured to send stereo, i.e. I2SCFG0.TXMONO is 0, the I2SSTAT.TXLR flag can be used to determine whether the leftor right-channel sample is to be written to the data registers. 12.15.6 Reading a Word (RX) If each sample fits into a single byte or if µ-Law compression is enabled (I2SCFG0.ULAWC=1), only the I2SDATH register needs to be read. When each sample is more than 8 bits the low byte must be read from the I2SDATL register before the high byte is being read from the SWRS033H Page 163 of 246 CC1110Fx / CC1111Fx I2SDATH register, hence reading from the I2SDATH register indicates the completion of the read operation. division is given by the 15 bit numerator, NUM , and 9-bit denominator, DENOM, as shown in the following formula: 2 When the I S is configured to receive stereo, i.e. I2SCFG0.RXMONO is 0, the I2SSTAT.RXLR flag can be used to determine whether the sample currently in the data registers is a left- or right-channel sample. 12.15.7 Full vs. Half Duplex 2 The I S interface supports full duplex and half duplex operation. In full duplex both the RX and TX lines will be used. Both the I2SCFG0.TXIEN and I2SCFG0.RXIEN interrupt enable bits must be set to 1 if interrupts are used and both DMA triggers I2STX and I2SRX must be used. When half duplex is used only one of the RX and TX lines are typically connected. Only the appropriate interrupt flag should be set and only one of the DMA triggers should be used. 12.15.8 Master Mode 2 The I S is configured as a master device by setting I2SCFG0.MASTER to 1. When the module is in master mode, it drives the SCK and WS lines. 12.15.8.1 Clock Generation 2 When the I S is configured as master, the frequency of the SCK clock signal must be set to match the sample rate. The clock frequency must be set before master mode is enabled. Fclk NUM 2( ) DENOM Fsck where NUM DENOM 3.35 Fclk is the system clock frequency and Fsck is the 2 I S SCK sample clock frequency. The value of the numerator is set in the I2SCLKF2.NUM[14:8]:I2SCLKF1.NUM[7:0] registers and the denominator value is set in I2SCLKF2.DENOM[8]:I2SCLKF0.DENOM[7:0]. Please note that to stay within the timing 2 requirements of the I S specification [7], a minimum value of 3.35 should be used for the (NUM / DENOM) fraction. The fractional divider is made such that most normal sample rates should be supported for most normal word sizes with a 24 MHz system clock frequency (CC1111Fx). Examples of supported configurations for a 24 MHz system clock are given in Table 57. Table 58 shows the configuration values for a 26 MHz system clock 2 frequency. Notice that the generated I S frequency is not exact for the 44.1 kHz, 16 bits word size configuration at 26 MHz. The numbers are calculated using the following formulas, where Fs is the sample rate and W is the word size: Fs SCK is generated by dividing the system clock using a fractional clock divider. The amount of CLKDIV Fsck 2 W Fclk NUM DENOM 4 W Fs Fs (kHz) Word Size (W) CLKDIV I2SCLKF2 I2SCLKF1 I2SCLKF0 Exact 8 8 93.75 0x01 0x77 0x04 Yes 8 16 46.875 0x01 0x77 0x08 Yes 44.1 16 8.503401 0x04 0xE2 0x93 Yes 48 16 7.8125 0x00 0x7D 0x10 Yes Table 57: Example I S Clock Configurations (CC1111Fx, 24 MHz) 2 Fs (kHz) Word Size (W) CLKDIV I2SCLKF2 I2SCLKF1 I2SCLKF0 Exact 8 8 101.5625 0x06 0x59 0x10 Yes 8 16 50.78125 0x06 0x59 0x20 Yes 44.1 16 9.21201 0x8A 0x2F 0x1B No 48 16 8.46354 0x06 0x59 0xC0 Yes Table 58: Example I S Clock Configurations (CC1110Fx, 26 MHz) 2 SWRS033H Page 164 of 246 CC1110Fx / CC1111Fx 12.15.8.2 Word Size 12.15.11 Word Counter The word size must be set before master mode is enabled. The word size is the number of bits used for each sample and can be set to a value between 1 and 33. To set the word size, write word size – 1 to the I2SCFG1.WORDS[4:0] bits. Setting the word 2 size to a value of 17 or more causes the I S to pad each word with 0’s in the least significant bits since the data registers provide maximum 16 bits. This feature allows samples to be sent 2 to an I S device that takes a higher resolution than 16 bits. The I S contains a 10-bit word counter, which is counting transitions on the WS line. The counter can be cleared by triggers or by writing to the I2SWCNT register. When a trigger occurs, or a value is written to I2SWCNT, the current value of the word counter is copied into the I2SSTAT.WCNT[9:8]:I2SWCNT.WCNT[7:0]regi sters and the word counter is cleared. If the size of the received samples exceeds 16 bits, only the 16 most significant bits will be put in the data registers and the remaining low order bits will be discarded. USB SOF: USB Start of Frame. Occurs every ms (CC1111Fx only) 2 Three triggers can be used to copy/clear the word counter. T1_CH0: Timer 1, compare, channel 0 IOC_1: IO pin input transition (P1_3) 12.15.9 Slave Mode 2 The I S is configured as a slave device by setting I2SCFG0.MASTER to 0. When in slave mode the SCK and WS signals are generated 2 by an external I S master and are inputs to the 2 I S interface. 12.15.9.1 Word Size 2 When the I S operates in slave mode, the word size is determined by the master that generates the WS signal. 2 The I S will provide bits from the internal 16-bit buffer until the buffer is empty. If the buffer becomes empty and the master still requests 2 more bits, the I S will send 0’s (low order bits). If more than 16 bits are being received, the low order bits are discarded. 12.15.10 Mono 2 The I S also supports mono audio samples. To receive mono samples, I2SCFG0.RXMONO should be set to 1. Words from the right channel will then not be read into the data registers. This feature is included because some mono devices repeat their audio data in both channels and the left channel is the default mono channel. To send mono samples, I2SCFG0.TXMONO should be set to 1. Each word will then be repeated in both channels before a new word is fetched from the data registers. This is to enable sending a mono audio signal to a stereo audio sink device. Which trigger to use is configured through the TRIGNUM field in the I2SCFG1 register. When 2 the I S is configured not to use any trigger (I2SCFG1.TRIGNUM=0), the word counter can only be copied/cleared from software. The word counter will saturate if it reaches its maximum value. Software should configure the trigger-interval and sample-rate to ensure this never happens. CC1111Fx: The word counter is typically used to calculate the average sample rate over a long period of time (e.g. 1 second) needed by adaptive isochronous USB endpoints. The USB SOF event must then be used as trigger. 12.15.12 µ-Law Compression and Expansion 2 The I S interface can be configured to perform μ-Law compression and expansion. µ-Law compression is enabled by setting the I2SCFG0.ULAWC bit to 1 and µ-Law expansion is enabled by setting the I2SCFG0.ULAWE bit to 1. 2 When the I S interface is enabled, i.e. the I2SCFG0.ENAB bit is 1, and µ-Law expansion is enabled, every byte of μ-Law compressed data written to the I2SDATH register is expanded to a 16-bit sample before being 2 transmitted. When the I S interface is enabled and µ-Law compression is enabled each sample received is compressed to an 8-bit μLaw sample and put in the I2SDATH register. 2 When the I S interface is disabled, i.e. the I2SCFG0.ENAB bit is 0, it can still be used to perform μ-Law compression/expansion for other resources in the system. To perform an expansion, I2SCFG0.ULAWE must be 1 and SWRS033H Page 165 of 246 CC1110Fx / CC1111Fx I2SCFG0.ULAWC must be 0 before writing a byte of compressed data to the I2SDATH register. The expansion takes one clock cycle to perform, and then the result can be read from the I2SDATH:I2SDATL registers. To perform a compression I2SCFG0.ULAWE must be 0 and I2SCFG0.ULAWC must be 1. To start the compression, an un-compressed 16bit sample should be written to the I2SDATH:I2SDATL registers. The compression takes one clock cycle to perform, and then the result can be read from the I2SDATH register. Only one of the flags I2SCFG0.ULAWC and I2SCFG0.ULAWE should be set to 1 when the I2SCFG0.ENAB bit is 0. 2 12.15.13 I S Registers This section describes all the registers used for 2 2 I S control and status. The I S registers reside in XDATA memory space in the region 0xDF40 - 0xDF48. Table 33 on Page 52 gives an overview of register addresses while the tables in this section describe each register. Notice that the reset values for the registers reflect a configuration with 16-bit stereo samples and 2 44.1 kHz sample rate. The I S is not enabled at reset. SWRS033H Page 166 of 246 CC1110Fx / CC1111Fx 2 0xDF40: I2SCFG0 - I S Configuration Register 0 Bit Field Name Reset R/W Description 7 TXIEN 0 R/W Transmit interrupt enable 6 5 4 3 2 1 0 RXIEN ULAWE ULAWC TXMONO RXMONO MASTER ENAB 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled Receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled µ-Law expansion enable 0 Expansion disabled 1 Expansion enabled ENAB=0 Expand data written to I2SDATH ENAB=1 Enable expansion of data to transmit µ-Law compression enable 0 Compression disabled 1 Compression enabled ENAB=0 Compress data written to I2SDATH:I2SDATL ENAB=1 Enable compression of data received TX mono enable 0 Stereo mode 1 Each sample of audio data will be repeated in both channels before a new sample is fetched. This is to enable sending a mono signal to a stereo audio sink device. RX mono enable 0 Stereo mode 1 Data from the right channel will be discarded, i.e. not be read into the data registers. This feature is included because some mono devices repeat their audio data in both channels and left is the default mono channel. Master mode enable 0 Slave (CLK and WS are read from the pads) 1 Master (generate the CLK and WS) 2 I S interface enable 0 Disable (I2S can be used as a µ-Law compression/expansion unit) 1 Enable SWRS033H Page 167 of 246 CC1110Fx / CC1111Fx 2 0xDF41: I2SCFG1 - I S Configuration Register 1 Bit Field Name Reset R/W Description 7:3 WORDS[4:0] 01111 R/W This field gives the word size – 1. The word size is the bit-length of one sample for one channel. Used to generate the WS signal when in master mode. Reset value 01111 corresponds to 16 bit samples. 2:1 0 TRIGNUM[1:0] IOLOC 00 0 R/W R/W Word counter copy / clear trigger 00 No trigger. Counter copied / cleared by writing to the I2SWCNT register 01 USB SOF (CC1111Fx only) 10 IOC_1 (P1_3) 11 T1_CH0 The pin locations for the I2S signals. This bit selects between the two alternative pin mapping alternatives. Refer to Table 50 on Page 92 for an overview of pin locations. 0 Alt. 1 in Table 50 is used 1 Alt. 2 in Table 50 is used Note: If the I2S interface is enabled (I2SCFG0_ENAB=1), the I2S interface will have precedence in cases where other peripherals (except for the debug interface) are configured to be on the same location. This is the case even if the pins are configured to be general purpose I/O pins. 2 0xDF42: I2SDATL - I S Data Low Byte Bit Field Name Reset R/W Description 7:0 I2SDAT[7:0] 0x00 R/W Data register low byte. If this register is not written between two writes to the I2SDATH register, the low byte of the TX register will be cleared. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 2 0xDF43: I2SDATH - I S Data High Byte Bit Field Name Reset R/W Description 7:0 I2SDAT[15:8] 0x00 R/W Data register high byte. When this register is read, I2SSTAT.RXIRQ is de-asserted and the RX buffer is considered empty. When this register is written, I2SSTAT.TXIRQ is de-asserted and the TX buffer is considered full. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 2 0xDF44: I2SWCNT - I S Word Count Register Bit Field Name Reset R/W Description 7:0 WCNT[7:0] 0x00 R/W This register contains the 8 low order bits of the 10-bit internal word counter at the time of the last trigger. If this register is written (any value), the value of the internal word counter is copied into this register and I2SSTAT.WCNT[9:8], and the internal word counter is cleared. Refer to Section 12.15.11 for details about how to use this register. SWRS033H Page 168 of 246 CC1110Fx / CC1111Fx 2 0xDF45: I2SSTAT - I S Status Register Bit Field Name Reset R/W Description 7 TXUNF 0 R/W TX buffer underflow. This bit must be cleared by software 6 RXOVF 0 R/W Rx buffer overflow. This bit must be cleared by software 5 TXLR 0 R 0 Left channel should be placed in transmit buffer 1 Right channel should be placed in transmit buffer 0 Left channel currently in receive buffer 1 Right channel currently in receive buffer 4 3 2 1:0 RXLR TXIRQ RXIRQ WCNT[9:8] 0 0 0 00 R R/W1 H0 R/W1 H0 R TX interrupt flag. This bit is cleared by hardware when the I2SDATH register is written. 0 Interrupt not pending 1 Interrupt pending RX Interrupt flag. This is cleared by hardware when the I2SDATH register is read. 0 Interrupt not pending 1 Interrupt pending Upper 2 bits of the 10-bit internal word counter at the time of the last trigger 2 0xDF46: I2SCLKF0 - I S Clock Configuration Register 0 Bit Field Name Reset R/W Description 7:0 DENOM[7:0] 0x93 R/W The clock division denominator low bits 2 0xDF47: I2SCLKF1 - I S Clock Configuration Register 1 Bit Field Name Reset R/W Description 7:0 NUM[7:0] 0xE2 R/W Clock division numerator low bits 2 0xDF48: I2SCLKF2 - I S Clock Configuration Register 2 Bit Field Name Reset R/W Description 7 DENOM[8] 0 R/W Clock division denominator high bits 6:0 NUM[14:8] 0x04 R/W Clock division numerator high bits SWRS033H Page 169 of 246 CC1110Fx / CC1111Fx 12.16 USB Controller Appropriate response to USB interrupts and loading/unloading of packets into/from endpoint FIFOs is the responsibility of the firmware. The firmware must be able to reply correctly to all standard requests from the USB host and work according to the protocol implemented in the driver on the PC. Note: The USB controller is only available on the CC1111Fx. The CC1111Fx contains a Full-Speed USB 2.0 compatible USB controller for serial communication with a PC or other equipment with USB host functionality. The USB Controller has the following features: Full-Speed operation (up to 12 Mbps) Note: This section will focus on describing the functionality of the USB controller, and it is assumed that the reader has a good understanding of USB and is familiar with the terms and concepts used. Refer to the Universal Serial Bus Specification for details [6]. 5 endpoints (in addition to endpoint 0) that can be used as IN, OUT, or IN/OUT and can be configured as bulk/interrupt or isochronous. 1 KB SRAM FIFO available for storing USB packets Standard USB nomenclature is used regarding IN and OUT. I.e., IN is always into the host (PC) and OUT is out of the host (into the CC1111Fx) Endpoints supporting packet sizes from 8 – 512 bytes Support for double buffering of USB packets Figure 43 shows a block diagram of the USB controller. The USB PHY is the physical interface with input and output drivers. The USB SIE is the Serial Interface Engine which controls the packet transfer to/from the endpoints. The USB controller is connected to the rest of the system through the Memory Arbiter. The USB controller monitors the USB bus for relevant activity and handles packet transfers. The CC1111Fx will always operate as a slave on the USB bus and responds only on requests from the host (a packet can only be sent (or received) when the USB host sends a request in the form of a token). USB Controller EP0 EP1 DP EP2 USB PHY USB SIE Memory Arbiter EP3 DM EP4 EP5 1 KB SRAM (FIFOs) Figure 43: USB Controller Block Diagram 12.16.1 48 MHz Clock A 48 MHz external crystal must be used for the USB Controller to operate correctly. This 48 MHz clock is divided by two internally to generate a maximum system clock frequency of 24 MHz. It is important that the crystal oscillator is stable before the USB Controller is SWRS033H Page 170 of 246 CC1110Fx / CC1111Fx accessed. See 12.1.5.1 for details on how to set up the crystal oscillator. SLEEP.USB_EN controller. 12.16.2 USB Enable 12.16.3 USB Interrupts The USB Controller must be enabled before it is used. This is performed by setting the SLEEP.USB_EN bit to 1. Setting There are 3 interrupt flag registers with associated interrupt enable mask registers. to 0 will reset the USB Interrupt Flag Description Associated Interrupt Enable Mask Register USBCIF Contains flags for common USB interrupts USBCIE USBIIF Contains interrupt flags for endpoint 0 and all the IN endpoints USBIIE USBOIF Contains interrupt flags for all OUT endpoints USBOIE Note: All interrupts except SOF and suspend are initially enabled after reset Table 59: USB Interrupt Flags Interrupt Enable Mask Registers In addition to the interrupt flags in the registers shown in Table 59, there are two CPU interrupt flags associated with the USB controller; IRCON2.USBIF and IRCON.P0IF. For an interrupt request to be generated, IEN1.P0IE and/or IEN2.USBIE must be set to 1 together with the desired interrupt enable bits from the USBCIE, USBIIE, and USBOIE registers. When an interrupt request has been generated, the CPU will start executing the ISR if there are no higher priority interrupts pending. The USB controller uses interrupt #6 for USB interrupts. This interrupt number is shared with Port 2 inputs, hence the interrupt routine must also handle Port 2 interrupts if they are enabled. The interrupt routine should read all the interrupt flag registers and take action depending on the status of the flags. The interrupt flag registers will be cleared when they are read and the status of the individual interrupt flags should therefore be saved in memory (typically in a local variable on the stack) to allow them to be accessed multiple times. At the end of the ISR, after the interrupt flags have been read, the interrupt flags should be cleared to allow for new USB/P2 interrupts to be detected. The port 2 interrupt status flags in the P2IFG register should be cleared prior to clearing IRCON2.P2IF (see Section 10.5.2). Refer to Table 39 and Table 40 for a complete list of interrupts, and Section 10.5 for more details about interrupts. 12.16.3.1 USB Resume Interrupt P0_7 does not exist on the CC1111Fx, but the corresponding interrupt is used for USB resume interrupt. This means that to be able to wake up the CC1111Fx from PM1/suspend when resume signaling has been detected on the USB bus, IEN1.P0IE must be set to 1 together with PICTL.P0IENH. PICTL.P0ICON must be 0 to enable interrupts on rising edge. The P0 ISR should check the P0IFG.USB_RESUME, and resume if this bit is set to 1. If PM1 is entered from within an ISR due to a suspend interrupt, it is important that the priority of the P0 interrupt is set higher than the priority of the interrupt from which PM1 was entered. See Section 12.16.9 for more details about suspend and resume. 12.16.4 Endpoint 0 Endpoint 0 (EP0) is a bi-directional control endpoint and during the enumeration phase all communication is performed across this endpoint. Before the USBADDR register has been set to a value other than 0, the USB controller will only be able to communicate through endpoint 0. Setting the USBADDR register to a value between 1 and 127 will bring the USB function out of the Default state in the enumeration phase and into the Address state. All configured endpoints will then be available for the application. The EP0 FIFO is only used as either IN or OUT and double buffering is not provided for endpoint 0. The maximum packet size for endpoint 0 is fixed at 32 bytes. SWRS033H Page 171 of 246 CC1110Fx / CC1111Fx Endpoint 0 is controlled through the USBCS0 register by setting the USBINDEX register to 0. The USBCNT0 register contains the number of bytes received. 12.16.5 Endpoint 0 Interrupts The following events may generate an EP0 interrupt request: A data packet has been received (USBCS0.OUTPKT_RDY=1) A data packet that was loaded into the EP0 FIFO has been sent to the USB host (USBCS0.INPKT_RDY should be set to 1 when a new packet is ready to be transferred. This bit will be cleared by HW when the data packet has been sent) An IN transaction has been completed (the interrupt is generated during the Status stage of the transaction) A STALL has been (USBCS0.SENT_STALL=1) sent A control transfer ends due to a premature end of control transfer (USBCS0.SETUP_END=1) Any of these events will cause the USBIIF.EP0IF to be asserted regardless of the status of the EP0 interrupt mask bit USBIIE.EP0IE. If the EP0 interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.USBIF will also be asserted. An interrupt request is only generated if IEN2.USBIE and USBIIE.EP0IE are both set to 1. 12.16.5.1 Error Conditions When a protocol error occurs, the USB controller sends a STALL handshake. The USBCS0.SENT_STALL bit is asserted and an interrupt request is generated if the endpoint 0 interrupt is properly enabled. A protocol error can be any of the following: An OUT token is received after USBCS0.DATA_END has been set to complete the OUT Data stage (the host tries to send more data than expected) An IN token is received after USBCS0.DATA_END has been set to complete the IN Data stage (the host tries to receive more data than expected) The USB host tries to send a packet that exceeds the maximum packet size during the OUT Data stage The size of the DATA1 packet received during the Status stage is not 0 The firmware can also terminate the current transaction by setting the USBCS0.SEND_STALL bit to 1. The USB controller will then send a STALL handshake in response to the next requests from the USB host. If an EP0 interrupt is caused by the assertion of the USBCS0.SENT_STALL bit, this bit should be de-asserted and firmware should consider the transfer as aborted (free memory buffers etc.). If EP0 receives an unexpected token during the Data stage, the USBCS0.SETUP_END bit will be asserted and an EP0 interrupt will be generated (if enabled properly). EP0 will then switch to the IDLE state. Firmware should then set the USBCS0.CLR_SETUP_END bit to 1 and abort the current transfer. If USBCS0.OUTPKT_RDY is asserted, this indicates that another Setup Packet has been received that firmware should process. 12.16.5.2 SETUP Transactions (IDLE State) The control transfer consists of 2 - 3 stages of transactions (Setup - Data - Status or Setup Status). The first transaction is a Setup transaction. A successful Setup transaction comprises three sequential packets (a token packet, a data packet, and a handshake packet), where the data field (payload) of the data packet is exactly 8 bytes long and are referred to as the Setup Packet. In the Setup stage of a control transfer, EP0 will be in the IDLE state. The USB controller will reject the data packet if the Setup Packet is not 8 bytes. Also, the USB controller will examine the contents of the Setup Packet to determine whether or not there is a Data stage in the control transfer. If there is a Data stage, EP0 will switch state to TX (IN transaction) or RX (OUT transaction) when the USBCS0.CLR_OUTPKT_RDY bit is set to 1 (if USBCS0.DATA_END=0). When a packet is received, the USBCS0.OUTPKT_RDY bit will be asserted and an interrupt request is generated (EP0 interrupt) if the interrupt has been enabled. Firmware should perform the following when a Setup Packet has been received: SWRS033H Page 172 of 246 CC1110Fx / CC1111Fx 1. Unload the Setup Packet from the EP0 FIFO is working, but temporarily has no data to send. 2. Examine the contents and perform the appropriate operations 12.16.5.4 OUT Transactions (RX state) 3. Set the USBCS0.CLR_OUTPKT_RDY bit to 1. This denotes the end of the Setup stage. If the control transfer has no Data stage, the USBCS0.DATA_END bit must also be set. If there is no Data stage, the USB Controller will stay in the IDLE state. 12.16.5.3 IN Transactions (TX state) If the control transfer requires data to be sent to the host, the Setup stage will be followed by one or more IN transactions in the Data stage. In this case the USB controller will be in TX state and only accept IN tokens. A successful IN transaction comprises two or three sequential packets (a token packet, a data 19 packet, and a handshake packet ). If more than 32 bytes (maximum packet size) is to be sent, the data must be split into a number of 32 byte packets followed by a residual packet. If the number of bytes to send is a multiple of 32, the residual packet will be a zero length data packet, hence a packet size less than 32 bytes denotes the end of the transfer. Firmware should load the EP0 FIFO with the first data packet and set the USBCS0.INPKT_RDY bit as soon as possible after the USBCS0.CLR_OUTPKT_RDY bit has been set. The USBCS0.INPKT_RDY will be cleared and an EP0 interrupt will be generated when the data packet has been sent. Firmware might then load more data packets as necessary. An EP0 interrupt will be generated for each packet sent. Firmware must set USBCS0.DATA_END in addition to USBCS0.INPKT_RDY when the last data packet has been loaded. This will start the Status stage of the control transfer. EP0 will switch to the IDLE state when the Status stage has completed. The Status stage may fail if the USBCS0.SEND_STALL bit is set to 1. The USBCS0.SENT_STALL bit will then be asserted and an EP0 interrupt will be generated as explained in Section 12.16.5.1. If USBCS0.INPKT_RDY is not set when receiving an IN token, the USB Controller will reply with a NAK to indicate that the endpoint If the control transfer requires data to be received from the host, the Setup stage will be followed by one or more OUT transactions in the Data stage. In this case the USB controller will be in RX state and only accept OUT tokens. A successful OUT transaction comprises two or three sequential packets (a token packet, a data packet, and a handshake 20 packet ). If more than 32 bytes (maximum packet size) is to be received, the data must be split into a number of 32 byte packets followed by a residual packet. If the number of bytes to receive is a multiple of 32, the residual packet will be a zero length data packet, hence a data packet with payload less than 32 bytes denotes the end of the transfer. The USBCS0.OUTPKT_RDY bit will be set and an EP0 interrupt will be generated when a data packet has been received. The firmware should set USBCS0.CLR_OUTPKT_RDY when the data packet has been unloaded from the EP0 FIFO. When the last data packet has been received (packet size less than 32 bytes) firmware should also set the USBCS0.DATA_END bit. This will start the Status stage of the control transfer. The size of the data packet is kept in the USBCNT0 registers. Note that this value is only valid when USBCS0.OUTPKT_RDY=1. EP0 will switch to the IDLE state when the Status stage has completed. The Status stage may fail if the DATA1 packet received is not a zero length data packet or if the USBCS0.SEND_STALL bit is set to 1. The USBCS0.SENT_STALL bit will then be asserted and an EP0 interrupt will be generated as explained in Section 12.16.5.1. 12.16.6 Endpoints 1 - 5 Each endpoint can be used as an IN only, an OUT only, or IN/OUT. For an IN/OUT endpoint there are basically two endpoints, an IN endpoint and an OUT endpoint associated with the endpoint number. Configuration and control of IN endpoints is performed through the USBCSIL and USBCSIH registers. The USBCSOL and USBCSOH registers are used to 20 19 For isochronous transfers there would not be a handshake packet from the host SWRS033H For isochronous transfers there would not be a handshake packet from the CC1111Fx Page 173 of 246 CC1110Fx / CC1111Fx configure and control OUT endpoints. Each IN and OUT endpoint can be configured as either Isochronous (USBCSIH.ISO=1 and/or USBCSOH.ISO=1) or Bulk/Interrupt (USBCSIH.ISO=0 and/or USBCSOH.ISO=0) endpoints. Bulk and Interrupt endpoints are handled identically by the USB controller but will have different properties from a firmware perspective. The USBINDEX register must have the value of the endpoint number before the Indexed Endpoint Registers are accessed (see Table 35 on Page 53). 12.16.6.1 FIFO Management Each endpoint has a certain number of FIFO memory bytes available for incoming and outgoing data packets. Table 60 shows the FIFO size for endpoints 1 - 5. It is the firmware that is responsible for setting the USBMAXI and USBMAXO registers correctly for each endpoint to prevent data from being overwritten. the top of the endpoint memory region while the OUT FIFO grows up from the bottom of the endpoint memory region. When the IN or OUT endpoint of an endpoint number use double buffering, the sum of USBMAXI and USBMAXO must not exceed half the FIFO size for the endpoint. Figure 44 b) illustrates the IN and OUT FIFO memory for an endpoint that uses double buffering. Notice that the second OUT buffer starts from the middle of the memory region and grows upwards. The second IN buffer also starts from the middle of the memory region but grows downwards. To configure an endpoint as IN only, set USBMAXO to 0 and to configure an endpoint as OUT only, set USBMAXI to 0. For unused endpoints, both USBMAXO and USBMAXI should be set to 0. When both the IN and the OUT endpoint of an endpoint number do not use double buffering, the sum of USBMAXI and USBMAXO must not exceed the FIFO size for the endpoint. Figure 44 a) shows how the IN and OUT FIFO memory for an endpoint is organized with single buffering. The IN FIFO grows down from EP Number FIFO Size (in bytes) 1 32 2 64 3 128 4 256 5 512 Table 60: FIFO Sizes for EP{1 - 5} 0 0 IN FIFO (Buffer 1) IN FIFO USBMAXI - 1 USBMAXI - 1 USBMAX0 - 1 0 0 OUT FIFO (Buffer 2) IN FIFO (Buffer 2) USBMAXI - 1 USBMAX0 - 1 USBMAX0 - 1 OUT FIFO 0 0 OUT FIFO (Buffer 1) b) a) Figure 44: IN/OUT FIFOs, a) Single Buffering b) Double Buffering 12.16.6.2 Double Buffering To enable faster transfer and reduce the need for retransmissions, CC1111Fx implements double buffering, allowing two packets to be buffered in the FIFO in each direction. This is highly recommended for isochronous endpoints, which are expected to transfer one data packet every USB frame without any retransmission. For isochronous endpoint one data packet will be sent/received every USB frame. However, the data packet may be sent/received at any time during the USB frame period and there is a chance that two SWRS033H Page 174 of 246 CC1110Fx / CC1111Fx data packets may be sent/received at a few micro seconds interval. For isochronous endpoints, an incoming packet will be lost if there is no buffer available and a zero length data packet will be sent if there is no data packet ready for transmission when the USB host requests data. Double buffering is not as critical for bulk and interrupt endpoints as it is for isochronous endpoint since packets will not be lost. Double buffering, however, may improve the effective data rate for bulk endpoints. To enable double buffering for an IN endpoint, USBCSIH.IN_DBL_BUF must be set to 1. To enable double buffering for an OUT endpoint, set USBCSOH.OUT_DBL_BUF to 1. 12.16.6.3 FIFO Access The endpoint FIFOs are accessed by reading and writing to the registers in Table 36 on Page 53. Writing to a register causes the byte written to be inserted into the IN FIFO. Reading a register causes the next byte in the OUT FIFO to be extracted and the value of this byte to be returned. When a data packet has been written to an IN FIFO, the USBCSIL.INPKT_RDY bit must be set to 1. If double buffering is enabled, the USBCSIL.INPKT_RDY bit will be cleared immediately after it has been written and another data packet can be loaded. This will not generate an IN endpoint interrupt, since an interrupt is only generated when a packet has been sent. When double buffering is used firmware should check the status of the USBCSIL.PKT_PRESENT bit before writing to the IN FIFO. If this bit is 0, two data packets can be written. Double buffered isochronous endpoints should only need to load two packets the first time the IN FIFO is loaded. After that, one packet is loaded for every USB frame. To send a zero length data packet, USBCSIL.INPKT_RDY should be set to 1 without loading a data packet into the IN FIFO. A data packet can be read from the OUT FIFO when the USBCSOL.OUTPKT_RDY bit is 1. An interrupt will be generated when this occurs, if enabled. The size of the data packet is kept in the USBCNTH:USBCNTL registers. Note that this value is only valid when USBCSOL.OUTPKT_RDY=1. When the data packet has been read from the OUT FIFO, the USBCSOL.OUTPKT_RDY bit must be cleared. If double buffering is enabled there may be two data packets in the FIFO. If another data packet is ready when the USBCSOL.OUTPKT_RDY bit is cleared the USBCSOL.OUTPKT_RDY bit will be asserted immediately and an interrupt will be generated (if enabled) to signal that a new data packet has been received. The USBCSOL.FIFO_FULL bit will be set when there are two data packets in the OUT FIFO. The AutoClear feature is supported for OUT endpoints. When enabled, the USBCSOL.OUTPKT_RDY bit is cleared automatically when USBMAXO bytes have been read from the OUT FIFO. The AutoClear feature is enabled by setting USBCSOH.AUTOCLEAR=1. The AutoClear feature can be used to reduce the time the data packet occupies the OUT FIFO buffer and is typically used for bulk endpoints. A complementary AutoSet feature is supported for IN endpoints. When enabled, the USBCSIL.INPKT_RDY bit is set automatically when USBMAXI bytes have been written to the IN FIFO. The AutoSet feature is enabled by setting USBCSIH.AUTOSET=1. The AutoSet feature can reduce the overall time it takes to send a data packet and is typically used for bulk endpoints. 12.16.6.4 Endpoint 1 - 5 Interrupts The following events may generate an IN EPx interrupt request (x indicates the endpoint number): A data packet that was loaded into the IN FIFO has been sent to the USB host (USBCSIL.INPKT_RDY should be set to 1 when a new packet is ready to be transferred. This bit will be cleared by HW when the data packet has been sent) A STALL has been sent (USBCSIL.SENT_STALL=1). Only Bulk/Interrupt endpoints can be stalled The IN FIFO is flushed due to the USBCSIH.FLUSH_PACKET bit being set to 1 Any of these events will cause USBIIF.INEPxIF to be asserted regardless of the status of the IN EPx interrupt mask bit USBIIE.INEPxIE. If the IN EPx interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.USBIF will also be asserted. An interrupt request is only generated if IEN2.USBIE and USBIIE.INEPxIE are both set to 1. The x in the register names refer to the endpoint number 1 - 5) SWRS033H Page 175 of 246 CC1110Fx / CC1111Fx The following events may generate an OUT EPx interrupt request: A data packet has been received (USBCSOL.OUTPKT_RDY=1) A STALL has been sent (USBCSIL.SENT_STALL=1). Only Bulk/Interrupt endpoints can be stalled Any of these events will cause USBOIF.OUTEPxIF to be asserted regardless of the status of the OUT EPx interrupt mask bit USBOIE.OUTEPxIE. If the OUT EPx interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.USBIF will also be asserted. An interrupt request is only generated if IEN2.USBIE and USBOIE.OUTEPxIE are both set to 1. 12.16.6.5 Bulk/Interrupt IN Endpoint Interrupt IN transfers occur at regular intervals while bulk IN transfers utilize available bandwidth not allocated to isochronous, interrupt, or control transfers. Interrupt IN endpoints may set the USBCSIH.FORCE_DATA_TOG bit. When this bit is set the data toggle bit is continuously toggled regardless of whether an ACK was received or not. This feature is typically used by interrupt IN endpoints that are used to communicate rate feedback for Isochronous endpoints. A Bulk/Interrupt IN endpoint can be stalled by setting the USBCSIL.SEND_STALL bit to 1. When the endpoint is stalled, the USB controller will respond with a STALL handshake to IN tokens. The USBCSIL.SENT_STALL bit will then be set and an interrupt will be generated, if enabled. A bulk transfer longer than the maximum packet size is performed by splitting the transfer into a number of data packets of maximum size followed by a smaller data packet containing the remaining bytes. If the transfer length is a multiple of the maximum packet size, a zero length data packet is sent last. This means that a packet with a size less than the maximum packet size denotes the end of the transfer. The AutoSet feature can be useful in this case, since many data packets will be of maximum size. 12.16.6.6 Isochronous IN Endpoint An Isochronous IN endpoint is used to transfer periodic data from the USB controller to the host (one data packet every USB frame). If there is no data packet loaded in the IN FIFO when the USB host requests data, the USB controller sends a zero length data packet and the USBCSIL.UNDERRUN bit will be asserted. Double buffering requires that a data packet is loaded into the IN FIFO during the frame preceding the frame where it should be sent. If the first data packet is loaded before an IN token is received, the data packet will be sent during the same frame as it was loaded and hence violate the double buffering strategy. Thus, when double buffering is used, the USBPOW.ISO_WAIT_SOF bit should be set to 1 to avoid this. Setting this bit will ensure that a loaded data packet is not sent until the next SOF token has been received. The AutoSet feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame. 12.16.6.7 Bulk/Interrupt OUT Endpoint Interrupt OUT transfers occur at regular intervals while bulk OUT transfers utilize available bandwidth not allocated to isochronous, interrupt, or control transfers. A Bulk/Interrupt OUT endpoint can be stalled by setting the USBCSOL.SEND_STALL bit to 1. When the endpoint is stalled, the USB controller will respond with a STALL handshake when the host is done sending the data packet. The data packet is discarded and is not placed in the OUT FIFO. The USB controller will assert the USBCSOL.SENT_STALL bit when the STALL handshake is sent and generate an interrupt request if the OUT endpoint interrupt is enabled. As the AutoSet feature is useful for bulk IN endpoints, the AutoClear feature is useful for OUT endpoints since many packets will be of maximum size. 12.16.6.8 Isochronous OUT Endpoint An Isochronous OUT endpoint is used to transfer periodic data from the host to the USB controller (one data packet every USB frame). If there is no buffer available when a data packet is being received, the USBCSOL.OVERRUN bit will be asserted and the packet data will be lost. Firmware can reduce the chance for this to happen by using double buffering and use DMA to effectively unload data packets. SWRS033H Page 176 of 246 CC1110Fx / CC1111Fx An isochronous data packet in the OUT FIFO may have bit errors. The hardware will detect this condition and set USBCSOL.DATA_ERROR. Firmware should therefore always check this bit when unloading a data packet. The word size can be byte (8 bits) or word (16 bits). When word size transfer is used the ENDIAN register must be set correctly (see Section 12.5.7). The ENDIAN.USBRLE bit selects whether a word is read as little or big endian from the OUT FIFOs and the ENDIAN.USBWLE bit selects whether a word is written as little or big endian to the IN FIFOs. Writing and reading words for the different settings is shown in The AutoClear feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame. Figure 45 and Figure 46 respectively. Notice that the setting for these bits will be used for all endpoints. Consequently, it is not possible to have multiple DMA channels active at once that use different endianness. The ENDIAN register must be configured to use big endian for both read and write for a word size transfer to produce the same result as a byte size transfer of an even number of bytes. Word size transfers are slightly more efficient than byte transfers. 12.16.7 DMA DMA should be used to fill the IN endpoint FIFOs and empty the OUT endpoint FIFOs. Using DMA will improve the read/write performance significantly compared to using the 8051 CPU. It is therefore highly recommended to use DMA unless timing is not critical or only a few bytes are to be transferred. There are no DMA triggers for the USB controller, meaning that DMA transfers must be triggered by firmware. MSB Refer to Section regarding DMA. 12.5 for more details LSB ENDIAN.USBWLE = 0 To Host SYNC PID MSB LSB MSB LSB MSB LSB MSB LSB CRC16 EOP LSB MSB CRC16 EOP ENDIAN.USBWLE = 1 SYNC To Host PID LSB MSB LSB MSB Figure 45: Writing Big/Little Endian SYNC PID ENDIAN.USBRLE = 0 B0 B1 B0 B1 B2 B3 Bn-1 Bn CRC16 EOP From Host ENDIAN.USBRLE = 1 B1 B0 Figure 46: Reading Big/Little Endian SWRS033H Page 177 of 246 CC1110Fx / CC1111Fx 12.16.8 USB Reset When reset signaling is detected on the bus, the USBCIF.RSTIF flag will be asserted. If USBCIE.RSTIE is enabled, IRCON2.USBIF will also be asserted and an interrupt request is generated if IEN2.USBIE=1. The firmware should take appropriate action when a USB reset occurs. A USB reset should place the device in the Default state where it will only respond to address 0 (the default address). One or more resets will normally take place during the enumeration phase right after the USB cable is connected. The following actions are performed by the USB controller when a USB reset occurs: USBADDR is set to 0 USBINDEX is set to 0 All endpoint FIFOs are flushed USBCS0, USBCSIL, USBCSIH, USBCSOL, USBCSOH are cleared. All interrupts, except SOF and suspend, are enabled An interrupt request is generated (if IEN2.USBIE=1 and USBCIE.RSTIE=1) Firmware should close all pipes and wait for a new enumeration phase when USB reset is detected. 12.16.9 Suspend and Resume The USB controller will assert USBCIF.SUSPENDIF and enter suspend mode when the USB bus has been continuously idle for 3 ms, provided that USBPOW.SUSPEND_EN=1. IRCON2.USBIF will be asserted if USBCIE.SUSPENDIE is enabled, and an interrupt request is generated if IEN2.USBIE=1. While in suspend mode, only limited current can be sourced from the USB bus. See the USB 2.0 Specification [6] for details about this. To be able to meet the suspend-current requirement, the CC1111Fx should be taken down to PM1 when suspend is detected. The CC1111Fx should not enter PM2 or PM3 since this will reset the USB controller. Any valid non-idle signaling on the USB bus will cause the USBCIF.RESUMEIF to be asserted and an interrupt request to be generated and wake up the system if the USB resume interrupt is configured correctly. Refer to 12.16.3.1 for details about how to set up the USB resume interrupt. Any valid non-idle signaling on the USB bus will cause the USBCIF.RESUMEIF to be asserted and an interrupt request to be generated and wake up the system if the USB resume interrupt is configured correctly. Refer to 12.16.3.1 for details about how to set up the USB resume interrupt. When the system wakes up (enters active mode) from suspend, no USB registers must be accessed before the 48 MHZ crystal oscillator has stabilized. A USB reset will also wake up the system from suspend. A USB resume interrupt request will be generated, if the interrupt is configured as described in 12.16.3.1, but the USBCIF.RSTIF interrupt flag will be set instead of the USBCIF.RESUMEIF interrupt flag. 12.16.10 Remote Wakeup The USB controller can resume from suspend by signaling resume to the USB hub. Resume is performed by setting USBPOW.RESUME to 1 for approximately 10 ms. According to the USB 2.0 Specification [6], the resume signaling must be present for at least 1 ms and no more than 15 ms. It is, however, recommended to keep the resume signaling for approximately 10 ms. Notice that support for remote wakeup must be declared in the USB descriptor, and that the USB host must grant the device the privilege to perform remote wakeup (through a SET_FEATURE request). 12.16.11 USB Registers This section describes all USB registers used for control and status for the USB. The USB registers reside in XDATA memory space in the region 0xDE00 - 0xDE3F. These registers can be divided into three groups: The Common USB Registers, the Indexed Endpoint Registers, and the Endpoint FIFO Registers. Table 34, Table 35, and Table 36 give an overview of the registers in the three groups respectively, while the remaining of this section will describe each register in detail. The Indexed Endpoint Registers represent the currently selected endpoint. The USBINDEX register is used to select the endpoint. Notice that the upper register addresses 0xDE2C - 0xDE3F are reserved. SWRS033H Page 178 of 246 CC1110Fx / CC1111Fx 0xDE00: USBADDR - Function Address Bit Field Name Reset R/W Description 7 UPDATE 0 R This bit is set when the USBADDR register is written and cleared when the address becomes effective. 6:0 USBADDR[6:0] 0000000 R/W Device address 0xDE01: USBPOW - Power/Control Register Bit Field Name Reset R/W Description 7 ISO_WAIT_SOF 0 R/W When this bit is set to 1, the USB controller will send zero length data packets from the time INPKT_RDY is asserted and until the first SOF token has been received. This only applies to isochronous endpoints. 6:4 - R0 Not used 3 RST 0 R During reset signaling, this bit is set to1 2 RESUME 0 R/W Drive resume signaling for remote wakeup. According to the USB Specification the duration of driving resume must be at least 1 ms and no more than 15 ms. It is recommended to keep this bit set for approximately 10 ms. 1 SUSPEND 0 R Suspend mode entered. This bit will only be used when SUSPEND_EN=1. Reading the USBCIF register or asserting RESUME will clear this bit. 0 SUSPEND_EN 0 R/W Suspend Enable. When this bit is set to 1, suspend mode will be entered when USB bus has been idle for 3 ms. 0xDE02: USBIIF - IN Endpoints and EP0 Interrupt Flags Bit Field Name 7:6 Reset R/W Description 00 R0 Reserved 5 INEP5IF 0 R H0 Interrupt flag for IN endpoint 5. Cleared by HW when read 4 INEP4IF 0 R H0 Interrupt flag for IN endpoint 4. Cleared by HW when read 3 INEP3IF 0 R H0 Interrupt flag for IN endpoint 3. Cleared by HW when read 2 INEP2IF 0 R H0 Interrupt flag for IN endpoint 2. Cleared by HW when read 1 INEP1IF 0 R H0 Interrupt flag for IN endpoint 1. Cleared by HW when read 0 EP0IF 0 R H0 Interrupt flag for endpoint 0. Cleared by HW when read 0xDE04: USBOIF - Out Endpoints Interrupt Flags Bit Field Name 7:6 Reset R/W Description 00 R0 Reserved 5 OUTEP5IF 0 R H0 Interrupt flag for OUT endpoint 5. Cleared by HW when read 4 OUTEP4IF 0 R H0 Interrupt flag for OUT endpoint 4. Cleared by HW when read 3 OUTEP3IF 0 R H0 Interrupt flag for OUT endpoint 3. Cleared by HW when read 2 OUTEP2IF 0 R H0 Interrupt flag for OUT endpoint 2. Cleared by HW when read 1 OUTEP1IF 0 R H0 Interrupt flag for OUT endpoint 1. Cleared by HW when read - R0 Not used 0 SWRS033H Page 179 of 246 CC1110Fx / CC1111Fx 0xDE06: USBCIF - Common USB Interrupt Flags Bit Field Name 7:4 Reset R/W Description - R0 Not used 3 SOFIF 0 R H0 Start-Of-Frame interrupt flag. Cleared by HW when read 2 RSTIF 0 R H0 Reset interrupt flag. Cleared by HW when read 1 RESUMEIF 0 R H0 Resume interrupt flag. Cleared by HW when read 0 SUSPENDIF 0 R H0 Suspend interrupt flag. Cleared by HW when read 0xDE07: USBIIE - IN Endpoints and EP0 Interrupt Enable Mask Bit Field Name 7:6 5 4 3 2 1 0 INEP5IE INEP4IE INEP3IE INEP2IE INEP1IE EP0IE Reset R/W Description 00 R/W Reserved. Always write 00 1 R/W IN endpoint 5 interrupt enable 1 1 1 1 1 R/W R/W R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled IN endpoint 4 interrupt enable 0 Interrupt disabled 1 Interrupt enabled IN endpoint 3 interrupt enable 0 Interrupt disabled 1 Interrupt enabled IN endpoint 2 interrupt enable 0 Interrupt disabled 1 Interrupt enabled IN endpoint 1 interrupt enable 0 Interrupt disabled 1 Interrupt enabled Endpoint 0 interrupt enable 0 Interrupt disabled 1 Interrupt enabled SWRS033H Page 180 of 246 CC1110Fx / CC1111Fx 0xDE09: USBOIE - Out Endpoints Interrupt Enable Mask Bit Field Name 7:6 5 4 3 2 1 OUTEP5IE OUTEP4IE OUTEP3IE OUTEP2IE OUTEP1IE 0 Reset R/W Description 00 R/W Reserved. Always write 00 1 R/W OUT endpoint 5 interrupt enable 1 1 1 1 - R/W R/W R/W R/W R0 0 Interrupt disabled 1 Interrupt enabled OUT endpoint 4 interrupt enable 0 Interrupt disabled 1 Interrupt enabled OUT endpoint 3 interrupt enable 0 Interrupt disabled 1 Interrupt enabled OUT endpoint 2 interrupt enable 0 Interrupt disabled 1 Interrupt enabled OUT endpoint 1 interrupt enable 0 Interrupt disabled 1 Interrupt enabled Not used 0xDE0B: USBCIE - Common USB Interrupt Enable Mask Bit Field Name 7:4 3 2 1 0 SOFIE RSTIE RESUMEIE SUSPENDIE Reset R/W Description - R0 Not used 0 R/W Start-Of-Frame interrupt enable 1 1 0 R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled Reset interrupt enable 0 Interrupt disabled 1 Interrupt enabled Resume interrupt enable 0 Interrupt disabled 1 Interrupt enabled Suspend interrupt enable 0 Interrupt disabled 1 Interrupt enabled 0xDE0C: USBFRML - Current Frame Number (Low byte) Bit Field Name Reset R/W Description 7:0 FRAME[7:0] 0x00 R Low byte of 11-bit frame number SWRS033H Page 181 of 246 CC1110Fx / CC1111Fx 0xDE0D: USBFRMH - Current Frame Number (High byte) Bit Field Name 7:3 2:0 FRAME[10:8] Reset R/W Description - R0 Not used 000 R 3 MSB of 11-bit frame number 0xDE0E: USBINDEX - Current Endpoint Index Register Bit Field Name 7:4 3:0 USBINDEX[3:0] Reset R/W Description - R0 Not used 0000 R/W Endpoint selected. Must be set to value in the range 0 - 5 0xDE10: USBMAXI - Max. Packet Size for IN Endpoint{1 - 5} Bit Field Name Reset R/W Description 7:0 USBMAXI[7:0] 0x00 R/W Maximum packet size in units of 8 bytes for IN endpoint selected by USBINDEX register. The value of this register should correspond to the wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint. This register must not be set to a value grater than the available FIFO memory for the endpoint. 0xDE11: USBCS0 - EP0 Control and Status (USBINDEX=0) Bit Field Name Reset R/W Description 7 CLR_SETUP_END 0 R/W H0 Set this bit to 1 to de-assert the SETUP_END bit of this register. This bit will be cleared automatically. 6 CLR_OUTPKT_RDY 0 R/W H0 Set this bit to 1 to de-assert the OUTPKT_RDY bit of this register. This bit will be cleared automatically. 5 SEND_STALL 0 R/W H0 Set this bit to 1 to terminate the current transaction. The USB controller will send the STALL handshake and this bit will be de-asserted. 4 SETUP_END 0 R This bit is set if the control transfer ends due to a premature end of control transfer. The FIFO will be flushed and an interrupt request (EP0) will be generated if the interrupt is enabled. Setting CLR_SETUP_END=1 will deassert this bit 3 DATA_END 0 R/W H0 This bit is used to signal the end of a data transfer and must be asserted in the following three situations: 1 When the last data packet has been loaded and USBCS0.INPKT_RDY is set to 1 2 When the last data packet has been unloaded and USBCS0.CLR_OUTPKT_RDY is set to 1 3 When USBCS0.INPKT_RDY has been asserted without having loaded the FIFO (for sending a zero length data packet). The USB controller will clear this bit automatically 2 SENT_STALL 0 R/W H1 This bit is set when a STALL handshake has been sent. An interrupt request (EP0) will be generated if the interrupt is enabled This bit must be cleared from firmware. 1 INPKT_RDY 0 R/W H0 Set this bit when a data packet has been loaded into the EP0 FIFO to notify the USB controller that a new data packet is ready to be transferred. When the data packet has been sent, this bit is cleared and an interrupt request (EP0) will be generated if the interrupt is enabled. 0 OUTPKT_RDY 0 R Data packet received. This bit is set when an incoming data packet has been placed in the OUT FIFO. An interrupt request (EP0) will be generated if the interrupt is enabled. Set CLR_OUTPKT_RDY=1 to de-assert this bit. SWRS033H Page 182 of 246 CC1110Fx / CC1111Fx 0xDE11: USBCSIL - IN EP{1 - 5} Control and Status Low Bit Field Name 7 Reset R/W Description - R0 Not used 6 CLR_DATA_TOG 0 R/W H0 Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the next data packet to be a DATA0 packet. This bit is automatically cleared. 5 SENT_STALL 0 R/W This bit is set when a STALL handshake has been sent. The FIFO will be flushed and the INPKT_RDY bit in this register will be de-asserted. An interrupt request (IN EP{1 - 5}) will be generated if the interrupt is enabled. This bit must be cleared from firmware. 4 SEND_STALL 0 R/W Set this bit to 1 to make the USB controller reply with a STALL handshake when receiving IN tokens. Firmware must clear this bit to end the STALL condition. It is not possible to stall an isochronous endpoint, thus this bit will only have effect if the IN endpoint is configured as bulk/interrupt. 3 FLUSH_PACKET 0 R/W H0 Set to 1 to flush next packet that is ready to transfer from the IIN FIFO. The INPKT_RDY bit in this register will be cleared. If there are two packets in the IN FIFO due to double buffering, this bit must be set twice to completely flush the IN FIFO. This bit is automatically cleared. 2 UNDERRUN 0 R/W In isochronous mode, this bit is set if an IN token is received when INPKT_RDY=0, and a zero length data packet is transmitted in response to the IN token. In Bulk/Interrupt mode, this bit is set when a NAK is returned in response to an IN token. Firmware should clear this bit. 1 PKT_PRESENT 0 R This bit is 1 when there is at least one packet in the IN FIFO. 0 INPKT_RDY 0 R/W H0 Set this bit when a data packet has been loaded into the IN FIFO to notify the USB controller that a new data packet is ready to be transferred. When the data packet has been sent, this bit is cleared and an interrupt request (IN EP{1 - 5}) will be generated if the interrupt is enabled. 0xDE12: USBCSIH - IN EP{1 - 5} Control and Status High Bit Field Name Reset R/W Description 7 AUTOSET 0 R/W When this bit is 1, the USBCSIL.INPKT_RDY bit is automatically asserted when a data packet of maximum size (specified by USBMAXI) has been loaded into the IN FIFO. 6 ISO 0 R/W Selects IN endpoint type 5:4 3 FORCE_DATA_TOG 2:1 0 IN_DBL_BUF 0 Bulk/Interrupt 1 Isochronous 10 R/W Reserved. Always write 10 0 R/W Setting this bit will force the IN endpoint data toggle to switch and the data packet to be flushed from the IN FIFO even though an ACK was received. This feature can be useful when reporting rate feedback for isochronous endpoints. - R0 Not used 0 R/W Double buffering enable (IN FIFO) 0 Double buffering disabled 1 Double buffering enabled 0xDE13: USBMAXO - Max. Packet Size for OUT{1 - 5} Endpoint Bit Field Name Reset R/W Description 7:0 USBMAXO[7:0] 0x00 R/W Maximum packet size in units of 8 bytes for OUT endpoint selected by USBINDEX register. The value of this register should correspond to the wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint. This register must not be set to a value grater than the available FIFO memory for the endpoint. SWRS033H Page 183 of 246 CC1110Fx / CC1111Fx 0xDE14: USBCSOL - OUT EP{1 - 5} Control and Status Low Bit Field Name Reset R/W Description 7 CLR_DATA_TOG 0 R/W H0 Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the next data packet to be a DATA0 packet. This bit is automatically cleared. 6 SENT_STALL 0 R/W This bit is set when a STALL handshake has been sent. An interrupt request (OUT EP{1 - 5}) will be generated if the interrupt is enabled. This bit must be cleared from firmware 5 SEND_STALL 0 R/W Set this bit to 1 to make the USB controller reply with a STALL handshake when receiving OUT tokens. Firmware must clear this bit to end the STALL condition. It is not possible to stall an isochronous endpoint, thus this bit will only have effect if the IN endpoint is configured as bulk/interrupt. 4 FLUSH_PACKET 0 R/W H0 Set to 1 to flush next packet that is to be read from the OUT FIFO. The OUTPKT_RDY bit in this register will be cleared. If there are two packets in the OUT FIFO due to double buffering, this bit must be set twice to completely flush the OUT FIFO. This bit is automatically cleared. 3 DATA_ERROR 0 R This bit is set if there is a CRC or bit-stuff error in the packet received. Cleared when OUTPKT_RDY is cleared. This bit will only be valid if the OUT endpoint is isochronous. 2 OVERRUN 0 R/W This bit is set when an OUT packet cannot be loaded into the OUT FIFO. Firmware should clear this bit. This bit is only valid in isochronous mode 1 FIFO_FULL 0 R This bit is asserted when no more packets can be loaded into the OUT FIFO full. 0 OUTPKT_RDY 0 R/W This bit is set when a packet has been received and is ready to be read from OUT FIFO. An interrupt request (OUT EP{1 - 5}) will be generated if the interrupt is enabled. This bit should be cleared when the packet has been unloaded from the FIFO. 0xDE15: USBCSOH - OUT EP{1 - 5} Control and Status High Bit Field Name Reset R/W Description 7 AUTOCLEAR 0 R/W When this bit is set to 1, the USBCSOL.OUTPKT_RDY bit is automatically cleared when a data packet of maximum size (specified by USBMAXO) has been unloaded to the OUT FIFO. 6 ISO 0 R/W Selects OUT endpoint type 0 Bulk/Interrupt 1 Isochronous 5:4 00 R/W Reserved. Always write 00 3:1 - R0 Not used 0 R/W Double buffering enable (OUT FIFO) 0 OUT_DBL_BUF 0 Double buffering disabled 1 Double buffering enabled 0xDE16: USBCNT0 - Number of Received Bytes in EP0 FIFO (USBINDEX=0) Bit Field Name 7:6 5:0 USBCNT0[5:0] Reset R/W Description - R0 Not used 000000 R Number of received bytes into EP 0 FIFO. Only valid when OUTPKT_RDY is asserted 0xDE16: USBCNTL - Number of Bytes in EP{1 - 5} OUT FIFO Low Bit Field Name Reset R/W Description 7:0 USBCNT[7:0] 0x00 R 8 LSB of number of received bytes into OUT FIFO selected by USBINDEX register. Only valid when USBCSOL.OUTPKT_RDY is asserted. SWRS033H Page 184 of 246 CC1110Fx / CC1111Fx 0xDE17: USBCNTH - Number of Bytes in EP{1 - 5} OUT FIFO High Bit Field Name 7:3 2:0 USBCNT[10:8] Reset R/W Description - R0 Not used 000 R 3 MSB of number of received bytes into OUT FIFO selected by USBINDEX register. Only valid when USBCSOL.OUTPKT_RDY is set 0xDE20: USBF0 - Endpoint 0 FIFO Bit Field Name Reset R/W Description 7:0 USBF0[7:0] 0x00 R/W Endpoint 0 FIFO. Reading this register unloads one byte from the EP0 FIFO. Writing to this register loads one byte into the EP0 FIFO. Note: The FIFO memory for EP0 is used for both incoming and outgoing data packets. 0xDE22: USBF1 - Endpoint 1 FIFO Bit Field Name Reset R/W Description 7:0 USBF1[7:0] 0x00 R/W Endpoint 1 FIFO register. Reading this register unloads one byte from the EP1 OUT FIFO. Writing to this register loads one byte into the EP1 IN FIFO. 0xDE24: USBF2 - Endpoint 2 FIFO Bit Field Name Reset R/W Description 7:0 USBF2[7:0] 0x00 R/W See Endpoint 1 FIFO description. 0xDE26: USBF3 - Endpoint 3 FIFO Bit Field Name Reset R/W Description 7:0 USBF3[7:0] 0x00 R/W See Endpoint 1 FIFO description. 0xDE28: USBF4 - Endpoint 4 FIFO Bit Field Name Reset R/W Description 7:0 USBF4[7:0] 0x00 R/W See Endpoint 1 FIFO description. 0xDE2A: USBF5 - Endpoint 5 FIFO Bit Field Name Reset R/W Description 7:0 USBF5[7:0] 0x00 R/W See Endpoint 1 FIFO description. SWRS033H Page 185 of 246 CC1110Fx / CC1111Fx 13 Radio RF_P FREQ SYNTH 0 RF_N MODULATOR 90 PA CPU INTERFACE ADC PACKET HANDLER LNA FEC / INTERLEAVER ADC DEMODULATOR RADIO CONTROL Figure 47: CC1110Fx/CC1111Fx Radio Module A simplified block diagram of the radio module in the CC1110Fx/CC1111Fx is shown in Figure 47. CC1110Fx/CC1111Fx features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitized by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization are performed digitally. The transmitter part of CC1110Fx/CC1111Fx is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode. The 26/48 MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. An SFR interface is used for data buffer access from the CPU. Configuration and status registers are accessed through registers mapped to XDATA memory. The digital baseband includes support for channel configuration, packet handling, and data buffering. Note: In this section of the document, fRef is used to denote the reference frequency for the synthesizer. For CC1110Fx f ref f XOSC and for CC1111Fx, f ref f XOSC 2 13.1 Command Strobes The CPU uses a set of command strobes to control operation of the radio. Command strobes may be viewed as single byte instructions which each start an internal sequence in the radio. These command strobes are used to enable the frequency synthesizer, enable receive mode, enable transmit mode, etc. (see Figure 48). Note: An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This means that if for example an SIDLE strobe is issued while the radio is in RX state, any other command strobes issued before the radio reached IDLE state will be ignored. The 6 command strobes are listed in Table 61 on Page 188. SWRS033H Page 186 of 246 CC1110Fx / CC1111Fx SIDLE Default state when the radio is not receiving or transmitting. Used for calibrating frequency synthesizer upfront (entering Manual freq. receive or transmit mode can synth. calibration then be done quicker). Transitional state. SCAL SFSTXON Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe. Idle SRX or STX or SFSTXON Frequency synthesizer startup, optional calibration, settling Frequency synthesizer is turned on, can optionally be calibrated, and then settles to correct frequency. Transitional state Frequency synthesizer on STX SRX STX TXOFF_MODE=01 SFSTXON or RXOFF_MODE=01 Transmit mode STX or RXOFF_MODE=10 Receive mode SRX or TXOFF_MODE=11 TXOFF_MODE=00 Transmission is turned off and this state is entered if the RFD register becomes empty in the middle of a packet. Typ. current consumption: 1.8 mA RXOFF_MODE=00 Optional transitional state. TX Overflow Optional freq. synth. calibration SIDLE RX Overflow Reception is turned off and this state is entered if the RFD register overflows. SIDLE Idle . Figure 48: Simplified State Diagram with Typical Usage and Current Consumption in Radio at 250 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized) SWRS033H Page 187 of 246 CC1110Fx / CC1111Fx RFST Value Command Strobe Name Description 0x00 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=01). If in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). 0x01 SCAL Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=00) 0x02 SRX Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=01. 0x03 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=01. If in RX state and CCA is enabled: Only go to TX if channel is clear. 0x04 SIDLE Enter IDLE state (frequency synthesizer turned off). All others SNOP No operation. Table 61: Command Strobes 13.2 Radio Registers The operation of the radio is configured through a set of RF registers. These RF registers are mapped to XDATA memory space as shown in Figure 14 on Page 43 . In addition to configuration registers, the RF registers also provide status information from the radio. Section 10.2.3.4 on Page 50 gives a full description of all RF registers. 13.3 Interrupts There are two interrupt vector assigned to the radio. These are the RFTXRX interrupt (interrupt #0) and the RF interrupt (interrupt #16): RFTXRX: RX data ready or TX data complete (related to the RFD register) issued, meaning that one can not write to the RFD register before issuing an STX strobe. For an interrupt request to be generated when TCON.RFTXRXIF is asserted, IEN0.RFTXRXIE must be 1. Note: When append status is enabled, PKTCTRL1.APPEND_STATUS=1, reading status byte 1 (see Section 13.8) from the RFD register will trigger the assertion of the RFTXRXIF flag for status byte 2. If this flag is cleared AFTER reading status byte 1, the new flag will be cleared as well. One RFTXRXIF assertion will therefore be missed by software. After assertion of the RFTXRXIF flag one should therefore clear the flag BEFORE reading the RFD register. RF: All other general RF interrupts The RF interrupt vector combines the interrupts shown in the RFIM register shown on Page 190. Note that these RF interrupts are rising-edge triggered meaning that an interrupt is generated when e.g. the SFD status flag goes from 0 to 1. The RF interrupt flags are described in the next section. 13.3.1 13.3.1.1 Interrupt Registers 13.3.1.2 RFTXRX The RFTXRX interrupt is related to the RFD register. The CPU interrupt flag RFTXRXIF found in the TCON register is asserted when there are data in the RFD register ready to be read (RX), and when a new byte can be written (TX). In TX, the RFTXRXIF flag will not be asserted before an STX strobe has been RF There are 8 different events that can generate an RF interrupt request. These events are: SWRS033H TX underflow RX overflow RX timeout Packet received/transmitted. Also used to detect overflow/underflow conditions Page 188 of 246 CC1110Fx / CC1111Fx CS PQT reached CCA SFD Each of these events has a corresponding interrupt flag in the RFIF register which is asserted when the event occurs. If the corresponding mask bit is set in the RFIM register, the CPU interrupt flag S1CON.RFIF will also be asserted in addition to the interrupt flag in RFIF. If IEN2.RFIE=1 when S1CON.RFIF is asserted, and interrupt request will be generated. Refer to 0 for details about the interrupts. RFIF (0xE9) - RF Interrupt Flags Bit Field Name Reset R/W Description 7 IRQ_TXUNF 0 R/W0 TX underflow 6 5 4 3 2 1 0 IRQ_RXOVF IRQ_TIMEOUT IRQ_DONE IRQ_CS IRQ_PQT IRQ_CCA IRQ_SFD 0 0 0 0 0 0 0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 0 No interrupt pending 1 Interrupt pending RX overflow 0 No interrupt pending 1 Interrupt pending RX timeout, no packet has been received in the programmed period 0 No interrupt pending 1 Interrupt pending Packet received/transmitted. Also used to detect underflow/overflow conditions 0 No interrupt pending 1 Interrupt pending Carrier sense 0 No interrupt pending 1 Interrupt pending Preamble quality threshold reached 0 No interrupt pending 1 Interrupt pending Clear Channel Assessment 0 No interrupt pending 1 Interrupt pending Start of Frame Delimiter, sync word detected 0 No interrupt pending 1 Interrupt pending SWRS033H Page 189 of 246 CC1110Fx / CC1111Fx RFIM (0x91) - RF Interrupt Mask Bit Field Name Reset R/W Description 7 IM_TXUNF 0 R/W TX underflow 6 5 4 3 2 1 0 IM_RXOVF IM_TIMEOUT IM_DONE IM_CS IM_PQT IM_CCA IM_SFD 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 0 Interrupt disabled 1 Interrupt enabled RX overflow 0 Interrupt disabled 1 Interrupt enabled RX timeout, no packet has been received in the programmed period. 0 Interrupt disabled 1 Interrupt enabled Packet received/transmitted. Also used to detect underflow/overflow conditions 0 Interrupt disabled 1 Interrupt enabled Carrier sense 0 Interrupt disabled 1 Interrupt enabled Preamble quality threshold reached. 0 Interrupt disabled 1 Interrupt enabled Clear Channel Assessment 0 Interrupt disabled 1 Interrupt enabled Start of Frame Delimiter, sync word detected 0 Interrupt disabled 1 Interrupt enabled 13.4 TX/RX Data Transfer Data to transmit is written to the RF Data register, RFD. Received data is read from the same register. The RFD register can be viewed as a 1 byte FIFO. That means that if a byte is received in the RFD register, and it is not read before the next byte is received, the radio will enter RX_OVERFLOW state and the RFIF.IRQ_RXOVF flag will be set together with RFIF.IRQ_DONE. In TX, the radio will enter TX_UNDERFLOW state (RFIF.IRQ_TXUVF and RFIF.IRQ_DONE will be asserted) if too few bytes are written to the RFD register compared to what the radio expect. Note that if an STX strobe is issued but no data is written to the RFD register after the following assertion of the RFTXRXIF flag, the radio will start sending preamble without entering TX_UNDERFLOW state. To exit RX_OVERFLOW and/or TX_UNDERFLOW state, an SIDLE strobe command should be issued. Note: The RFD register content will not be retained in PM2 and PM3 RX and TX FIFOs can be implemented in memory and it is recommended to use the DMA to transfer data between the FIFOs and the RF Data register, RFD. The DMA channel used to transfer received data to memory when the radio is in RX mode would have RFD as the source (SRCADDR[15:0]), the RX FIFO in memory as destination (DRSTADDR[15:0]), and RADIO as DMA trigger (TRIG[4:0]). For description on the usage of DMA, refer to Section 12.5 on Page 101. SWRS033H Page 190 of 246 CC1110Fx / CC1111Fx A simple example of transmitting data is shown in Figure 49. This example does not use DMA. ; Transmit the following data: 0x02, 0x12, 0x34 ; (Assume that the radio has already been configured, the high speed ; crystal oscillator is selected as system clock, and CLKCON.CLKSPD=000) C1: C2: C3: MOV JNB CLR MOV JNB CLR MOV JNB CLR MOV RFST,#03H RFTXRXIF,C1 RFTXRXIF RFD,#02H RFTXRXIF,C2 RFTXRXIF RFD,#12H RFTXRXIF,C3 RFTXRXIF RFD,#34H ; ; ; ; ; ; ; ; ; ; ; Start TX with STX command strobe Wait for interrupt flag telling radio is ready to accept data, then write first data byte to radio (packet length = 2) Wait for radio Send first byte in payload Wait for radio Send second byte in payload Done Figure 49: Simple RF Transmit Example 13.5 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. RDATA 256 DRATE _ M 2 DRATE _ E f ref 2 28 The following approach can be used to find suitable values for a given data rate: RDATA 2 20 f ref DRATE _ E log 2 DRATE _ M RDATA 2 28 f ref 2 DRATE _ E 256 If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. Note that the maximum data rate will be limited by the system clock speed. Please see 12.1.5.2 for more details. 13.6 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth. The following formula gives the relation between the register settings and the channel filter bandwidth: BWchannel f ref 8 (4 CHANBW _ M )·2CHANBW _ E For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. The following example illustrates this: With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of 500 kHz, which is 400 kHz. Assuming 915 MHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915 MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400 kHz, the transmitted signal bandwidth should be maximum 400 kHz - 2·37 kHz, which is 326 kHz. The CC1110Fx/CC1111Fx supports channel filter bandwidths shown in Table 62 and Table 63 respectively. SWRS033H Page 191 of 246 CC1110Fx / CC1111Fx MDMCFG4. MDMCFG4.CHANBW_E MDMCFG4. CHANBW_M 00 01 10 11 CHANBW_M 00 01 10 11 00 812 406 203 102 00 750 375 188 94 01 650 325 162 81 01 600 300 150 75 10 541 270 135 68 10 500 250 125 63 11 464 232 116 58 11 429 214 107 54 Table 62: Channel Filter Bandwidths [kHz] (assuming fref = 26 MHz) 13.7 Table 63: Channel Filter Bandwidths [kHz] (assuming fref = 24 MHz) Demodulator, Symbol Synchronizer, and Data Decision CC1110Fx/CC1111Fx contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 13.10.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 13.7.1 MDMCFG4.CHANBW_E Frequency Offset Compensation 13.7.2 The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 13.5 on Page 191. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate. 13.7.3 When using 2-FSK, GFSK, or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data. This value is available in the FREQEST status register. Writing the value from FREQEST into FSCTRL0.FREQOFF the frequency synthesizer is automatically adjusted according to the estimated frequency offset. The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register. If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise. The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found. Note that frequency offset compensation is not supported for ASK or OOK modulation. Bit Synchronization Byte Synchronization Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet by the modulator in transmit mode. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 13.10.1). The sync word detector correlates against the userconfigured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is configured through the SYNC1 and SYNC0 registers and is sent MSB first. In order to make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted. See Section 13.10.2 on Page 197 for more details. SWRS033H Page 192 of 246 CC1110Fx / CC1111Fx 13.8 Packet Handling Hardware Support The CC1110Fx/CC1111Fx has built-in hardware support for packet oriented radio protocols. Whitening of the data with a PN9 sequence. In transmit mode, the packet handler can be configured to add the following elements to the packet: Forward error correction by the use of interleaving and coding of the data (convolutional coding). A programmable number of preamble bytes In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled): A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word. Preamble detection Sync word detection CRC computation and CRC check A CRC checksum computed over the data field One byte address check Packet length check (length byte checked against a programmable maximum length) The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes. In addition, the following can be implemented on the data field and the optional 2-byte CRC checksum: De-whitening De-interleaving and decoding Optionally, two status bytes (see Table 64 and Table 65) with RSSI value, Link Quality Indication, and CRC status can be appended to the received packet. Bit Field Name Description 7:0 RSSI RSSI value Table 64: Received Packet Status Byte 1 (first byte appended after the data) Bit Field name Description 7 CRC_OK 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data 6:0 LQI The Link Quality Indicator estimates how easily a received signal can be demodulated Table 65: Received Packet Status Byte 2 (second byte appended after the data) Note that register fields that control the packet handling features should only be altered when CC1110Fx/CC1111Fx is in the IDLE state. 13.8.1 Data Whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies). Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening the data in the receiver. With CC1110Fx/CC1111Fx, this can be done automatically by setting PKTCTRL0.WHITE_DATA=1. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) SWRS033H Page 193 of 246 CC1110Fx / CC1111Fx sequence before being transmitted as shown in Figure 50. At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, 8 TX_DATA and the original data appear in the receiver. The PN9 sequence is reset to all 1’s. Data whitening can only be used when PKTCTRL0.CC2400_EN=0 (default). 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 The first TX_DATA byte is shifted in before doing the XOR-operation providing the first TX_OUT[7:0] byte. The second TX_DATA byte is then shifted in before doing the XOR-operation providing the second TX_OUT[7:0] byte. TX_OUT[7:0] Figure 50: Data Whitening in TX Mode 13.8.2 Packet Format The format of the data packet can be configured and consists of the following items: Length byte or constant programmable packet length Optional Address byte Preamble Payload Synchronization word Optional 2 byte CRC Data field 16/32 bits 8 bits 8 bits 8 x n bits Legend: Inserted automatically in TX, processed and removed in RX. CRC-16 Address field 8 x n bits Length field Preamble bits (1010...1010) Sync word Optional data whitening Optionally FEC encoded/decoded Optional CRC-16 calculation Optional user-provided fields processed in TX, processed but not removed in RX. Unprocessed user data (apart from FEC and/or whitening) 16 bits Figure 51: Packet Format SWRS033H Page 194 of 246 CC1110Fx / CC1111Fx The preamble pattern is an alternating sequence of ones and zeros (101010101…). The minimum length of the preamble is programmable through the NUM_PREAMBLE field in the MDMCFG1 register. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes have been transmitted, the modulator will send the sync word, and then data from the RFD register. If no data has been written to the RFD register when the radio is done transmitting the programmed number of preamble bytes, the modulator will continue to send preamble bytes until the first byte is written to RFD. It will then send the sync word followed by the data written to RFD. The sync. word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using MDMCFG2.SYNC_MODE set to 3 or 7. The sync word will then be repeated twice. register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 or both 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is accepted and the RFTXRXIF flag is asserted and a DMA trigger is generated. If the address match fails, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). The RFIF.IRQ_DONE flag will be asserted but the DMA will not be triggered. 13.8.3.2 Maximum Length Filtering In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). The RFIF.IRQ_DONE flag will be asserted but the DMA will not be triggered. CC1110Fx/CC1111Fx supports both fixed packet length protocols and variable packet length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. 13.8.3 Packet Filtering in Receive Mode CC1110Fx/CC1111Fx supports two different types of packet-filtering: address maximum length filtering. 13.8.3.1 filtering and Address Filtering Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR 13.8.4 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into RFD. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to RFD is interpreted as the destination address, if this feature is enabled in the device that receives the packet. The modulator will first send the programmed number of preamble bytes. If data has been written to RFD, the modulator will send the twobyte (optionally 4-byte) sync word and then the content of the RFD register. If CRC is enabled, the checksum is calculated over all the data pulled from the RFD register and the result is sent as two extra bytes following the payload data. If fewer bytes are written to the RFD registers than what the radio expects the radio will enter TX_UNDERFLOW state and the RFIF.IRQ_TXUNF flag will be set together with RFIF.IRQ_DONE. An SIDLE strobe needs to be issued to return to IDLE state. If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1. SWRS033H Page 195 of 246 CC1110Fx / CC1111Fx If FEC/Interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is enabled by setting MDMCFG1.FEC_EN=1. 13.8.5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronism and will receive the first payload byte. If FEC/Interleaving is enabled, the FEC decoder will start to decode the first payload byte. The interleaver will de-scramble the bits before any other processing is done to the data. If whitening is enabled, the data will be dewhitened at this stage. When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum. At the end of the payload, the packet handler will optionally write two extra packet status bytes that contain CRC status, link quality indication and RSSI value. If a byte is received in the RFD register, and it is not read before the next byte is received, the radio will enter RX_OVERFLOW state and the RFIF.IRQ_RXOVF flag will be set together with RFIF.IRQ_DONE. An SIDLE strobe needs to be issued to return to IDLE state. 13.9 Modulation Formats CC1110Fx/CC1111Fx supports frequency and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Note: Manchester encoding is not supported at the same time as using the FEC/Interleaver option or when using MSK modulation. 13.9.1 When FSK/GFSK modulation is used the DEVIATN register specifies the expected frequency deviation of incoming signal in RX and should be the same as the TX deviation for demodulation to be performed reliably and robustly. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by: f dev f ref 217 (8 DEVIATION _ M ) 2 DEVIATION _ E The symbol encoding is shown in Table 66. Frequency Shift Keying 2-FSK can optionally be shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal. Format Symbol Coding 2-FSK/GFSK ‘0’ –Deviation ‘1’ +Deviation Table 66: Symbol Encoding for 2-FSK/GFSK Modulation SWRS033H Page 196 of 246 CC1110Fx / CC1111Fx 13.9.2 Minimum Shift Keying 13.9.3 Amplitude Modulation When using MSK , the complete transmission (preamble, sync word, and payload) will be MSK modulated. CC1110Fx/CC1111Fx supports two different forms Phase shifts are performed with a constant transition time. OOK modulation simply turns on or off the PA to modulate 1 and 0 respectively. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol. The 21 The MSK modulation format implemented in CC1110Fx/CC1111Fx inverts the sync word and data compared to e.g. signal generators. of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift Keying (ASK). variant supported by the modulation depth (the difference between 1 and 0), and shaping of the pulse amplitude. Pulse shaping will produce a more bandwidth constrained output spectrum. Note: The DEVIATN register setting has no effect in either RX or TX when using OOK/ASK. Note: The DEVIATN register setting has no effect in RX when using MSK. Also, when using MSK Manchester encoding/decoding should be disabled (MDMCFG2.MANCHESTER_EN=0) 21 ASK CC1110Fx/CC1111Fx allows programming of the Identical to offset QPSK with half-sine shaping (data coding may differ) 13.10 Received Signal Qualifiers and Link Quality Information CC1110Fx/CC1111Fx has several qualifiers that MDMCFG2. can be used to increase the likelihood that a valid sync word is detected. SYNC_MODE 13.10.1 Sync Word Qualifier If sync word detection in RX is enabled in register MDMCFG2 the CC1110Fx/CC1111Fx will not start writing received data to the RFD register and perform the packet filtering described in Section 13.8.3 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table 67. Carrier sense in Table 67 is described in Section 13.10.4. Sync Word Qualifier Mode 000 No preamble/sync 001 15/16 sync word bits detected 010 16/16 sync word bits detected 011 30/32 sync word bits detected 100 No preamble/sync, carrier sense above threshold 101 15/16 + carrier sense above threshold 110 16/16 + carrier sense above threshold 111 30/32 + carrier sense above threshold Table 67: Sync Word Qualifier mode 13.10.2 Preamble Quality Threshold (PQT) The Preamble Quality Threshold (PQT) syncword qualifier adds the requirement that the received sync word must be preceded with a preamble with a quality above a programmed threshold. Another use of the preamble quality threshold is as a qualifier for the optional RX termination SWRS033H Page 197 of 246 CC1110Fx / CC1111Fx timer. See Section 13.12.3 on Page 205 for details. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. The threshold is configured with the register field PKTCTRL1.PQT. A threshold of 4∙PQT for this counter is used to gate sync word detection. By setting the value to zero, the preamble quality qualifier of the sync word is disabled. A “Preamble Quality Reached” signal can be observed on P1_5, P1_6, or P1_7 by setting IOCFGx.GDOx_CFG=1000. It is also possible to determine if preamble quality is reached by checking the PQT_REACHED bit in the PKTSTATUS register. This signal / bit asserts when the received signal exceeds the PQT. The RSSI value is in dBm with ½ dB resolution. The RSSI update rate, f RSSI, depends on the receiver filter bandwidth (BW channel defined in Section 13.6) and AGCCTRL0.FILTER_LENGTH. f RSSI 2 BWchannel 8 2 FILTER _ LENGTH If PKTCTRL1.APPEND_STATUS is enabled the RSSI value at sync word detection is automatically added to the first byte appended after the data payload. The RSSI value read from the RSSI status register is a 2’s complement number. The following procedure can be used to convert the RSSI reading to an absolute power level (RSSI_dBm). 1) Read the RSSI status register 2) Convert the reading from a hexadecimal number to a decimal number (RSSI_dec) 13.10.3 RSSI The RSSI value is an estimate of the signal level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel. In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state. 3) If RSSI_dec ≥ 128 then RSSI_dBm = (RSSI_dec – 256)/2 – RSSI_offset 4) Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 – RSSI_offset Table 68 provides typical values for the RSSI_offset. Figure 52 and Figure 53 shows typical plots of RSSI readings as a function of input power level for different data rates. Note: It takes some time from the radio enters RX mode until a valid RSSI value is present in the RSSI register. Please see DN505 [16] for details on how the RSSI response time can be estimated. Data rate [kBaud] RSSI_offset [dB], 315 MHz RSSI_offset [dB], 433 MHz RSSI_offset [dB], 868 MHz 1.2 74 75 73 38.4 73 74 73 250 74 73 77 Table 68: Typical RSSI_offset Values Figure 52 and Figure 53 show typical plots of RSSI readings as a function of input power level for different data rates. SWRS033H Page 198 of 246 CC1110Fx / CC1111Fx 0 -10 -20 -30 RSSI Readout [dBm] -40 -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBaud 38.4 kBaud 250 kBaud Figure 52: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz 0 -10 -20 RSSI Readout [dBm] -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBaud 38.4 kBaud 250 kBaud Figure 53: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz 13.10.4 Carrier Sense (CS) The Carrier Sense (CS) flag is used as a sync word qualifier and for CCA. The CS flag can be set based on two conditions, which can be individually adjusted: CS is asserted when the RSSI is above a programmable absolute threshold, and de-asserted when RSSI is below the same threshold (with hysteresis). SWRS033H CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and de-asserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. Page 199 of 246 CC1110Fx / CC1111Fx Carrier Sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. The signal can also be observed on P1_5, P1_6, or P1_7 by setting IOCFGx.GDOx_CFG=1110 and in the status register bit PKTSTATUS.CS. MAX_LNA_GAIN[2:0] MAX_DVGA_GAIN[1:0] Other uses of Carrier Sense include the TX-ifCCA function (see Section 13.10.7 on Page 201) and the optional fast RX termination (see Section 13.12.3 on Page 205). CS can be used to avoid interference from other RF sources in the ISM bands. 00 01 10 11 000 –99 –93 –87 –81.5 001 –97 –90.5 –85 –78.5 010 –93.5 –87 –82 –76 011 –91.5 –86 –80 –74 100 –90.5 –84 –78 –72.5 101 –88 –82.5 –76 –70 110 –84.5 –78.5 –73 –67 111 –82.5 –76 –70 –64 Table 69: Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 2.4 kBaud 13.10.5 CS Absolute Threshold The absolute threshold related to the RSSI value depends on the following register fields: MAX_DVGA_GAIN[1:0] AGCCTRL2.MAX_LNA_GAIN 00 01 10 11 000 –96 –90 –84 –78.5 AGCCTRL1.CARRIER_SENSE_ABS_THR 001 –94.5 –89 –83 –77.5 010 –92.5 –87 –81 –75 011 –91 –85 –78.5 –73 100 –87.5 –82 –76 –70 101 –85 –79.5 –73.5 –67.5 110 –83 –76.5 –70.5 –65 111 –78 –72 –66 –60 MAX_LNA_GAIN[2:0] AGCCTRL2.MAX_DVGA_GAIN AGCCTRL2.MAGN_TARGET For a given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN setting the absolute threshold can be adjusted ±7 dB in steps of 1 dB using CARRIER_SENSE_ABS_THR. The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroom for blockers, and therefore close-in selectivity. It is ® strongly recommended to use SmartRF Studio [9] to generate the correct MAGN_TARGET setting. Table 69 and Table 70 show the typical RSSI readout values at the CS threshold at 2.4 kBaud and 250 kBaud data rate respectively. The default CARRIER_SENSE_ABS_THR=0 (0 dB) and MAGN_TARGET=11 (33 dB) have been used. For other data rates the user must generate similar tables to find the CS absolute threshold. Table 70: Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 250 kBaud If the threshold is set high, i.e. only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reduce power consumption in the receiver front end, since the highest gain settings are avoided. 13.10.6 CS Relative Threshold The relative threshold detects sudden changes in the measured signal level. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, and to select threshold of 6 dB, 10 dB or 14 dB RSSI change SWRS033H Page 200 of 246 CC1110Fx / CC1111Fx 13.10.7 Clear Channel Assessment (CCA) Always (CCA disabled, always goes to TX) The Clear Channel Assessment CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on P1_5, P1_6, or P1_7 by setting IOCFGx.GDOx_CFG=1001. If RSSI is below threshold Unless currently receiving a packet Both the above (RSSI below threshold and not currently receiving a packet) MCSM1.CCA_MODE selects the mode to use when determining CCA. When the STX or SFSTXON command strobe is given while CC1110Fx/CC1111Fx is in the RX state, the TX or FSTXON state is only entered if the clear channel requirements are fulfilled. The chip will otherwise remain in RX (if the channel becomes available, the radio will not enter TX or FSTXON state before a new strobe command is being issued). This feature is called TX-if-CCA. Note that when using this function the register TEST1 on Page 226 should be set to 0x31. Four CCA requirements can be programmed: 13.10.8 Link Quality Indicator (LQI) The Link Quality Indicator is a metric of the current quality of the received signal. If PKTCTRL1.APPEND_STATUS is enabled, the value is automatically added to the last byte appended after the payload. The value can also be read from the LQI status register. The LQI gives an estimate of how easily a received signal can be demodulated by accumulating the magnitude of the error between ideal constellations and the received signal over the 64 symbols immediately following the sync word. LQI is best used as a relative measurement of the link quality (a high value indicates a better link than what a low value does), since the value is dependent on the modulation format. 13.11 Forward Error Correction with Interleaving 13.11.1 Forward Error Correction (FEC) CC1110Fx/CC1111Fx has built in support for Forward Error Correction (FEC). To enable this option, set MDMCFG1.FEC_EN to 1. FEC is only supported in fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors. The use of FEC allows correct reception at a lower SNR, thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by: PER 1 (1 BER) packet _ length , a lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors). The FEC scheme adopted for CC1110Fx/CC1111Fx is convolutional coding, in which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m-bit window). The convolutional coder is a rate 1/2 code with a constraint length of m=4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. I.e. to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate. This will require a higher receiver bandwidth, and thus reduce sensitivity. In other words, the improved reception by using FEC and the degraded sensitivity from a higher receiver bandwidth will be counteracting factors. 13.11.2 Interleaving Data received through radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning SWRS033H Page 201 of 246 CC1110Fx / CC1111Fx multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RFD data register. CC1110Fx/CC1111Fx employs matrix interleaving, which is illustrated in Figure 54. The on-chip interleaving and de-interleaving buffers are 4 x 4 matrices. In the transmitter, the data bits from the rate ½ convolutional coder are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix. In the receiver, the received symbols are written into the rows of the matrix, whereas the data passed onto the convolutional decoder is read from the columns of the matrix. When FEC and interleaving is used the minimum data payload is 2 bytes. Note: When using FEC (MDMCFG1.FEC_EN=1), CLKCON.CLKSPD must be set to 000. When FEC and interleaving is used at least one extra byte is required for trellis termination. Interleaver Write buffer Packet Engine Interleaver Read buffer FEC Encoder Modulator Interleaver Write buffer Interleaver Read buffer FEC Decoder Demodulator Packet Engine Figure 54: General Principle of Matrix Interleaving 13.12 Radio Control CC1110Fx/CC1111Fx has a built-in state machine that is used to switch between different operation states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. Figure 48 on Page 187. The complete radio control state diagram is shown in Figure 55. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes. A simplified state diagram, together with typical usage and current consumption, is shown in SWRS033H Page 202 of 246 CC1110Fx / CC1111Fx SIDLE CAL_COMPLETE MANCAL 3,4,5 IDLE 1 SCAL SRX | STX | SFSTXON FS_WAKEUP 6,7 FS_AUTOCAL = 01 & SRX | STX | SFSTXON FS_AUTOCAL = 00 | 10 | 11 & SRX | STX | SFSTXON CALIBRATE 8 CAL_COMPLETE SETTLING 9,10,11 SFSTXON FSTXON 18 STX STX TXOFF_MODE=01 SRX SFSTXON | RXOFF_MODE = 01 SRX STX | RXOFF_MODE = 10 TXOFF_MODE = 10 RXTX_SETTLING 21 TX 19,20 SRX | TXOFF_MODE = 11 ( STX | SFSTXON ) & CCA | RXOFF_MODE = 01 | 10 RX 13,14,15 RXOFF_MODE = 11 TXRX_SETTLING 16 RXOFF_MODE = 00 & FS_AUTOCAL = 10 | 11 TXOFF_MODE = 00 & FS_AUTOCAL = 10 | 11 TXFIFO_UNDERFLOW RXFIFO_OVERFLOW TXOFF_MODE = 00 & FS_AUTOCAL = 00 | 01 CALIBRATE 12 RXOFF_MODE = 00 & FS_AUTOCAL = 00 | 01 RX_OVERFLOW 17 TX_UNDERFLOW 22 SIDLE IDLE 1 SIDLE Figure 55: Complete Radio Control State Diagram SWRS033H Page 203 of 246 CC1110Fx / CC1111Fx 13.12.1 Active Modes The radio has two active modes: receive and transmit. These modes are activated directly by writing the SRX and STX command strobes to the RFST register. The frequency synthesizer must be calibrated regularly. CC1110Fx/CC1111Fx has one manual calibration option (using the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL setting: Calibrate when going from IDLE to either RX or TX (or FSTXON) Calibrate when going from either RX or TX to IDLE automatically Calibrate every fourth time when going from either RX or TX to IDLE automatically If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibration takes a constant number of XOSC cycles (see Table 71 for timing details regarding calibration. When RX is activated, the chip will remain in receive mode until a packet is successfully received or the RX termination timer expires (see Section 13.12.3). Note: the probability that a false sync word is detected can be reduced by using PQT, CS, maximum sync word length, and sync word qualifier mode as describe in Section 13.10.1. After a packet is successfully received the radio controller will then go to the state indicated by the MCSM1.RXOFF_MODE setting. The possible destinations are: IDLE FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX. TX: Start sending preambles RX: Start search for a new packet Note: When MCSM1.RXOFF_MODE=11 and a packet has been received, it will take some time before a valid RSSI value is present in the RSSI register again even if the radio has never exited RX mode. This time is the same as the RSSI response time discussed in DN505 [16]. Similarly, when TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are the same as for RX. It is possible to change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and an SRX strobe is written to the RFST register, the current transmission will be ended and the transition to RX will be done. If the radio controller is in RX when the STX or SFSTXON command strobes are used and MCSM1.CCA_MODE≠00, the TX-if-CCA function will be used. Note that for TX-if-CCA function the register TEST1 on Page 226 TEST1 should be set to 0x31. If the channel is not clear, the chip will remain in RX. For more details on clear channel assessment see Section 13.10.7 on Page 201 for details. The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. 13.12.2 Timing The radio controller controls most timing in CC1110Fx/CC1111Fx, such as synthesizer calibration, PLL lock time, and RX/TX turnaround times. Table 71 shows the timing for key state transitions when the system clock frequency fSys is equal to fRef and the data rate is 250 kBaud. No PA ramping/shaping is implemented. See DN110 [15] for more details on how the state transition times changes under other conditions. Power on time and XOSC start-up times are variable, but within the limits stated in Table 11 and Table 12 Note that in a frequency hopping spread spectrum or a multi-channel protocol it is possible to reduce the calibration time significantly. This is explained in Section 13.18.2. SWRS033H Page 204 of 246 CC1110Fx / CC1111Fx Transmission Time as a function of fRef and/or fSymbol22 Description Transition Time [μs] fRef = 26 MHz fRef = 24 MHz 1953/fSys 75.1 81.4 20768/fSys 799 865 1954/fSys 75.2 81.4 20768/fSys 799 865 TX to RX switch 782/fSys + 0.25/fSymbol 31.1 33.6 RX to TX switch 782/fSys 30.1 32.6 ~0.25/fSymbol ~1 ~1 ~0.25/fSymbol +18815/fSys 725 785 2/fSys 0.1 0.1 18817/fSys 724 784 19098/fSys 735 796 Idle to RX, no calibration 23 Idle to RX, with calibration Idle to TX/FSTXON, no calibration Idle to TX/FSTXON, with calibration 23 TX to IDLE, no calibration TX to IDLE, with calibration 23 RX to IDLE, no calibration RX to IDLE, with calibration 23 Manual calibration Table 71: State Transition Timing 13.12.3 RX Termination Timer CC1110Fx/CC1111Fx has optional functions for automatic termination of RX after a programmable time. The termination timer starts when in RX state. The timeout is programmable with the MCSM2.RX_TIME setting. When the timer expires, the radio controller will check the condition for staying in RX; if the condition is not met, RX will terminate. The programmable conditions are: MCSM2.RX_TIME_QUAL=0: Continue receive if sync word has been found MCSM2.RX_TIME_QUAL=1: Continue receive if sync word has been found or preamble quality is above threshold (PQT) If the system can expect the transmission to have started when enabling the receiver, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section 13.10.4 on Page 199 for details on Carrier Sense. For ASK/OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in ASK/OOK mode when the distance between “1” symbols is 8 or less. If RX terminates due to no carrier sense when the MCSM2.RX_TIME_RSSI function is used, or if no sync word was found when using the MCSM2.RX_TIME timeout function, the chip will always go back to IDLE. 13.13 Frequency Programming The frequency programming in CC1110Fx/CC1111Fx is designed to minimize the programming needed in a channel-oriented system. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be 22 fSymbol is the symbol rate for the data transmission (in this case 250 kBaud). Please see DN110 [15] for more details 23 This is the calibration time given that TEST0=0x0B and FSCAL3.CHP_CURR_CAL_EN=10 (max calibration time). Please see DN110 [15] for more details SWRS033H Page 205 of 246 CC1110Fx / CC1111Fx set to the centre of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, f carrier f ref 216 FREQ CHAN (256 With a reference frequency, fRef, equal to 26 MHz, the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing one solution is to use 333 kHz channel spacing and select each third channel in CHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is given by: f IF f ref 210 FREQ _ IF CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by: CHANSPC _ M ) 2CHANSPC _ E 2 ® Note that the SmartRF Studio software [9] automatically calculates the optimum register setting based on channel spacing and channel filter bandwidth. If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state. 13.14 VCO The VCO is completely integrated on-chip. 13.14.1 VCO and PLL Self-Calibration The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, CC1110Fx/CC1111Fx includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of fRef periods for completing the PLL calibration is given in Table 71 on Page 205. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode. Note that the calibration values are maintained in power-down modes PM1/2/3, so the calibration is still valid after waking up from these power-down modes (unless supply voltage or temperature has changed significantly). 13.15 Output Power Programming The RF output power level from the device has two levels of programmability, as illustrated in Figure 56. Firstly, the PA_TABLE7 PA_TABLE0 registers can hold up to eight user selected output power settings. Secondly, the 3-bit FREND0.PA_POWER value selects the PA_TABLE7 - PA_TABLE0 register to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK modulation shaping. All the PA power settings in the PA_TABLE7 - PA_TABLE0 registers, from index 0 up to the index set by FREND0.PA_POWER, values are used. The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWER to zero and then program the desired output power to PA_TABLE0 register. If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively, i.e. PA_TABLE0 and PA_TABLE1. Table 72 contains recommended PA_TABLE settings for various output levels and frequency bands. Using PA settings from 0x68 to 0x6F is not recommended. SWRS033H Page 206 of 246 CC1110Fx / CC1111Fx 315 MHz 433 MHz 868 MHz 915 MHz Output Power [dBm] Setting Current Consumption, Typ. [mA] Setting Current Consumption, Typ. [mA] Setting Current Consumption, Typ. [mA] Setting Current Consumption, Typ. [mA] –30 0x12 14 0x12 15 0x03 16 0x03 16 –20 0x0D 15 0x0E 16 0x0E 17 0x0D 16 –15 0x1C 16 0x1D 16 0x1E 17 0x1D 17 –10 0x34 17 0x34 18 0x27 19 0x26 18 –5 0x2B 19 0x2C 20 0x8F 19 0x57 18 0 0x51 19 0x60 20 0x50 21 0x8E 21 5 0x85 22 0x84 23 0x84 25 0x83 25 7 0xCB 25 0xC8 28 0xCB 31 0xC7 31 10 0xC2 31 0xC0 33 0xC2 36 0xC0 36 Table 72: Optimum PA_TABLE Settings for Various Output Power Levels and Frequency Bands 13.16 Shaping and PA Ramping With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate. The counter saturates at FREND0.PA_POWER and 0 respectively. This counter value can be viewed as an index for a lookup table in the power table (see Figure 56). Thus, in order to utilize the whole table, FREND0.PA_POWER should be 7 when ASK is active. The shaping of the ASK signal is dependent on the configuration of PA_TABLE7 - PA_TABLE0 registers. Figure 57 shows some examples of ASK shaping. PA_TABLE7[7:0] The PA uses this setting. PA_TABLE6[7:0] PA_TABLE5[7:0] PA_TABLE4[7:0] Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for ASK/OOK modulation. PA_TABLE3[7:0] PA_TABLE2[7:0] PA_TABLE1[7:0] PA_TABLE0[7:0] Index into PA_TABLE The SmartRF® Studio software should be used to obtain optimum PA_TABLE settings for various output powers. e.g 6 PA_POWER[2:0] in FREND0 register Figure 56: PA_POWER and PA_TABLE Output Power PA_TABLE7 PA_TABLE6 PA_TABLE5 PA_TABLE4 PA_TABLE3 PA_TABLE2 PA_TABLE1 PA_TABLE0 1 0 0 1 0 1 1 0 Time Bit Sequence FREND0.PA_POWER = 3 FREND0.PA_POWER = 7 Figure 57: Shaping of ASK Signal SWRS033H Page 207 of 246 CC1110Fx / CC1111Fx 13.17 Selectivity Figure 58 to Figure 60 show the typical selectivity performance (adjacent and alternate rejection). 50.0 40.0 Selectivity [dB] 30.0 20.0 10.0 0.0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 -10.0 -20.0 Frequency offset [MHz] Figure 58: Typical Selectivity at 1.2 kBaud @ 868 MHz. IF Frequency is 152 kHz. MDMCFG2.DEM_DCFILT_OFF=0 50.0 40.0 Selectivity [dB] 30.0 20.0 10.0 0.0 -1.0 -0.8 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 0.8 1.0 -10.0 -20.0 Frequency offset [MHz] Figure 59: Typical Selectivity at 38.4 kBaud@ 868 MHz. IF Frequency is 152 kHz. MDMCFG2.DEM_DCFILT_OFF=0 SWRS033H Page 208 of 246 CC1110Fx / CC1111Fx 50.0 40.0 Selectivity [dB] 30.0 20.0 10.0 0.0 -3.00 -2.25 1.50 -1.00 -0.75 0.00 0.75 1.00 1.50 2.25 3.00 -10.0 -20.0 Frequency offset [MHz] Figure 60: Typical Selectivity at 250 kBaud @ 868 MHz. IF Frequency is 304 kHz. MDMCFG2.DEM_DCFILT_OFF=0 13.18 System Considerations and Guidelines 13.18.1 SRD/ISM Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz or 915 MHz frequency bands. The CC1110Fx/CC1111Fx is specifically designed for such use with its 300 - 348 MHz, 391 - 464 MHz, and 782 - 928 MHz operating ranges. The most important regulations when using the CC1110Fx/CC1111Fx in the 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 part 15 (USA). A summary of the most important aspects of these regulations can be found in [10] or [11]. Please note that compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to ensure that the system complies with regulations. 13.18.2 Frequency Hopping Channel Systems and Multi- The 433 MHz, 868 MHz, or 915 MHz are shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading. Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC1110Fx/CC1111Fx. There are 3 ways of obtaining the calibration data from the chip: 1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately 24 735 µs and the blanking interval between each frequency hop is then approximately 799 24 μs when fRef is 26 MHz. When fRef is 24 MHz, 24 24 these numbers are 796 μs and 865 μs respectively. 2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in memory. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. The PLL turn on time is 24 approximately 75 µs when fRef is 26 MHz and 24 81 µs when fRef is 24 MHz. The blanking interval between each frequency hop is then approximately equal to the PLL turn on time. The VCO current calibration result is available in FSCAL2 and is not dependent on the RF frequency. Neither is the charge pump current calibration result available in FSCAL3. The same value can therefore be used for all frequencies. 24 The system clock frequency is equal to f Ref and no PA ramping/shaping is implemented. Max calibration time is used (TEST0=0x0B and FSCAL3.CHP_CURR_CAL_EN=10) Please see DN110 [15] for more details. SWRS033H Page 209 of 246 CC1110Fx / CC1111Fx 3) Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4] strobe SRX (or STX) with MCSM0.FS_AUTOCAL=01 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done but not charge pump current calibration. When charge pump current calibration is disabled the calibration 24 25 time is reduced from 735 µs to 168 µs 24 when fRef is 26 MHz and from 799 µs to 182 25 µs when fRef is 24 MHz. The blanking interval between each frequency hop is then 243 µs and 263 µs respectively. There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3) gives 631 µs smaller blanking interval than solution 1 when fRef is 26 MHz and 683 µs smaller blanking interval than solution 1 when fRef is 24 MHz). 13.18.3 Wideband Modulation Spread Spectrum not Using Digital modulation systems under FCC part 15.247 includes 2-FSK and GFSK modulation. A maximum peak output power of 1 W (30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than 8 dBm in any 3 kHz band. Pleas refer to DN006 [12] for further details concerning wideband modulation and CC1110Fx/CC1111Fx. Operating with high frequency separation, the CC1110Fx/CC1111Fx is suited for systems targeting compliance with digital modulation systems as defined by FCC part 15.247. An external power amplifier is needed to increase the output above 10 dBm. 13.18.4 Data Burst Transmissions The maximum data rate of opens up for burst transmissions. A low average data rate link (e.g. 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in active mode, and hence also reduce the average current consumption significantly. Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequency range. Note that sensitivity and thus transmission range is reduced in high data rate bursts compared to lower data rates. 13.18.5 Crystal Drift Compensation The CC1110Fx/CC1111Fx has a very fine frequency resolution (see Table 16). This feature can be used to compensate for frequency offset and drift. The frequency offset between an ‘external’ transmitter and the receiver is measured in the CC1110Fx/CC1111Fx and can be read back from the FREQEST status register as described in Section 13.7.1. The measured frequency offset can be used to calibrate the frequency using the ‘external’ transmitter as the reference. That is, the received signal of the device will match the receiver’s channel filter better. In the same way the centre frequency of the transmitted signal will match the ‘external’ transmitter’s signal. 13.18.6 Spectrum Efficient Modulation CC1110Fx/CC1111Fx also has the possibility to use Gaussian shaped 2-FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In ‘true’ 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift ‘softer’, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK. 13.18.7 Low Cost Systems A HC-49 type SMD crystal is used in the CC1110EM reference design [1]. Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used. high CC1110Fx/CC1111Fx 13.18.8 Battery Operated Systems In low power applications, PM2 or PM3 should be used when the CC1110Fx/CC1111Fx is not active. The Sleep Timer can be used in PM2. 25 TEST0=0x0B. Please see DN110 [15] for more details. SWRS033H Page 210 of 246 CC1110Fx / CC1111Fx 13.18.9 Increasing Output Power In some applications it may be necessary to extend the link range. Adding an external power amplifier is the most effective way of doing this. The power amplifier should be inserted between the antenna and the balun, and two T/R switches are needed to disconnect the PA in RX mode. See Figure 61. Antenna Filter PA CC1110Fx / Balun T/R switch CC1111Fx T/R switch Figure 61: Block Diagram of CC1110Fx/CC1111Fx Usage with External Power Amplifier SWRS033H Page 211 of 246 CC1110Fx / CC1111Fx 13.19 Radio Registers This section describes all RF registers used for control and status for the radio. 0xDF2F: IOCFG2 - Radio Test Signal Configuration (P1_7) Bit Field Name 7 Reset R/W Description - R0 Not used 6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO2_CFG[5:0] 000000 R/W Debug output on P1_7 pin. See Table 73 for a description of internal signals which can be output on this pin for debug purpose 0xDF30: IOCFG1 - Radio Test Signal Configuration (P1_6) Bit Field Name Reset R/W Description 7 GDO_DS 0 R/W Drive strength control for I/O pins in output mode. Selects output drive capability to account for low I/O supply voltage VDD on pin DVDD 6 5:0 GDO1_INV GDO1_CFG[5:0] 0 000000 R/W R/W 0 Minimum drive capability. VDD equal or greater than 2.6 V 1 Maximum drive capability. VDD less than 2.6 V Invert output 0 Active high 1 Active low Debug output on P1_6 pin. See Table 73 for a description of internal signals which can be output on this pin for debug purpose 0xDF31: IOCFG0 - Radio Test Signal Configuration (P1_5) Bit Field Name 7 Reset R/W Description - R0 Not used 6 GDO0_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO0_CFG[5:0] 000000 R/W Debug output on P1_5 pin. See Table 73 for a description of internal signals which can be output on this pin for debug purpose. 0xDF00: SYNC1 - Sync Word, High Byte Bit Field Name Reset R/W Description 7:0 SYNC[15:8] 0xD3 R/W 8 MSB of 16-bit sync word 0xDF01: SYNC0 - Sync Word, Low Byte Bit Field Name Reset R/W Description 7:0 SYNC[7:0] 0x91 R/W 8 LSB of 16-bit sync word 0xDF02: PKTLEN - Packet Length Bit Field Name Reset R/W Description 7:0 PACKET_LENGTH 0xFF R/W Indicates the packet length when fixed length packets are enabled. If variable length packets are used, this value indicates the maximum length packets allowed SWRS033H Page 212 of 246 CC1110Fx / CC1111Fx 0xDF03: PKTCTRL1 - Packet Automation Control Bit Field Name Reset R/W Description 7:5 PQT[2:0] 000 R/W Preamble quality estimator threshold. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. A threshold of 4∙PQT for this counter is used to gate sync word detection. When PQT=0 a sync word is always accepted 4:3 - R0 Not used 2 APPEND_STATUS 1 R/W When enabled, two status bytes will be appended to the payload of the packet. The status bytes contain RSSI and LQI values, as well as the CRC OK flag 1:0 ADR_CHK[1:0] 00 R/W Controls address check configuration of received packages. 00 No address check 01 Address check, no broadcast 10 Address check, 0 (0x00) broadcast 11 Address check, 0 (0x00) and 255 (0xFF) broadcast 0xDF04: PKTCTRL0 - Packet Automation Control Bit Field Name 7 6 5:4 WHITE_DATA PKT_FORMAT[1:0] 3 2 1:0 CRC_EN LENGTH_CONFIG[1:0] Reset R/W Description - R0 Not used 1 R/W Whitening enable. Data whitening can only be used when PKTCTRL0.CC2400_EN=0 (default). 00 R/W 0 Disabled 1 Enabled Packet format of RX and TX data 00 Normal mode 01 Reserved 10 Random TX mode; sends random data using PN9 generator. Used for test. Works as normal mode, setting 00, in RX. 11 Reserved 0 R/W Reserved. Always write 0 1 R/W CRC calculation in TX and CRC check in RX enable 01 R/W 0 Disable 1 Enable Packet Length Configuration 00 Fixed packet length mode. Length configured in PKTLEN register 01 Variable packet length mode. Packet length configured by the first byte after sync word 10 Reserved 11 Reserved SWRS033H Page 213 of 246 CC1110Fx / CC1111Fx 0xDF05: ADDR - Device Address Bit Field Name Reset R/W Description 7:0 DEVICE_ADDR[7:0] 0x00 R/W Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF). 0xDF06: CHANNR - Channel Number Bit Field Name Reset R/W Description 7:0 CHAN[7:0] 0x00 R/W The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency. 0xDF07: FSCTRL1 - Frequency Synthesizer Control Bit Reset R/W Description 7:6 - R0 Not used 5 0 R/W Reserved 01111 R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. 4:0 Field Name FREQ_IF[4:0] f ref f IF FREQ _ IF 210 The default value gives an IF frequency of 381 kHz when fRef = 26 MHz and 352 kHz when fRef = 24 MHz. 0xDF08: FSCTRL0 - Frequency Synthesizer Control Bit Field Name Reset R/W Description 7:0 FREQOFF[7:0] 0x00 R/W Frequency offset added to the base frequency before being used by the FS. (2’s complement). Resolution is fRef /214 Range is ±202 kHz to ±209 kHz for CC1110Fx and ±186 kHz for CC1111Fx 0xDF09: FREQ2 - Frequency Control Word, High Byte Bit Field Name Reset R/W Description 7:6 FREQ[23:22] 01 R FREQ[23:22] 5:0 FREQ[21:16] 011110 R/W FREQ[23:0] is the base frequency for the frequency synthesizer in increments of fRef /216. f carrier f ref 216 FREQ 23 : 0 0xDF0A: FREQ1 - Frequency Control Word, Middle Byte Bit Field Name Reset R/W Description 7:0 FREQ[15:8] 11000100 R/W Ref. FREQ2 register 0xDF0B: FREQ0 - Frequency Control Word, Low Byte Bit Field Name Reset R/W Description 7:0 FREQ[7:0] 11101100 R/W Ref. FREQ2 register SWRS033H Page 214 of 246 CC1110Fx / CC1111Fx 0xDF0C: MDMCFG4 - Modem configuration Bit Field Name Reset R/W 7:6 CHANBW_E[1:0] 10 R/W 5:4 CHANBW_M[1:0] 00 R/W Description Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. f ref BWchannel 8 (4 CHANBW _ M )·2CHANBW _ E The default values give 203 kHz channel filter bandwidth when fRef = 26 MHz and 188 kHz when fRef = 24 MHz. 3:0 DRATE_E[3:0] 1100 R/W The exponent of the user specified symbol rate. 0xDF0D: MDMCFG3 - Modem Configuration Bit Field Name Reset R/W Description 7:0 DRATE_M[7:0] 0x22 R/W The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden ‘1’. The resulting data rate is: RDATA 256 DRATE _ M 2 28 2 DRATE _ E f ref The default values give a data rate of 115.051 kBaud when fRef = 26 MHz and 106.201 kHz when fRef = 24 MHz. SWRS033H Page 215 of 246 CC1110Fx / CC1111Fx 0xDF0E: MDMCFG2 - Modem Configuration Bit Field Name Reset R/W Description 7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator. The recommended IF frequency changes when the DC blocking is disabled. Please use SmartRF Studio [9] to calculate correct register setting. 6:4 MOD_FORMAT[2:0] 000 R/W 0 Enable Better Sensitivity 1 Disable Current optimized. Only for data rates ≤ 100 kBaud The modulation format of the radio signal 000 2-FSK 001 GFSK 010 Reserved 011 ASK/OOK 100 Reserved 101 Reserved 110 Reserved 111 MSK Note that MSK is only supported for data rates above 26 kBaud and GFSK, ASK , and OOK is only supported for data rate up until 250 kBaud. MSK cannot be used if Manchester encoding/decoding is enabled. 3 MANCHESTER_EN 0 R/W Manchester encoding/decoding enable 0 Disable 1 Enable Note that Manchester encoding/decoding cannot be used at the same time as using the FEC/Interleaver option or when using MSK modulation. 2:0 SYNC_MODE[2:0] 010 R/W Sync-word qualifier mode. The values 000 and 100 disables preamble and sync word transmission in TX and preamble and sync word detection in RX. The values 001, 010, 101 and 110 enables 16-bit sync word transmission in TX and 16-bits sync word detection in RX. Only 15 of 16 bits need to match in RX when using setting 001 or 101. The values 011 and 111 enables repeated sync word transmission in TX and 32-bits sync word detection in RX (only 30 of 32 bits need to match). 000 No preamble/sync 001 15/16 sync word bits detected 010 16/16 sync word bits detected 011 30/32 sync word bits detected 100 No preamble/sync, carrier-sense above threshold 101 15/16 + carrier-sense above threshold 110 16/16 + carrier-sense above threshold 111 30/32 + carrier-sense above threshold SWRS033H Page 216 of 246 CC1110Fx / CC1111Fx 0xDF0F: MDMCFG1 - Modem Configuration Bit Field Name Reset R/W Description 7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for packet payload. FEC is only supported for fixed packet length mode, i.e. PKTCTRL0.LENGTH_CONFIG=0 6:4 NUM_PREAMBLE[2:0] 3:2 1:0 CHANSPC_E[1:0] 010 R/W 0 Disable 1 Enable Sets the minimum number of preamble bytes to be transmitted 000 2 001 3 010 4 011 6 100 8 101 12 110 16 111 24 - R0 Not used 10 R/W 2 bit exponent of channel spacing 0xDF10: MDMCFG0 - Modem Configuration Bit Field Name Reset R/W Description 7:0 CHANSPC_M[7:0] 0xF8 R/W 8-bit mantissa of channel spacing (initial 1 assumed). The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: f CHANNEL f ref 218 256 CHANSPC _ M 2 CHANSPC _ E The default values give 199.951 kHz channel spacing when fRef = 26 MHz and 184.570 kHz when fRef = 24 MHz. SWRS033H Page 217 of 246 CC1110Fx / CC1111Fx 0xDF11: DEVIATN - Modem Deviation Setting Bit Field Name 7 6:4 DEVIATION_E[2:0] 3 2:0 DEVIATION_M[2:0] Reset R/W Description - R0 Not used 100 R/W Deviation exponent - R0 Not used 111 R/W TX 2-FSK/ GFSK Specifies the nominal frequency deviation from the carrier frequency for a ‘0’ (-DEVIATN) and a ‘1’ (+DEVIATN) in a mantissa-exponent format. The resulting deviation is given by: f dev f ref 217 (8 DEVIATION _ M ) 2 DEVIATION _ E The default values give ±47.607 kHz deviation when MHz and 43.945 kHz when fRef = 24 MHz. fRef = 26 MSK Specifies the fraction of a symbol period (1/8-8/8) during which a phase change occurs (‘0’: +90deg, ‘1’: -90deg). Refer to the SmartRF Studio software [9] for correct DEVIATN setting when using MSK. ASK This settings has no effect RX 2-FSK/ GFSK Specifies the expected frequency deviation of incoming signal, must be approximately right for demodulation to be performed reliably and robustly MSK/ASK This settings has no effect 0xDF12: MCSM2 - Main Radio Control State Machine Configuration Bit Field Name 7:5 Reset R/W Description - R0 Not used 4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier sense). For ASK/OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods. 3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires the chip stays in RX mode if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQT is reached when RX_TIME_QUAL=1. 2:0 RX_TIME[2:0] 111 R/W Timeout for sync word search in RX. The timeout is relative to the programmed tEvent0. The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and X is the reference frequency (fRef) in MHz: RX_TIME[2:0] WOR_RES=0 WOR_RES=1 WOR_RES=2 WOR_RES=3 000 3.6058 18.0288 32.4519 46.8750 001 1.8029 9.0144 16.2260 23.4375 010 0.9014 4.5072 8.1130 11.7188 011 0.4507 2.2536 4.0565 5.8594 100 0.2254 1.1268 2.0282 2.9297 101 0.1127 0.5634 1.0141 1.4648 110 0.0563 0.2817 0.5071 0.7324 111 Until end of packet As an example, EVENT0 = 34666, WOR_RES = 0 and RX_TIME = 6 corresponds to 1.96 ms RX timeout SWRS033H Page 218 of 246 CC1110Fx / CC1111Fx 0xDF13: MCSM1 - Main Radio Control State Machine Configuration Bit Field Name 7:6 5:4 3:2 CCA_MODE[1:0] RXOFF_MODE[1:0] Reset R/W Description - R0 Not used 11 R/W Selects CCA_MODE; Reflected in CCA signal 00 R/W 00 Always 01 If RSSI below threshold 10 Unless currently receiving a packet 11 If RSSI below threshold unless currently receiving a packet Select what should happen (next state) when a packet has been received 00 IDLE 01 FSTXON 10 TX 11 Stay in RX It is not possible to set RXOFF_MODE to be TX or FSTXON and at the same time use CCA. 1:0 TXOFF_MODE[1:0] 00 R/W Select what should happen (next state) when a packet has been sent (TX) 00 IDLE 01 FSTXON 10 Stay in TX (start sending preamble) 11 RX 0xDF14: MCSM0 - Main Radio Control State Machine Configuration Bit Field Name 7:6 5:4 FS_AUTOCAL[1:0] Reset R/W Description - R0 Not used 00 R/W Select calibration mode (when to calibrate) 00 Never (manually calibrate using SCAL strobe) 01 When going from IDLE to RX or TX (or FSTXON) 10 When going from RX or TX back to IDLE automatically 11 Every 4th time when going from RX or TX to IDLE automatically 3 0 R/W Reserved. Refer to SmartRF Studio software [9] for settings. 2 1 R/W Reserved. Refer to SmartRF Studio software [9] for settings. 00 R/W Sets RX attenuation. Used in order to avoid saturation in RX when two or more chips are close (within ~3 m). 1:0 CLOSE_IN_RX[1:0] RX attenuation, typical values: 00 0 dB 01 6 dB 10 12 dB 11 18 dB SWRS033H Page 219 of 246 CC1110Fx / CC1111Fx 0xDF15: FOCCFG - Frequency Offset Compensation Configuration Bit Field Name Reset R/W Description 7 - R0 Not used 6 1 R/W Reserved. Always write 0 5 FOC_BS_CS_GATE 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CARRIER_SENSE signal goes high. 4:3 FOC_PRE_K[1:0] 10 R/W The frequency compensation loop gain to be used before a sync word is detected. 2 1:0 FOC_POST_K FOC_LIMIT[1:0] 1 10 R/W R/W 00 K 01 2K 10 3K 11 4K The frequency compensation loop gain to be used after a sync word is detected. 0 Same as FOC_PRE_K 1 K/2 The saturation point for the frequency offset compensation algorithm: 00 ±0 (no frequency offset compensation) 01 ±BWCHAN / 8 10 ±BW CHAN / 4 11 ±BW CHAN / 2 Frequency offset compensation is not supported for ASK/OOK; Always use FOC_LIMIT=0 with these modulation formats. SWRS033H Page 220 of 246 CC1110Fx / CC1111Fx 0xDF16: BSCFG - Bit Synchronization Configuration Bit Field Name Reset R/W Description 7:6 BS_PRE_KI[1:0] 01 R/W The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): 5:4 3 2 1:0 BS_PRE_KP[1:0] BS_POST_KI BS_POST_KP BS_LIMIT[1:0] 10 1 1 00 R/W R/W R/W R/W 00 KI 01 2KI 10 3KI 11 4KI The clock recovery feedback loop proportional gain to be used before a sync word is detected 00 KP 01 2KP 10 3KP 11 4KP The clock recovery feedback loop integral gain to be used after a sync word is detected. 0 Same as BS_PRE_KI 1 KI /2 The clock recovery feedback loop proportional gain to be used after a sync word is detected. 0 Same as BS_PRE_KP 1 KP The saturation point for the data rate offset compensation algorithm: 00 ±0 (No data rate offset compensation performed) 01 ±3.125% data rate offset 10 ±6.25% data rate offset 11 ±12.5% data rate offset SWRS033H Page 221 of 246 CC1110Fx / CC1111Fx 0xDF17: AGCCTRL2 - AGC Control Bit Field Name Reset R/W Description 7:6 MAX_DVGA_GAIN[1:0] 00 R/W Reduces the maximum allowable DVGA gain. 5:3 2:0 MAX_LNA_GAIN[2:0] MAGN_TARGET[2:0] 000 011 R/W R/W 00 All gain settings can be used 01 The highest gain setting can not be used 10 The 2 highest gain settings can not be used 11 The 3 highest gain settings can not be used Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain. 000 Maximum possible LNA + LNA 2 gain 001 Approx. 2.6 dB below maximum possible gain 010 Approx. 6.1 dB below maximum possible gain 011 Approx. 7.4 dB below maximum possible gain 100 Approx. 9.2 dB below maximum possible gain 101 Approx. 11.5 dB below maximum possible gain 110 Approx. 14.6 dB below maximum possible gain 111 Approx. 17.1 dB below maximum possible gain These bits set the target value for the averaged amplitude from the digital channel filter (1 LSB = 0 dB). 000 24 dB 001 27 dB 010 30 dB 011 33 dB 100 36 dB 101 38 dB 110 40 dB 111 42 dB SWRS033H Page 222 of 246 CC1110Fx / CC1111Fx 0xDF18: AGCCTRL1 - AGC Control Bit Field Name 7 Reset R/W Description - R0 Not used 6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA2 gain is decreased to minimum before decreasing LNA gain. 5:4 CARRIER_SENSE_REL_THR[1:0] 00 R/W Sets the relative change threshold for asserting carrier sense 3:0 CARRIER_SENSE_ABS_THR[3:0] 0000 R/W 00 Relative carrier sense threshold disabled 01 6 dB increase in RSSI value 10 10 dB increase in RSSI value 11 14 dB increase in RSSI value Sets the absolute RSSI threshold for asserting carrier sense (Equal to channel filter amplitude when AGC has not decreased gain). The 2-complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN_TARGET setting. 1000 (–8) Absolute carrier sense threshold disabled 1001 (–7) 7 dB below MAGN_TARGET setting … … 1111 (–1) 1 dB below MAGN_TARGET setting 0000 (0) At MAGN_TARGET setting 0001 (1) 1 dB above MAGN_TARGET setting … … 0111 (7) 7 dB above MAGN_TARGET setting SWRS033H Page 223 of 246 CC1110Fx / CC1111Fx 0xDF19: AGCCTRL0 - AGC Control Bit Field Name Reset R/W Description 7:6 HYST_LEVEL[1:0] 10 R/W Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determines gain changes). 5:4 3:2 1:0 WAIT_TIME[1:0] AGC_FREEZE[1:0] FILTER_LENGTH[1:0] 01 00 01 R/W R/W R/W 00 No hysteresis, small symmetric dead zone, high gain 01 Low hysteresis, small asymmetric dead zone, medium gain 10 Medium hysteresis, medium asymmetric dead zone, medium gain 11 Large hysteresis, large asymmetric dead zone, low gain Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples. 00 8 01 16 10 24 11 32 Controls when the AGC gain should be frozen. 00 Normal operation. Always adjust gain when required. 01 The gain setting is frozen when a sync word has been found. 10 Manually freeze the analog gain setting and continue to adjust the digital gain. 11 Manually freezes both the analog and the digital gain settings. Used for manually overriding the gain. Sets the averaging length for the amplitude from the channel filter. Sets the OOK/ASK decision boundary for OOK/ASK reception. Please use the SmartRF Studio software [9] for recommended settings. 00 8 01 16 10 32 11 64 0xDF1A: FREND1 - Front End RX Configuration Bit Field Name Reset R/W Description 7:6 LNA_CURRENT[1:0] 01 R/W Adjusts front-end LNA PTAT current output 5:4 LNA2MIX_CURRENT[1:0] 01 R/W Adjusts front-end PTAT outputs 3:2 LODIV_BUF_CURRENT_RX[1:0] 01 R/W Adjusts current in RX LO buffer (LO input to mixer) 1:0 MIX_CURRENT[1:0] 10 R/W Adjusts current in mixer SWRS033H Page 224 of 246 CC1110Fx / CC1111Fx 0xDF1B: FREND0 - Front End TX Configuration Bit Field Name 7:6 5:4 LODIV_BUF_CURRENT_TX[1:0] 3 2:0 PA_POWER[2:0] Reset R/W Description - R0 Not used 01 R/W Adjusts current TX LO buffer (input to PA). The value to use in this field is given by the SmartRF Studio software [9]. - R0 Not used 000 R/W Selects PA power setting. This value is an index to the PATABLE (PA_TABLE7 - PA_TABLE0 registers), which can be programmed with up to 8 different PA settings. In ASK mode, this selects the PATABLE index to use when transmitting a ‘1’. PATABLE index zero is used in ASK when transmitting a ‘0’. The PATABLE settings from index ‘0’ to the PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats. 0xDF1C: FSCAL3 - Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 FSCAL3[7:6] 10 R/W Frequency synthesizer calibration configuration. The value to write in this register before calibration is given by the SmartRF Studio software [9]. 5:4 CHP_CURR_CAL_EN[1:0] 10 R/W Disable charge pump calibration stage when 0 3:0 FSCAL3[3:0] 1001 R/W Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an exponential scale: IOUT=I0·2FSCAL3[3:0]/4 Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 0xDF1D: FSCAL2 - Frequency Synthesizer Calibration Bit Field Name 7:6 5 4:0 VCO_CORE_H_EN FSCAL2[4:0] Reset R/W Description - R0 Not used 0 R/W Select VCO 01010 R/W 0 Low 1 High Frequency synthesizer calibration result register. VCO current calibration result and override value Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. SWRS033H Page 225 of 246 CC1110Fx / CC1111Fx 0xDF1E: FSCAL1 - Frequency Synthesizer Calibration Bit Field Name 7:6 5:0 FSCAL1[5:0] Reset R/W Description - R0 Not used 100000 R/W Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 0xDF1F: FSCAL0 - Frequency Synthesizer Calibration Bit Field Name 7 6:0 FSCAL0[6:0] Reset R/W Description - R0 Not used 0001101 R/W Frequency synthesizer calibration control. The value to use in this register is given by the SmartRF Studio software [9]. 0xDF23: TEST2 - Various Test Settings Bit Field Name Reset R/W Description 7:0 TEST2[7:0] 0x88 R/W At low data rates, the sensitivity can be improved by changing it to 0x81 (MDMCFG2.DEM_DCFILT_OFF should be 0). 0xDF24: TEST1 - Various Test Settings Bit Field Name Reset R/W Description 7:0 TEST1[7:0] 0x11 R/W Always set this register to 0x31 when being in TX. At low data rates, the sensitivity can be improved by changing it to 0x35 in RX. (MDMCFG2.DEM_DCFILT_OFF should be 0). 0xDF25: TEST0 - Various Test Settings Bit Field Name Reset R/W Description 7:2 TEST0[7:2] 000010 R/W The value to use in this register is given by the SmartRF Studio software [9]. 1 VCO_SEL_CAL_EN 1 R/W Enable VCO selection calibration stage when 1 0 TEST0[0] 1 R/W The value to use in this register is given by the SmartRF Studio software [9]. 0xDF27: PA_TABLE7 - PA Power Setting 7 Bit Field Name Reset R/W Description 7:0 PA_TABLE7[7:0] 0x00 R/W Power amplifier output power setting 7 0xDF28: PA_TABLE6 - PA Power Setting 6 Bit Field Name Reset R/W Description 7:0 PA_TABLE6[7:0] 0x00 R/W Power amplifier output power setting 6 SWRS033H Page 226 of 246 CC1110Fx / CC1111Fx 0xDF29: PA_TABLE5 - PA Power Setting 5 Bit Field Name Reset R/W Description 7:0 PA_TABLE5[7:0] 0x00 R/W Power amplifier output power setting 5 0xDF2A: PA_TABLE4 - PA Power Setting 4 Bit Field Name Reset R/W Description 7:0 PA_TABLE4[7:0] 0x00 R/W Power amplifier output power setting 4 0xDF2B: PA_TABLE3 - PA Power Setting 3 Bit Field Name Reset R/W Description 7:0 PA_TABLE3[7:0] 0x00 R/W Power amplifier output power setting 3 0xDF2C: PA_TABLE2 - PA Power Setting 2 Bit Field Name Reset R/W Description 7:0 PA_TABLE2[7:0] 0x00 R/W Power amplifier output power setting 2 0xDF2D: PA_TABLE1 - PA Power Setting 1 Bit Field Name Reset R/W Description 7:0 PA_TABLE1[7:0] 0x00 R/W Power amplifier output power setting 1 0xDF2E: PA_TABLE0 - PA Power Setting 0 Bit Field Name Reset R/W Description 7:0 PA_TABLE0[7:0] 0x00 R/W Power amplifier output power setting 0 0xDF36: PARTNUM - Chip ID[15:8] Bit Field Name Reset R/W Description 7:0 PARTNUM[7:0] 0x01 CC1110Fx 0x11 CC1111Fx R Chip part number 0xDF37: VERSION - Chip ID[7:0] Bit Field Name Reset R/W Description 7:0 VERSION[7:0] 0x03 R Chip version number. 0xDF38: FREQEST - Frequency Offset Estimate from Demodulator Bit Field Name Reset R/W Description 7:0 FREQOFF_EST 0x00 R The estimated frequency offset (2’s complement) of the carrier. Resolution is fRef/214 Range is ±202 kHz to ±209 kHz for CC1110Fx and ±186 kHz for CC1111Fx Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK modulation. This register will read 0 when using ASK or OOK modulation. SWRS033H Page 227 of 246 CC1110Fx / CC1111Fx 0xDF39: LQI - Demodulator Estimate for Link Quality Bit Field Name Reset R/W Description 7 CRC_OK 0 R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6:0 LQI_EST[6:0] 0000000 R The Link Quality Indicator estimates how easily a received signal can be demodulated. Calculated over the 64 symbols following the sync word. 0xDF3A: RSSI - Received Signal Strength Indication Bit Field Name Reset R/W Description 7:0 RSSI 0x80 R Received signal strength indicator 0xDF3B: MARCSTATE - Main Radio Control State Machine State Bit Field Name 7:5 4:0 MARC_STATE[4:0] Reset R/W Description - R0 Not used 0001 R Main Radio Control FSM State Value State Name State (Figure 55, Page203) 00000 SLEEP SLEEP 00001 IDLE IDLE 00010 Not used 00011 VCOON_MC MANCAL 00100 REGON_MC MANCAL 00101 MANCAL MANCAL 00110 VCOON FS_WAKEUP 00111 REGON FS_WAKEUP 01000 STARTCAL CALIBRATE 01001 BWBOOST SETTLING 01010 FS_LOCK SETTLING 01011 IFADCON SETTLING 01100 ENDCAL CALIBRATE 01101 RX RX 01110 RX_END RX 01111 RX_RST RX 10000 TXRX_SWITCH TXRX_SETTLING 10001 RX_OVERFLO W RX_OVERFLOW 10010 FSTXON FSTXON 10011 TX TX 10100 TX_END TX 10101 RXTX_SWITCH RXTX_SETTLING 10110 TX_UNDERFLO W TX_UNDERFLOW SWRS033H Page 228 of 246 CC1110Fx / CC1111Fx 0xDF3C: PKTSTATUS - Packet Status Bit Field Name Reset R/W Description 7 CRC_OK 0 R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6 CS 0 R Carrier sense 5 PQT_REACHED 0 R Preamble Quality reached 4 CCA 0 R Channel is clear 3 SFD 0 R Asserted when sync word has been sent / received, and de-asserted at the end of the packet. In RX, this bit will de-assert when the optional address check fails or the radio enter RX_OVERFLOW state. In TX this bit will deassert if the radio enters TX_UNDERFLOW state. - R0 Not used 2:0 0xDF3D: VCO_VC_DAC - Current Setting from PLL Calibration Module Bit Field Name Reset R/W Description 7:0 VCO_VC_DAC[7:0] 0x94 R Status register for test only. SWRS033H Page 229 of 246 CC1110Fx / CC1111Fx 14 Voltage Regulators The CC1110Fx/CC1111Fx includes a low drop-out voltage regulator. This is used to provide a 1.8 V power supply to the CC1110Fx/CC1111Fx digital power supply. The voltage regulator should not be used to provide power to external circuits because of limited power sourcing capability and also due to noise considerations. The voltage regulator input pin AVDD_DREG is to be connected to the unregulated 2.0 V to 3.6 V power supply. The output of the digital regulator is connected internally in the CC1110Fx/CC1111Fx to the digital power supply. The voltage regulator requires an external decoupling capacitor connected to the DCOUPL pin as described in Section 9 on Page 36. 14.1 Voltage Regulator Power-on The voltage regulator is disabled when the CC1110Fx/CC1111Fx is placed in power modes PM2 or PM3 (see Section 12.1). When the 15 voltage regulator is disabled, register and RAM contents will be retained while the unregulated 2.0 V - 3.6 V power supply is present. Radio Test Output Signals For debug and test purposes, a number of internal status signals in the radio may be output on the port pins P1_7 - P1_5. This debug option is controlled through the RF registers IOCFG2 - IOCFG0. Table 73 shows the value written to IOCFGx.GDOx_CFG[5:0] with the corresponding internal signals that will be output in each case. Setting IOCFGx.GDOx_CFG to a value other than 0 will override the P1SEL_SELP1_7, P1SEL_SELP1_6, and P1SEL_SELP1_5 settings, and the pins will automatically become outputs. SWRS033H Page 230 of 246 CC1110Fx / CC1111Fx GDO0_CFG[5:0] GDO1_CFG[5:0] GDO2_CFG[5:0] Description 000000 The pin is configured according to the I/O registers. See 12.4.7 000001 - 000111 Reserved 001000 Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value. 001001 Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting) 001010 - 001101 Reserved 001110 Carrier sense. High if RSSI level is above threshold. 001111 CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. 010000 - 010101 Reserved 010110 RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. 010111 RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. 011000 - 011010 Reserved 011011 PA_PD. Can be used to control an external PA or RX/TX switch. Signal is asserted when the radio enters TX state and de-asserted when the radio exits TX state. The signal is active low 011100 LNA_PD. Can be used to control an external LNA or RX/TX switch. Signal is asserted when the radio enters RX state and de-asserted when the radio exits RX state. The signal is active low 011101 RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output. 011110 - 101110 Reserved 101111 HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch. 110000 - 111111 Reserved Table 73: Radio Test Output Signals SWRS033H Page 231 of 246 CC1110Fx / CC1111Fx 16 Register Overview MPAGE (0x93) - Memory Page Select ......................................................................................... 53 MEMCTR (0xC7) - Memory Arbiter Control ............................................................................... 54 DPH0 (0x83) - Data Pointer 0 High Byte ...................................................................................... 54 DPL0 (0x82) - Data Pointer 0 Low Byte ....................................................................................... 54 DPH1 (0x85) - Data Pointer 1 High Byte ...................................................................................... 54 DPL1 (0x84) - Data Pointer 1 Low Byte ....................................................................................... 54 DPS (0x92) - Data Pointer Select .................................................................................................. 55 PSW (0xD0) - Program Status Word ............................................................................................. 55 ACC (0xE0) - Accumulator ........................................................................................................... 56 B (0xF0) - B Register..................................................................................................................... 56 SP (0x81) - Stack Pointer ............................................................................................................... 56 IEN1 (0xB8) - Interrupt Enable 1 Register .................................................................................... 63 IEN2 (0x9A) - Interrupt Enable 2 Register .................................................................................... 64 TCON (0x88) - CPU Interrupt Flag 1 ............................................................................................ 65 S0CON (0x98) - CPU Interrupt Flag 2 .......................................................................................... 66 S1CON (0x9B) - CPU Interrupt Flag 3 ......................................................................................... 66 IRCON (0xC0) - CPU Interrupt Flag 4 .......................................................................................... 67 IRCON2 (0xE8) - CPU Interrupt Flag 5 ........................................................................................ 68 IP1 (0xB9) - Interrupt Priority 1 .................................................................................................... 68 IP0 (0xA9) - Interrupt Priority 0 .................................................................................................... 69 PCON (0x87) - Power Mode Control ............................................................................................ 78 SLEEP (0xBE) - Sleep Mode Control ........................................................................................... 79 CLKCON (0xC6) - Clock Control ................................................................................................. 82 FCTL (0xAE) - Flash Control........................................................................................................ 89 FWDATA (0xAF) - Flash Write Data ........................................................................................... 89 FADDRH (0xAD) - Flash Address High Byte .............................................................................. 89 FADDRL (0xAC) - Flash Address Low Byte ............................................................................... 89 FWT (0xAB) - Flash Write Timing ............................................................................................... 89 P0 (0x80) - Port 0........................................................................................................................... 95 P1 (0x90) - Port 1........................................................................................................................... 95 P2 (0xA0) - Port 2 .......................................................................................................................... 95 PERCFG (0xF1) - Peripheral Control ............................................................................................ 95 ADCCFG (0xF2) - ADC Input Configuration ............................................................................... 96 P0SEL (0xF3) - Port 0 Function Select ......................................................................................... 96 P1SEL (0xF4) - Port 1 Function Select ......................................................................................... 96 P2SEL (0xF5) - Port 2 Function Select ......................................................................................... 97 P0DIR (0xFD) - Port 0 Direction................................................................................................... 97 P1DIR (0xFE) - Port 1 Direction ................................................................................................... 97 P2DIR (0xFF) - Port 2 Direction ................................................................................................... 98 P0INP (0x8F) - Port 0 Input Mode ................................................................................................ 98 P1INP (0xF6) - Port 1 Input Mode ................................................................................................ 98 P2INP (0xF7) - Port 2 Input Mode ................................................................................................ 98 P0IFG (0x89) - Port 0 Interrupt Status Flag .................................................................................. 99 P1IFG (0x8A) - Port 1 Interrupt Status Flag.................................................................................. 99 P2IFG (0x8B) - Port 2 Interrupt Status Flag .................................................................................. 99 PICTL (0x8C) - Port Interrupt Control ........................................................................................ 100 P1IEN (0x8D) - Port 1 Interrupt Mask ........................................................................................ 100 DMAARM (0xD6) - DMA Channel Arm ................................................................................... 109 DMAREQ (0xD7) - DMA Channel Start Request and Status ..................................................... 110 DMA0CFGH (0xD5) - DMA Channel 0 Configuration Address High Byte .............................. 110 DMA0CFGL (0xD4) - DMA Channel 0 Configuration Address Low Byte ............................... 110 DMA1CFGH (0xD3) - DMA Channel 1 - 4 Configuration Address High Byte ......................... 110 DMA1CFGL (0xD2) - DMA Channel 1 - 4 Configuration Address Low Byte .......................... 110 SWRS033H Page 232 of 246 CC1110Fx / CC1111Fx DMAIRQ (0xD1) - DMA Interrupt Flag ..................................................................................... 111 ENDIAN (0x95) - USB Endianess Control (CC1111Fx) ................................................................ 111 T1CNTH (0xE3) - Timer 1 Counter High ................................................................................... 120 T1CNTL (0xE2) - Timer 1 Counter Low .................................................................................... 120 T1CTL (0xE4) - Timer 1 Control and Status ............................................................................... 120 T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control ............................................. 121 T1CC0H (0xDB) - Timer 1 Channel 0 Capture/Compare Value High........................................ 121 T1CC0L (0xDA) - Timer 1 Channel 0 Capture/Compare Value Low ........................................ 121 T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control ............................................. 122 T1CC1H (0xDD) - Timer 1 Channel 1 Capture/Compare Value High ....................................... 122 T1CC1L (0xDC) - Timer 1 Channel 1 Capture/Compare Value Low......................................... 122 T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control ............................................. 123 T1CC2H (0xDF) - Timer 1 Channel 2 Capture/Compare Value High ........................................ 123 T1CC2L (0xDE) - Timer 1 Channel 2 Capture/Compare Value Low ......................................... 123 T2CTL (0x9E) - Timer 2 Control ................................................................................................ 125 T2CT (0x9C) - Timer 2 Count ..................................................................................................... 125 T2PR (0x9D) - Timer 2 Prescaler ................................................................................................ 125 WORTIME0 (0xA5) - Sleep Timer Low Byte ............................................................................ 128 WORTIME1 (0xA6) - Sleep Timer High Byte ........................................................................... 128 WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High ........................................................... 128 WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low ............................................................ 128 WORCTRL (0xA2) - Sleep Timer Control ................................................................................. 129 WORIRQ (0xA1) - Sleep Timer Interrupt Control ...................................................................... 129 T3CNT (0xCA) - Timer 3 Counter .............................................................................................. 133 T3CTL (0xCB) - Timer 3 Control ............................................................................................... 134 T3CCTL0 (0xCC) - Timer 3 Channel 0 Compare Control .......................................................... 135 T3CC0(0xCD) - Timer 3 Channel 0 Compare Value .................................................................. 135 T3CCTL1 (0xCE) - Timer 3 Channel 1 Compare Control .......................................................... 136 T3CC1 (0xCF) - Timer 3 Channel 1 Compare Value .................................................................. 136 T4CNT (0xEA) - Timer 4 Counter .............................................................................................. 136 T4CTL (0xEB) - Timer 4 Control................................................................................................ 137 T4CCTL0 (0xEC) - Timer 4 Channel 0 Compare Control .......................................................... 138 T4CC0 (0xED) - Timer 4 Channel 0 Compare Value ................................................................. 138 T4CCTL1 (0xEE) - Timer 4 Channel 1 Compare Control .......................................................... 139 T4CC1 (0xEF) - Timer 4 Channel 1 Compare Value .................................................................. 139 TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag ..................................................................... 140 ADCL (0xBA) - ADC Data Low ................................................................................................. 144 ADCH (0xBB) - ADC Data High ................................................................................................ 144 ADCCON1 (0xB4) - ADC Control 1 .......................................................................................... 144 ADCCON2 (0xB5) - ADC Control 2 .......................................................................................... 145 ADCCON3 (0xB6) - ADC Control 3 .......................................................................................... 146 RNDL (0xBC) - Random Number Generator Data Low Byte .................................................... 148 RNDH (0xBD) - Random Number Generator Data High Byte ................................................... 148 ENCCS (0xB3) - Encryption Control and Status......................................................................... 150 ENCDI (0xB1) - Encryption Input Data ...................................................................................... 150 ENCDO (0xB2) - Encryption Output Data .................................................................................. 150 WDCTL (0xC9) - Watchdog Timer Control ............................................................................... 152 U0CSR (0x86) - USART 0 Control and Status ........................................................................... 158 U0UCR (0xC4) - USART 0 UART Control ................................................................................ 159 U0GCR (0xC5) - USART 0 Generic Control .............................................................................. 159 U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer ..................................................... 160 U0BAUD (0xC2) - USART 0 Baud Rate Control ....................................................................... 160 U1CSR (0xF8) - USART 1 Control and Status ........................................................................... 160 U1UCR (0xFB) - USART 1 UART Control ............................................................................... 161 SWRS033H Page 233 of 246 CC1110Fx / CC1111Fx U1GCR (0xFC) - USART 1 Generic Control .............................................................................. 161 U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer ..................................................... 162 U1BAUD (0xFA) - USART 1 Baud Rate Control ...................................................................... 162 0xDF40: I2SCFG0 - I2S Configuration Register 0 ...................................................................... 167 0xDF41: I2SCFG1 - I2S Configuration Register 1 ...................................................................... 168 0xDF42: I2SDATL - I2S Data Low Byte..................................................................................... 168 0xDF43: I2SDATH - I2S Data High Byte.................................................................................... 168 0xDF44: I2SWCNT - I2S Word Count Register .......................................................................... 168 0xDF45: I2SSTAT - I2S Status Register...................................................................................... 169 0xDF46: I2SCLKF0 - I2S Clock Configuration Register 0 ......................................................... 169 0xDF47: I2SCLKF1 - I2S Clock Configuration Register 1 ......................................................... 169 0xDF48: I2SCLKF2 - I2S Clock Configuration Register 2 ......................................................... 169 0xDE00: USBADDR - Function Address ................................................................................... 179 0xDE01: USBPOW - Power/Control Register ............................................................................ 179 0xDE02: USBIIF - IN Endpoints and EP0 Interrupt Flags .......................................................... 179 0xDE04: USBOIF - Out Endpoints Interrupt Flags ..................................................................... 179 0xDE06: USBCIF - Common USB Interrupt Flags..................................................................... 180 0xDE07: USBIIE - IN Endpoints and EP0 Interrupt Enable Mask ............................................. 180 0xDE09: USBOIE - Out Endpoints Interrupt Enable Mask ........................................................ 181 0xDE0B: USBCIE - Common USB Interrupt Enable Mask ....................................................... 181 0xDE0C: USBFRML - Current Frame Number (Low byte) ....................................................... 181 0xDE0D: USBFRMH - Current Frame Number (High byte) ...................................................... 182 0xDE0E: USBINDEX - Current Endpoint Index Register .......................................................... 182 0xDE10: USBMAXI - Max. Packet Size for IN Endpoint{1 - 5} ............................................... 182 0xDE11: USBCS0 - EP0 Control and Status (USBINDEX=0) ................................................... 182 0xDE11: USBCSIL - IN EP{1 - 5} Control and Status Low ...................................................... 183 0xDE12: USBCSIH - IN EP{1 - 5} Control and Status High ..................................................... 183 0xDE13: USBMAXO - Max. Packet Size for OUT{1 - 5} Endpoint ......................................... 183 0xDE14: USBCSOL - OUT EP{1 - 5} Control and Status Low ................................................. 184 0xDE15: USBCSOH - OUT EP{1 - 5} Control and Status High ................................................ 184 0xDE16: USBCNT0 - Number of Received Bytes in EP0 FIFO (USBINDEX=0) ..................... 184 0xDE16: USBCNTL - Number of Bytes in EP{1 - 5} OUT FIFO Low ..................................... 184 0xDE17: USBCNTH - Number of Bytes in EP{1 - 5} OUT FIFO High .................................... 185 0xDE20: USBF0 - Endpoint 0 FIFO............................................................................................ 185 0xDE22: USBF1 - Endpoint 1 FIFO............................................................................................ 185 0xDE24: USBF2 - Endpoint 2 FIFO............................................................................................ 185 0xDE26: USBF3 - Endpoint 3 FIFO............................................................................................ 185 0xDE28: USBF4 - Endpoint 4 FIFO............................................................................................ 185 0xDE2A: USBF5 - Endpoint 5 FIFO........................................................................................... 185 RFIF (0xE9) - RF Interrupt Flags ................................................................................................ 189 RFIM (0x91) - RF Interrupt Mask ............................................................................................... 190 0xDF2F: IOCFG2 - Radio Test Signal Configuration (P1_7) ..................................................... 212 0xDF30: IOCFG1 - Radio Test Signal Configuration (P1_6) ..................................................... 212 0xDF31: IOCFG0 - Radio Test Signal Configuration (P1_5) ..................................................... 212 0xDF00: SYNC1 - Sync Word, High Byte .................................................................................. 212 0xDF01: SYNC0 - Sync Word, Low Byte .................................................................................. 212 0xDF02: PKTLEN - Packet Length ............................................................................................. 212 0xDF03: PKTCTRL1 - Packet Automation Control ................................................................... 213 0xDF04: PKTCTRL0 - Packet Automation Control ................................................................... 213 0xDF05: ADDR - Device Address .............................................................................................. 214 0xDF06: CHANNR - Channel Number ....................................................................................... 214 0xDF07: FSCTRL1 - Frequency Synthesizer Control ................................................................. 214 0xDF08: FSCTRL0 - Frequency Synthesizer Control ................................................................. 214 0xDF09: FREQ2 - Frequency Control Word, High Byte ............................................................ 214 SWRS033H Page 234 of 246 CC1110Fx / CC1111Fx 0xDF0A: FREQ1 - Frequency Control Word, Middle Byte ........................................................ 214 0xDF0B: FREQ0 - Frequency Control Word, Low Byte ............................................................ 214 0xDF0C: MDMCFG4 - Modem configuration ............................................................................ 215 0xDF0D: MDMCFG3 - Modem Configuration........................................................................... 215 0xDF0E: MDMCFG2 - Modem Configuration ........................................................................... 216 0xDF0F: MDMCFG1 - Modem Configuration ........................................................................... 217 0xDF10: MDMCFG0 - Modem Configuration ........................................................................... 217 0xDF11: DEVIATN - Modem Deviation Setting ........................................................................ 218 0xDF12: MCSM2 - Main Radio Control State Machine Configuration...................................... 218 0xDF13: MCSM1 - Main Radio Control State Machine Configuration...................................... 219 0xDF14: MCSM0 - Main Radio Control State Machine Configuration...................................... 219 0xDF15: FOCCFG - Frequency Offset Compensation Configuration ........................................ 220 0xDF16: BSCFG - Bit Synchronization Configuration ............................................................... 221 0xDF17: AGCCTRL2 - AGC Control ......................................................................................... 222 0xDF18: AGCCTRL1 - AGC Control ......................................................................................... 223 0xDF19: AGCCTRL0 - AGC Control ......................................................................................... 224 0xDF1A: FREND1 - Front End RX Configuration ..................................................................... 224 0xDF1B: FREND0 - Front End TX Configuration ..................................................................... 225 0xDF1C: FSCAL3 - Frequency Synthesizer Calibration............................................................. 225 0xDF1D: FSCAL2 - Frequency Synthesizer Calibration ............................................................ 225 0xDF1E: FSCAL1 - Frequency Synthesizer Calibration ............................................................. 226 0xDF1F: FSCAL0 - Frequency Synthesizer Calibration ............................................................. 226 0xDF23: TEST2 - Various Test Settings ..................................................................................... 226 0xDF24: TEST1 - Various Test Settings ..................................................................................... 226 0xDF25: TEST0 - Various Test Settings ..................................................................................... 226 0xDF27: PA_TABLE7 - PA Power Setting 7 ............................................................................. 226 0xDF28: PA_TABLE6 - PA Power Setting 6 ............................................................................. 226 0xDF29: PA_TABLE5 - PA Power Setting 5 ............................................................................. 227 0xDF2A: PA_TABLE4 - PA Power Setting 4............................................................................. 227 0xDF2B: PA_TABLE3 - PA Power Setting 3 ............................................................................. 227 0xDF2C: PA_TABLE2 - PA Power Setting 2 ............................................................................. 227 0xDF2D: PA_TABLE1 - PA Power Setting 1............................................................................. 227 0xDF2E: PA_TABLE0 - PA Power Setting 0 ............................................................................. 227 0xDF36: PARTNUM - Chip ID[15:8] ......................................................................................... 227 0xDF37: VERSION - Chip ID[7:0] ............................................................................................. 227 0xDF38: FREQEST - Frequency Offset Estimate from Demodulator ........................................ 227 0xDF39: LQI - Demodulator Estimate for Link Quality ............................................................. 228 0xDF3A: RSSI - Received Signal Strength Indication ................................................................ 228 0xDF3B: MARCSTATE - Main Radio Control State Machine State ......................................... 228 0xDF3C: PKTSTATUS - Packet Status ...................................................................................... 229 0xDF3D: VCO_VC_DAC - Current Setting from PLL Calibration Module .............................. 229 SWRS033H Page 235 of 246 CC1110Fx / CC1111Fx 17 Package Description (QFN 36) available in RoHS lead-free package only. Compliant with JEDEC: MO-220. All dimensions are in millimeters, angles in degrees. Note: The CC1110Fx/CC1111Fx is Figure 62: Package Dimensions Drawing (RSP, CC1111Fx) Quad Leadless Package (QLP) QFN 36 Min Max A A1 A2 D D1 E E1 0.80 0.005 0.60 5.90 5.65 5.90 5.65 0.85 0.025 0.65 6.00 5.75 6.00 5.75 0.90 0.045 0.70 6.10 5.85 6.10 5.85 e 0.50 b L 0.18 0.45 0.23 0.55 0.30 0.65 D2 E2 4.40 4.40 Table 74: Package Dimensions (RSP, CC1111Fx) SWRS033H Page 236 of 246 CC1110Fx / CC1111Fx Figure 63: Package Dimensions Drawing (RHH, CC1110Fx) SWRS033H Page 237 of 246 CC1110Fx / CC1111Fx 17.1 Recommended PCB Layout for Package (QFN 36) Figure 64: Recommended PCB Layout for QFN 36 Package Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC1110EM reference design [1] and theCC1111 USB-Dongle reference design [4]. Thermal Resistance Air velocity [m/s] 0 Rth,j-a [C/W] 32 Table 75: Thermal Properties of QFN 36 Package 17.2 Soldering information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020D should be followed. The lead finish is annealed (150 °C for 1 hr) pure matte tin. 17.3 Tray Specification Tray Specification Package Tray Length Tray Width Tray Height Units per Tray QFN 36 322.6 mm 135.9 mm 7.62 mm 490 Table 76: Tray Specification SWRS033H Page 238 of 246 CC1110Fx / CC1111Fx 17.4 Carrier Tape and Reel Specification Carrier tape and reel is in accordance with EIA Specification 481. Tape and Reel Specification Package Carrier Tape Width Component Pitch Hole Pitch Reel Diameter Reel Hub Diameter Units per Reel QFN 36 16 mm 12 mm 4 mm 13 inches 100 mm 2500 Table 77: Carrier Tape and Reel Specification (CC1111Fx) 18 Ordering Information Ordering Part Number CC1110F8RHHT CC1110F8RHHR CC1110F16RHHT CC1110F16RHHR CC1110F32RHHT CC1110F32RHHR CC1111F8RSP CC1111F8RSPR CC1111F16RSP CC1111F16RSPR CC1111F32RSP CC1111F32RSPR Description Minimum Order Quantity 8 kB flash, 1 kB RAM, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 250 pcs per reel. 8 kB flash, 1 kB RAM, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. 16 kB flash, 2 kB RAM, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 250 pcs per reel. 16 kB flash, 2 kB RAM, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. 32 kB flash, 4 kB RAM, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 250 pcs per reel. 32 kB flash, 4 kB RAM, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. 8 kB flash, 1 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. 8 kB flash, 1 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. 16 kB flash, 2 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. 16 kB flash, 2 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. 32 kB flash, 4 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. 32 kB flash, 4 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QFN 36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. 250 2500 250 2500 250 2500 490 2500 490 2500 490 2500 CC1110-CC1111DK CC1110Fx and CC1111Fx Development Kit 1 CC1110EMK433 CC1110 Evaluation Module Kit, for 433 MHz operation 1 CC1110EMK868-915 CC1110 Evaluation Module Kit, for 868/915 MHz operation 1 CC1111EMK868-915 CC1111 Evaluation Module Kit, for 868/915 MHz operation 1 Table 78: Ordering Information SWRS033H Page 239 of 246 CC1110Fx / CC1111Fx 19 References [1] CC1110EM315 Reference Design (swrr050.zip) [2] CC1110EM433 Reference Design (swrr047.zip) [3] CC1110EM868 - 915 Reference Design (swrr049.zip) [4] CC1111 USB-Dongle Reference Design (swrr049.zip) [5] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf [6] Universal Serial Bus Revision 2.0 Specification. Available from the USB Implementors Forum website. http://www.usb.org/developers/docs/ [7] 2 I S bus specification, Philips Semiconductors, Available from the Philips Semiconductors website. http://www.semiconductors.philips.com/acrobat_download/various/I2SBUS.pdf [8] IEEE Std 1241-2000, IEEE standard for terminology and test methods for analog-to-digital converters. [9] SmartRF Studio (swrc046.zip) [10] AN001 SRD regulations for license free transceiver operation(swra090.pdf) [11] ISM-Band and Short Range Device Regulatory Compliance Overview (swra048.pdf) [12] DN006 CC11xx settings for FCC15.247 Solutions (swra123.pdf) [13] AN050 Using the CC1101 in the European 868 MHz SRD band (swra146.pdf) [14] DN016 Compact Antenna Solutions for 868/915MHz (swra160.pdf) [15] DN110 State Transition Times on CC111xFx and CC251xFx(swra191.pdf) ® [16] DN505 RSSI Interpretation and Timing (swra114.pdf) SWRS033H Page 240 of 246 CC1110Fx / CC1111Fx 20 General Information 20.1 Document History Revision Date Description/Changes SWRS033 2006.01.04 First release SWRS033A 2006.05.11 Preliminary status updated SWRS033B 2007.09.14 First data sheet for released product. Preliminary data sheets exist for engineering samples and pre-production prototype devices, but these data sheets are not complete and may be incorrect in some aspects compared with the released product. SWRS033C 2007.09.20 Data sheet update before release of product. - Operating frequency range changed to 391 - 464 MHz and 782 - 928 MHz - Changed restricted range for PA power in Section 13.15 (now 0x68 to 0x6F) - Added information about register TEST1 when TX-if-CCA is to be used - Changed register FREQEST and FSCTRL0 max range from ±20910 to ±209 - Added reference to SmartRF Studio for register MCSM0. - Changed bit description for bit FSCAL2.VCO_CORE_H_EN - Added Section 12.1.5.2, describing data rate limitations caused by system clock speed - Added power numbers for RX (Table 6) when using other system clock speeds SWRS033D 2007.10.19 Data sheet update before release of CC1111Fx. - Electrical Specification Section 6 updated with CC1111Fx performance - Minimum power down time of CC1110Fx high speed crystal oscillator stated in Section 6.4.1, Section 6.4.2, Section 12.1.1 and Section 12.1.5.1. - Removed 3rd overtone crystal option for CC1111Fx - Replaced Figure 14, Figure 15, and Figure 16 to correct error in address ranges. - Fixed Table 32 - Fixed bit range for register FADDRH and stated that register WORTIME0 and WORTIME1 defines a combined 16 bit word (WORTIME) - Replaced all occurrences of WORCTL with WORCTRL - Made consistent use of VDD for power with reference to power pin if so needed - Corrected part number for these devices, register PARTNUM - Stated that P1_0 and P1_1 does not have pull capability in register P2INP - Corrected code example in Figure 49 - Corrected unimplemented RAM range in Section 10.2.3.1 - Updated Sections 12.1.3, 12.1.5.1, and 12.1.5.3 with information about system clock source change - Rewrote RAM range in Section 12.3.2 - Updated Section 12.8.2 with information about power modes. Changed code examples - Changed heading text for Section 12.8.5 - Corrected received symbol write and read location in Section 13.11.2 SWRS033E 2007.10.26 - Corrected Table of contents - Updated guard time and stated for which crystal this applies in Table 11 SWRS033H Page 241 of 246 CC1110Fx / CC1111Fx Revision Date Description/Changes SWRS033F 2007.11.23 - Changed title on front page - TX power consumption @ 1.2 kBaud, −6 dBm output power changed to 15.2 mA on front page - “Crystal shunt capacitance” changed to C0 in Table 13 - Temperature coefficient changed to 2.47 mV/°C in Table 17 - Zout @ 868/915 MHz = 86.5 + j43 Ω changed to Zout @ 868 MHz = 86.5 + j43 Ω - Changed component name in Figure 10, Figure 11, and Figure 12 in accordance with reference designs and added optional filter in Figure 11 and Figure 12 - Table 28: Made changes to component names and descriptions - Table 29: Changes to component names. Added components for optional filter. R2626/R263 changed to 33 Ω. C203/C214 changed to 22 pF - Table 37: Added footer explaining opcode for ACALL and AJMP - CLKCON.OSC bit. Changed description. It is not longer necessary to set SLEEP.OSC_PD=0 to power up the HS crystal oscillator. - 10.5.1: Added note emphasizing that an interrupt must not be enabled without having proper code located at the corresponding interrupt vector address - :10.5.2: Changes made to code example. - 12.1.5: Changed HS crystal oscillator operating range to 26 - 27 MHz - 12.1.5.1: Changed HS crystal oscillator operating range to 26 - 27 MHz and HS RCOSC operating range to 13 - 13.5 MHz - 12.1.5.1 and 12.1.7: Added info regarding retention of HS RCOSC calibration result. - 12.1.5.2: Rewritten to improve readability - 12.1.5.3: Changed low power RCOSC range to 34.667 - 36 kHz. Added/rewritten info regarding calibration of the low power RCOSC. - 12.5: Chapter rewritten to be more consistent in the use of the terms “transfer” and “transfer count”. Added new info regarding the LEN setting. Changes made to Figure 26 and Figure 27 - 12.6.2.1 and 12.6.2.2: Emphasized that the timer wraps around/is loaded with 0x0000 on the next timer tick after the terminal count value is reached - 12.8.4: Added more detailed info about interrupt and associated flags - 12.9.3 and 12.9.3.1 Emphasized that the timer wraps around/is loaded with 0x00 on the next timer tick after the terminal count value is reached - USBCIF.RESUMIF changed to USBCIF.RESUMEIF several places in the document - 13.7.1: Added note saying that frequency offset compensation is not supported for ASK/OOK - 13.11.2: Added note saying that when FEC is used, CLKCON.CLKSPD must be 000 -.PKTCTRL0: Bit 3 set as reserved - FSCTRL0: Changed range to ±202 kHz to ±209 kHz for CC1110Fx - MDMCFG2.DEM_DCFILT_OFF=1: Only for data rates ≤ 100 kBaud: - MDMCFG2.MOD_FORMAT: Added setting for ASK/OOK - MCSM2.RX_TIME_RSSI: Added note regarding ASK/OOK modulation - FOCCFG.FOC_LIMIT: Added note regarding ASK/OOK modulation AGCCTRL0.FILTER_LENGTH Added note regarding ASK/OOK modulation - TEST2: Changed value for improved sensitivity - FREQEST: Changed range to ±202 kHz to ±209 kHz for CC1110Fx. Added info regarding ASK/OOK modulation - LQI.CRC_OK: Removed reference to CC2400_EN bit, which has been removed SWRS033H Page 242 of 246 CC1110Fx / CC1111Fx Revision Date Description/Changes SWRS033G 2008.07.11 - Changed description of T1CCTL1.MODE bit. - UxGDR changed to UxGCR several places in the document - Changed FREQ2.FREQ[21:16] reset value from 11110 to 011110 - Added changes to the DEVIATN register, and added also info regarding the same register to sections 13.9.1, 13.9.2, and 13.9.3 - 12.14.2.2: Changed description of the UxCSR.ACTIVE bit - 12.8: Added note stating that the Sleep timer should not be used in active mode. This info has in earlier edition only been available in section 8.1 - Added section 9.4: Reference Signal - Table 57 and Table 58: Fsck changed to Fs - 12.8.1: WOREVT1 = desired event0; changed to WOREVT1 = desired event0 >> 8; - Table 39: Added footnote saying that the Sleep Timer compare interrupt has additional interrupt mask bits and interrupt flags found in its SFRs - Updated Figure 26 - Changed the description of PKTSTATUS.SFD - MCSM0.FS_AUTOCAL=1 changed to MCSM0.FS_AUTOCAL=01 and MCSM0.FS_AUTOCAL=0 changed to MCSM0.FS_AUTOCAL=00 throughout the document - 13.1: Added note about SIDLE strobe - Table 16, Table 71, and Section 13.18: Changed the state transition timing - 13.10.3: Added reference to DN505 [16] regarding RSSI response time. - Changes made to the description of I2SCFG0.ULAWE and I2SCFG0.ULAWC - Section 13.9 and 13.9.2 and MDMCFG2 register: Added info saying that Manchester encoding/decoding should not be used when using MSK modulation. - Table 11: Changes done to the condition/note on Power Down Guard Time - Added Section 6.11.1 (info regarding the RESET_N pin being sensitive to noise) - Changes made to the ADCCON1 register. - Changes made to Section 12.11.2.1 regarding how to generate pseudo-random bytes. - Section13.3.1.1: Added note explaining how the RFTXRXIF flag should be cleared when it is not cleared by HW. - The drive strength for I/O pins in output mode is not controlled by the PICTL register but by IOCFG1.GDO_DS. This has been changes several places in the data sheet. - Table 14: Changed the minimum calibrated frequency to 34.7 kHz Removed the Sleep Timer trigger for the DMA since the Sleep Timer should not be used in active mode. - Section 13.12.1: Added note regarding RSSI response time when using MCSM1.RXOFF_MODE=11 - Changed the description of the T2CTL.INT field - Several changes added throughout the document regarding calibration of the two RC oscillators - Added info several places in the document stating that the I2S interface will have precedence in cases where other peripherals (except for the debug interface) are configured to be on the same location even if the pins are configured to be general purpose I/O pins. - Table 78: Changed ordering information for the Development Kits (DKs) - QLP36 / QLP 36 replaced by QFN 36 -12.8.2: Changes made to the description on how entering PM{0 - 2}, updating EVENT0, and resetting the sleep timer should be done with respect to the 32 kHz clock source. SWRS033H 2013.02.27 Updated the package designator from RSP to RHH for the CC1110Fx devices Updated ordering information Table 79: Document History SWRS033H Page 243 of 246 CC1110Fx / CC1111Fx 20.2 Product Status Definitions Data Sheet Identification Product Status Definition Advance Information Planned or Under Development This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary Experimental and Prototype Devices This data sheet contains preliminary data, and supplementary data will be published at a later date. Texas Instruments reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product at this point is not yet fully qualified. No Identification Noted Full Production This data sheet contains the final specifications. Texas Instruments reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by Texas Instruments. The data sheet is printed for reference information only. Table 80: Product Status Definitions SWRS033H Page 244 of 246 CC1110Fx / CC1111Fx 21 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw 22 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: TI Semiconductor KnowledgeBase Home Page: support.ti.com support.ti.com/sc/knowledgebase Product Information Centers Americas Phone: Fax: Internet/Email: +1(972) 644-5580 +1(972) 927-6377 support.ti.com/sc/pic/americas.htm Europe, Middle East and Africa Phone: Belgium (English) Finland (English) France Germany Israel (English) Italy Netherlands (English) Russia Spain Sweden (English) United Kingdom Fax: Internet: +32 (0) 27 45 54 32 +358 (0) 9 25173948 +33 (0) 1 30 70 11 64 +49 (0) 8161 80 33 11 180 949 0107 800 79 11 37 +31 (0) 546 87 95 45 +7 (4) 95 98 10 701 +34 902 35 40 28 +46 (0) 8587 555 22 +44 (0) 1604 66 33 99 +49 (0) 8161 80 2045 support.ti.com/sc/pic/euro.htm Japan Fax International +81-3-3344-5317 Internet/Email Domestic International 0120-81-0036 support.ti.com/sc/pic/japan.htm Domestic www.tij.co.jp/pic SWRS033H Page 245 of 246 CC1110Fx / CC1111Fx Asia Phone Fax Email Internet International +886-2-23786800 Domestic Australia China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand Toll-Free Number 1-800-999-084 800-820-8682 800-96-5941 +91-80-51381665 (Toll) 001-803-8861-1006 080-551-2804 1-800-80-3973 0800-446-934 1-800-765-7404 800-886-1028 0800-006800 001-800-886-0010 +886-2-2378-6808 tiasia@ti.com or ti-china@ti.com support.ti.com/sc/pic/asia.htm SWRS033H Page 246 of 246 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device CC1111F32RSPR Package Package Pins Type Drawing VQFN RSP 36 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC1111F32RSPR VQFN RSP 36 2500 378.0 70.0 346.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2022 TRAY L - Outer tray length without tabs KO Outer tray height WOuter tray width Text P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array Max L (mm) W matrix temperature (mm) (°C) CC1110F16RHHR RHH VQFN 36 2500 35 X 14 150 315 K0 (µm) P1 (mm) CL (mm) CW (mm) 135.9 7620 8.8 7.9 8.15 CC1110F16RHHT RHH VQFN 36 250 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1110F32RHHR RHH VQFN 36 2500 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1110F32RHHR RHH VQFN 36 2500 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1110F32RHHT RHH VQFN 36 250 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1110F32RHHT RHH VQFN 36 250 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1110F8RHHR RHH VQFN 36 2500 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1110F8RHHT RHH VQFN 36 250 35 X 14 150 315 135.9 7620 8.8 7.9 8.15 CC1111F32RSP RSP VQFNP 36 490 14x35 150 322.6 135.9 7620 8.8 7.9 8.15 CC1111F8RSP RSP VQFNP 36 490 14x35 150 322.6 135.9 7620 8.8 7.9 8.15 Pack Materials-Page 3 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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