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CC1120
SWRS112H – JUNE 2011 – REVISED JULY 2015
CC1120 High-Performance RF Transceiver for Narrowband Systems
1 Device Overview
1.1
Features
1
• High-Performance, Single-Chip Transceiver
– Adjacent Channel Selectivity:
64 dB at 12.5-kHz Offset
– Blocking Performance: 91 dB at 10 MHz
– Excellent Receiver Sensitivity:
• –123 dBm at 1.2 kbps
• –110 dBm at 50 kbps
• –127 dBm Using Built-in Coding Gain
– Very Low Phase Noise:
–111 dBc/Hz at 10-kHz Offset
• Suitable for Systems Targeting ETSI Category 1
Compliance in 169-MHz and 433-MHz Bands
• High Spectral Efficiency (9.6 kbps in 12.5-kHz
Channel in Compliance With FCC Narrowbanding
Mandate)
• Separate 128-Byte RX and TX FIFOs
• Support for Seamless Integration With the CC1190
Device for Increased Range Giving up to 3-dB
Improvement in Sensitivity and up to +27-dBm
Output Power
• Power Supply
– Wide Supply Voltage Range (2.0 V to 3.6 V)
– Low Current Consumption:
• RX: 2 mA in RX Sniff Mode
• RX: 17 mA Peak Current in Low-Power
Mode
• RX: 22 mA Peak Current in
High-Performance Mode
• TX: 45 mA at +14 dBm
– Power Down: 0.12 μA
(0.5 μA With eWOR Timer Running)
• Programmable Output Power up to +16 dBm With
0.4-dB Step Size
1.2
•
•
•
• Automatic Output Power Ramping
• Configurable Data Rates: 0 to 200 kbps
• Supported Modulation Formats: 2-FSK,
2-GFSK, 4-FSK, 4-GFSK, MSK, OOK
• WaveMatch: Advanced Digital Signal Processing
for Improved Sync Detect Performance
• RoHS-Compliant 5-mm × 5-mm No-Lead QFN
32-Pin Package (RHB)
• Regulations – Suitable for Systems Targeting
Compliance With
– Europe: ETSI EN 300 220, ETSI EN 54-25
– US: FCC CFR47 Part 15, FCC CFR47 Part 90,
24, and 101
– Japan: ARIB RCR STD-T30, ARIB STD-T67,
ARIB STD-T108
• Peripherals and Support Functions
– Enhanced Wake-On-Radio (eWOR)
Functionality for Automatic Low-Power Receive
Polling
– Includes Functions for Antenna Diversity
Support
– Support for Retransmissions
– Support for Automatic Acknowledge of Received
Packets
– TCXO Support and Control, Also in Power
Modes
– Automatic Clear Channel Assessment (CCA) for
Listen-Before-Talk (LBT) Systems
– Built-in Coding Gain Support for Increased
Range and Robustness
– Digital RSSI Measurement
– Temperature Sensor
Applications
Narrowband Ultra-Low-Power Wireless Systems
With Channel Spacing Down to
12.5 kHz
169-, 315-, 433-, 868-, 915-, 920-, 950-MHz
ISM/SRD Band
Wireless Metering and Wireless Smart Grid
(AMR and AMI)
•
•
•
•
•
•
•
IEEE 802.15.4g Systems
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
Wireless Healthcare Applications
Wireless Sensor Networks and Active RFID
Private Mobile Radios
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC1120
SWRS112H – JUNE 2011 – REVISED JULY 2015
1.3
www.ti.com
Description
The CC1120 device is a fully integrated single-chip radio transceiver designed for high performance at
very low-power and low-voltage operation in cost-effective wireless systems. All filters are integrated, thus
removing the need for costly external SAW and IF filters. The device is mainly intended for Industrial,
Scientific, and Medical (ISM) applications and Short Range Device (SRD) frequency bands at
164 to 192 MHz, 274 to 320 MHz, 410 to 480 MHz, and 820 to 960 MHz.
The CC1120 device provides extensive hardware support for packet handling, data buffering, burst
transmissions, clear channel assessment, link quality indication, and wake-on-radio. The main operating
parameters of the CC1120 device can be controlled through an SPI interface. In a typical system, the
CC1120 device is used with a microcontroller and only a few external passive components.
Device Information (1)
PART NUMBER
CC1120
(1)
1.4
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
For more information, see Section 8, Mechanical Packaging and Orderable Information
Functional Block Diagram
Figure 1-1 shows the system block diagram of the CC1120 device.
CC112X
(optional 32kHz
clock intput)
Ultra low power 32kHz
auto-calibrated RC oscillator
4k byte
ROM
Power on reset
MARC
Main Radio Control Unit
Ultra low power 16 bit
MCU
CSn (chip select)
SPI
Serial configuration
and data interface
SI (serial input)
Interrupt and
IO handler
System bus
SO (serial output)
SCLK (serial clock)
eWOR
Enhanced ultra low power
Wake On Radio timer
Configuration and
status registers
Battery sensor /
temp sensor
256 byte
FIFO RAM
buffer
Packet handler
and FIFO control
(optional GPIO0-3)
RF and DSP frontend
Output power ramping and OOK / ASK modulation
I
Fully integrated Fractional-N
Frequency Synthesizer
Q
High linearity
LNA
LNA_N
(optional GPIO for
antenna diversity)
ifamp
XOSC
XOSC_Q2
90dB dynamic
range ADC
(optional bit clock)
Channel
filter
ifamp
LNA_P
XOSC_Q1
Data interface with
signal chain access
Cordic
14dBm high
efficiency PA
Modulator
PA
(optional autodetected
external XOSC / TCXO)
Highly flexible FSK / OOK
demodulator
(optional low jitter serial
data output for legacy
protocols)
90dB dynamic
range ADC
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Figure 1-1. Functional Block Diagram
2
Device Overview
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SWRS112H – JUNE 2011 – REVISED JULY 2015
Table of Contents
1
2
3
Device Overview ......................................... 1
Thermal Resistance Characteristics for RHB
Package ............................................. 15
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
4.15
Timing Requirements
1.3
Description ............................................ 2
4.16
Regulatory Standards ............................... 16
1.4
Functional Block Diagram ............................ 2
4.17
Typical Characteristics .............................. 17
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
5
...............................
16
Detailed Description ................................... 20
5.1
Block Diagram....................................... 20
5
5.2
Frequency Synthesizer .............................. 20
6
5.3
Receiver ............................................. 21
7
5.4
Transmitter .......................................... 21
7
5.5
Radio Control and User Interface ................... 21
7
Recommended Operating Conditions (General
Characteristics) ....................................... 7
5.6
Enhanced Wake-On-Radio (eWOR) ................ 21
5.7
Sniff Mode ........................................... 22
5.8
Antenna Diversity
4.3
RF Characteristics .................................... 7
5.9
WaveMatch .......................................... 23
4.4
Power Consumption Summary ....................... 8
4.5
Receive Parameters .................................. 9
4.6
Transmit Parameters ................................ 12
4.7
PLL Parameters ..................................... 13
4.8
32-MHz Clock Input (TCXO)
4.9
4.10
4.11
32-kHz RC Oscillator
..........................................
3.2
Pin Configuration .....................................
Specifications ............................................
Absolute Maximum Ratings .................................
4.1
ESD Ratings ..........................................
3.1
4
4.14
4.2
4.12
4.13
Pin Diagram
...................................
22
6
Application, Implementation, and Layout ......... 24
7
Device and Documentation Support ............... 26
6.1
Application Information .............................. 24
7.1
Device Support ...................................... 26
14
7.2
Documentation Support ............................. 27
32-MHz Crystal Oscillator ........................... 14
7.3
Trademarks.......................................... 27
32-kHz Clock Input .................................. 14
7.4
Electrostatic Discharge Caution ..................... 27
...............................
I/O and Reset .......................................
Temperature Sensor ................................
7.5
Glossary ............................................. 27
.......................
15
15
15
8
Mechanical Packaging and Orderable
Information .............................................. 28
Table of Contents
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3
CC1120
SWRS112H – JUNE 2011 – REVISED JULY 2015
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (September 2014) to Revision H
•
•
•
•
•
•
•
Moved storage temperature range back to Absolute Maximum Ratings table ............................................... 7
Updated the formatting of the Specifications section ........................................................................... 7
Changed clock frequency minimum value FROM: 32 MHz TO: 31.25 MHz in 32-MHz Clock Input (TCXO) .......... 14
Added clock frequency typical value of 32 MHz to 32-MHz Clock Input (TCXO) .......................................... 14
Changed crystal frequency minimum value FROM: 32 MHz TO: 31.25 MHz in the 32-MHz Crystal Oscillator table . 14
Added crystal frequency typical value of 32 MHz in the 32-MHz Crystal Oscillator table ................................. 14
Changed table title FROM: Wakeup and Timing TO: Timing Requirements ............................................... 16
Changes from Revision F (July 2014) to Revision G
•
•
4
Page
Page
Added "Ambient" to the temperature range condition and removed Tj from Temperature range ......................... 7
Added data to TCXO table ......................................................................................................... 14
Revision History
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SWRS112H – JUNE 2011 – REVISED JULY 2015
3 Terminal Configuration and Functions
3.1
Pin Diagram
25 AVDD_PFD_CHP
26 DCPL_PFD_CHP
27 AVDD_SYNTH2
28 AVDD_XOSC
DCPL_XOSC
29
30 XOSC_Q1
XOSC_Q2
31
32 EXT_XOSC
Figure 3-1 shows pin names and locations for the CC1120 device.
VDD_GUARD
1
24
LPF1
RESET_N
2
23
LPF0
GPIO3
3
22
AVDD_SYNTH1
GPIO2
4
21
DCPL_VCO
DVDD
5
20
LNA_N
DCPL
6
SI
7
SCLK
8
CC1120
19 LNA_P
GND
GROUND PAD
18
TRX_SW
17
PA
11
12
13
14
15
16
GPIO0
CSn
DVDD
AVDD_IF
RBIAS
AVDD_RF
N.C.
SO (GPIO1)
10
9
Figure 3-1. Package 5-mm × 5-mm QFN
Terminal Configuration and Functions
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5
CC1120
SWRS112H – JUNE 2011 – REVISED JULY 2015
3.2
www.ti.com
Pin Configuration
The following table lists the pinout configuration for the CC1120 device.
PIN
NO.
NAME
TYPE
1
VDD_GUARD
2
RESET_N
3
GPIO3
Digital I/O
General-purpose I/O
4
GPIO2
Digital I/O
General-purpose I/O
5
DVDD
Power
2.0–3.6 VDD to internal digital regulator
6
DCPL
Power
Digital regulator output to external decoupling capacitor
7
SI
Digital input
Serial data in
8
SCLK
Digital input
Serial data clock
9
SO(GPIO1)
Digital I/O
Serial data out (general-purpose I/O)
10
GPIO0
Digital I/O
General-purpose I/O
11
CSn
Digital input
Active-low chip select
12
DVDD
Power
2.0–3.6 V VDD
13
AVDD_IF
Power
2.0–3.6 V VDD
14
RBIAS
Analog
External high-precision resistor
15
AVDD_RF
Power
2.0–3.6 V VDD
16
N.C.
—
Not connected
17
PA
Analog
Single-ended TX output (requires DC path to VDD)
18
TRX_SW
Analog
TX and RX switch. Connected internally to GND in TX and floating
(high-impedance) in RX.
19
LNA_P
Analog
Differential RX input (requires DC path to ground)
20
LNA_N
Analog
Differential RX input (requires DC path to ground)
21
DCPL_VCO
Power
Pin for external decoupling of VCO supply regulator
22
AVDD_SYNTH1
Power
2.0–3.6 V VDD
23
LPF0
Analog
External loop filter components
24
LPF1
Analog
External loop filter components
25
AVDD_PFD_CHP
Power
2.0–3.6 V VDD
26
DCPL_PFD_CHP
Power
Pin for external decoupling of PFD and CHP regulator
27
AVDD_SYNTH2
Power
2.0–3.6 V VDD
28
AVDD_XOSC
Power
2.0–3.6 V VDD
29
DCPL_XOSC
Power
Pin for external decoupling of XOSC supply regulator
30
XOSC_Q1
Analog
Crystal oscillator pin 1 (must be grounded if a TCXO or other external
clock connected to EXT_XOSC is used)
31
XOSC_Q2
Analog
Crystal oscillator pin 2 (must be left floating if a TCXO or other
external clock connected to EXT_XOSC is used)
32
EXT_XOSC
Digital input
Pin for external clock input (must be grounded if a regular crystal
connected to XOSC_Q1 and XOSC_Q2 is used)
—
GND
Ground pad
The ground pad must be connected to a solid ground plane.
6
Power
DESCRIPTION
Digital input
2.0–3.6 V VDD
Asynchronous, active-low digital reset
Terminal Configuration and Functions
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SWRS112H – JUNE 2011 – REVISED JULY 2015
4 Specifications
All measurements performed on CC1120EM_868_915
CC1120EM_420_470 rev.1.0.1, or CC1120EM_169 rev.1.2.
rev.1.0.1,
CC1120EM_955
rev.1.2.1,
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Supply voltage (VDD, AVDD_x)
All supply pins must have the same voltage
MAX
–0.3
3.9
V
+10
dBm
VDD + 0.3
V
Input RF level
Voltage on any digital pin
Max 3.9 V
–0.3
UNIT
Voltage on analog pins (including DCPL pins)
–0.3
2.0
V
Storage temperature, Tstg
–40
125
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under general characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed
under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS unless otherwise noted.
4.1
ESD Ratings
VESD
(1)
(2)
4.2
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
Electrostatic
discharge (ESD)
performance
Charged device model (CDM), per JESD22-C101
(2)
All pins
VALUE
UNIT
±2
kV
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions (General Characteristics)
over operating free-air temperature range (unless otherwise noted)
MIN
Voltage supply range
All supply pins must have the same voltage
Voltage on digital inputs
Ambient temperature range
4.3
NOM
MAX
UNIT
2.0
3.6
V
0
VDD
V
–40
85
°C
RF Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Frequency bands
TEST CONDITIONS
See SWRA398, Using the CC112x/CC1175 at 274 to
320 MHz, for more information
Contact TI for more information about the use of these
frequency bands
Frequency resolution
MIN
MAX
960
410
480
(273.3)
(320)
164
192
(205)
(240)
(136.7)
30
In 410–480 MHz band
15
6
0
200
Transparent mode
0
100
1e-4
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kbps
bps
Specifications
Copyright © 2011–2015, Texas Instruments Incorporated
MHz
Hz
Packet mode
Data rate step size
UNIT
(160)
In 820–950 MHz band
In 164–192 MHz band
Data rate
TYP
820
7
CC1120
SWRS112H – JUNE 2011 – REVISED JULY 2015
4.4
www.ti.com
Power Consumption Summary
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.12
1
UNIT
CURRENT CONSUMPTION: STATIC MODES
Power down with retention
µA
Low-power RC oscillator running
0.5
XOFF mode
Crystal oscillator / TCXO disabled
170
µA
IDLE mode
Clock running, system waiting with no radio
activity
1.3
mA
37
mA
26
mA
45
mA
34
mA
50
mA
45
mA
34
mA
54
mA
49
mA
41
mA
32
mA
CURRENT CONSUMPTION, TRANSMIT MODES
TX current consumption +10 dBm
TX current consumption 0 dBm
TX current consumption +14 dBm
TX current consumption +10 dBm
950-MHz band (high-performance mode)
868-, 915-, and 920-MHz bands (highperformance mode)
TX current consumption +15 dBm
TX current consumption +14 dBm
434-MHz band (high-performance mode)
TX current consumption +10 dBm
TX current consumption +15 dBm
TX current consumption +14 dBm
169-MHz band (high-performance mode)
TX current consumption +10 dBm
LOW-POWER MODE
(1)
TX current consumption +10 dBm
CURRENT CONSUMPTION, RECEIVE MODE (HIGH-PERFORMANCE MODE) (1)
1.2 kbps, 4-byte preamble
RX wait for sync
RX peak current
38.4 kbps, 4-byte preamble
433-, 868-, 915-, 920-, and
950–MHz bands
169-MHz band
Average current consumption
Check for data packet every 1 second using Wake
on Radio
Using RX sniff mode, where the receiver
wakes up at regular intervals to look for an
incoming packet (2)
Peak current consumption during packet
reception at the sensitivity threshold
50 kbps, 5-byte preamble, 40-kHz RC
oscillator used as sleep timer
2
13.4
22
mA
mA
23
15
µA
17
mA
CURRENT CONSUMPTION, RECEIVE MODE (LOW-POWER MODE) (1)
RX peak current
Low-power RX
mode
(1)
(2)
8
1.2 kbps
Peak current consumption during packet
reception at the sensitivity level
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated.
See the sniff mode design note for more information (SWRA428).
Specifications
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4.5
SWRS112H – JUNE 2011 – REVISED JULY 2015
Receive Parameters
All RX measurements made at the antenna connector, to a bit error rate (BER) limit of 1%.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL RECEIVE PARAMETERS (HIGH-PERFORMANCE MODE) (1)
Saturation
+10
Digital channel filter programmable bandwidth
8
IIP3, normal mode
At maximum gain
IIP3, high linearity mode
Using 6-dB gain reduction in front end
Data rate offset tolerance
With carrier sense detection enabled and assuming
4-byte preamble
±12%
With carrier sense detection disabled
±0.2%
Radiated emissions measured according to
ETSI EN 300 220, fc = 869.5 MHz
< –57
Spurious
emissions
1–13 GHz (VCO leakage at 3.5 GHz)
30 MHz to 1 GHz
433-MHz band
kHz
–14
dBm
–8
dBm
–56
dBm
60 + j60 /
30 + j30
868-, 915-, and 920-MHz bands
Optimum
source
impedance
dBm
200
(Differential or single-ended RX configurations)
100 + j60 /
50 + j30
Ω
140 + j40 /
70 + j20
169-MHz band
RX PERFORMANCE IN 950-MHZ BAND (HIGH-PERFORMANCE MODE) (2)
Sensitivity (3)
1.2 kbps 2FSK, 12.5-kHz channel
separation, 4-kHz deviation,
10-kHz channel filter
1.2 kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation,
50-kHz channel filter
Blocking
and
Selectivity
50 kbps 2GFSK, 200-kHz channel
separation, 25-kHz deviation,
100-kHz channel filter (Same modulation
format as 802.15.4g Mandatory Mode)
200 kbps 4GFSK, 83-kHz deviation (outer
symbols), 200-kHz channel filter, zero IF
(1)
(2)
(3)
(4)
(5)
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4)
–120
1.2 kbps, DEV = 20 kHz CHF = 50 kHz (4)
–114
50 kbps 2GFSK, DEV = 25 kHz,
CHF = 100 kHz (4)
–107
200 kbps, DEV = 83 kHz (outer symbols),
CHF = 200 kHz (4), 4GFSK (5)
–100
± 12.5 kHz (adjacent channel)
51
± 25 kHz (alternate channel)
52
± 1 MHz
73
± 2 MHz
76
± 10 MHz
81
± 50 kHz (adjacent channel)
47
+ 100 kHz (alternate channel)
48
± 1 MHz
69
± 2 MHz
71
± 10 MHz
78
± 200 kHz (adjacent channel)
43
± 400 kHz (alternate channel)
51
± 1 MHz
62
± 2 MHz
65
± 10 MHz
71
± 200 kHz (adjacent channel)
37
± 400 kHz (alternate channel)
44
± 1 MHz
55
± 2 MHz
58
± 10 MHz
64
dBm
dB
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated.
TA = 25°C, VDD = 3.0 V if nothing else stated.
Sensitivity can be improved if the TX and RX matching networks are separated.
DEV is short for deviation, CHF is short for Channel Filter Bandwidth
BT = 0.5 is used in all GFSK measurements
Specifications
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CC1120
SWRS112H – JUNE 2011 – REVISED JULY 2015
www.ti.com
Receive Parameters (continued)
All RX measurements made at the antenna connector, to a bit error rate (BER) limit of 1%.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RX PERFORMANCE IN 868-, 915-, AND 920-MHZ BANDS (HIGH-PERFORMANCE MODE) (2)
Sensitivity
1.2-kbps 2-FSK, 12.5-kHz channel
separation, 4-kHz deviation,
10-kHz channel filter
1.2-kbps 2-FSK, 12.5-kHz channel
separation, using settings optimized for
blocking performance
(3-kHz deviation, 7.8-kHz channel filter,
minimum loop bandwidth)
1.2-kbps 2-FSK, 50-kHz channel
separation, 20-kHz deviation,
50-kHz channel filter
Blocking
and
Selectivity
38.4-kbps 2-GFSK, 100-kHz channel
separation, 20-kHz deviation, 100-kHz
channel filter
50-kbps 2-GFSK, 200-kHz channel
separation, 25-kHz deviation, 100-kHz
channel filter
(Same modulation format as 802.15.4g
Mandatory Mode)
200-kbps 4-GFSK, 83-kHz deviation (outer
symbols), 200-kHz channel filter, zero IF
Image rejection (image compensation enabled)
10
300 bps with coding gain (using a PN spreading
sequence with 4 chips per data bit) DEV = 4 kHz
CHF = 10 kHz (4)
–127
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4)
–123
1.2 kbps, DEV = 10 kHz CHF = 42 kHz (4)
–120
1.2 kbps, DEV = 20 kHz CHF = 50 kHz (4)
–117
4.8 kbps OOK
–114
38.4 kbps, DEV = 20 kHz CHF = 100 kHz (4)
–110
50 kbps 2GFSK, DEV = 25 kHz,
CHF = 100 kHz (4)
–110
200 kbps, DEV = 83 kHz (outer symbols),
CHF = 200 kHz (4), 4GFSK
–103
± 12.5 kHz (adjacent channel)
54
± 25 kHz (alternate channel)
54
± 1 MHz
75
± 2 MHz
79
± 10 MHz
87
± 1 kHz
78
± 2 kHz
82
± 8 MHz
88
± 10 MHz
88
± 50 kHz (adjacent channel)
48
+ 100 kHz (alternate channel)
48
± 1 MHz
69
± 2 MHz
74
± 10 MHz
81
+ 100 kHz (adjacent channel)
42
± 200 kHz (alternate channel)
43
± 1 MHz
62
± 2 MHz
66
± 10 MHz
74
± 200 kHz (adjacent channel)
43
± 400 kHz (alternate channel)
50
± 1 MHz
61
± 2 MHz
65
± 10 MHz
74
± 200 kHz (adjacent channel)
36
± 400 kHz (alternate channel)
44
± 1 MHz
55
± 2 MHz
59
± 10 MHz
67
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4), image at
–125 kHz
54
Specifications
dBm
dB
dB
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Receive Parameters (continued)
All RX measurements made at the antenna connector, to a bit error rate (BER) limit of 1%.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RX PERFORMANCE IN 434-MHZ BAND (HIGH-PERFORMANCE MODE) (2)
Sensitivity
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4)
–123
50 kbps 2GFSK, DEV = 25 kHz,
CHF = 100 kHz
–109
1.2 kbps, DEV = 20 kHz CHF = 50 kHz
1.2 kbps 2FSK, 12.5-kHz channel
separation, 4-kHz deviation,
10-kHz channel filter
Blocking
and
Selectivity
1.2 kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation,
50-kHz channel filter
38.4 kbps 2GFSK, 100-kHz channel
separation, 20-kHz deviation,
100-kHz channel filter
(4)
60
± 25 kHz (alternate channel)
60
± 1 MHz
79
± 2 MHz
82
± 10 MHz
91
± 50 kHz (adjacent channel)
54
+ 100 kHz (alternate channel)
54
± 1 MHz
74
± 2 MHz
78
± 10 MHz
86
+ 100 kHz (adjacent channel)
47
± 200 kHz (alternate channel)
50
± 1 MHz
67
± 2 MHz
71
RX PERFORMANCE IN 169-MHZ BAND (HIGH-PERFORMANCE MODE)
Sensitivity
1.2 kbps 2FSK, 12.5-kHz channel
separation, 4-kHz deviation,
10-kHz channel filter
Blocking
and
Selectivity
1.2 kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation,
50-kHz channel filter
Spurious
response
rejection
dB
78
(2)
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4)
–123
1.2 kbps, DEV = 20 kHz CHF = 50 kHz (4)
–117
± 12.5 kHz (adjacent channel)
64
± 25 kHz (alternate channel)
66
± 1 MHz
82
± 2 MHz
83
± 10 MHz
89
± 50 kHz (adjacent channel)
60
+ 100 kHz (alternate channel)
60
± 1 MHz
76
± 2 MHz
77
± 10 MHz
83
1.2 kbps 2FSK, 12.5-kHz channel
separation, 4-kHz deviation,
10-kHz channel filter
Image rejection (image compensation enabled)
–116
± 12.5 kHz (adjacent channel)
± 10 MHz
dBm
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4), image at
–125 kHz
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70
dB
66
dB
Specifications
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dbm
11
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Receive Parameters (continued)
All RX measurements made at the antenna connector, to a bit error rate (BER) limit of 1%.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RX PERFORMANCE IN LOW-POWER MODE (1)
1.2 kbps, DEV = 4 kHz CHF = 10 kHz (4)
Sensitivity
1.2 kbps 2FSK, 12.5-kHz channel
separation, 4-kHz deviation,
10-kHz channel filter
1.2 kbps 2FSK, 50-kHz channel
separation, 20-kHz deviation,
50-kHz channel filter
Blocking
and
Selectivity
38.4 kbps 2GFSK, 100-kHz channel
separation, 20-kHz deviation, 100-kHz
channel filter
50 kbps 2GFSK, 200-kHz channel
separation, 25-kHz deviation, 100-kHz
channel filter
(Same modulation format as 802.15.4g
Mandatory Mode)
–111
38.4 kbps, DEV = 50 kHz CHF = 100 kHz (4)
–99
50 kbps 2GFSK, DEV = 25 kHz,
CHF = 100 kHz (4)
–99
± 12.5 kHz (adjacent channel)
46
± 25 kHz (alternate channel)
46
± 1 MHz
73
± 2 MHz
78
± 10 MHz
79
± 50 kHz (adjacent channel)
43
+ 100 kHz (alternate channel)
45
± 1 MHz
71
± 2 MHz
74
± 10 MHz
75
+ 100 kHz (adjacent channel)
37
+ 200 kHz (alternate channel)
43
± 1 MHz
58
± 2 MHz
62
+ 10 MHz
64
+ 200 kHz (adjacent channel)
43
+ 400 kHz (alternate channel)
52
± 1 MHz
60
± 2 MHz
64
± 10 MHz
dB
65
Saturation
4.6
dBm
+10
dBm
Transmit Parameters
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
Maximum output power
Minimum output power
Output power step size
Adjacent channel power
TEST CONDITIONS
TYP
At 950 MHz
+12
At 915- and 920-MHz
+14
At 915- and 920-MHz with VDD = 3.6 V
+15
At 868 MHz
+15
At 868 MHz with VDD = 3.6 V
+16
At 433 MHz
+15
At 433 MHz with VDD = 3.6 V
+16
At 169 MHz
+15
At 169 MHz with VDD = 3.6 V
+16
Within fine step size range
–11
Within coarse step size range
–40
Within fine step size range
0.4
4-GFSK 9.6 kbps in 12.5-kHz channel, measured in
100-Hz bandwidth at 434 MHz (FCC Part 90 Mask D
compliant)
–75
4-GFSK 9.6 kbps in 12.5-kHz channel, measured in
8.75-kHz bandwidth (ETSI EN 300 220 compliant)
–58
2-GFSK 2.4 kbps in 12.5-kHz channel, 1.2-kHz deviation
–61
Spurious emissions
(not including harmonics)
12
MIN
UNIT
dBm
dBm
dB
dBc
50-ms periods)
dBm
–60
–45
–40
–42
56
52
4th Harm, 915 MHz
60
2nd Harm, 950 MHz
–58
3rd Harm, 950 MHz
–42
868-, 915-, and 920-MHz
Optimum
bands
load
433 MHz band
impedance
169 MHz band
4.7
TYP
2nd Harm, 169 MHz
dBµV/m
dBm
35 + j35
Ω
55 + j25
80 + j0
PLL Parameters
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-PERFORMANCE MODE
Phase noise in 950-MHz band
± 10 kHz offset
–99
± 100 kHz offset
–99
± 1 MHz offset
Phase noise in 868-, 915-, 920-MHz bands
Phase noise in 433-MHz band
Phase noise in 169-MHz band
dBc/Hz
–123
± 10 kHz offset
–99
± 100 kHz offset
–100
± 1 MHz offset
–122
± 10 kHz offset
–106
± 100 kHz offset
–107
± 1 MHz offset
–127
± 10 kHz offset
–111
± 100 kHz offset
–116
± 1 MHz offset
–135
dBc/Hz
dBc/Hz
dBc/Hz
Specifications
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PLL Parameters (continued)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW-POWER MODE (1)
± 10 kHz offset
Phase noise in 950-MHz band
–90
± 100 kHz offset
Phase noise in 868-, 915-, 920-MHz bands
–92
± 1 MHz offset
–124
± 10 kHz offset
–95
± 100 kHz offset
–95
± 1 MHz offset
Phase noise in 433-MHz band
Phase noise in 169-MHz band
(1)
dBc/Hz
dBc/Hz
–124
± 10 kHz offset
–98
± 100 kHz offset
–102
± 1 MHz offset
–129
± 10 kHz offset
–106
± 100 kHz offset
–110
± 1 MHz offset
–136
dBc/Hz
dBc/Hz
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
4.8
32-MHz Clock Input (TCXO)
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
Clock frequency
TCXO with CMOS output (1)
Clipped sine output
(1)
High input voltage
TCXO with CMOS output
directly coupled to pin
EXT_OSC
Low input voltage
Clock input amplitude
(peak-to-peak)
TCXO clipped sine output
connected to pin EXT_OSC
through series capacitor
MIN
TYP
MAX
UNIT
31.25
32
33.6
MHz
1.4
VDD
0
0.6
0.8
1.5
V
V
For TCXO with CMOS output rise and fall time, see Section 4.15.
4.9
32-MHz Crystal Oscillator
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
MIN
It is expected that there be will degraded
sensitivity at multiples of XOSC/2 in RX, and
an increase in spurious emissions when the
RF channel is close to multiples of XOSC in
TX. We recommend that the RF channel is
kept RX_BW/2 away from XOSC/2 in RX,
and that the level of spurious emissions be
evaluated if the RF channel is closer than 1
MHz to multiples of XOSC in TX.
Crystal frequency
31.25
Load capacitance (CL)
TYP
MAX
UNIT
32
33.6
MHz
10
ESR
Simulated over operating conditions
pF
60
Ω
4.10 32-kHz Clock Input
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
MIN
Clock frequency
MAX
32
32-kHz clock input pin input high voltage
V
0.2 × VDD
Specifications
UNIT
kHz
0.8 × VDD
32-kHz clock input pin input high voltage
14
TYP
V
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4.11 32-kHz RC Oscillator
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
Frequency
After calibration
Frequency accuracy after calibration
Relative to frequency reference
(32-MHz crystal or TCXO)
MIN
TYP
MAX
32
UNIT
kHz
±0.1%
Initial calibration time (1)
(1)
For Initial calibration time of the 32-kHz RC Oscillator, see Section 4.15.
4.12 I/O and Reset
TA = 25°C, VDD = 3.0 V if nothing else stated
PARAMETER
TEST CONDITIONS
Logic input high voltage
MIN
TYP
MAX
UNIT
0.8 × VDD
V
Logic input low voltage
0.2 × VDD
Logic output high voltage
At 4-mA output load or less
Logic output low voltage
Power-on reset threshold
V
0.8 × VDD
V
0.2 × VDD
Voltage on DVDD pin
V
1.3
V
4.13 Temperature Sensor
TA = 25°C, VDD = 3.0 V if nothing else stated (1)
PARAMETER
TEST CONDITIONS
Temperature sensor range
MIN
TYP
–40
MAX
UNIT
85
°C
Temperature coefficient
Change in sensor output voltage versus change in
temperature
2.66
mV/°C
Typical output voltage
Typical sensor output voltage at TA = 25°C,
VDD = 3.0 V
794
mV
VDD coefficient
Change in sensor output voltage versus change in
VDD
1.17
mV/V
(1)
The CC1120 device can be configured to provide a voltage proportional to temperature on GPIO1. The temperature can be estimated
by measuring this voltage (see Section 4.13, Temperature Sensor). For more information, refer to CC112X/CC120X On-Chip
Temperature Sensor (SWRA415).
4.14 Thermal Resistance Characteristics for RHB Package
°C/W (1)
NAME
DESCRIPTION
RΘJC(top)
Junction-to-case (top)
RΘJB
Junction-to-board
5.3
RΘJA
Junction-to-free air
31.3
PsiJT
Junction-to-package top
0.2
PsiJB
Junction-to-board
5.3
RΘJC(bot)
Junction-to-case (bottom)
0.8
(1)
21.1
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 40 mW and an ambient temperature of 25ºC is assumed.
Specifications
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4.15 Timing Requirements
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated
PARAMETER
TEST CONDITIONS
Power down to IDLE
IDLE to RX/TX
MIN NOM MAX
UNIT
Depends on crystal
0.4
ms
Calibration disabled
166
Calibration enabled
461
RX/TX turnaround
µs
50
RX/TX to IDLE time
Calibrate when leaving RX/TX
enabled
296
Calibrate when leaving RX/TX
disabled
0
µs
µs
Frequency synthesizer calibration
When using SCAL strobe
391
Time from start RX until valid RSSI
Including gain settling (function of channel bandwidth. Programmable for
trade-off between speed and accuracy)
12.5-kHz channels
4.6
200-kHz channels
0.3
µs
ms
32-MHz CLOCK INPUT (TCXO) (1)
TCXO with CMOS output
32-kHz RC OSCILLATOR
Rise and fall time
2
Initial calibration time
(1)
(2)
ns
(2)
1.6
ns
See Section 4.8 for more information about the 32-MHz Clock Input (TCXO).
See Section 4.11 for more information about the 32-kHz RC Oscillator.
4.16 Regulatory Standards
PERFORMANCE MODE
FREQUENCY BAND
SUITABLE FOR COMPLIANCE WITH
820–960 MHz (1)
ARIB T-96
ARIB T-108
ETSI EN 300 220 category 2
ETSI EN 54-25
FCC PART 101
FCC PART 24 SUBMASK D
FCC PART 15.247
FCC PART 15.249
FCC PART 90 MASK G
FCC PART 90 MASK J
410–480 MHz (2)
ARIB T-67
ARIB RCR STD-30
ETSI EN 300 220 category 1
FCC PART 90 MASK D
FCC PART 90 MASK G
164–192 MHz (2)
ETSI EN 300 220 category 1
FCC PART 90 MASK D
820–960 MHz
ETSI EN 300 220 category 2
FCC PART 15.247
FCC PART 15.249
410–480 MHz
ETSI EN 300 220 category 2
164–192 MHz
ETSI EN 300 220 category 2
High-performance mode
Low-power mode
(1)
(2)
16
Performance also suitable for systems targeting maximum allowed output power in the respective bands, using a range extender such
as the CC1190 device
Performance also suitable for systems targeting maximum allowed output power in the respective bands, using a range extender
Specifications
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4.17 Typical Characteristics
TA = 25°C, VDD = 3.0 V, fc = 869.5 MHz if nothing else stated.
All
measurements
performed
on
CC1120EM_868_915
CC1120EM_420_470 rev.1.0.1, or CC1120EM_169 rev.1.2.
rev.1.0.1,
CC1120EM_955
rev.1.2.1,
Figure 4-17 was measured at the 50-Ω antenna connector.
-120
-121
Sensitivity (dBm)
Sensitivity (dBm)
-120
-122
-123
-124
-125
-121
-122
-123
-124
-40
0
40
80
2
2.5
3
Temperature (ºC)
1.2 kbps,
10-kHz Channel
Filter Bandwidth
4-kHz Deviation,
1.2 kbps,
Figure 4-1. Sensitivity vs Temperature
23.2
-116
22.8
-118
RX Current (mA)
Sensitivity (dBm)
10-kHz Channel
Filter Bandwidth
4-kHz Deviation,
Figure 4-2. Sensitivity vs Voltage
-114
-120
-122
-124
-126
22.4
22
21.6
21.2
-128
-130
3
5
7
9
11
13
15
20.8
-130
17
-80
Sync Word Detect Threshold
1.2 kbps,
10-kHz Channel
Filter Bandwidth
4-kHz Deviation,
1.2 kbps,
4-kHz Deviation,
10-kHz Channel
Filter Bandwidth
70
60
50
40
30
20
10
0
169.95
170
170.05
170.1
-10
859.9
4-kHz Deviation,
859.95
860
860.05
860.1
Frequency (MHz)
Frequency (MHz)
1.2 kbps,
20
Figure 4-4. RX Current vs Input Level
Selectivity (dB)
70
60
50
40
30
20
10
0
-10
-20
169.9
-30
Input Level (dBm)
Figure 4-3. Sync Word Sensitivity vs Voltage
Selectivity (dB)
3.5
Supply Voltage (V)
10-kHz Channel
Filter Bandwidth
Figure 4-5. Selectivity vs Offset Frequency (12.5-kHz Channels)
1.2 kbps,
4-kHz Deviation,
10-kHz Channel
Filter Bandwidth
Figure 4-6. Selectivity vs Offset Frequency (12.5-kHz Channels)
Specifications
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Typical Characteristics (continued)
17
100
Output Power (dBm)
80
40
20
0
-20
16.5
16
15.5
15
-40
-150
-100
-50
-40
0
0
Input Level (dBm)
1.2 kbps,
10-kHz Channel Filter
Bandwidth
4-kHz Deviation,
Max Setting,
Figure 4-7. RSSI vs Input Level
80
170 MHz,
3.6 V
Figure 4-8. Output Power vs Temperature
18
20
16
10
Output Power (dBm)
14
12
10
8
0
-10
-20
-30
-40
Max Setting,
43
47
4B
53
4F
57
5B
3.5
67
3
Supply Voltage (V)
6B
2.5
73
6F
2
77
-50
6
7F
7B
Output Power (dBm)
40
Temperature (ºC)
63
5F
RSSI
60
PA power setting
170 MHz,
Figure 4-9. Output Power vs Voltage
Figure 4-10. Output Power at 868 MHz vs PA Power Setting
60
TX Current (mA)
50
40
30
20
10
43
47
4F
4B
53
57
5B
63
5F
67
6B
73
6F
77
7F
7B
0
PA power setting
Figure 4-11. TX Current at 868 MHz
vs PA Power Setting
18
Figure 4-12. Phase Noise in 868-MHz Band
Specifications
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Typical Characteristics (continued)
9.6 kbps in 12.5-kHz Channel
1.2 kbps 2-FSK,
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
0
5
10
15
20
25
DEV = 4 kHz
Figure 4-14. Eye Diagram
GPIO Output Low Voltage (mV)
GPIO Output High Voltage (V)
Figure 4-13. FCC Part 90 Mask D
30
35
1400
1200
1000
800
600
400
200
0
0
5
10
15
20
25
30
35
Current (mA)
Current (mA)
Figure 4-15. GPIO Output High Voltage vs Current Being Sourced Figure 4-16. GPIO Output Low Voltage vs Current Being Sinked
Figure 4-17. Output Power vs Load Impedance (+14-dBm Setting)
Specifications
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5 Detailed Description
5.1
Block Diagram
Figure 5-1 shows the system block diagram of the CC1120 devices.
CC112X
(optional 32kHz
clock intput)
Ultra low power 32kHz
auto-calibrated RC oscillator
4k byte
ROM
Power on reset
MARC
Main Radio Control Unit
Ultra low power 16 bit
MCU
CSn (chip select)
SPI
Serial configuration
and data interface
SI (serial input)
Interrupt and
IO handler
System bus
SO (serial output)
SCLK (serial clock)
eWOR
Enhanced ultra low power
Wake On Radio timer
Configuration and
status registers
Battery sensor /
temp sensor
256 byte
FIFO RAM
buffer
Packet handler
and FIFO control
(optional GPIO0-3)
RF and DSP frontend
Output power ramping and OOK / ASK modulation
I
Fully integrated Fractional-N
Frequency Synthesizer
Q
(optional GPIO for
antenna diversity)
ifamp
XOSC
XOSC_Q2
90dB dynamic
range ADC
(optional bit clock)
Cordic
High linearity
LNA
LNA_N
Data interface with
signal chain access
Channel
filter
ifamp
LNA_P
XOSC_Q1
Modulator
14dBm high
efficiency PA
PA
(optional autodetected
external XOSC / TCXO)
Highly flexible FSK / OOK
demodulator
(optional low jitter serial
data output for legacy
protocols)
90dB dynamic
range ADC
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Figure 5-1. System Block Diagram
5.2
Frequency Synthesizer
At the center of the CC1120 device there is a fully integrated, fractional-N, ultra-high-performance
frequency synthesizer. The frequency synthesizer is designed for excellent phase noise performance,
providing very high selectivity and blocking performance. The system is designed to comply with the most
stringent regulatory spectral masks at maximum transmit power.
Either a crystal can be connected to XOSC_Q1 and XOSC_Q2, or a TCXO can be connected to the
EXT_XOSC input. The oscillator generates the reference frequency for the synthesizer, as well as clocks
for the analog-to-digital converter (ADC) and the digital part. To reduce system cost, CC1120 device has
high-accuracy frequency estimation and compensation registers to measure and compensate for crystal
inaccuracies. This compensation enables the use of lower cost crystals. If a TCXO is used, the CC1120
device automatically turns on and off the TCXO when needed to support low-power modes and Wake-OnRadio operation.
20
Detailed Description
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5.3
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Receiver
The CC1120 device features a highly flexible receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and is down-converted in quadrature (I/Q) to the intermediate frequency (IF). At IF,
the I/Q signals are digitized by the high dynamic-range ADCs.
An advanced automatic gain control (AGC) unit adjusts the front-end gain, and enables the CC1120
device to receive strong and weak signals, even in the presence of strong interferers. High-attenuation
channels and data filtering enable reception with strong neighbor channel interferers. The I/Q signal is
converted to a phase and magnitude signal to support the FSK and OOK modulation schemes.
NOTE
A unique I/Q compensation algorithm removes any problem of I/Q mismatch, thus avoiding
time-consuming and costly I/Q image calibration steps.
The CC1120 device only requires preamble to settle the AGC. The minimum number of preamble required
is 0.5 byte.
5.4
Transmitter
The CC1120 transmitter is based on direct synthesis of the RF frequency (in-loop modulation). To use the
spectrum effectively, the CC1120 device has extensive data filtering and shaping in TX mode to support
high throughput data communication in narrowband channels. The modulator also controls power ramping
to remove issues such as spectral splattering when driving external high-power RF amplifiers.
5.5
Radio Control and User Interface
The CC1120 digital control system is built around the main radio control (MARC), which is implemented
using an internal high-performance, 16-bit ultra-low-power processor. MARC handles power modes, radio
sequencing, and protocol timing.
A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband
includes support for channel configuration, packet handling, and data buffering. The host MCU can stay in
power-down mode until a valid RF packet is received. This greatly reduces power consumption. When the
host MCU receives a valid RF packet, it burst-reads the data. This reduces the required computing power.
The CC1120 radio control and user interface are based on the widely used CC1101 transceiver. This
relationship enables an easy transition between the two platforms. The command strobes and the main
radio states are the same for the two platforms.
For legacy formats, the CC1120 device also supports two serial modes.
• Synchronous serial mode: The CC1120 device performs bit synchronization and provides the MCU
with a bit clock with associated data.
• Transparent mode: The CC1120 device outputs the digital baseband signal using a digital interpolation
filter to eliminate jitter introduced by digital filtering and demodulation.
5.6
Enhanced Wake-On-Radio (eWOR)
eWOR, using a flexible integrated sleep timer, enables automatic receiver polling with no intervention from
the MCU. When the CC1120 device enters RX mode, it listens and then returns to sleep if a valid RF
packet is not received. The sleep interval and duty cycle can be configured to make a trade-off between
network latency and power consumption. Incoming messages are time-stamped to simplify timer resynchronization.
The eWOR timer runs off an ultra-low-power 32-kHz RC oscillator. To improve timing accuracy, the RC
oscillator can be automatically calibrated to the RF crystal in configurable intervals.
Detailed Description
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5.7
www.ti.com
Sniff Mode
The CC1120 device supports quick start up times, and requires few preamble bits. Sniff mode uses these
conditions to dramatically reduce the current consumption while the receiver is waiting for data.
Because the CC1120 device can wake up and settle much faster than the duration of most preambles, it
is not required to be in RX mode continuously while waiting for a packet to arrive. Instead, the enhanced
Wake-On-Radio feature can be used to put the device into sleep mode periodically. By setting an
appropriate sleep time, the CC1120 device can wake up and receive the packet when it arrives with no
performance loss. This sequence removes the need for accurate timing synchronization between
transmitter and receiver, and lets the user trade off current consumption between the transmitter and
receiver.
For more information, see the sniff mode design note (SWRA428).
5.8
Antenna Diversity
Antenna diversity can increase performance in a multipath environment. An external antenna switch is
required. The CC1201 device uses one of the GPIO pins to automatically control the switch. This device
also supports differential output control signals typically used in RF switches.
If antenna diversity is enabled, the GPIO alternates between high and low states until a valid RF input
signal is detected. An optional acknowledge packet can be transmitted without changing the state of the
GPIO.
An incoming RF signal can be validated by received signal strength or by using the automatic preamble
detector. Using the automatic preamble detector ensures a more robust system and avoids the need to
set a defined signal strength threshold (such a threshold sets the sensitivity limit of the system).
22
Detailed Description
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5.9
SWRS112H – JUNE 2011 – REVISED JULY 2015
WaveMatch
Advanced capture logic locks onto the synchronization word and does not require preamble settling bytes.
Therefore, receiver settling time is reduced to the settling time of the AGC, typically 4 bits.
The WaveMatch feature also greatly reduces false sync triggering on noise, further reducing the power
consumption and improving sensitivity and reliability. The same logic can also be used as a highperformance preamble detector to reliably detect a valid preamble in the channel.
See SWRC046 for more information.
Figure 5-2. Receiver Configurator in SmartRF™ Studio
Detailed Description
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6 Application, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
6.1
6.1.1
Application Information
Typical Application Circuit
NOTE
This section is intended only as an introduction. The reference designs listed in Section 6.1.2
show everything required.
Very few external components are required for the operation of the CC1120 device. Figure 6-1 shows a
typical application circuit. The board layout will greatly influence the RF performance of the CC1120
device. Figure 6-1 does not show decoupling capacitors for power pins.
Optional
vdd
25
AVDD_PFD_CHP
vdd
VDD_GUARD
DCPL_PFD_CHP 26
vdd
AVDD_SYNTH2 27
1
AVDD_XOSC 28
2 RESET_N
vdd
LPF1 24
LPF0 23
3 GPIO3
AVDD_SYNTH1 22
4 GPIO2
DCPL_VCO 21
CC1120
5 DVDD
vdd
LNA_N 20
6 DCPL
LNA_P 19
7 SI
TRX_SW 18
8 SCLK
N.C.
16
AVDD_RF
15
vdd
13 AVDD_IF
vdd
14 RBIAS
12 DVDD
vdd
CSn
11
10 GPIO0
9 SO (GPIO1)
PA 17
vdd
vdd
DCPL_XOSC 29
(optional control pin
from CC1120)
XOSC_Q1 30
EXT_XOSC 32
XOSC/
TCXO
XOSC_Q2 31
32 MHz
crystal
MCU connection
SPI interface and
optional gpio pins
Figure 6-1. Typical Application Circuit
24
Application, Implementation, and Layout
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6.1.2
SWRS112H – JUNE 2011 – REVISED JULY 2015
TI Reference Designs
The following reference designs are available for the CC1120 device:
CC1120EM-868-915-RD CC1120EM 868- to 915-MHz Reference Design
This RF Layout Reference Design demonstrates good decoupling and layout techniques for a low power
RF device operating in the 868-MHz and 915-MHz frequency bands.
CC1120EM 868/915 MHz Reference Design (SWRC222)
CC112x IPC 868- and 915-MHz 2-layer Reference Design (SWRR106)
CC112x IPC 868- and 915-MHz 4-layer Reference Design (SWRR107)
CC1120EM-169-RD CC1120EM 169-MHz Reference Design
This RF Layout Reference Design demonstrates good decoupling and layout techniques for a low power
RF device operating in the 169-MHz frequency band. (SWRC220)
CC1120EM-420-470-RD CC1120EM 420- to 470-MHz Reference Design
This RF Layout Reference Design demonstrates good decoupling and layout techniques for a low power
RF device operating in the 420-470 MHz frequency band. (SWRC221)
Application, Implementation, and Layout
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CC1120
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7 Device and Documentation Support
7.1
Device Support
7.1.1
Development Support
7.1.1.1
Configuration Software
The CC1120 device can be configured using the SmartRF Studio software (SWRC046). The SmartRF
Studio software is highly recommended for obtaining optimum register settings, and for evaluating
performance and functionality.
7.1.2
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, CC1120). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RHB) and the temperature range (for example, blank is the default commercial
temperature range) provides a legend for reading the complete device name for any CC1120 device.
For orderable part numbers of CC1120 devices in the QFN package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
26
Device and Documentation Support
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CC1120
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7.2
SWRS112H – JUNE 2011 – REVISED JULY 2015
Documentation Support
The following documents supplement the CC1120 transceiver. Copies of these documents are available
on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
7.2.1
SWRU295
CC112X/CC1175 Low-Power High Performance Sub-1 GHz RF Transceivers/Transmitter
User's Guide
SWRA398
Using the CC112x/CC1175 at 274 to 320 MHz
SWRC046
SmartRF Studio Software
SWRA428
CC112x/CC120x Sniff Mode Application Note
SWRZ039
CC112x, CC1175 Silicon Errata
SWRR106
CC112x IPC 868- and 915-MHz 2-layer Reference Design
SWRR107
CC112x IPC 868- and 915-MHz 4-layer Reference Design
SWRC220
CC1120EM 169-MHz Reference Design
SWRC221
CC1120EM 420- to 470-MHz Reference Design
SWRC222
CC1120EM 868- to 915-MHz Reference Design
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
7.3
Trademarks
SmartRF, E2E are trademarks of Texas Instruments.
7.4
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.5
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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8 Mechanical Packaging and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Mechanical Packaging and Orderable Information
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Copyright © 2011–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CC1120RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC1120
CC1120RHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 85
CC1120
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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