CC1311P3
SWRS255 – MARCH 2022
CC1311P3 SimpleLink™ High-Performance Sub-1 GHz Wireless MCU
With Integrated Power Amplifier
1 Features
Wireless microcontroller
•
•
•
•
•
•
Powerful 48-MHz Arm® Cortex®-M4 processor
352KB flash program memory
32KB of ultra-low leakage SRAM
8KB of Cache SRAM (Alternatively available as
general-purpose RAM)
Programmable radio includes support for 2(G)FSK, 4-(G)FSK, MSK, OOK, IEEE 802.15.4
PHY and MAC
Supports over-the-air upgrade (OTA)
Low power consumption
•
•
MCU consumption:
– 2.63 mA active mode, CoreMark®
– 55 μA/MHz running CoreMark
– 0.7 μA standby mode, RTC, 32KB RAM
– 0.1 μA shutdown mode, wake-up on pin
Radio Consumption:
– 5.4 mA RX at 868 MHz
– 24.9 mA TX at +14 dBm at 868 MHz
– 65 mA TX at +20 dBm at 915 MHz
Wireless protocol support
•
•
•
•
•
mioty
Wireless M-Bus
SimpleLink™ TI 15.4-stack
6LoWPAN
Proprietary systems
High performance radio
•
•
•
•
•
•
MCU peripherals
•
•
•
•
•
•
•
•
Digital peripherals can be routed to any GPIO
Four 32-bit or eight 16-bit general-purpose timers
12-bit ADC, 200 kSamples/s, 8 channels
8-bit DAC
Analog Comparator
UART, SSI, I2C, I2S
Real-time clock (RTC)
Integrated temperature and battery monitor
Security enablers
•
•
•
AES 128-bit cryptographic accelerator
True random number generator (TRNG)
Additional cryptography drivers available in
Software Development Kit (SDK)
Development tools and software
•
•
•
•
LP-CC1311P3 Development Kit
SimpleLink™ CC13xx and CC26xx Software
Development Kit (SDK)
SmartRF™ Studio for simple radio configuration
SysConfig system configuration tool
Operating range
•
•
•
On-chip buck DC/DC converter
1.8-V to 3.8-V single supply voltage
-40 to +105°C
Package
•
•
7-mm × 7-mm RGZ VQFN48 (26 GPIOs)
RoHS-compliant package
-121 dBm for 2.5-kbps long-range mode
-120 dBm at 4.8 kbps narrowband mode, 433 MHz
-118 dBm at 9.6 kbps narrowband mode, 868 MHz
-110 dBm at 50 kbps, 802.15.4, 868 MHz
Output power up to +20 dBm with temperature
compensation
Down to 4 kHz receiver filter bandwidth
Regulatory compliance
•
Suitable for systems targeting compliance with
these standards:
– ETSI EN 300 220 Receiver Cat. 1.5 and 2, EN
303 131, EN 303 204
– FCC CFR47 Part 15
– ARIB STD-T108
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC1311P3
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SWRS255 – MARCH 2022
2 Applications
•
•
Grid infrastructure
– Smart Meters – electricity meter, water meter,
gas meter, and heat cost allocator
– Grid communications – wireless
communications
– EV charging infrastructure – AC charging (pile)
station
– Other alternative energy – energy harvesting
Building automation
– Building security systems – motion detector,
door and window sensor, glass break detector,
panic button, electronic smart lock and IP
network camera
– HVAC systems – thermostat, environmental
sensor and HVAC controller
•
•
•
– Fire safety – smoke and head detector, gas
detector and fire alarm control panel
Retail Automation
– Retail automation & payment applications
– electronic shelf labels andportable POS
terminal
Personal Electronics
– RF remote controls
– Smart Speakers and Smart Displays
– Gaming and electronic and robotic toys
– Wearables (non-medical) and smart trackers
Wireless Modules
– Wireless third party modules
– Wireless communications modules
3 Description
The SimpleLink™ CC1311P3 device is a multiprotocol Sub-1 GHz wireless microcontroller (MCU) supporting
IEEE 802.15.4g, IPv6-enabled smart objects (6LoWPAN), mioty, proprietary systems, including the TI 15.4-Stack
(Sub-1 GHz). The CC1311P3 is based on an Arm® Cortex® M4 main processor and optimized for low-power
wireless communication and advanced sensing in grid infrastructure, building automation, retail automation,
personal electronics and medical applications.
The CC1311P3 has a software defined radio powered by an Arm® Cortex® M0, which allows support for
multiple physical layers and RF standards. The device supports operation in 143 to 176-MHz, 287 to 351-MHz,
359 to 527-MHz, 861 to 1054-MHz, and 1076 to 1315-MHz frequency bands. The CC1311P3 has an efficient
built-in PA that supports +14 dBm TX at 24.9 mA and +20 dBm TX at 65 mA. In RX it has -121 dBm sensitivity
and 88 dB blocking ±10 MHz in SimpleLink™ long-range mode with 2.5-kbps data rate.
The CC1311P3 has a low sleep current of 0.7 μA with RTC and 32KB RAM retention.
Consistent with many customers’ 10 to 15 years or longer life cycle requirements, TI has a product life cycle
policy with a commitment to product longevity and continuity of supply.
The CC1311P3 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth® Low
Energy, Thread, Zigbee, Wi-SUN®, Amazon Sidewalk, mioty, Sub-1 GHz MCUs, and host MCUs. CC1311P3 is
part of a scalable portfolio with flash sizes from 32KB to 704KB with pin-to-pin compatible package options.
The common SimpleLink™CC13xx and CC26xx Software Development Kit (SDK) and SysConfig system
configuration tool supports migration between devices in the portfolio. A comprehensive number of software
stacks, application examples and SimpleLink™ Academy training sessions are included in the SDK. For more
information, visit wireless connectivity.
Device Information
PART NUMBER(1)
CC1311P31T0RGZR
(1)
2
PACKAGE
BODY SIZE (NOM)
VQFN (48)
7.00 mm × 7.00 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section
12, or see the TI website.
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1
Su
b-
20
-d
B
m
G
H
z
PA
4 Functional Block Diagram
RF Core
cJTAG
Main CPU
40KB
ROM
ADC
ADC
®
®
Arm Cortex -M4
Processor
352KB
Flash
with 8KB
Cache
Digital PLL
DSP Modem
48 MHz
32KB
SRAM
SRAM
Arm® Cortex®-M0
Processor
ROM
General Hardware Peripherals and Modules
I2C
4× 32-bit Timers
8-bit DAC
UART
SSI (SPI)
12-bit ADC, 200 ks/s
I2S
Watchdog Timer
Low-Power Comparator
26 GPIOs
32 ch. µDMA
Time-to-Digital Converter
AES & TRNG
RTC
Temperature and
Battery Monitor
LDO, Clocks, and References
Optional DC/DC Converter
Figure 4-1. CC1311P3 Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Comparison......................................................... 5
7 Pin Configuration and Functions...................................6
7.1 Pin Diagram – RGZ Package (Top View)....................6
7.2 Signal Descriptions – RGZ Package...........................7
7.3 Connections for Unused Pins and Modules................8
8 Specifications.................................................................. 9
8.1 Absolute Maximum Ratings........................................ 9
8.2 ESD Ratings............................................................... 9
8.3 Recommended Operating Conditions.........................9
8.4 Power Supply and Modules........................................ 9
8.5 Power Consumption - Power Modes........................ 10
8.6 Power Consumption - Radio Modes......................... 11
8.7 Nonvolatile (Flash) Memory Characteristics............. 11
8.8 Thermal Resistance Characteristics......................... 11
8.9 RF Frequency Bands................................................ 12
8.10 861 MHz to 1054 MHz - Receive (RX)....................13
8.11 861 MHz to 1054 MHz - Transmit (TX) .................. 16
8.12 861 MHz to 1054 MHz - PLL Phase Noise
Wideband Mode.......................................................... 17
8.13 861 MHz to 1054 MHz - PLL Phase Noise
Narrowband Mode.......................................................18
8.14 359 MHz to 527 MHz - Receive (RX)......................19
8.15 359 MHz to 527 MHz - Transmit (TX) .................... 21
8.16 359 MHz to 527 MHz - PLL Phase Noise............... 21
8.17 Timing and Switching Characteristics..................... 22
8.18 Peripheral Characteristics.......................................25
8.19 Typical Characteristics............................................ 31
9 Detailed Description......................................................40
9.1 Overview................................................................... 40
9.2 System CPU............................................................. 40
9.3 Radio (RF Core)........................................................41
9.4 Memory..................................................................... 43
9.5 Cryptography............................................................ 44
9.6 Timers....................................................................... 45
9.7 Serial Peripherals and I/O.........................................46
9.8 Battery and Temperature Monitor............................. 46
9.9 µDMA........................................................................ 46
9.10 Debug..................................................................... 46
9.11 Power Management................................................ 47
9.12 Clock Systems........................................................ 48
9.13 Network Processor..................................................48
10 Application, Implementation, and Layout................. 49
10.1 Reference Designs................................................. 49
11 Device and Documentation Support..........................50
11.1 Device Nomenclature..............................................50
11.2 Tools and Software..................................................51
11.3 Documentation Support.......................................... 53
11.4 Support Resources................................................. 53
11.5 Trademarks............................................................. 53
11.6 Electrostatic Discharge Caution.............................. 54
11.7 Glossary.................................................................. 54
12 Mechanical, Packaging, and Orderable
Information.................................................................... 55
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
March 2022
4
REVISION
*
NOTES
Initial Release
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6 Device Comparison
X
7 X 7 mm VQFN (48)
X
5 X 5 mm VQFN (40)
RAM +
GPIO
Cache (KB)
5 X 5 mm VQFN (32)
X
FLASH
(KB)
4 X 4 mm VQFN (32)
X
X
+20 dBm PA
X
X
Multiprotocol
X
CC1311P3
Thread
CC1311R3
PACKAGE SIZE
ZigBee
X
Bluetooth® 5.2 LE
X
Sidewalk
X
Wi-SUN®
mioty
CC1310
Device
2.4GHz Prop.
Wireless M-Bus
Sub-1 GHz Prop.
RADIO SUPPORT
32-128
16-20 + 8
10-30
352
32 + 8
22-30
352
32 + 8
26
X
352
80 + 8
30
X
704
144 + 8
30
X
X
X
X
X
CC1312R
X
X
X
X
CC1312R7
X
X
X
X
CC1352R
X
X
X
X
X
X
X
X
X
352
80 + 8
28
X
CC1352P
X
X
X
X
X
X
X
X
X
X
352
80 + 8
26
X
CC1352P7
X
X
X
X
X
X
X
X
X
X
X
X
X
704
144 + 8
26
CC2640R2F
X
128
20 + 8
10-31
CC2642R
X
352
80 + 8
31
X
CC2642R-Q1
X
352
80 + 8
31
X
352
32 + 8
23-31
X
X
352
32 + 8
22-26
X
X
CC2651R3
X
X
X
CC2651P3
X
X
X
X
X
X
X
X
CC2652R
X
X
X
X
X
352
80 + 8
31
X
CC2652RB
X
X
X
X
X
352
80 + 8
31
X
CC2652R7
X
X
X
X
X
704
144 + 8
31
X
CC2652P
X
X
X
X
X
X
352
80 + 8
26
X
CC2652P7
X
X
X
X
X
X
704
144 + 8
26
X
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7 Pin Configuration and Functions
38 DIO_25
37 DIO_24
40 DIO_27
39 DIO_26
42 DIO_29
41 DIO_28
44 VDDS
43 DIO_30
46 X48M_N
45 VDDR
48 VDDR_RF
47 X48M_P
7.1 Pin Diagram – RGZ Package (Top View)
NC
1
36 DIO_23
NC
2
35 RESET_N
RF_P
3
34 VDDS_DCDC
RF_N
4
33 DCDC_SW
X32K_Q1
8
29 DIO_19
X32K_Q2
9
28 DIO_18
DIO_5 10
27 DIO_17
DIO_6 11
26 DIO_16
DIO_7 12
25 JTAG_TCKC
DCOUPL 23
JTAG_TMSC 24
30 DIO_20
DIO_15 21
VDDS3 22
31 DIO_21
7
DIO_13 19
DIO_14 20
6
RX_TX
DIO_11 17
DIO_12 18
32 DIO_22
DIO_9 15
DIO_10 16
5
VDDS2 13
DIO_8 14
TX_20DBM_P
TX_20DBM_N
Figure 7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:
•
•
•
•
•
•
Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 24, JTAG_TMSC
Pin 26, DIO_16
Pin 27, DIO_17
The following I/O pins marked in Figure 7-1 in italics have analog capabilities:
•
•
•
•
•
•
•
•
6
Pin 36, DIO_23
Pin 37, DIO_24
Pin 38, DIO_25
Pin 39, DIO_26
Pin 40, DIO_27
Pin 41, DIO_28
Pin 42, DIO_29
Pin 43, DIO_30
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7.2 Signal Descriptions – RGZ Package
Table 7-1. Signal Descriptions – RGZ Package
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
DCDC_SW
33
—
Power
Output from internal DC/DC converter(1)
DCOUPL
23
—
Power
For decoupling of internal 1.27 V regulated digital-supply (2)
DIO_5
10
I/O
Digital
GPIO, high-drive capability
DIO_6
11
I/O
Digital
GPIO, high-drive capability
DIO_7
12
I/O
Digital
GPIO, high-drive capability
DIO_8
14
I/O
Digital
GPIO
DIO_9
15
I/O
Digital
GPIO
DIO_10
16
I/O
Digital
GPIO
DIO_11
17
I/O
Digital
GPIO
DIO_12
18
I/O
Digital
GPIO
DIO_13
19
I/O
Digital
GPIO
DIO_14
20
I/O
Digital
GPIO
DIO_15
21
I/O
Digital
GPIO
DIO_16
26
I/O
Digital
GPIO, JTAG_TDO, high-drive capability
DIO_17
27
I/O
Digital
GPIO, JTAG_TDI, high-drive capability
DIO_18
28
I/O
Digital
GPIO
DIO_19
29
I/O
Digital
GPIO
DIO_20
30
I/O
Digital
GPIO
DIO_21
31
I/O
Digital
GPIO
DIO_22
32
I/O
Digital
GPIO
DIO_23
36
I/O
Digital or Analog
GPIO, analog capability
DIO_24
37
I/O
Digital or Analog
GPIO, analog capability
DIO_25
38
I/O
Digital or Analog
GPIO, analog capability
DIO_26
39
I/O
Digital or Analog
GPIO, analog capability
DIO_27
40
I/O
Digital or Analog
GPIO, analog capability
DIO_28
41
I/O
Digital or Analog
GPIO, analog capability
DIO_29
42
I/O
Digital or Analog
GPIO, analog capability
DIO_30
43
I/O
Digital or Analog
GPIO, analog capability
EGP
—
—
GND
Ground – exposed ground pad(3)
JTAG_TMSC
24
I/O
Digital
JTAG TMSC, high-drive capability
JTAG_TCKC
25
I
Digital
JTAG TCKC
RESET_N
35
I
Digital
Reset, active low. No internal pullup resistor
RF_P
3
—
RF
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_N
4
—
RF
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RX_TX
7
—
RF
Optional bias pin for the RF LNA
TX_20DBM_P
5
—
RF
Positive high-power TX signal
TX_20DBM_N
6
—
RF
Negative high-power TX signal
VDDR
45
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (4) (6)
VDDR_RF
48
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (5) (6)
VDDS
44
—
Power
1.8-V to 3.8-V main chip supply(1)
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Table 7-1. Signal Descriptions – RGZ Package (continued)
PIN
I/O
TYPE
13
—
Power
1.8-V to 3.8-V DIO supply(1)
VDDS3
22
—
Power
1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC
34
—
Power
1.8-V to 3.8-V DC/DC converter supply
X48M_N
46
—
Analog
48-MHz crystal oscillator pin 1
X48M_P
47
—
Analog
48-MHz crystal oscillator pin 2
X32K_Q1
8
—
Analog
32-kHz crystal oscillator pin 1
X32K_Q2
9
—
Analog
32-kHz crystal oscillator pin 2
NAME
NO.
VDDS2
(1)
(2)
(3)
(4)
(5)
(6)
DESCRIPTION
For more details, see the device technical reference manual listed in Section 11.3.
Do not supply external circuitry from this pin.
EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
Output from internal DC/DC and LDO is trimmed to 1.68 V.
7.3 Connections for Unused Pins and Modules
Table 7-2. Connections for Unused Pins – RGZ Package
FUNCTION
GPIO
DIO_n
32.768-kHz crystal
No Connects
DC/DC converter(2)
(1)
(2)
8
SIGNAL NAME
PIN NUMBER
ACCEPTABLE PRACTICE(1)
PREFERRED
PRACTICE(1)
10–12
14–21
26–32
36–43
NC or GND
NC
NC or GND
NC
X32K_Q1
8
X32K_Q2
9
NC
1–2
NC
NC
DCDC_SW
33
NC
NC
VDDS_DCDC
34
VDDS
VDDS
NC = No connect
When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
VDDS(3)
MIN
MAX
–0.3
4.1
V
–0.3
VDDS + 0.3, max 4.1
V
–0.3
VDDR + 0.3, max 2.25
V
Voltage scaling enabled
–0.3
VDDS
Voltage scaling disabled, internal reference
–0.3
1.49
Voltage scaling disabled, VDDS as reference
–0.3
VDDS / 2.9
Supply voltage
Voltage on any digital
pin(4) (5)
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
Vin
Voltage on ADC input
Input level, RF pins (RF_P and RF_N)
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature
–40
UNIT
V
10
dBm
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
All voltage values are with respect to ground, unless otherwise noted.
VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
Including analog capable DIOs.
Injection current is not supported on any GPIO pin
8.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
All pins
±2000
V
Charged device model (CDM), per JESD22-C101(2)
All pins
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Operating ambient temperature(1) (2)
–40
105
°C
temperature(1) (2)
–40
115
°C
1.8
3.8
V
Operating junction
Operating supply voltage (VDDS)
Operating supply voltage (VDDS), boost mode
VDDR = 1.95 V
+14 dBm RF output sub-1 GHz power amplifier
2.1
3.8
V
Operating supply voltage (VDDS), boost mode
+20 dBm RF output high power amplifier
3.3
3.8
V
Rising supply voltage slew rate
0
100
mV/µs
Falling supply voltage slew rate(3)
0
20
mV/µs
(1)
(2)
(3)
Operation at or near maximum operating temperature for extended durations will result in lifetime reduction.
For thermal resistance characteristics refer to Section 8.8.
For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VDDS Power-on-Reset (POR) threshold
TYP
MAX
UNIT
1.1 - 1.55
V
VDDS Brown-out Detector (BOD) (1)
Rising threshold
1.77
V
VDDS Brown-out Detector (BOD), before initial boot (2)
Rising threshold
1.70
V
Falling threshold
1.75
V
VDDS Brown-out Detector (BOD)
(1)
(1)
For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V)
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(2)
Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
8.5 Power Consumption - Power Modes
When measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled
unless otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold
115
Shutdown. No clocks running, no retention
115
RTC running, CPU, 32KB RAM and (partial) register retention.
RCOSC_LF
0.7
µA
RTC running, CPU, 32KB RAM and (partial) register retention
XOSC_LF
0.8
µA
RTC running, CPU, 32KB RAM and (partial) register retention.
RCOSC_LF
2.1
µA
RTC running, CPU, 32KB RAM and (partial) register retention.
XOSC_LF
2.2
µA
Idle
Supply Systems and RAM powered
RCOSC_HF
570
µA
Active
MCU running CoreMark at 48 MHz
RCOSC_HF
2.50
mA
Peripheral power
domain
Delta current with domain enabled
47.0
Serial power domain
Delta current with domain enabled
3.3
RF Core
Delta current with power domain enabled,
clock enabled, RF core idle
122
µDMA
Delta current with clock enabled, module is idle
58.1
Timers
Delta current with clock enabled, module is idle(1)
87.0
I2C
Delta current with clock enabled, module is idle
11.6
I2S
Delta current with clock enabled, module is idle
25.8
SSI
Delta current with clock enabled, module is idle
61.3
UART
Delta current with clock enabled, module is idle
125
CRYPTO (AES)
Delta current with clock enabled, module is idle
25.2
TRNG
Delta current with clock enabled, module is idle
23.3
Reset and Shutdown
Standby
without cache retention
Icore
Standby
with cache retention
nA
Peripheral Current Consumption
Iperi
(1)
10
µA
Only one GPTimer running
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8.6 Power Consumption - Radio Modes
When measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled
unless otherwise noted.
High power PA connected to VDDS unless otherwise noted.
Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm
setting where this current is already included).
Relevant Icore and Iperi currents are included in below numbers.
PARAMETER
TEST CONDITIONS
TYP
UNIT
5.4
mA
7.4
mA
+10 dBm output power setting
868 MHz
13.9
mA
Radio transmit current
Boost mode, regular PA
+14 dBm output power setting
868 MHz
24.9
mA
Radio transmit current
High-power PA
Transmit (TX), +20 dBm output power setting
915 MHz, VDDS = 3.3 V
65
mA
Radio receive current, 868 MHz
0 dBm output power setting
868 MHz
Radio transmit current
Regular PA
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Flash sector size
MAX
8
UNIT
KB
Supported flash erase cycles before failure, full bank(1) (5)
30
k Cycles
Supported flash erase cycles before failure, single sector(2)
60
k Cycles
Maximum number of write operations per row before sector
erase(3)
83
Flash retention
105 °C
Flash sector erase current
Average delta current
9.7
Zero cycles
10
Flash sector erase time(4)
Average delta current, 4 bytes at a time
Flash write time(4)
4 bytes at a time
(3)
(4)
(5)
Years
30k cycles
Flash write current
(1)
(2)
11.4
Write
Operations
mA
ms
4000
ms
5.3
mA
21.6
µs
A full bank erase is counted as a single erase cycle on each sector.
Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
This number is dependent on Flash aging and increases over time and erase cycles
Aborting flash during erase or program modes is not a safe operation.
8.8 Thermal Resistance Characteristics
PACKAGE
THERMAL METRIC(1)
RGZ
(VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
25.0
°C/W(2)
RθJC(top)
Junction-to-case (top) thermal resistance
14.5
°C/W(2)
RθJB
Junction-to-board thermal resistance
8.7
°C/W(2)
ψJT
Junction-to-top characterization parameter
0.2
°C/W(2)
ψJB
Junction-to-board characterization parameter
8.6
°C/W(2)
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
°C/W(2)
(1)
(2)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
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8.9 RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
Frequency bands
12
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TYP
MAX
1076
1315
861
1054
431
527
359
439
287
351
143
176
UNIT
MHz
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8.10 861 MHz to 1054 MHz - Receive (RX)
When measured on CC1311-P3EM-7XD7793-PA915 with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4000
kHz
General Parameters
Digital channel filter programmable receive
bandwidth
4
Data rate step size
Spurious emissions 25 MHz to 1 GHz
Spurious emissions 1 GHz to 13 GHz
868 MHz
Conducted emissions measured according to ETSI EN 300 220
1.5
bps
< -57
dBm
< -47
dBm
IEEE 802.15.4, 50 kbps, ±25 kHz Deviation, 2-GFSK, 100 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
–110
dBm
Saturation limit
BER = 10–2, 868 MHz
10
dBm
Selectivity, ±200 kHz
BER =
MHz(1)
44
dB
Selectivity, ±400 kHz
BER = 10–2, 868 MHz(1)
48
dB
Blocking, ±1 MHz
BER = 10–2, 868 MHz(1)
58
dB
Blocking, ±2 MHz
BER = 10–2, 868 MHz(1)
62
dB
Blocking, ±5 MHz
BER = 10–2, 868 MHz(1)
70
dB
Blocking, ±10 MHz
BER = 10–2, 868 MHz(1)
77
dB
Image rejection (image compensation
enabled)
BER = 10–2, 868 MHz(1)
41
dB
RSSI dynamic range
Starting from the sensitivity limit
95
dB
RSSI accuracy
Starting from the sensitivity limit across the given dynamic range
±3
dB
10–2,
868
100 kbps, ±25 kHz Deviation, 2-GFSK, 137 kHz RX Bandwidth
Sensitivity 100 kbps
1% PER, 127 byte payload, 868 MHz
Selectivity, ±200 kHz
1% PER, 127 byte payload, 868 MHz. Wanted signal at -96 dBm
-104
31
dBm
dB
Selectivity, ±400 kHz
1% PER, 127 byte payload, 868 MHz. Wanted signal at -96 dBm
37
dB
Co-channel rejection
1% PER, 127 byte payload, 868 MHz. Wanted signal at -79 dBm
-9
dB
200 kbps, ±50 kHz Deviation, 2-GFSK, 311 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
10–2,
915 MHz
–103
dBm
–102
dBm
Sensitivity
BER =
Selectivity, ±400 kHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
45
dB
Selectivity, ±800 kHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
49
dB
Blocking, ±2 MHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
57
dB
Blocking, ±10 MHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
69
dB
500 kbps, ±190 kHz Deviation, 2-GFSK, 1150 kHz RX Bandwidth
Sensitivity 500 kbps
1% PER, 127 byte payload, 915 MHz
-94
dBm
Selectivity, ±1 MHz
1% PER, 127 byte payload, 915 MHz. Wanted signal at -88 dBm
14
dB
Selectivity, ±2 MHz
1% PER, 127 byte payload, 915 MHz. Wanted signal at -88 dBm
42
dB
Co-channel rejection
1% PER, 127 byte payload, 915 MHz. Wanted signal at -71 dBm
-9
dB
1 Mbps, ±350 kHz Deviation, 2-GFSK, 1.3 MHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
-97
dBm
Sensitivity
BER = 10–2, 915 MHz
-96
dBm
Blocking, +2 MHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
43
dB
Blocking, -2 MHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
26
dB
Blocking, +10 MHz
BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit.
54
dB
48
dB
Blocking, -10 MHz
BER =
10–2,
915 MHz. Wanted signal 3 dB above sensitivity limit.
SimpleLink™ Long Range, 2.5/5 kbps (20 ksps), ±5 kHz Deviation, 2-GFSK, 34 kHz RX Bandwidth, FEC = 1:2, DSSS = 1:4/1:2
Sensitivity
2.5 kbps, BER = 10–2, 868 MHz
-121
dBm
Sensitivity
5 kbps, BER = 10–2, 868 MHz
-119
dBm
Saturation limit
2.5 kbps, BER = 10–2, 868 MHz
10
dBm
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When measured on CC1311-P3EM-7XD7793-PA915 with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
10–2,
MIN
TYP
MAX
UNIT
Selectivity, ±100 kHz
2.5 kbps, BER =
MHz(1)
49
dB
Selectivity, ±200 kHz
2.5 kbps, BER = 10–2, 868 MHz(1)
50
dB
Selectivity, ±300 kHz
2.5 kbps, BER = 10–2, 868 MHz(1)
51
dB
Blocking, ±1 MHz
2.5 kbps, BER = 10–2, 868 MHz(1)
63
dB
Blocking, ±2 MHz
2.5 kbps, BER = 10–2, 868 MHz(1)
69
dB
Blocking, ±5 MHz
2.5 kbps, BER =
MHz(1)
79
dB
Blocking, ±10 MHz
2.5 kbps, BER = 10–2, 868 MHz(1)
88
dB
47
dB
10–2,
868
868
Image rejection (image compensation
enabled)
2.5 kbps, BER =
RSSI dynamic range
Starting from the sensitivity limit
97
dB
RSSI accuracy
Starting from the sensitivity limit across the given dynamic range
±3
dB
10–2,
868
MHz(1)
Narrowband, 9.6 kbps, ±2.4 kHz Deviation, 2-GFSK, 17.1 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
Adjacent Channel Rejection
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm). Interferer ±20 kHz
41
dB
Alternate Channel Rejection
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm). Interferer ±40 kHz
42
dB
Blocking, ±1 MHz
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm).
65
dB
10–2,
-117
dBm
Blocking, ±2 MHz
BER =
868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm).
70
dB
Blocking, ±10 MHz
BER = 10–2, 868 MHz. Wanted signal 3 dB above the ETSI
reference sensitivity limit (-104.6 dBm).
85
dB
Wi-SUN, 2-GFSK
Sensitivity
50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,
868 MHz, 10% PER, 250 byte payload
-107
Selectivity, ±100 kHz, 50 kbps, ±12.5 kHz
deviation, 2-GFSK, 868.3 MHz
50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
30
dB
Selectivity, ±200 kHz, 50 kbps, ±12.5 kHz
deviation, 2-GFSK, 868.3 MHz
50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
36
dB
Sensitivity
50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,
918.2 MHz, 10% PER, 250 byte payload
Selectivity, ±200 kHz, 50 kbps, ±25 kHz
deviation, 2-GFSK, 918.2 MHz
50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,
918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
34
dB
Selectivity, ±400 kHz, 50 kbps, ±25 kHz
deviation, 2-GFSK, 918.2 MHz
50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth,
918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
41
dB
Sensitivity
100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,
868 MHz, 10% PER, 250 byte payload
-104
Selectivity, ±200 kHz, 100 kbps, ±25 kHz
deviation, 2-GFSK, 868.3 MHz
100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
37
dB
Selectivity, ±400 kHz, 100 kbps, ±25 kHz
deviation, 2-GFSK, 868.3 MHz
100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth,
868.3 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
45
dB
Sensitivity
100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload
-102
Selectivity, ±400 kHz, 100 kbps, ±50 kHz
deviation, 2-GFSK, 920.9 MHz
100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
40
dB
Selectivity, ±800 kHz, 100 kbps, ±50 kHz
deviation, 2-GFSK, 920.9 MHz
100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
49
dB
14
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dBm
dBm
dBm
dBm
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When measured on CC1311-P3EM-7XD7793-PA915 with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Sensitivity
150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload
-99
dBm
Selectivity, ±400 kHz, 150 kbps, ±37.5 kHz
deviation, 2-GFSK, 920.9 MHz
150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
41
dB
Selectivity, ±800 kHz, 150 kbps, ±37.5 kHz
deviation, 2-GFSK, 920.9 MHz
150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth,
920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
47
dB
Sensitivity
200 kbps, ±50 kHz deviation, 2-GFSK, 918.4 MHz, 273 kHz RX
BW, 10% PER, 250 byte payload
-99
dBm
Selectivity, ±400 kHz, 200 kbps, ±50 kHz
deviation, 2-GFSK, 918.4 MHz
200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
42
dB
Selectivity, ±800 kHz, 200 kbps, ±50 kHz
deviation, 2-GFSK, 918.4 MHz
200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
49
dB
Sensitivity
200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 920.8 MHz, 10% PER, 250 byte payload
-99
dBm
Selectivity, ±600 kHz, 200 kbps, ±100 kHz
deviation, 2-GFSK, 920.8 MHz
200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 920.8 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
45
dB
Selectivity, ±1200 kHz, 200 kbps, ±100 kHz
deviation, 2-GFSK, 920.8 MHz
200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX
Bandwidth, 920.8 MHz, 10% PER, 250 byte payload. Wanted
signal 3 dB above sensitivity level
52
dB
Sensitivity
300 kbps, ±75 kHz deviation, 2-GFSK, 917.6 MHz, 498 kHz RX
BW, 10% PER, 250 byte payload
-97
dBm
Selectivity, ±600 kHz, 300 kbps, ±75 kHz
deviation, 2-GFSK, 917.6 MHz
300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth,
917.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
42
dB
Selectivity, ±1200 kHz, 300 kbps, ±75 kHz
deviation, 2-GFSK, 917.6 MHz
300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth,
917.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB
above sensitivity level
47
dB
(1)
Wanted signal 3 dB above the reference sensitivity limit according to ETSI EN 300 220 v. 3.1.1
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8.11 861 MHz to 1054 MHz - Transmit (TX)
Measured on the CC1311-P3EM-7XD7793-PA915 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled and high power PA connected to VDDS using 2-GFSK, 50 kbps, ±25 kHz deviation unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General parameters
Max output power, boost mode
Regular PA
VDDR = 1.95 V
Minimum supply voltage (VDDS ) for boost
mode is 2.1 V
868 MHz and 915 MHz
14
dBm
Max output power,
Regular PA
868 MHz and 915 MHz
13
dBm
Max output power,
High power PA
915 MHz
VDDS = 3.3V
20
dBm
Output power programmable range
Regular PA
868 MHz and 915 MHz
24
dB
Output power programmable range
High power PA
868 MHz and 915 MHz
VDDS = 3.3V
6
dB
Output power variation over temperature
Regular PA
+10 dBm setting
Over recommended temperature operating
range
±2
dB
Output power variation over temperature
Boost mode, regular PA
+14 dBm setting
Over recommended temperature operating
range
±1.5
dB
+14 dBm setting
ETSI restricted bands
< -54
dBm
+14 dBm setting
ETSI outside restricted bands
< -36
dBm
1 GHz to 12.75 GHz
(outside ETSI restricted bands)
+14 dBm setting
measured in 1 MHz bandwidth (ETSI)
< -30
dBm
30 MHz to 88 MHz
(within FCC restricted bands)
+14 dBm setting
< -56
dBm
88 MHz to 216 MHz
(within FCC restricted bands)
+14 dBm setting
< -52
dBm
216 MHz to 960 MHz
(within FCC restricted bands)
+14 dBm setting
< -50
dBm
960 MHz to 2390 MHz and above
2483.5 MHz (within FCC restricted
band)
+14 dBm setting
–1
LSB
±4
LSB
INL
Integral nonlinearity
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
reference(2),
Internal 4.3 V equivalent
9.6 kHz input tone, DC/DC enabled
SFDR
Bits
200
Internal 4.3 V equivalent reference(2)
Differential nonlinearity
SINAD,
SNDR
V
Offset
DNL(4)
THD
UNIT
12
Sample Rate
ENOB
MAX
VDDS
Effective number of bits
Total harmonic distortion
Signal-to-noise
and
distortion ratio
Spurious-free dynamic range
200 kSamples/s,
9.8
9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
10.1
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
11.1
Internal reference, voltage scaling disabled,
14-bit mode, 200 kSamples/s, 300 Hz input tone (5)
11.3
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 300 Hz input tone (5)
11.6
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
–65
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
–70
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
–72
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
60
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
63
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
68
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
70
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
73
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
75
dB
dB
dB
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Current consumption
Internal 4.3 V equivalent reference(2)
0.39
mA
Current consumption
VDDS as reference
0.56
mA
Reference voltage
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Reference voltage
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage
Reference voltage
50
Bits
Clock Cycles
4.3(2) (3)
V
1.48
V
VDDS as reference, input voltage scaling enabled
VDDS
V
VDDS as reference, input voltage scaling disabled
VDDS /
2.82(3)
V
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8.18.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
Input impedance
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
TYP
MAX
>1
UNIT
MΩ
Using IEEE Std 1241-2010 for terminology and test methods
Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
Applied voltage must be within Absolute Maximum Ratings at all times
No missing codes
ADC_output = Σ(4n samples ) >> n, n = desired extra bits
8.18.2 DAC
8.18.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Resolution
VDDS
FDAC
Supply voltage
Clock frequency
Voltage output settling time
8
1.8
3.8
External Load(4), any VREF, pre-charge OFF, DAC charge-pump
OFF
2.0
3.8
Any load, VREF = DCOUPL, pre-charge ON
2.6
3.8
Buffer ON (recommended for external load)
16
250
Buffer OFF (internal load)
16
1000
VREF = VDDS, buffer OFF, internal load
VREF = VDDS, buffer ON, external capacitive load = 20
13
pF(3)
20
External resistive load
200
10
kHz
pF
MΩ
Short circuit current
400
VDDS = 3.8 V, DAC charge-pump OFF
50.8
VDDS = 3.0 V, DAC charge-pump ON
51.7
VDDS = 3.0 V, DAC charge-pump OFF
53.2
Max output impedance Vref =
VDDS, buffer ON, CLK 250
VDDS = 2.0 V, DAC charge-pump ON
kHz
VDDS = 2.0 V, DAC charge-pump OFF
V
1 / FDAC
13.8
External capacitive load
ZMAX
Bits
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
48.7
µA
kΩ
70.2
VDDS = 1.8 V, DAC charge-pump ON
46.3
VDDS = 1.8 V, DAC charge-pump OFF
88.9
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
Differential nonlinearity
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 250 kHz
±1
Differential nonlinearity
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 16 kHz
±1.2
DNL
Offset error(2)
Load = Continuous Time
Comparator
26
LSB(1)
VREF = VDDS = 3.8 V
±0.64
VREF = VDDS= 3.0 V
±0.81
VREF = VDDS = 1.8 V
±1.27
VREF = DCOUPL, pre-charge ON
±3.43
VREF = DCOUPL, pre-charge OFF
±2.88
VREF = ADCREF
±2.37
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8.18.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Offset error(2)
Load = Low Power Clocked
Comparator
Max code output voltage
variation(2)
Load = Continuous Time
Comparator
Max code output voltage
variation(2)
Load = Low Power Clocked
Comparator
Output voltage range(2)
Load = Continuous Time
Comparator
Output voltage range(2)
Load = Low Power Clocked
Comparator
TEST CONDITIONS
MIN
TYP
VREF = VDDS= 3.8 V
±0.78
VREF = VDDS = 3.0 V
±0.77
VREF = VDDS= 1.8 V
±3.46
VREF = DCOUPL, pre-charge ON
±3.44
VREF = DCOUPL, pre-charge OFF
±4.70
VREF = ADCREF
±4.11
VREF = VDDS = 3.8 V
±1.53
VREF = VDDS = 3.0 V
±1.71
VREF = VDDS= 1.8 V
±2.10
VREF = DCOUPL, pre-charge ON
±6.00
VREF = DCOUPL, pre-charge OFF
±3.85
VREF = ADCREF
±5.84
VREF = VDDS= 3.8 V
±2.92
VREF =VDDS= 3.0 V
±3.06
VREF = VDDS= 1.8 V
±3.91
VREF = DCOUPL, pre-charge ON
±7.84
VREF = DCOUPL, pre-charge OFF
±4.06
VREF = ADCREF
±6.94
VREF = VDDS = 3.8 V, code 1
0.03
VREF = VDDS = 3.8 V, code 255
3.62
VREF = VDDS= 3.0 V, code 1
0.02
VREF = VDDS= 3.0 V, code 255
2.86
VREF = VDDS= 1.8 V, code 1
0.01
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.01
VREF = DCOUPL, pre-charge OFF, code 255
1.21
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
VREF = ADCREF, code 1
0.01
VREF = ADCREF, code 255
1.41
VREF = VDDS = 3.8 V, code 1
0.03
VREF = VDDS= 3.8 V, code 255
3.61
VREF = VDDS= 3.0 V, code 1
0.02
VREF = VDDS= 3.0 V, code 255
2.85
VREF = VDDS = 1.8 V, code 1
0.01
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.01
VREF = DCOUPL, pre-charge OFF, code 255
1.21
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
VREF = ADCREF, code 1
0.01
VREF = ADCREF, code 255
1.41
MAX
UNIT
LSB(1)
LSB(1)
LSB(1)
V
V
External Load (Keysight 34401A Multimeter)
INL
Integral nonlinearity
DNL
Differential nonlinearity
VREF = VDDS, FDAC = 250 kHz
±1
VREF = DCOUPL, FDAC = 250 kHz
±1
VREF = ADCREF, FDAC = 250 kHz
±1
VREF = VDDS, FDAC = 250 kHz
±1
LSB(1)
LSB(1)
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8.18.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Offset error
Max code output voltage
variation
Output voltage range
Load = Low Power Clocked
Comparator
(1)
(2)
(3)
(4)
28
TEST CONDITIONS
MIN
TYP
VREF = VDDS= 3.8 V
±0.20
VREF = VDDS= 3.0 V
±0.25
VREF = VDDS = 1.8 V
±0.45
VREF = DCOUPL, pre-charge ON
±1.55
VREF = DCOUPL, pre-charge OFF
±1.30
VREF = ADCREF
±1.10
VREF = VDDS= 3.8 V
±0.60
VREF = VDDS= 3.0 V
±0.55
VREF = VDDS= 1.8 V
±0.60
VREF = DCOUPL, pre-charge ON
±3.45
VREF = DCOUPL, pre-charge OFF
±2.10
VREF = ADCREF
±1.90
VREF = VDDS = 3.8 V, code 1
0.03
VREF = VDDS = 3.8 V, code 255
3.61
VREF = VDDS = 3.0 V, code 1
0.02
VREF = VDDS= 3.0 V, code 255
2.85
VREF = VDDS= 1.8 V, code 1
0.02
VREF = VDDS = 1.8 V, code 255
1.71
VREF = DCOUPL, pre-charge OFF, code 1
0.02
VREF = DCOUPL, pre-charge OFF, code 255
1.20
VREF = DCOUPL, pre-charge ON, code 1
1.27
VREF = DCOUPL, pre-charge ON, code 255
2.46
VREF = ADCREF, code 1
0.02
VREF = ADCREF, code 255
1.42
MAX
UNIT
LSB(1)
LSB(1)
V
1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
Includes comparator offset
A load > 20 pF will increases the settling time
Keysight 34401A Multimeter
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8.18.3 Temperature and Battery Monitor
8.18.3.1 Temperature Sensor
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
2
°C
Accuracy
-40 °C to 0 °C
±4.0
°C
Accuracy
0 °C to 105 °C
±2.5
°C
3.9
°C/V
Supply voltage
(1)
coefficient(1)
The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.18.3.2 Battery Monitor
Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
25
Range
mV
1.8
3.8
Integral nonlinearity (max)
Accuracy
UNIT
VDDS = 3.0 V
V
23
mV
22.5
mV
Offset error
-32
mV
Gain error
-1
%
8.18.4 Comparator
8.18.4.1 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range(1)
TYP
0
Offset
Measured at VDDS / 2
Decision time
Step from –10 mV to 10 mV
Current consumption
Internal reference
(1)
MIN
MAX
UNIT
VDDS
V
±5
mV
0.78
µs
9.2
µA
The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.18.5 GPIO
8.18.5.1 GPIO DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
1.56
V
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
0.24
V
GPIO VOH at 4 mA load
IOCURR = 1
1.59
V
GPIO VOL at 4 mA load
IOCURR = 1
0.21
V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
73
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
19
µA
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.08
V
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
0.73
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.35
V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
2.59
V
GPIO VOL at 8 mA load
IOCURR = 2, high-drive GPIOs only
0.42
V
GPIO VOH at 4 mA load
IOCURR = 1
2.63
V
GPIO VOL at 4 mA load
IOCURR = 1
0.40
V
TA = 25 °C, VDDS = 3.0 V
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8.18.5.1 GPIO DC Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
282
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
110
µA
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.97
V
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
1.55
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.42
V
TA = 25 °C
VIH
Lowest GPIO input voltage reliably interpreted as a
High
VIL
Highest GPIO input voltage reliably interpreted as a
Low
30
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0.8*VDDS
V
0.2*VDDS
V
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8.19 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Recommended Operating Conditions, Section 8.3, for device limits. Values exceeding these limits are for
reference only.
8.19.1 MCU Current
Figure 8-4. Active Mode (MCU) Current vs. Supply
Voltage (VDDS)
Figure 8-5. Standby Mode (MCU) Current vs.
Temperature
8.19.2 RX Current
RX Current vs. Temperature
50 kbps, 868.3 MHz
8
7.8
7.6
7.4
Current [mA]
7.2
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40
-30
-20
-10
0
10
20
30
40
50
Temperature [°C]
60
70
80
90
100
D008
Figure 8-6. RX Current vs. Temperature (50 kbps,
868.3 MHz)
Figure 8-7. RX Current vs. Temperature (50 kbps,
868.3 MHz, VDDS = 3.6 V)
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RX Current vs. VDDS
50 kbps, 868.3 MHz
11.5
11
10.5
Current [mA]
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
Voltage [V]
3.4
3.6
3.8
D012
Figure 8-8. RX Current vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
32
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18
17.7
17.4
17.1
16.8
16.5
16.2
15.9
15.6
15.3
15
14.7
14.4
14.1
13.8
13.5
13.2
12.9
12.6
12.3
12
-40
TX Current vs. Temperature
TX Current vs. Temperature
50 kbps, 868.3 MHz, +10 dBm, VDDS = 3.6 V
50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V
85
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
80
75
70
Current [mA]
Current [mA]
8.19.3 TX Current
65
60
55
50
45
40
35
30
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
90
25
-40
100
-30
-20
-10
0
Figure 8-9. TX Current vs. Temperature (50 kbps,
868.3 MHz, VDDS = 3.6 V)
20
30
40
50
60
70
80
90
100 110
Temperature [°C]
D016
Figure 8-10. TX Current vs. Temperature (50 kbps,
915 MHz, VDDS = 3.3 V)
TX Current vs. VDDS
TX Current vs. VDDS
50 kbps, 868.3 MHz, +10 dBm
50 kbps, 915 MHz, +20 dBm PA
26
70
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
25
65
24
23
60
Current [mA]
22
Current [mA]
10
D015
21
20
19
18
17
55
50
45
40
16
35
15
14
30
13
12
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
25
1.8
2
2.2
Figure 8-11. TX Current vs. Supply Voltage (VDDS)
(50 kbps, 868.3 MHz)
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
D022
3.8
D023
Figure 8-12. TX Current vs. Supply Voltage (VDDS)
(50 kbps, 915 MHz)
Table 8-2 shows typical TX current and output power for different output power settings.
Table 8-1. Typical TX Current and Output Power, high power PA (915 MHz, VDDS = 3.3 V)
CC1311P3 at 915 MHz, VDDS = 3.3 V (Measured on CC1311-P3EM-7XD7793-PA915)
txPower
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
0x1B8ED2
20
20.6
64.9
0x448CF
19
19.5
55.4
0x48022
18
18.0
46.0
0x2661C
17
17.1
41.5
0x5618
16
16.2
37.6
0x4812
15
15.2
33.9
0x380D
14
14.0
30.2
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Table 8-2. Typical TX Current and Output Power (868 MHz, VDDS = 3.0 V)
CC1311P3 at 868 MHz, VDDS = 3.0 V (Measured on CC1311-P3EM-7XD7793-PA915)
txPower
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
0x013F1
14
13.8
30.0
0xB224
12.5
12.2
21.5
0x895E
12
11.8
20.3
0x669A
11
10.8
18.1
0x3E92
10
9.8
16.4
0x3EDC
9
8.9
15.5
0x2CD8
8
8.1
14.5
0x26D4
7
7.0
13.3
0x20D1
6
5.8
12.2
0x1CCE
5
4.4
10.9
0x16CD
4
3.7
10.5
0x14CB
3
2.2
9.7
0x12CA
2
1.5
9.2
0x12C9
1
0.6
8.8
0x10C8
0
-0.5
8.3
0xAC4
-5
-7.3
6.5
0xAC2
-10
-13.1
5.6
0x6C1
-15
-18.3
5.2
0x4C0
-20
-22.6
4.9
1
34
Boost mode enabled. VDDR regulated to 1.95 V.
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8.19.4 RX Performance
Sensitivity vs. Frequency
Sensitivity vs. Frequency
50 kbps
-105
-105
-106
-106
-107
-107
-108
-108
Sensitivity [dBm ]
Sensitivity [dBm ]
50 kbps
-109
-110
-111
-112
-109
-110
-111
-112
-113
-113
-114
-114
-115
863
864
865
866
867
868
869
-115
900
870
Frequency [MHz]
903
906
909
Figure 8-13. Sensitivity vs. Frequency (50 kbps,
868 MHz)
-106
-106
-107
-107
-108
-108
Sensitivity [dBm ]
Sensitivity [dBm]
-105
-109
-110
-111
-112
30
40
50
D027
-112
-114
20
930
-111
-113
10
927
-110
-114
0
924
-109
-113
-10
921
50 kbps, 868.3 MHz
-105
-20
918
Sensitivity vs. VDDS
50 kbps, 868.3 MHz
-30
915
Figure 8-14. Sensitivity vs. Frequency (50 kbps,
915 MHz)
Sensitivity vs. Temperature
-115
-40
912
Frequency [MHz]
D026
60
70
80
90
Temperature [°C]
-115
1.8
100
2
2.2
2.4
Figure 8-15. Sensitivity vs. Temperature (50 kbps,
868.3 MHz)
2.6
2.8
3
3.2
3.4
3.6
Voltage [V]
D030
3.8
D033
Figure 8-16. Sensitivity vs. Supply Voltage (VDDS)
(50 kbps, 868.3 MHz)
Selectivity vs. Frequency Offset
Packet error rate vs level and frequency offset for SLR 5 kbps.
50 kbps, 868.3 MHz
0
100
80
90
-20
80
60
70
Level [dBm]
Selectivity [dB]
-40
40
20
60
-60
50
40
-80
30
-100
0
20
-20
-10
10
-120
-8
-6
-4
-2
0
2
Frequency [MHz]
4
6
8
10
D038
Figure 8-17. Selectivity vs. Frequency Offset (50
kbps, 868.3 MHz)
0
-30
-20
-10
0
10
20
30
Offset frequency [ppm]
Figure 8-18. PER vs. Level vs. Frequency
(SimpleLink™ Long Range 5 kbps, 868 MHz)
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Figure 8-19. 802.15.4, 50 kbps, ±25 kHz deviation,
2-GFSK, 100 kHz RX Bandwidth
36
Figure 8-20. Narrowband, 9.6 kbps ±2.4 kHz
deviation, 2-GFSK, 868 MHz, 17.1 kHz RX
Bandwidth
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8.19.5 TX Performance
Output Power vs. Temperature
Output Power vs. Temperature
50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V
50 kbps, 868.3 MHz, +14 dBm
26
14
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
13.8
24
Output Power [dBm]
Output Power [dBm]
13.6
13.4
13.2
13
12.8
12.6
22
20
18
16
12.4
14
12.2
12
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
12
-40
100
-30
-20
-10
0
Figure 8-21. Output Power vs. Temperature (50
kbps, 868.3 MHz)
Output Power [dBm]
Output Power [dBm]
70
80
90
100
D040
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
20
18
16
14
12
3
10
1.8
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
2
2.2
2.4
2.8
3
3.2
3.4
3.6
3.8
D045
Figure 8-24. Output Power vs. Supply Voltage
(VDDS) (50 kbps, 915 MHz)
Output Power vs. Frequency
50 kbps, +14 dBm
Output Power [dBm]
867
Frequency [MHz]
2.6
Voltage [V]
D044
50 kbps, +14 dBm
Output Power [dBm]
60
50 kbps, 915 MHz, +20 dBm PA
Output Power vs. Frequency
866
50
22
Figure 8-23. Output Power vs. Supply Voltage
(VDDS) (50 kbps, 868.3 MHz)
865
40
Output Power vs. VDDS
Voltage [V]
864
30
Figure 8-22. Output Power vs. Temperature (50
kbps, 915 MHz)
50 kbps, 868.3 MHz, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
863
20
Temperature [°C]
Output Power vs. VDDS
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
10
D039
868
869
870
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
902
904
D052
906
908
910
912
914
916
918
Frequency [MHz]
920
922
924
926
928
D053
Figure 8-25. Output Power vs. Frequency (50 kbps, Figure 8-26. Output Power vs. Frequency (50 kbps,
868 MHz)
915 MHz)
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Output Power vs. Frequency
50 kbps, +20 dBm PA, VDDS = 3.3 V
22
+20 dBm
+17 dBm
21.6
21.2
Output Power [dBm]
20.8
20.4
20
19.6
19.2
18.8
18.4
18
17.6
17.2
16.8
16.4
16
902
904
906
908
910
912
914
916
918
920
922
Frequency [MHz]
924
926
928
D056
Figure 8-27. Output Power vs. Frequency (50 kbps, 915 MHz, VDDS = 3.3 V)
38
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8.19.6 ADC Performance
ENOB vs. Input Frequency
ENOB vs. Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference,
Fin = Fs / 10
11.4
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
10.2
11.1
10.15
10.1
ENOB [Bit]
ENOB [Bit]
10.8
10.5
10.2
10.05
10
9.95
9.9
9.9
9.85
9.6
0.2
9.8
0.3
0.5 0.7
1
2
3
4 5 6 7 8 10
20
30 40 50
1
70 100
Frequency [kHz]
4 5 6 7 8 10
20
30 40 50
70
100
200
D062
Figure 8-29. ENOB vs. Sampling Frequency
INL vs. ADC Code
DNL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
1.5
2.5
1
2
0.5
1.5
DNL [LSB]
INL [LSB]
3
Frequency [kHz]
Figure 8-28. ENOB vs. Input Frequency
0
1
-0.5
0.5
-1
0
-1.5
-0.5
0
400
800
1200
1600
2000
2400
2800
3200
3600
4000
ADC Code
0
1200
1600
2000
2400
2800
3200
ADC Accuracy vs. VDDS
Vin = 1 V, Internal reference,
200 kSamples/s
Vin = 1 V, Internal reference,
200 kSamples/s
1.008
1.008
1.007
1.007
Voltage [V]
1.01
1.009
1.006
1.005
1.004
1.006
1.005
1.004
1.003
1.003
1.002
1.002
1.001
1.001
-10
0
10
20
30
40
50
60
70
80
4000
D065
ADC Accuracy vs. Temperature
-20
3600
Figure 8-31. DNL vs. ADC Code
1.01
-30
800
ADC Code
1.009
1
-40
400
D064
Figure 8-30. INL vs. ADC Code
Voltage [V]
2
D061
90
1
1.8
100
Temperature [°C]
2
Figure 8-32. ADC Accuracy vs. Temperature
2.2
2.4
2.6
2.8
Voltage [V]
D066
3
3.2
3.4
3.6
3.8
D067
Figure 8-33. ADC Accuracy vs. Supply Voltage
(VDDS)
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9 Detailed Description
9.1 Overview
Section 4 shows the core modules of the CC1311P3 device.
9.2 System CPU
The CC1311P3 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4 system CPU, which runs the
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
40
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9.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor
that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF core offers a high level, command-based
API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the
main CPU, which reduces power and leaves more resources for the user application. Several signals are also
available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) updates while still using the same silicon.
Note
Not all combinations of features, frequencies, data rates, and modulation formats described in this
chapter are supported. Over time, TI can enable new physical radio formats (PHYs) for the device and
provides performance numbers for selected PHYs in the data sheet. Supported radio formats for a
specific device, including optimized settings to use with the TI RF driver, are included in the SmartRF
Studio tool with performance numbers of selected formats found in Section 8.
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9.3.1 Proprietary Radio Formats
The CC1311P3 radio can support a wide range of physical radio formats through a set of hardware peripherals
combined with firmware available in the device ROM, covering various customer needs for optimizing towards
parameters such as speed or sensitivity. This allows great flexibility in tuning the radio both to work with legacy
protocols as well as customizing the behavior for specific application needs.
Table 9-1 gives a simplified overview of features of the various radio formats available in ROM. Other radio
formats may be available in the form of radio firmware patches or programs through the Software Development
Kit (SDK) and may combine features in a different manner, as well as add other features.
Table 9-1. Feature Support
Feature
Main 2-(G)FSK Mode
High Data Rates
Low Data Rates
SimpleLink™ Long Range
Programmable preamble,
sync word and CRC
Yes
Yes
Yes
No
Programmable receive
bandwidth
Yes
Yes
Yes (down to 4 kHz)
Yes
20 to 1000 kbps
≤ 2 Msps
≤ 100 ksps
≤ 20 ksps
2-(G)FSK
2-(G)FSK
4-(G)FSK
2-(G)FSK
4-(G)FSK
2-(G)FSK
Dual Sync Word
Yes
Yes
No
No
Carrier Sense (1) (2)
Yes
No
No
No
Data / Symbol rate(3)
Modulation format
Preamble
Detection(2)
Yes
Yes
Yes
No
Data Whitening
Yes
Yes
Yes
Yes
Digital RSSI
Yes
Yes
Yes
Yes
CRC filtering
Yes
Yes
Yes
Yes
Direct-sequence spread
spectrum (DSSS)
No
No
No
1:2
1:4
1:8
Forward error correction
(FEC)
No
No
No
Yes
Link Quality Indicator (LQI)
Yes
Yes
Yes
Yes
(1)
(2)
(3)
42
Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance
with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API.
Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power.
Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a
smaller range might be supported.
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9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is
in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is a single 32-KB block and can be used for both storage
of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and
included in Standby mode power consumption numbers.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
The ROM contains a serial (SPI and UART) bootloader that can be used for initial programming of the device.
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9.5 Cryptography
The CC1311P3 device comes with a wide set of cryptography-related hardware accelerators, reducing code
footprint and execution time for cryptographic operations. It also has the benefit of being lower power
and improves availability and responsiveness of the system because the cryptography operations run in a
background hardware thread.
The hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Advanced Encryption Standard (AES) with 128 bit key lengths
Together with the hardware accelerator module, a large selection of open-source cryptography libraries provided
with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily
built on top of the platform. The TI provided cryptography drivers are:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P256
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• Hash
– SHA256
• MACs
– HMAC with SHA256
– AES CBC-MAC
• Block ciphers
– AESECB
– AESCBC
– AESCTR
• Authenticated Encryption
– AESCCM
• Random number generation
– True Random Number Generator
– AES CTR DRBG
44
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9.6 Timers
A large selection of timers are available as part of the CC1311P3 device. These timers are:
• Real-Time Clock (RTC)
•
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. By default, the RTC halts when a debugger
halts the device.
General Purpose Timers (GPTIMER)
•
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
Radio Timer
•
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields
in the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the
source of SCLK_HF.
Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.
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9.7 Serial Peripherals and I/O
The SSI is a synchronous serial interface that is compatible with SPI, MICROWIRE, and TI's synchronous serial
interfaces. The SSI support both SPI master and slave up to 4 MHz. The SSI module support configurable phase
and polarity.
The UART implement universal asynchronous receiver and transmitter functions. It support flexible baud-rate
generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in Section 7. All digital peripherals can be connected to
any digital pin on the device.
For more information, see the CC13x1x3, CC26x1x3 SimpleLink™ Wireless MCU Technical Reference Manual.
9.8 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC1311P3 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.9 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
•
•
•
•
Highly flexible and configurable channel operation of up to 32 channels
Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
Data sizes of 8, 16, and 32 bits
Ping-pong mode for continuous streaming of data
9.10 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
46
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9.11 Power Management
To minimize power consumption, the CC1311P3 supports a number of power modes and power management
features (see Table 9-2).
Table 9-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
MODE
ACTIVE
IDLE
STANDBY
SHUTDOWN
RESET PIN
HELD
CPU
Active
Off
Off
Off
Off
Flash
On
Available
Off
Off
Off
SRAM
On
On
Retention
Off
Off
Radio
Available
Available
Off
Off
Off
Supply System
On
On
Duty Cycled
Off
Off
Register and CPU retention
Full
Full
Partial
No
No
SRAM retention
Full
Full
Full
No
No
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Off
Off
Peripherals
Available
Available
Off
Off
Off
Wake-up on RTC
Available
Available
Available
Off
Off
Wake-up on pin edge
Available
Available
Available
Available
Off
Wake-up on reset pin
On
On
On
On
On
Brownout detector (BOD)
On
On
Duty Cycled
Off
Off
Power-on reset (POR)
On
On
On
Off
Off
Watchdog timer (WDT)
Available
Available
Paused
Off
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the processor and all of the peripherals that are currently enabled. The system clock can be any available
clock source (see Table 9-2).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event or RTC event is
required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured
when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are
latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with
the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from
shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in
this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in
this mode is the latched I/O state and the flash memory contents.
Note
The power, RF and clock management for the CC1311P3 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in
the TI-provided drivers that are part of the CC1311P3 software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in
source code.
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9.12 Clock Systems
The CC1311P3 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by
the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used for the RTC and to synchronize
the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC
Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost.
9.13 Network Processor
Depending on the product configuration, the CC1311P3 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
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10 Application, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
For optimum RF performance, especially when using the high-power PA, it is important to accurately follow
the reference design with respect to component values and layout. Failure to do so may lead to reduced RF
performance due to balun mismatch. The amplitude- and phase balance through the balun must be
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