CC1352P74T0RGZR

CC1352P7 SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 CC1352P7 SimpleLink™ High-Performance Multi-Band Wireless MCU With Integrated Power Amplifier 1 Features Wireless microcontroller • • • • • • • • • Powerful 48-MHz Arm® Cortex®-M4F processor 704KB flash program memory 256KB of ROM for protocols and library functions 8KB of cache SRAM 144KB of ultra-low leakage SRAM with parity for high-reliability operation Dual-band Sub-1 GHz and 2.4 GHz operation Dynamic multiprotocol manager (DMM) driver Programmable radio includes support for 2(G)FSK, 4-(G)FSK, MSK, OOK, Bluetooth® 5.2 Low Energy, IEEE 802.15.4 PHY and MAC Supports over-the-air upgrade (OTA) High performance radio • • • • -121 dBm for 2.5-kbps long-range mode -110 dBm at 50 kbps, 802.15.4, 868 MHz -104 dBm for Bluetooth® Low Energy 125-kbps Output power up to +20 dBm with temperature compensation Regulatory compliance • Suitable for systems targeting compliance with these standards: – ETSI EN 300 220 Receiver Cat. 1.5 and 2, EN 300 328, EN 303 131, EN 303 204, EN 300 440 Cat. 2 and 3 – FCC CFR47 Part 15 – ARIB STD-T108 and STD-T66 Ultra-low power sensor controller MCU peripherals • • • • • • • • • • • • • Autonomous MCU with 4KB of SRAM Sample, store, and process sensor data Fast wake-up for low-power operation Software defined peripherals; capacitive touch, flow meter, LCD Low power consumption • • • MCU consumption: – 2.63 mA active mode, CoreMark – 55 μA/MHz running CoreMark – 0.8 μA standby mode, RTC, 144KB RAM – 0.1 μA shutdown mode, wake-up on pin Ultra low-power sensor controller consumption: – 25.2 μA in 2 MHz mode – 701 μA in 24 MHz mode Radio Consumption: – 5.4 mA RX at 868 MHz – 6.4 mA RX at 2.4 GHz – 21 mA TX at +10 dBm at 2.4 GHz – 24.9 mA TX at +14 dBm at 868 MHz – 64 mA TX at +20 dBm at 915 MHz – 101 mA TX at +20 dBm at 2.4 GHz Digital peripherals can be routed to any GPIO Four 32-bit or eight 16-bit general-purpose timers 12-bit ADC, 200 kSamples/s, 8 channels 8-bit DAC Two comparators Programmable current source Two UART, two SSI, I2C, I2S Real-time clock (RTC) Integrated temperature and battery monitor Security enablers • • • • AES 128- and 256-bit cryptographic accelerator ECC and RSA public key hardware accelerator SHA2 Accelerator (full suite up to SHA-512) True random number generator (TRNG) Development tools and software • • • • LP-CC1352P7 Development Kits SimpleLink™ CC13xx and CC26xx Software Development Kit (SDK) SmartRF™ Studio for simple radio configuration Sensor Controller Studio for building low-power sensing applications SysConfig system configuration tool Wireless protocol support • • • • • • • • • • Operating range Thread, Zigbee®, Matter Bluetooth® 5.2 Low Energy Wi-SUN® mioty® Amazon Sidewalk Wireless M-Bus SimpleLink™ TI 15.4-stack 6LoWPAN Proprietary systems • • • On-chip buck DC/DC converter 1.8-V to 3.8-V single supply voltage -40 to +105°C Package • • 7-mm × 7-mm RGZ VQFN48 (26 GPIOs) RoHS-compliant package An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 • 2 Applications • • Grid infrastructure – Smart Meters – electricity meter, water meter, gas meter and heat cost allocator – Grid communications – wireless communications – EV charging infrastructure – AC charging (pile) station – Other alternative energy – energy harvesting Building automation – Building security systems – motion detector, door and window sensor, glass break detector, panic button, electronic smart lock and IP network camera – HVAC systems – thermostat, environmental sensor andHVAC controller – Fire safety – smoke and head detector, gas detector and fire alarm control panel • • Retail Automation – Retail automation & payment applications – electronic shelf labels and portable POS terminal Personal Electronics – RF remote controls – Smart Speakers, Smart Displays and Set-top box – Gaming and electronic and robotic toys – Wearables (non-medical), smart trackers, smart clothing and smartwatch Wireless Modules – Wireless third party modules including Bluetooth Low Energy, Thread, Zigbee, Matter, Wi-SUN®, Amazon Sidewalk, mioty® and multiprotocol – Wireless communications modules 3 Description The SimpleLink™ CC1352P7 device is a multiprotocol and multi-band Sub-1 GHz and 2.4-GHz wireless microcontroller (MCU) supporting Thread, Zigbee®, Bluetooth® 5.2 Low Energy, IEEE 802.15.4g, IPv6-enabled smart objects (6LoWPAN), mioty®, Wi-SUN®, proprietary systems, including the TI 15.4-Stack (Sub-1 GHz and 2.4 GHz), and concurrent multiprotocol through a Dynamic Multiprotocol Manager (DMM) driver. The CC1352P7 is based on an Arm® Cortex® M4F main processor and optimized for low-power wireless communication and advanced sensing in grid infrastructure, building automation, retail automation, personal electronics and medical applications. The CC1352P7 has a software defined radio powered by an Arm® Cortex®-M0, which allows support for multiple physical layers and RF standards. CC1352P7 supports operation in 287 to 351-MHz, 359 to 527-MHz, 861 to 1054-MHz, 1076 to 1315-MHz, and 2360 to 2500-MHz frequency bands. PHY and frequency band switching can be done runtime through a dynamic multiprotocol manager (DMM) driver. The CC1352P7 has an efficient built-in PA that supports +10 dBm TX at 21 mA and +20 dBm TX at 101 mA in the 2.4-GHz band, and +20 dBm TX at 64 mA in the Sub-1 GHz band. The CC1352P7 has a low sleep current of 0.9 μA with RTC and 144KB RAM retention. In addition to the main Cortex® M4F processor, the device also has an autonomous ultra-low power Sensor Controller CPU with fast wake-up capability. As an example, the sensor controller is capable of 1-Hz ADC sampling at 1-μA system current. The CC1352P7 has Low SER (Soft Error Rate) FIT (Failure-in-time) for long operational lifetime. Always-on SRAM parity minimizes risk for corruption due to potential radiation events. Consistent with many customers’ 10 to 15 years or longer life cycle requirements, TI has a product life cycle policy with a commitment to product longevity and continuity of supply. The CC1352P7 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth® Low Energy, Thread, Zigbee, Wi-SUN®, Amazon Sidewalk, mioty®, Sub-1 GHz MCUs, and host MCUs. CC1352P7 is part of a scalable portfolio with flash sizes from 32KB to 704KB with pin-to-pin compatible package options. The common SimpleLink™CC13xx and CC26xx Software Development Kit (SDK) and SysConfig system configuration tool supports migration between devices in the portfolio. A comprehensive number of software stacks, application examples and SimpleLink™ Academy training sessions are included in the SDK. For more information, visit wireless connectivity. 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 Device Information PART NUMBER(1) CC1352P74T0RGZR (1) PACKAGE BODY SIZE (NOM) VQFN (48) 7.00 mm × 7.00 mm For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 11, or see the TI website. z 2. 4 G H 1 bSu 20 -d B m G H z PA 3.1 Functional Block Diagram RF Core cJTAG Main CPU 256KB ROM ADC ADC Arm® Cortex®-M4F Processor 704KB Flash with 8KB Cache Digital PLL DSP Modem 48 MHz 144KB SRAM with Parity Arm® Cortex®-M0 Processor 16KB SRAM ROM General Hardware Peripherals and Modules Sensor Interface Interface Sensor I2C and I2S 4× 32-bit Timers ULP Sensor Controller ULP Sensor Controller 2× UART 2× SSI (SPI) 8-bit DAC 32 ch. µDMA Watchdog Timer 12-bit ADC, 200 ks/s 12-bit ADC, 200 ks/s 31 GPIOs TRNG Low-Power Comparator 2x Low-Power Comparator AES-256, SHA2-512 Temperature and Battery Monitor ECC, RSA RTC SPI-I2C Digital Sensor IF SPI-I2C Digital Sensor IF Constant Current Source Constant Current Source Time-to-Digital Converter Time-to-Digital Converter LDO, Clocks, and References Optional DC/DC Converter 4KB SRAM 4KB SRAM Figure 3-1. CC1352P7 Block Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 3 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 2 3 Description.......................................................................2 3.1 Functional Block Diagram........................................... 3 4 Revision History.............................................................. 4 5 Device Comparison......................................................... 5 6 Terminal Configuration and Functions..........................6 6.1 Pin Diagram – RGZ Package (Top View)....................6 6.2 Signal Descriptions – RGZ Package...........................7 6.3 Connections for Unused Pins and Modules................8 7 Specifications.................................................................. 9 7.1 Absolute Maximum Ratings........................................ 9 7.2 ESD Ratings............................................................... 9 7.3 Recommended Operating Conditions.........................9 7.4 Power Supply and Modules...................................... 10 7.5 Power Consumption - Power Modes........................ 10 7.6 Power Consumption - Radio Modes......................... 11 7.7 Nonvolatile (Flash) Memory Characteristics............. 11 7.8 Thermal Resistance Characteristics......................... 12 7.9 RF Frequency Bands................................................ 12 7.10 861 MHz to 1054 MHz - Receive (RX)....................13 7.11 861 MHz to 1054 MHz - Transmit (TX) .................. 16 7.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode.......................................................... 17 7.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode.......................................................18 7.14 Bluetooth Low Energy - Receive (RX).................... 18 7.15 Bluetooth Low Energy - Transmit (TX)....................21 7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX.................... 22 7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX.....................23 7.18 Timing and Switching Characteristics..................... 24 7.19 Peripheral Characteristics.......................................28 7.20 Typical Characteristics............................................ 34 8 Detailed Description......................................................48 8.1 Overview................................................................... 48 8.2 System CPU............................................................. 48 8.3 Radio (RF Core)........................................................49 8.4 Memory..................................................................... 51 8.5 Sensor Controller...................................................... 51 8.6 Cryptography............................................................ 53 8.7 Timers....................................................................... 54 8.8 Serial Peripherals and I/O.........................................55 8.9 Battery and Temperature Monitor............................. 55 8.10 µDMA...................................................................... 55 8.11 Debug......................................................................55 8.12 Power Management................................................56 8.13 Clock Systems........................................................ 57 8.14 Network Processor..................................................57 9 Application, Implementation, and Layout................... 58 9.1 Reference Designs................................................... 58 9.2 Junction Temperature Calculation.............................59 10 Device and Documentation Support..........................60 10.1 Device Nomenclature..............................................60 10.2 Tools and Software................................................. 60 10.3 Documentation Support.......................................... 63 10.4 Support Resources................................................. 63 10.5 Trademarks............................................................. 63 10.6 Electrostatic Discharge Caution..............................64 10.7 Glossary..................................................................64 11 Mechanical, Packaging, and Orderable Information.................................................................... 65 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 4 DATE REVISION NOTES November 2021 * Initial Release Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 5 Device Comparison Table 5-1. Device Family Overview DEVICE RADIO SUPPORT FLASH (KB) RAM (KB) GPIO PACKAGE SIZE CC1310 Sub-1 GHz Wireless M-Bus 32-128 16-20 10-30 RGZ (7-mm × 7-mm VQFN48) RHB (5 mm × 5 mm VQFN32) RSM (4 mm × 4 mm VQFN32) CC1312R Sub-1 GHz Wi-SUN® Amazon Sidewalk Wireless M-Bus 352-704 80-144 30 RGZ (7-mm × 7-mm VQFN48) CC1352P Multiprotocol Sub-1 GHz Wi-SUN® Amazon Sidewalk Wireless M-Bus Bluetooth 5.2 Low Energy Zigbee Thread 2.4 GHz proprietary FSK-based formats +20-dBm high-power amplifier 352-704 80-144 26 RGZ (7-mm × 7-mm VQFN48) CC1352R Multiprotocol Sub-1 GHz Wi-SUN® Wireless M-Bus Bluetooth 5.2 Low Energy Zigbee Thread 2.4 GHz proprietary FSK-based formats 352 80 28 RGZ (7-mm × 7-mm VQFN48) CC2642R Bluetooth 5.2 Low Energy 2.4 GHz proprietary FSK-based formats 352 80 31 RGZ (7-mm × 7-mm VQFN48) CC2642R-Q1 Bluetooth 5.2 Low Energy 352 80 31 RTC (7-mm × 7-mm VQFN48) CC2652R Multiprotocol Bluetooth 5.2 Low Energy Zigbee Thread 2.4 GHz proprietary FSK-based formats 352-704 80-144 31 RGZ (7-mm × 7-mm VQFN48) CC2652RB Multiprotocol Bluetooth 5.2 Low Energy Zigbee Thread 352 80 31 RGZ (7-mm × 7-mm VQFN48) CC2652P Multiprotocol Bluetooth 5.2 Low Energy Zigbee Thread 2.4 GHz proprietary FSK-based formats +19.5-dBm high-power amplifier 352-704 80-144 26 RGZ (7-mm × 7-mm VQFN48) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 5 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 6 Terminal Configuration and Functions 38 DIO_25 37 DIO_24 40 DIO_27 39 DIO_26 42 DIO_29 41 DIO_28 44 VDDS 43 DIO_30 46 X48M_N 45 VDDR 48 VDDR_RF 47 X48M_P 6.1 Pin Diagram – RGZ Package (Top View) RF_P_2_4GHZ 1 36 DIO_23 RF_N_2_4GHZ 2 35 RESET_N RF_P_SUB_1GHZ 3 34 VDDS_DCDC RF_N_SUB_1GHZ TX_20DBM_P 4 33 DCDC_SW 5 32 DIO_22 TX_20DBM_N 6 31 DIO_21 RX_TX 7 30 DIO_20 X32K_Q1 8 29 DIO_19 X32K_Q2 JTAG_TMSC 24 25 JTAG_TCKC VDDS3 22 DCOUPL 23 26 DIO_16 DIO_7 12 DIO_14 20 DIO_15 21 DIO_6 11 DIO_12 18 DIO_13 19 27 DIO_17 DIO_9 15 DIO_10 16 DIO_11 17 28 DIO_18 VDDS2 13 DIO_8 14 9 DIO_5 10 Figure 6-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View) The following I/O pins marked in Figure 6-1 in bold have high-drive capabilities: • • • • • • Pin 10, DIO_5 Pin 11, DIO_6 Pin 12, DIO_7 Pin 24, JTAG_TMSC Pin 26, DIO_16 Pin 27, DIO_17 The following I/O pins marked in Figure 6-1 in italics have analog capabilities: • • • • • • • • 6 Pin 36, DIO_23 Pin 37, DIO_24 Pin 38, DIO_25 Pin 39, DIO_26 Pin 40, DIO_27 Pin 41, DIO_28 Pin 42, DIO_29 Pin 43, DIO_30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 6.2 Signal Descriptions – RGZ Package Table 6-1. Signal Descriptions – RGZ Package PIN NAME NO. I/O TYPE DESCRIPTION DCDC_SW 33 — Power Output from internal DC/DC converter(1) DCOUPL 23 — Power For decoupling of internal 1.27 V regulated digital-supply (2) DIO_5 10 I/O Digital GPIO, high-drive capability DIO_6 11 I/O Digital GPIO, high-drive capability DIO_7 12 I/O Digital GPIO, high-drive capability DIO_8 14 I/O Digital GPIO DIO_9 15 I/O Digital GPIO DIO_10 16 I/O Digital GPIO DIO_11 17 I/O Digital GPIO DIO_12 18 I/O Digital GPIO DIO_13 19 I/O Digital GPIO DIO_14 20 I/O Digital GPIO DIO_15 21 I/O Digital GPIO DIO_16 26 I/O Digital GPIO, JTAG_TDO, high-drive capability DIO_17 27 I/O Digital GPIO, JTAG_TDI, high-drive capability DIO_18 28 I/O Digital GPIO DIO_19 29 I/O Digital GPIO DIO_20 30 I/O Digital GPIO DIO_21 31 I/O Digital GPIO DIO_22 32 I/O Digital GPIO DIO_23 36 I/O Digital or Analog GPIO, analog capability DIO_24 37 I/O Digital or Analog GPIO, analog capability DIO_25 38 I/O Digital or Analog GPIO, analog capability DIO_26 39 I/O Digital or Analog GPIO, analog capability DIO_27 40 I/O Digital or Analog GPIO, analog capability DIO_28 41 I/O Digital or Analog GPIO, analog capability DIO_29 42 I/O Digital or Analog GPIO, analog capability DIO_30 43 I/O Digital or Analog GPIO, analog capability EGP — — GND Ground – exposed ground pad(3) JTAG_TMSC 24 I/O Digital JTAG TMSC, high-drive capability JTAG_TCKC 25 I Digital JTAG TCKC RESET_N 35 I Digital Reset, active low. No internal pullup resistor RF_P_2_4GHZ 1 — RF Positive 2.4-GHz RF input signal to LNA during RX Positive 2.4-GHz RF output signal from PA during TX RF_N_2_4GHZ 2 — RF Negative 2.4-GHz RF input signal to LNA during RX Negative 2.4-GHz RF output signal from PA during TX RF_P_SUB_1GHZ 3 — RF Positive Sub-1 GHz RF input signal to LNA during RX Positive Sub-1 GHz RF output signal from PA during TX RF_N_SUB_1GHZ 4 — RF Negative Sub-1 GHz RF input signal to LNA during RX Negative Sub-1 GHz RF output signal from PA during TX RX_TX 7 — RF Optional bias pin for the RF LNA TX_20DBM_P 5 — RF Positive Sub-1 GHz or 2.4-GHz high-power TX signal TX_20DBM_N 6 — RF Negative Sub-1 GHz or 2.4-GHz high-power TX signal Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 Table 6-1. Signal Descriptions – RGZ Package (continued) PIN I/O TYPE 45 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2) (4) (6) VDDR_RF 48 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2) (5) (6) VDDS 44 — Power 1.8-V to 3.8-V main chip supply(1) VDDS2 13 — Power 1.8-V to 3.8-V DIO supply(1) VDDS3 22 — Power 1.8-V to 3.8-V DIO supply(1) VDDS_DCDC 34 — Power 1.8-V to 3.8-V DC/DC converter supply X48M_N 46 — Analog 48-MHz crystal oscillator pin 1 X48M_P 47 — Analog 48-MHz crystal oscillator pin 2 X32K_Q1 8 — Analog 32-kHz crystal oscillator pin 1 X32K_Q2 9 — Analog 32-kHz crystal oscillator pin 2 NAME NO. VDDR (1) (2) (3) (4) (5) (6) DESCRIPTION For more details, see technical reference manual listed in Section 10.3. Do not supply external circuitry from this pin. EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is imperative for proper device operation. If internal DC/DC converter is not used, this pin is supplied internally from the main LDO. If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO. Output from internal DC/DC and LDO is trimmed to 1.68 V. 6.3 Connections for Unused Pins and Modules Table 6-2. Connections for Unused Pins FUNCTION GPIO DIO_n 32.768-kHz crystal DC/DC converter(2) (1) (2) 8 SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE(1) PREFERRED PRACTICE(1) 10–12 14–21 26–32 36–43 NC or GND NC NC or GND NC X32K_Q1 8 X32K_Q2 9 DCDC_SW 33 NC NC VDDS_DCDC 34 VDDS VDDS NC = No connect When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still be connected and the 22 uF DCDC capacitor must be kept on the VDDR net. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) VDDS(3) MIN MAX –0.3 4.1 V –0.3 VDDS + 0.3, max 4.1 V –0.3 VDDR + 0.3, max 2.25 V Voltage scaling enabled –0.3 VDDS Voltage scaling disabled, internal reference –0.3 1.49 Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9 Supply voltage Voltage on any digital pin(4) Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P Vin Voltage on ADC input Input level, Sub-1 GHz RF pins (RF_P_SUB_1GHZ and RF_N_SUB_1GHZ) Input level, 2.4 GHz RF pins (RF_P_2_4GHZ and RF_N_2_4GHZ) Tstg (1) (2) (3) (4) Storage temperature –40 UNIT V 10 dBm 5 dBm 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to ground, unless otherwise noted. VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS. Including analog capable DIOs. 7.2 ESD Ratings VESD (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) All pins ±2000 V Charged device model (CDM), per JESD22-C101(2) All pins ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Operating ambient temperature(1) (3) –40 105 °C Operating junction temperature(1) (3) –40 115 °C Operating supply voltage (VDDS) 1.8 3.8 V 2.1 3.8 V Rising supply voltage slew rate 0 100 mV/µs Falling supply voltage slew rate(2) 0 20 mV/µs Operating supply voltage (VDDS), boost mode (1) (2) (3) VDDR = 1.95 V +14 dBm RF output sub-1 GHz power amplifier Operation at or near maximum operating temperature for extended durations will result in a reduction in lifetime. For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used to ensure compliance with this slew rate. For thermal resistance characteristics refer to Section 7.8. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 9 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.4 Power Supply and Modules over operating free-air temperature range (unless otherwise noted) PARAMETER MIN VDDS Power-on-Reset (POR) threshold TYP MAX UNIT 1.1 - 1.55 V VDDS Brown-out Detector (BOD) (1) Rising threshold 1.77 V VDDS Brown-out Detector (BOD), before initial boot (2) Rising threshold 1.70 V VDDS Brown-out Detector (BOD) (1) Falling threshold 1.75 V (1) (2) For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin 7.5 Power Consumption - Power Modes When measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled unless otherwise noted. PARAMETER TEST CONDITIONS TYP UNIT Core Current Consumption Reset. RESET_N pin asserted or VDDS below power-on-reset threshold 110 Shutdown. No clocks running, no retention 110 RTC running, CPU, 144KB RAM and (partial) register retention. RCOSC_LF 0.8 µA RTC running, CPU, 64KB RAM and (partial) register retention. RCOSC_LF 0.7 µA RTC running, CPU, 144KB RAM and (partial) register retention XOSC_LF 0.9 µA RTC running, CPU, 144KB RAM and (partial) register retention. RCOSC_LF 1.9 µA RTC running, CPU, 144KB RAM and (partial) register retention. XOSC_LF 2.0 µA Idle Supply Systems and RAM powered RCOSC_HF 590 µA Active MCU running CoreMark at 48 MHz RCOSC_HF 2.63 mA Peripheral power domain Delta current with domain enabled 39 Serial power domain Delta current with domain enabled 2.6 RF Core Delta current with power domain enabled, clock enabled, RF core idle 89 µDMA Delta current with clock enabled, module is idle 57 Timers Delta current with clock enabled, module is idle(3) 97 I2C Delta current with clock enabled, module is idle 9.2 I2S Delta current with clock enabled, module is idle 22 SSI Delta current with clock enabled, module is idle(2) 50 UART Delta current with clock enabled, module is idle(1) 110 CRYPTO (AES) Delta current with clock enabled, module is idle 16 PKA Delta current with clock enabled, module is idle 59 TRNG Delta current with clock enabled, module is idle 20 Reset and Shutdown Standby without cache retention Icore Standby with cache retention nA Peripheral Current Consumption Iperi µA Sensor Controller Engine Consumption ISCE (1) (2) (3) 10 Active mode 24 MHz, infinite loop 701 Low-power mode 2 MHz, infinite loop 25.2 µA Only one UART running Only one SSI running Only one GPTimer running Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.6 Power Consumption - Radio Modes When measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled unless otherwise noted. High power PA connected to VDDS unless otherwise noted. Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm setting where this current is already included). Relevant Icore and Iperi currents are included in below numbers. PARAMETER TEST CONDITIONS TYP UNIT 5.4 mA VDDS = 3.0 V 7.1 mA 0 dBm output power setting 868 MHz 8.0 mA +10 dBm output power setting 868 MHz 14.3 mA Radio transmit current Boost mode, Sub-1 GHz PA +14 dBm output power setting 868 MHz 24.9 mA Radio transmit current 2.4 GHz PA (Bluetooth Low Energy) 0 dBm output power setting, VDDS = 3.0 V 7.5 mA Radio transmit current 2.4 GHz PA (Bluetooth Low Energy) +5 dBm output power setting 2440 MHz, VDDS = 3.0 V 9.8 mA Radio transmit current High-power PA Transmit (TX), +20 dBm output power setting 915 MHz, VDDS = 3.3 V 64 mA Radio transmit current High-power PA(1) Transmit (TX), +20 dBm output power setting 2440 MHz (Bluetooth Low Energy), VDDS = 3.0 V 101 mA Radio transmit current High-power PA, 10 dBm configuration(2) Transmit (TX), +10 dBm output power setting 2440 MHz (Bluetooth Low Energy), VDDS = 3.0 V 21 mA Radio receive current, 868 MHz Radio receive current, 2.44 GHz (Bluetooth Low Energy) Radio transmit current Sub-1 GHz PA (1) (2) Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design. Measured on the CC1352-P7EM-XD7793-XD24-PA24_10dBm reference design. 7.7 Nonvolatile (Flash) Memory Characteristics Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Flash sector size Supported flash erase cycles before failure, TYP single-bank(1) (5) Supported flash erase cycles before failure, single sector(2) k Cycles k Cycles 83 Flash sector erase current Average delta current 9.5 Zero cycles 10 Average delta current, 4 bytes at a time Flash write time(4) 4 bytes at a time (3) (4) (5) 11.4 30k cycles Flash write current Write Operations Years at 105 °C 105 °C (2) KB 60 Flash retention Flash sector erase time(4) UNIT 30 Maximum number of write operations per row before sector erase(3) (1) MAX 8 mA ms 4000 ms 5.2 mA 21.6 µs A full bank erase is counted as a single erase cycle on each sector. If both flash banks are always cycled simultaneously they can be cycled 30K times each. Alternatively, the banks can be cycled a total of 30K times, e.g. the main bank X times and the second bank Y times (X+Y=30K) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached. This number is dependent on Flash aging and increases over time and erase cycles Aborting flash during erase or program modes is not a safe operation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 11 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.8 Thermal Resistance Characteristics PACKAGE RGZ (VQFN) THERMAL METRIC(1) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 23.7 °C/W(2) RθJC(top) Junction-to-case (top) thermal resistance 13.0 °C/W(2) RθJB Junction-to-board thermal resistance 7.7 °C/W(2) ψJT Junction-to-top characterization parameter 0.1 °C/W(2) ψJB Junction-to-board characterization parameter 7.6 °C/W(2) RθJC(bot) Junction-to-case (bottom) thermal resistance 1.9 °C/W(2) (1) (2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. °C/W = degrees Celsius per watt. 7.9 RF Frequency Bands Over operating free-air temperature range (unless otherwise noted). PARAMETER MIN Frequency bands 12 Submit Document Feedback TYP MAX 2360 2500 1076 1315 861 1054 431 527 359 439 287 351 UNIT MHz Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.10 861 MHz to 1054 MHz - Receive (RX) Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4000 kHz General Parameters Digital channel filter programmable receive bandwidth 4 Data rate step size Spurious emissions 25 MHz to 1 GHz Spurious emissions 1 GHz to 13 GHz 868 MHz Conducted emissions measured according to ETSI EN 300 220 1.5 bps < -57 dBm < -47 dBm 802.15.4, 50 kbps, ±25 kHz deviation, 2-GFSK, 100 kHz RX Bandwidth Sensitivity BER = 10–2, 868 MHz –110 dBm Saturation limit BER = 10–2, 868 MHz 10 dBm Selectivity, ±200 kHz BER = MHz(1) 44 dB Selectivity, ±400 kHz BER = 10–2, 868 MHz(1) 49 dB Blocking, ±1 MHz BER = 10–2, 868 MHz(1) 58 dB Blocking, ±2 MHz BER = 10–2, 868 MHz(1) 62 dB Blocking, ±5 MHz BER = 10–2, 868 MHz(1) 70 dB Blocking, ±10 MHz BER = 10–2, 868 MHz(1) 78 dB Image rejection (image compensation enabled) BER = 10–2, 868 MHz(1) 39 dB RSSI dynamic range Starting from the sensitivity limit 95 dB RSSI accuracy Starting from the sensitivity limit across the given dynamic range ±3 dB 10–2, 868 802.15.4, 100 kbps, ±25 kHz deviation, 2-GFSK, 137 kHz RX Bandwidth Sensitivity 100 kbps 868 MHz, 1% PER, 127 byte payload Selectivity, ±200 kHz 868 MHz, 1% PER, 127 byte payload. Wanted signal at -96 dBm -103 38 dBm dB Selectivity, ±400 kHz 868 MHz, 1% PER, 127 byte payload. Wanted signal at -96 dBm 45 dB Co-channel rejection 868 MHz, 1% PER, 127 byte payload. Wanted signal at -79 dBm -9 dB 802.15.4, 200 kbps, ±50 kHz deviation, 2-GFSK, 311 kHz RX Bandwidth Sensitivity BER = 10–2, 868 MHz 10–2, 915 MHz –103 dBm –103 dBm Sensitivity BER = Selectivity, ±400 kHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 44 dB Selectivity, ±800 kHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 49 dB Blocking, ±2 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 57 dB Blocking, ±10 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 69 dB 802.15.4, 500 kbps, ±190 kHz deviation, 2-GFSK, 655 kHz RX Bandwidth Sensitivity 500 kbps 916 MHz, 1% PER, 127 byte payload -95 dBm Selectivity, ±1 MHz 916 MHz, 1% PER, 127 byte payload. Wanted signal at -88 dBm 35 dB Selectivity, ±2 MHz 916 MHz, 1% PER, 127 byte payload. Wanted signal at -88 dBm 47 dB Co-channel rejection 916 MHz, 1% PER, 127 byte payload. Wanted signal at -71 dBm -9 dB SimpleLink™ Long Range 2.5 kbps or 5 kbps (20 ksym/s, 2-GFSK, ±5 kHz Deviation, FEC (Half Rate), DSSS = 1:2 or 1:4, 34 kHz RX Bandwidth Sensitivity 2.5 kbps, BER = 10–2, 868 MHz -121 dBm Sensitivity 5 kbps, BER = 10–2, 868 MHz -119 dBm Saturation limit 2.5 kbps, BER = 10–2, 868 MHz 10 dBm Selectivity, ±100 kHz 2.5 kbps, BER = 10–2, 868 MHz(1) 49 dB Selectivity, ±200 kHz 2.5 kbps, BER = 10–2, 868 MHz(1) 50 dB Selectivity, ±300 kHz 2.5 kbps, BER = MHz(1) 51 dB Blocking, ±1 MHz 2.5 kbps, BER = 10–2, 868 MHz(1) 63 dB Blocking, ±2 MHz 2.5 kbps, BER = 10–2, 868 MHz(1) 69 dB Blocking, ±5 MHz 2.5 kbps, BER = 10–2, 868 MHz(1) 79 dB 10–2, 868 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 13 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.10 861 MHz to 1054 MHz - Receive (RX) (continued) Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Blocking, ±10 MHz 2.5 kbps, BER = 10–2, 868 MHz(1) 88 dB Image rejection (image compensation enabled) 2.5 kbps, BER = 10–2, 868 MHz(1) 47 dB RSSI dynamic range Starting from the sensitivity limit 108 dB RSSI accuracy Starting from the sensitivity limit across the given dynamic range ±3 dB OOK, 4.8 kbps, 39 kHz RX Bandwidth Sensitivity BER = 10–2, 868 MHz -114 dBm Sensitivity BER = 10–2, 915 MHz -114 dBm -117 dBm Narrowband, 9.6 kbps ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX Bandwidth Sensitivity 1% BER Adjacent Channel Rejection 1% BER. Wanted signal 3 dB above the ETSI reference sensitivity limit (-104.6 dBm). Interferer ±20 kHz 41 dB Alternate Channel Rejection 1% BER. Wanted signal 3 dB above the ETSI reference sensitivity limit (-104.6 dBm). Interferer ±40 kHz 42 dB Blocking, ±1 MHz 1% BER. Wanted signal 3 dB above the ETSI reference sensitivity limit (-104.6 dBm). 65 dB Blocking, ±2 MHz 1% BER. Wanted signal 3 dB above the ETSI reference sensitivity limit (-104.6 dBm). 69 dB Blocking, ±10 MHz 1% BER. Wanted signal 3 dB above the ETSI reference sensitivity limit (-104.6 dBm). 85 dB -97 dBm 1 Mbps, ±350 kHz deviation, 2-GFSK, 2.2 MHz RX Bandwidth Sensitivity BER = 10–2, 868 MHz 10–2, Sensitivity BER = -97 dBm Blocking, +2 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 915 MHz 44 dB Blocking, -2 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 27 dB Blocking, +10 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 59 dB Blocking, -10 MHz BER = 10–2, 915 MHz. Wanted signal 3 dB above sensitivity limit. 54 dB Wi-SUN, 2-GFSK Sensitivity 50 kbps, ±12.5 kHz deviation, 2-GFSK, 866.6 MHz, 68 kHz RX BW, 10% PER, 250 byte payload -107 Selectivity, ±100 kHz, 50 kbps, ±12.5 kHz deviation, 2-GFSK, 866.6 MHz 50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth, 866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 30 dB Selectivity, ±200 kHz, 50 kbps, ±12.5 kHz deviation, 2-GFSK, 866.6 MHz 50 kbps, ±12.5 kHz deviation, 2-GFSK, 68 kHz RX Bandwidth, 866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 36 dB Sensitivity 50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth, 918.2 MHz, 10% PER, 250 byte payload Selectivity, ±200 kHz, 50 kbps, ±25 kHz deviation, 2-GFSK, 918.2 MHz 50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth, 918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 34 dB Selectivity, ±400 kHz, 50 kbps, ±25 kHz deviation, 2-GFSK, 918.2 MHz 50 kbps, ±25 kHz deviation, 2-GFSK, 98 kHz RX Bandwidth, 918.2 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 41 dB Sensitivity 100 kbps, ±25 kHz deviation, 2-GFSK, 866.6 MHz, 135 kHz RX BW, 10% PER, 250 byte payload -104 Selectivity, ±200 kHz, 100 kbps, ±25 kHz deviation, 2-GFSK, 866.6 MHz 100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth, 866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 37 dB Selectivity, ±400 kHz, 100 kbps, ±25 kHz deviation, 2-GFSK, 866.6 MHz 100 kbps, ±25 kHz deviation, 2-GFSK, 135 kHz RX Bandwidth, 866.6 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 45 dB Sensitivity 100 kbps, ±50 kHz deviation, 2-GFSK, 920.9 MHz, 196 kHz RX BW, 10% PER, 250 byte payload -102 14 Submit Document Feedback -107 dBm dBm dBm dBm Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.10 861 MHz to 1054 MHz - Receive (RX) (continued) Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Selectivity, ±400 kHz, 100 kbps, ±50 kHz deviation, 2-GFSK, 920.9 MHz 100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth, 920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 40 dB Selectivity, ±800 kHz, 100 kbps, ±50 kHz deviation, 2-GFSK, 920.9 MHz 100 kbps, ±50 kHz deviation, 2-GFSK, 196 kHz RX Bandwidth, 920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 49 dB Sensitivity 150 kbps, ±37.5 kHz deviation, 2-GFSK, 920.9 MHz, 273 kHz RX BW, 10% PER, 250 byte payload -99 dBm Selectivity, ±400 kHz, 150 kbps, ±37.5 kHz deviation, 2-GFSK, 920.9 MHz 150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth, 920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 41 dB Selectivity, ±800 kHz, 150 kbps, ±37.5 kHz deviation, 2-GFSK, 920.9 MHz 150 kbps, ±37.5 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth, 920.9 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 47 dB Sensitivity 200 kbps, ±50 kHz deviation, 2-GFSK, 918.4 MHz, 273 kHz RX BW, 10% PER, 250 byte payload -99 dBm Selectivity, ±400 kHz, 200 kbps, ±50 kHz deviation, 2-GFSK, 918.4 MHz 200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 42 dB Selectivity, ±800 kHz, 200 kbps, ±50 kHz deviation, 2-GFSK, 918.4 MHz 200 kbps, ±50 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth, 918.4 MHz, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 49 dB Sensitivity 200 kbps, ±100 kHz deviation, 2-GFSK, 920.8 MHz, 273 kHz RX BW, 10% PER, 250 byte payload -99 dBm Selectivity, ±600 kHz, 200 kbps, ±100 kHz deviation, 2-GFSK, 920.8 MHz 200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth, 920.8 MHz,, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 45 dB Selectivity, ±1200 kHz, 200 kbps, ±100 kHz deviation, 2-GFSK, 920.8 MHz 200 kbps, ±100 kHz deviation, 2-GFSK, 273 kHz RX Bandwidth, 920.8 MHz,, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 52 dB Sensitivity 300 kbps, ±75 kHz deviation, 2-GFSK, 917.6 MHz, 498 kHz RX BW, 10% PER, 250 byte payload -97 dBm Selectivity, ±600 kHz, 300 kbps, ±75 kHz deviation, 2-GFSK, 917.6 MHz 300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth, 917.6 MHz,, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 42 dB Selectivity, ±1200 kHz, 300 kbps, ±75 kHz deviation, 2-GFSK, 917.6 MHz 300 kbps, ±75 kHz deviation, 2-GFSK, 498 kHz RX Bandwidth, 917.6 MHz,, 10% PER, 250 byte payload. Wanted signal 3 dB above sensitivity level 47 dB (1) Wanted signal 3 dB above the reference sensitivity limit according to ETSI EN 300 220 v. 3.1.1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 15 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.11 861 MHz to 1054 MHz - Transmit (TX) Measured on the CC1352-P7EM-XD7793-XD24-PA9093 reference design with Tc = 25°C, VDDS = 3.6 V with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General parameters Max output power, boost mode Sub-1 GHz PA(2) VDDR = 1.95 V Minimum supply voltage (VDDS ) for boost mode is 2.1 V 868 MHz and 915 MHz 14 dBm Max output power, Sub-1 GHz PA(2) 868 MHz and 915 MHz 13 dBm Max output power, High power PA 915 MHz VDDS = 3.3V 20 dBm Output power programmable range Sub-1 GHz PA 868 MHz and 915 MHz 34 dB Output power programmable range High power PA 868 MHz and 915 MHz VDDS = 3.3V 6 dB Output power variation over temperature Sub-1 GHz PA +10 dBm setting Over recommended temperature operating range ±2 dB Output power variation over temperature Boost mode, Sub-1 GHz PA +14 dBm setting Over recommended temperature operating range ±1.5 dB +14 dBm setting ETSI restricted bands < -54 dBm +14 dBm setting ETSI outside restricted bands < -36 dBm 1 GHz to 12.75 GHz (outside ETSI restricted bands) +14 dBm setting measured in 1 MHz bandwidth (ETSI) < -30 dBm 30 MHz to 88 MHz (within FCC restricted bands) +14 dBm setting < -56 dBm 88 MHz to 216 MHz (within FCC restricted bands) +14 dBm setting < -52 dBm 216 MHz to 960 MHz (within FCC restricted bands) +14 dBm setting < -50 dBm 960 MHz to 2390 MHz and above 2483.5 MHz (within FCC restricted band) +14 dBm setting 5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–300 / 300) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–320 / 240) ppm Data rate error tolerance Difference between incoming data rate and the internally generated data rate (255-byte packets) > (–125 / 100) ppm Co-channel rejection(1) Wanted signal at –79 dBm, modulated interferer in channel, BER = 10–3 Selectivity, ±1 MHz(1) –1.5 dB Wanted signal at –79 dBm, modulated interferer at ±1 MHz, BER = 10–3 8 / 4.5(2) dB Selectivity, ±2 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±2 MHz, BER = 10–3 44 / 37(2) dB Selectivity, ±3 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±3 MHz, BER = 10–3 46 / 44(2) dB Selectivity, ±4 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±4 MHz, BER = 10–3 44 / 46(2) dB Selectivity, ±6 MHz(1) Wanted signal at –79 dBm, modulated interferer at ≥ ±6 MHz, BER = 10–3 48 / 44(2) dB Selectivity, ±7 MHz Wanted signal at –79 dBm, modulated interferer at ≥ ±7 MHz, BER = 10–3 51 / 45(2) dB Selectivity, Image frequency(1) Wanted signal at –79 dBm, modulated interferer at image frequency, BER = 10–3 37 dB Selectivity, Image frequency ±1 MHz(1) Note that Image frequency + 1 MHz is the Co- channel –1 MHz. Wanted signal at –79 dBm, modulated interferer at ±1 MHz from image frequency, BER = 10–3 4.5 / 44 (2) dB RSSI Range 89 dB RSSI Accuracy (+/-) ±4 dB 500 kbps (LE Coded) Receiver sensitivity Differential mode. BER = 10–3 –100 dBm Receiver saturation Differential mode. BER = 10–3 >5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–300 / 300) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–450 / 450) ppm Data rate error tolerance Difference between incoming data rate and the internally generated data rate (255-byte packets) > (–150 / 175) ppm 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.14 Bluetooth Low Energy - Receive (RX) (continued) Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS Co-channel rejection(1) Wanted signal at –72 dBm, modulated interferer in channel, BER = 10–3 Selectivity, ±1 MHz(1) MIN TYP MAX UNIT –3.5 dB Wanted signal at –72 dBm, modulated interferer at ±1 MHz, BER = 10–3 8 / 4(2) dB Selectivity, ±2 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±2 MHz, BER = 10–3 43 / 35(2) dB Selectivity, ±3 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±3 MHz, BER = 10–3 46 / 46(2) dB Selectivity, ±4 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±4 MHz, BER = 10–3 45 / 47(2) dB Selectivity, ±6 MHz(1) Wanted signal at –72 dBm, modulated interferer at ≥ ±6 MHz, BER = 10–3 46 / 45(2) dB Selectivity, ±7 MHz Wanted signal at –72 dBm, modulated interferer at ≥ ±7 MHz, BER = 10–3 49 / 45(2) dB Selectivity, Image frequency(1) Wanted signal at –72 dBm, modulated interferer at image frequency, BER = 10–3 35 dB Selectivity, Image frequency ±1 MHz(1) Note that Image frequency + 1 MHz is the Co- channel –1 MHz. Wanted signal at –72 dBm, modulated interferer at ±1 MHz from image frequency, BER = 10–3 4 / 46(2) dB RSSI Range 90 dB RSSI Accuracy (+/-) ±4 dB 1 Mbps (LE 1M) Receiver sensitivity Differential mode. BER = 10–3 –97 dBm Receiver saturation Differential mode. BER = 10–3 >5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–350 / 350) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–650 / 750) ppm Co-channel rejection(1) Wanted signal at –67 dBm, modulated interferer in channel, BER = 10–3 Selectivity, ±1 MHz(1) –6 dB Wanted signal at –67 dBm, modulated interferer at ±1 MHz, BER = 10–3 7 / 4(2) dB Selectivity, ±2 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±2 MHz,BER = 10–3 39 / 33(2) dB Selectivity, ±3 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±3 MHz, BER = 10–3 36 / 40(2) dB Selectivity, ±4 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±4 MHz, BER = 10–3 36 / 45(2) dB Selectivity, ±5 MHz or more(1) Wanted signal at –67 dBm, modulated interferer at ≥ ±5 MHz, BER = 10–3 40 dB Selectivity, image frequency(1) Wanted signal at –67 dBm, modulated interferer at image frequency, BER = 10–3 33 dB Selectivity, image frequency ±1 MHz(1) Note that Image frequency + 1 MHz is the Co- channel –1 MHz. Wanted signal at –67 dBm, modulated interferer at ±1 MHz from image frequency, BER = 10–3 4 / 41(2) dB Out-of-band blocking(3) 30 MHz to 2000 MHz –10 dBm Out-of-band blocking 2003 MHz to 2399 MHz –18 dBm Out-of-band blocking 2484 MHz to 2997 MHz –12 dBm Out-of-band blocking 3000 MHz to 12.75 GHz –2 dBm Intermodulation Wanted signal at 2402 MHz, –64 dBm. Two interferers at 2405 and 2408 MHz respectively, at the given power level –42 dBm Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 19 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.14 Bluetooth Low Energy - Receive (RX) (continued) Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Spurious emissions, 30 to 1000 MHz Measurement in a 50-Ω single-ended load. < –59 dBm Spurious emissions, 1 to 12.75 GHz Measurement in a 50-Ω single-ended load. < –47 dBm RSSI dynamic range 70 dB RSSI accuracy ±4 dB 2 Mbps (LE 2M) Receiver sensitivity Differential mode. Measured at SMA connector, BER = 10–3 –91 dBm Receiver saturation Differential mode. Measured at SMA connector, BER = 10–3 >5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–500 / 500) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–700 / 750) ppm Co-channel rejection(1) Wanted signal at –67 dBm, modulated interferer in channel,BER = 10–3 Selectivity, ±2 MHz(1) –7 dB Wanted signal at –67 dBm, modulated interferer at ±2 MHz, Image frequency is at –2 MHz, BER = 10–3 8 / 4(2) dB Selectivity, ±4 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±4 MHz, BER = 10–3 36 / 34(2) dB Selectivity, ±6 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±6 MHz, BER = 10–3 37 / 36(2) dB Selectivity, image frequency(1) Wanted signal at –67 dBm, modulated interferer at image frequency, BER = 10–3 4 dB Selectivity, image frequency ±2 MHz(1) Note that Image frequency + 2 MHz is the Co-channel. Wanted signal at –67 dBm, modulated interferer at ±2 MHz from image frequency, BER = 10–3 –7 / 36(2) dB Out-of-band blocking(3) 30 MHz to 2000 MHz –16 dBm Out-of-band blocking 2003 MHz to 2399 MHz –21 dBm Out-of-band blocking 2484 MHz to 2997 MHz –15 dBm Out-of-band blocking 3000 MHz to 12.75 GHz –12 dBm Intermodulation Wanted signal at 2402 MHz, –64 dBm. Two interferers at 2408 and 2414 MHz respectively, at the given power level –38 dBm RSSI Range 60 dB RSSI Accuracy (+/-) ±4 dB (1) (2) (3) 20 Numbers given as I/C dB X / Y, where X is +N MHz and Y is –N MHz Excluding one exception at Fwanted / 2, per Bluetooth Specification Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.15 Bluetooth Low Energy - Transmit (TX) Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Max output power, high power PA Differential mode, delivered to a single-ended 50 Ω load through a balun 20 dBm Output power programmable range high power PA Differential mode, delivered to a single-ended 50 Ω load through a balun 6 dB Max output power, high power PA, 10 dBm configuration(3) Differential mode, delivered to a single-ended 50 Ω load through a balun 10.5 Output power programmable range high power PA, 10 dBm configuration(3) Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dB Max output power, 2.4 GHz PA Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dBm Output power programmable range, 2.4 GHz PA Differential mode, delivered to a single-ended 50 Ω load through a balun 26 dB dBm Spurious emissions and harmonics Spurious emissions, high-power PA(1) f < 1 GHz, outside restricted bands < -36 dBm f < 1 GHz, restricted bands FCC < -55 dBm f > 1 GHz, including harmonics Harmonics, high-power PA(2) -37 dBm Second harmonic +20 dBm setting -35 dBm Third harmonic -42 dBm < -36 dBm < -54 dBm < -55 dBm -41 dBm < -42 dBm Third harmonic < -42 dBm f < 1 GHz, outside restricted bands < –36 dBm f < 1 GHz, restricted bands ETSI < –54 dBm < –55 dBm < –42 dBm Second harmonic < –42 dBm Third harmonic < –42 dBm f < 1 GHz, outside restricted bands Spurious emissions, f < 1 GHz, restricted bands ETSI high-power PA, 10 (1) (3) f < 1 GHz, restricted bands FCC, dBm configuration f > 1 GHz, including harmonics Harmonics, high-power PA, 10 dBm configuration(3) Spurious emissions, 2.4 GHz PA Second harmonic f < 1 GHz, restricted bands FCC f > 1 GHz, including harmonics Harmonics, 2.4 GHz PA (1) (2) (3) +10 dBm setting(3) +5 dBm setting To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting may be required when operating at the upper Bluetooth Low Energy channel(s). To ensure margins for passing FCC requirements for harmonic emission, a reduction of maximum output-power may be required. Measured on the CC1352-P7EM-XD7793-XD24-PA24_10dbm reference design. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 21 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.16 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Receiver sensitivity PER = 1% –99 dBm Receiver saturation PER = 1% >5 dBm Adjacent channel rejection Wanted signal at –82 dBm, modulated interferer at ±5 MHz, PER = 1% 36 dB Alternate channel rejection Wanted signal at –82 dBm, modulated interferer at ±10 MHz, PER = 1% 57 dB Channel rejection, ±15 MHz or more Wanted signal at –82 dBm, undesired signal is IEEE 802.15.4 modulated channel, stepped through all channels 2405 to 2480 MHz, PER = 1% 59 dB Blocking and desensitization, 5 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 57 dB Blocking and desensitization, 10 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 62 dB Blocking and desensitization, 20 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 62 dB Blocking and desensitization, 50 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 65 dB Blocking and desensitization, –5 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 59 dB Blocking and desensitization, –10 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 59 dB Blocking and desensitization, –20 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 63 dB Blocking and desensitization, –50 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 65 dB Spurious emissions, 30 MHz to 1000 MHz Measurement in a 50-Ω single-ended load –66 dBm Spurious emissions, 1 GHz to 12.75 GHz Measurement in a 50-Ω single-ended load –53 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > 350 ppm Symbol rate error tolerance Difference between incoming symbol rate and the internally generated symbol rate > 1000 ppm RSSI dynamic range 95 dB RSSI accuracy ±4 dB 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.17 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX Measured on the CC1352-P7EM-XD7793-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Max output power, high power PA Differential mode, delivered to a single-ended 50-Ω load through a balun 20 dBm Output power programmable range, high power PA Differential mode, delivered to a single-ended 50-Ω load through a balun 6 dB Max output power, high power PA, 10 dBm configuration(4) Differential mode, delivered to a single-ended 50-Ω load through a balun 10.5 Output power programmable range, high power PA, 10 dBm configuration(4) Differential mode, delivered to a single-ended 50-Ω load through a balun 5 dB Max output power, 2.4 GHz PA Differential mode, delivered to a single-ended 50-Ω load through a balun 5 dBm Output power programmable range, 2.4 GHz PA Differential mode, delivered to a single-ended 50-Ω load through a balun 26 dB dBm Spurious emissions and harmonics Spurious emissions, high-power PA(2) f < 1 GHz, outside restricted bands < -39 dBm < -49 dBm -40 dBm Second harmonic -35 dBm Third harmonic -42 dBm < -36 dBm < -47 dBm < -55 dBm -42 dBm Second harmonic < -42 dBm Third harmonic < -42 dBm f < 1 GHz, outside restricted bands < -36 dBm f < 1 GHz, restricted bands ETSI < -47 dBm f < 1 GHz, restricted bands FCC < -55 dBm f > 1 GHz, including harmonics < –42 dBm Second harmonic < -42 dBm Third harmonic < -42 dBm f < 1 GHz, restricted bands FCC f > 1 GHz, including harmonics Harmonics, high-power PA(3) Spurious emissions, high-power PA, 10 dBm configuration(2) (4) +20 dBm setting f < 1 GHz, outside restricted bands f < 1 GHz, restricted bands ETSI f < 1 GHz, restricted bands FCC +10 dBm setting(4) f > 1 GHz, including harmonics Harmonics, high-power PA, 10 dBm configuration(4) Spurious emissions, 2.4 GHz PA (1) Harmonics, 2.4 GHz PA +5 dBm setting IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) Error vector magnitude, high power PA +20 dBm setting 2 % Error vector magnitude, high power PA, 10 dBm configuration(4) +10 dBm setting 2 % Error vector magnitude, 2.4-GHz PA +5 dBm setting 2 % (1) (2) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at 2480 MHz. To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at the upper 802.15.4 channel(s). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 23 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 (3) (4) To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required. Measured on the CC1352-P7EM-XD7793-XD24-PA24_10dbm reference design. 7.18 Timing and Switching Characteristics 7.18.1 Reset Timing PARAMETER MIN RESET_N low duration TYP MAX UNIT 1 µs 7.18.2 Wakeup Timing Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not include software overhead. PARAMETER MCU, Reset to TEST CONDITIONS Active(1) MIN TYP MAX UNIT 850 - 4000 µs 850 - 4000 µs MCU, Standby to Active 165 µs MCU, Active to Standby 39 µs MCU, Idle to Active 15 µs MCU, Shutdown to Active(1) (1) 24 The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.18.3 Clock Specifications 7.18.3.1 48 MHz Crystal Oscillator (XOSC_HF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1) PARAMETER MIN TYP Crystal frequency 48 ESR Equivalent series resistance 6 pF < CL ≤ 9 pF 20 ESR Equivalent series resistance 5 pF < CL ≤ 6 pF LM Motional inductance, relates to the load capacitance that is used for the crystal (CL in Farads)(5) CL Crystal load capacitance(4) Start-up (1) (2) (3) (4) (5) MAX MHz 60 Ω 80 Ω < 3 × 10–25 / CL 2 H 7(3) 5 time(2) UNIT 9 200 pF µs Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device. Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used. On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed through software in the Customer Configuration section (CCFG). Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with certain regulations. See the device errata for further details. The crystal manufacturer's specification must satisfy this requirement for proper operation. 7.18.3.2 48 MHz RC Oscillator (RCOSC_HF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN TYP MAX UNIT Frequency 48 MHz Uncalibrated frequency accuracy ±1 % Calibrated frequency accuracy(1) ±0.25 % 5 µs Start-up time (1) Accuracy relative to the calibration source (XOSC_HF) 7.18.3.3 2 MHz RC Oscillator (RCOSC_MF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN TYP MAX UNIT Calibrated frequency 2 MHz Start-up time 5 µs 7.18.3.4 32.768 kHz Crystal Oscillator (XOSC_LF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN Crystal frequency ESR Equivalent series resistance CL Crystal load capacitance (1) TYP MAX 32.768 6 UNIT kHz 30 100 kΩ 7(1) 12 pF Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be used. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 25 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.18.3.5 32 kHz RC Oscillator (RCOSC_LF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN TYP Frequency Calibrated RTC variation(1) Calibrated periodically against XOSC_HF(2) Temperature coefficient (1) MAX UNIT 32.8 kHz ±600(3) ppm 50 ppm/°C When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This functionality is available through the TI-provided Power driver. TI driver software calibrates the RTC every time XOSC_HF is enabled. Some device's variation can exceed 1000 ppm. Further calibration will not improve variation. (2) (3) 7.18.4 Synchronous Serial Interface (SSI) Characteristics 7.18.4.1 Synchronous Serial Interface (SSI) Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER NO. PARAMETER MIN TYP UNIT 65024 System Clocks (2) S1 tclk_per SSIClk cycle time S2(1) tclk_high SSIClk high time 0.5 tclk_per S3(1) tclk_low SSIClk low time 0.5 tclk_per (1) (2) 12 MAX Refer to SSI timing diagrams Figure 7-1, Figure 7-2 and Figure 7-3. When using the TI-provided Power driver, the SSI system clock is always 48 MHz. S1 S2 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 7-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data Figure 7-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer S1 S2 SSIClk (SPO = 0) S3 SSIClk (SPO = 1) SSITx (Master) MSB SSIRx (Slave) MSB LSB LSB SSIFss Figure 7-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1 7.18.5 UART 7.18.5.1 UART Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN UART rate TYP MAX UNIT 2.89 MBaud Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 27 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.19 Peripheral Characteristics 7.19.1 ADC 7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers. PARAMETER TEST CONDITIONS Input voltage range MIN TYP 0 Resolution ±2 LSB Internal 4.3 V equivalent reference(2) ±7 LSB >–1 LSB ±4 LSB Integral nonlinearity Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone reference(2), Internal 4.3 V equivalent 9.6 kHz input tone, DC/DC enabled Effective number of bits Total harmonic distortion Signal-to-noise and distortion ratio 200 kSamples/s, 9.8 9.8 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 10.1 Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone 11.1 Internal reference, voltage scaling disabled, 14-bit mode, 200 kSamples/s, 600 Hz input tone (5) 11.3 Internal reference, voltage scaling disabled, 15-bit mode, 200 kSamples/s, 150 Hz input tone (5) 11.6 Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone –65 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone –70 Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone –72 Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone 60 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 63 Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone 68 Internal 4.3 V equivalent 9.6 kHz input tone 28 ksps Gain error INL SFDR Bits 200 Internal 4.3 V equivalent reference(2) Differential nonlinearity SINAD, SNDR V Offset DNL(4) THD UNIT 12 Sample Rate ENOB MAX VDDS reference(2), 200 kSamples/s, Bits dB dB 70 Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 73 Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone 75 50 dB Conversion time Serial conversion, time-to-output, 24 MHz clock Current consumption Internal 4.3 V equivalent reference(2) 0.40 Clock Cycles mA Current consumption VDDS as reference 0.57 mA Reference voltage Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/ offset compensation factors stored in FCFG1 Reference voltage Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows: Vref = 4.3 V × 1408 / 4095 Reference voltage Reference voltage 4.3(2) (3) V 1.48 V VDDS as reference, input voltage scaling enabled VDDS V VDDS as reference, input voltage scaling disabled VDDS / 2.82(3) V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.19.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued) Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) Performance numbers require use of offset and gain adjustments in software by TI-provided ADC drivers. PARAMETER Input impedance (1) (2) (3) (4) (5) TEST CONDITIONS MIN 200 kSamples/s, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time TYP MAX >1 UNIT MΩ Using IEEE Std 1241-2010 for terminology and test methods Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V Applied voltage must be within Absolute Maximum Ratings at all times No missing codes ADC_output = Σ(4n samples ) >> n, n = desired extra bits 7.19.2 DAC 7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Resolution VDDS FDAC Supply voltage Clock frequency Voltage output settling time 8 1.8 3.8 External Load(4), any VREF, pre-charge OFF, DAC charge-pump OFF 2.0 3.8 Any load, VREF = DCOUPL, pre-charge ON 2.6 3.8 Buffer ON (recommended for external load) 16 250 Buffer OFF (internal load) 16 1000 VREF = VDDS, buffer OFF, internal load VREF = VDDS, buffer ON, external capacitive load = 20 13 pF(3) 20 External resistive load 200 10 kHz pF MΩ Short circuit current 400 VDDS = 3.8 V, DAC charge-pump OFF 50.8 VDDS = 3.0 V, DAC charge-pump ON 51.7 VDDS = 3.0 V, DAC charge-pump OFF 53.2 Max output impedance Vref = VDDS, buffer ON, CLK 250 VDDS = 2.0 V, DAC charge-pump ON kHz VDDS = 2.0 V, DAC charge-pump OFF V 1 / FDAC 13.8 External capacitive load ZMAX Bits Any load, any VREF, pre-charge OFF, DAC charge-pump ON 48.7 µA kΩ 70.2 VDDS = 1.8 V, DAC charge-pump ON 46.3 VDDS = 1.8 V, DAC charge-pump OFF 88.9 Internal Load - Continuous Time Comparator / Low Power Clocked Comparator Differential nonlinearity VREF = VDDS, load = Continuous Time Comparator or Low Power Clocked Comparator FDAC = 250 kHz ±1 Differential nonlinearity VREF = VDDS, load = Continuous Time Comparator or Low Power Clocked Comparator FDAC = 16 kHz ±1.2 DNL Offset error(2) Load = Continuous Time Comparator LSB(1) VREF = VDDS = 3.8 V ±0.64 VREF = VDDS= 3.0 V ±0.81 VREF = VDDS = 1.8 V ±1.27 VREF = DCOUPL, pre-charge ON ±3.43 VREF = DCOUPL, pre-charge OFF ±2.88 VREF = ADCREF ±2.37 LSB(1) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 29 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued) Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER Offset error(2) Load = Low Power Clocked Comparator Max code output voltage variation(2) Load = Continuous Time Comparator Max code output voltage variation(2) Load = Low Power Clocked Comparator Output voltage range(2) Load = Continuous Time Comparator Output voltage range(2) Load = Low Power Clocked Comparator TEST CONDITIONS MIN TYP VREF = VDDS= 3.8 V ±0.78 VREF = VDDS = 3.0 V ±0.77 VREF = VDDS= 1.8 V ±3.46 VREF = DCOUPL, pre-charge ON ±3.44 VREF = DCOUPL, pre-charge OFF ±4.70 VREF = ADCREF ±4.11 VREF = VDDS = 3.8 V ±1.53 VREF = VDDS = 3.0 V ±1.71 VREF = VDDS= 1.8 V ±2.10 VREF = DCOUPL, pre-charge ON ±6.00 VREF = DCOUPL, pre-charge OFF ±3.85 VREF = ADCREF ±5.84 VREF = VDDS= 3.8 V ±2.92 VREF =VDDS= 3.0 V ±3.06 VREF = VDDS= 1.8 V ±3.91 VREF = DCOUPL, pre-charge ON ±7.84 VREF = DCOUPL, pre-charge OFF ±4.06 VREF = ADCREF ±6.94 VREF = VDDS = 3.8 V, code 1 0.03 VREF = VDDS = 3.8 V, code 255 3.62 VREF = VDDS= 3.0 V, code 1 0.02 VREF = VDDS= 3.0 V, code 255 2.86 VREF = VDDS= 1.8 V, code 1 0.01 VREF = VDDS = 1.8 V, code 255 1.71 VREF = DCOUPL, pre-charge OFF, code 1 0.01 VREF = DCOUPL, pre-charge OFF, code 255 1.21 VREF = DCOUPL, pre-charge ON, code 1 1.27 VREF = DCOUPL, pre-charge ON, code 255 2.46 VREF = ADCREF, code 1 0.01 VREF = ADCREF, code 255 1.41 VREF = VDDS = 3.8 V, code 1 0.03 VREF = VDDS= 3.8 V, code 255 3.61 VREF = VDDS= 3.0 V, code 1 0.02 VREF = VDDS= 3.0 V, code 255 2.85 VREF = VDDS = 1.8 V, code 1 0.01 VREF = VDDS = 1.8 V, code 255 1.71 VREF = DCOUPL, pre-charge OFF, code 1 0.01 VREF = DCOUPL, pre-charge OFF, code 255 1.21 VREF = DCOUPL, pre-charge ON, code 1 1.27 VREF = DCOUPL, pre-charge ON, code 255 2.46 VREF = ADCREF, code 1 0.01 VREF = ADCREF, code 255 1.41 MAX UNIT LSB(1) LSB(1) LSB(1) V V External Load INL Integral nonlinearity DNL Differential nonlinearity 30 VREF = VDDS, FDAC = 250 kHz ±1 VREF = DCOUPL, FDAC = 250 kHz ±2 VREF = ADCREF, FDAC = 250 kHz ±1 VREF = VDDS, FDAC = 250 kHz ±1 Submit Document Feedback LSB(1) LSB(1) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.19.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued) Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER Offset error Max code output voltage variation Output voltage range Load = Low Power Clocked Comparator (1) (2) (3) (4) TEST CONDITIONS MIN TYP VREF = VDDS= 3.8 V ±0.40 VREF = VDDS= 3.0 V ±0.50 VREF = VDDS = 1.8 V ±0.75 VREF = DCOUPL, pre-charge ON ±1.55 VREF = DCOUPL, pre-charge OFF ±1.30 VREF = ADCREF ±1.10 VREF = VDDS= 3.8 V ±1.00 VREF = VDDS= 3.0 V ±1.00 VREF = VDDS= 1.8 V ±1.00 VREF = DCOUPL, pre-charge ON ±3.45 VREF = DCOUPL, pre-charge OFF ±2.10 VREF = ADCREF ±1.90 VREF = VDDS = 3.8 V, code 1 0.03 VREF = VDDS = 3.8 V, code 255 3.61 VREF = VDDS = 3.0 V, code 1 0.02 VREF = VDDS= 3.0 V, code 255 2.85 VREF = VDDS= 1.8 V, code 1 0.02 VREF = VDDS = 1.8 V, code 255 1.71 VREF = DCOUPL, pre-charge OFF, code 1 0.02 VREF = DCOUPL, pre-charge OFF, code 255 1.20 VREF = DCOUPL, pre-charge ON, code 1 1.27 VREF = DCOUPL, pre-charge ON, code 255 2.46 VREF = ADCREF, code 1 0.02 VREF = ADCREF, code 255 1.42 MAX UNIT LSB(1) LSB(1) V 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV Includes comparator offset A load > 20 pF will increases the settling time Keysight 34401A Multimeter Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 31 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.19.3 Temperature and Battery Monitor 7.19.3.1 Temperature Sensor Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 2 °C Accuracy -40 °C to 0 °C ±4.0 °C Accuracy 0 °C to 105 °C ±2.5 °C 3.6 °C/V Supply voltage (1) coefficient(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided temperature driver. 7.19.3.2 Battery Monitor Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP Resolution MAX 25 Range 1.8 mV 3.8 Integral nonlinearity (max) Accuracy UNIT VDDS = 3.0 V V 23 mV 22.5 mV Offset error -32 mV Gain error -1 % 7.19.4 Comparators 7.19.4.1 Low-Power Clocked Comparator Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN Input voltage range Clock frequency Internal reference MAX UNIT VDDS V SCLK_LF voltage(1) Offset Using internal DAC with VDDS as reference voltage, DAC code = 0 - 255 0.024 - 2.865 Measured at VDDS / 2, includes error from internal DAC Decision time (1) TYP 0 Step from –50 mV to 50 mV V ±5 mV 1 Clock Cycle The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage selected. See #none# 7.19.4.2 Continuous Time Comparator Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS Input voltage range(1) Measured at VDDS / 2 Decision time Step from –10 mV to 10 mV Current consumption Internal reference 32 TYP 0 Offset (1) MIN MAX VDDS ±5 UNIT V mV 0.70 µs 8.0 µA The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using the DAC Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.19.5 Current Source 7.19.5.1 Programmable Current Source Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN Current source programmable output range (logarithmic range) Resolution TYP MAX UNIT 0.25 - 20 µA 0.25 µA 7.19.6 GPIO 7.19.6.1 GPIO DC Characteristics Measurements CBSed to PG2.1: PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25 °C, VDDS = 1.8 V GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 1.56 V GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.24 V GPIO VOH at 4 mA load IOCURR = 1 1.59 V GPIO VOL at 4 mA load IOCURR = 1 0.21 V GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 73 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 19 µA GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.08 V GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 0.73 V GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.35 V GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 2.59 V GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.42 V GPIO VOH at 4 mA load IOCURR = 1 2.63 V GPIO VOL at 4 mA load IOCURR = 1 0.40 V GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 282 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 110 µA GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.97 V GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 1.55 V GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.42 V TA = 25 °C, VDDS = 3.0 V TA = 25 °C, VDDS = 3.8 V TA = 25 °C VIH Lowest GPIO input voltage reliably interpreted as a High VIL Highest GPIO input voltage reliably interpreted as a Low 0.8*VDDS V 0.2*VDDS Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 V 33 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20 Typical Characteristics All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See Section 7.3 for device limits. Values exceeding these limits are for reference only. 7.20.1 MCU Current Active Current vs. VDDS Standby Current vs. Temperature Running CoreMark, SCLK_HF = 48 MHz RCOSC 144 kB RAM retention, no Cache Retention, RTC On SCLK_LF = 32 kHz XOSC 6 8 5.5 7 6 Current [A] Current [mA] 5 4.5 4 3.5 5 4 3 2 3 1 2.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 0 -40 3.8 Voltage [V] Figure 7-4. Active Mode (MCU) Current vs. Supply Voltage (VDDS) -30 -20 -10 0 10 20 30 40 50 Temperature [oC] 60 70 80 90 100 Figure 7-5. Standby Mode (MCU) Current vs. Temperature 7.20.2 RX Current RX Current vs. Temperature RX Current vs. Temperature Bluetooth Low Energy 1 Mbps, 2.44 GHz 50 kbps, 868.3 MHz, VDSS = 3.6 V 7.5 7 7.4 6.8 7.3 7.2 6.6 7.1 Current [mA] Current [mA] 6.4 6.2 6 5.8 5.6 6.8 6.7 6.6 6.5 6.4 6.3 5.4 6.2 5.2 5 -40 7 6.9 6.1 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 6 -40 -30 -20 Temperature [C] Figure 7-6. RX Current vs. Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V) 34 -10 0 10 20 30 40 50 Temperature [oC] 60 70 80 90 100 Figure 7-7. RX Current vs. Temperature (Bluetooth Low Energy 1 Mbps, 2.44 GHz) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.2 RX Current (continued) RX Current vs. VDSS RX Current vs. VDDS 50 kbps, 868.3 MHz Bluetooth Low Energy 1 Mbps, 2.44 GHz 11 11.5 10.5 11 10 10.5 10 9.5 9 Current [mA] Current [mA] 9.5 8.5 8 7.5 7 9 8.5 8 7.5 7 6.5 6.5 6 6 5.5 5.5 5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 5 1.8 2 Voltage [V] 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Voltage [V] Figure 7-8. RX Current vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz) Figure 7-9. RX Current vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 35 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 18 17.7 17.4 17.1 16.8 16.5 16.2 15.9 15.6 15.3 15 14.7 14.4 14.1 13.8 13.5 13.2 12.9 12.6 12.3 12 -40 TX Current vs. Temperature TX Current vs. Temperature 50 kbps, 868.3 MHz, +10 dBm, VDDS = 3.6 V 50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V 85 75 70 60 55 50 45 35 30 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 25 -40 100 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature [°C] D015 Figure 7-10. TX Current vs. Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V) D016 Figure 7-11. TX Current vs. Temperature (50 kbps, 915 MHz, VDDS = 3.3 V) TX Current vs. Temperature TX Current vs. Temperature Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA 8 150 7.8 140 7.6 130 120 Current [mA] 7.4 Current [mA] 65 40 Temperature [°C] 7.2 7 6.8 6.6 110 +20 +19 +18 +17 +16 +15 +14 dBm dBm dBm dBm dBm dBm dBm -20 -10 100 90 80 70 6.4 60 6.2 50 6 -40 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 80 Current [mA] Current [mA] 7.20.3 TX Current -30 -20 -10 0 10 20 30 40 50 Temperature [oC] 60 70 80 90 40 -40 100 -30 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 7-12. TX Current vs. Temperature (Bluetooth Low Energy Figure 7-13. TX Current vs. Temperature (Bluetooth Low Energy 1 Mbps, 2.44 GHz) 1 Mbps, 2.44 GHz, VDDS = 3.3 V) TX Current vs. Temperature TX Current vs. VDDS Bluetooth Low Energy 1 Mbps, 2.44 GHz, + 10 dBm PA 50 kbps, 868.3 MHz, +10 dBm 26 26 + + + + + 24 25 24 23 22 Current [mA] Current [mA] 22 10 dBm 9 dBm 8 dBm 7 dBm 6 dBm 20 18 16 21 20 19 18 17 16 14 15 14 12 -40 13 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [C] Figure 7-14. TX Current vs. Temperature (250 kbps, 2.44 GHz, +10 dBm PA) 36 12 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Voltage [V] 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 D022 Figure 7-15. TX Current vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.3 TX Current (continued) TX Current vs. VDDS TX Current vs. VDDS Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm 50 kbps, 915 MHz, +20 dBm PA 12 70 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm Current [mA] 60 55 11 10.5 10 Current [mA] 65 11.5 50 45 9.5 9 8.5 8 7.5 40 7 6.5 35 6 30 25 1.8 5.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage [V] 3.8 D023 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Figure 7-17. TX Current vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz) TX Current vs. VDDS TX Current vs. VDDS Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA Bluetooth Low Energy 1 Mbps 2.44GHz, + 10 dBm PA 130 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 1.8 1.9 2 3.8 Voltage [V] 45 +20 +19 +18 +17 +16 +15 +14 dBm dBm dBm dBm dBm dBm dBm + + + + + 40 35 Current [mA] Current [mA] Figure 7-16. TX Current vs. Supply Voltage (VDDS) (50 kbps, 915 MHz) 2 10 dBm 9 dBm 8 dBm 7 dBm 6 dBm 30 25 20 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 10 1.8 2 2.2 2.4 2.6 Figure 7-18. TX Current vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA) 2.8 3 3.2 3.4 3.6 3.8 Voltage [V] Voltage [V] Figure 7-19. TX Current vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz, +10 dBm PA) Table 7-1. Typical TX Current and Output Power CC1352P7 at 868 MHz, VDDS = 3.6 V (1) (Measured on CC1352P-7EM-XD7793-XD24-PA9093) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x013F1 14 13.6 24 0xB224 12.5 11.9 17 0x895E 12 11.5 16 0x669A 11 10.6 15 0x3E92 10 9.7 14 0x3EDC 9 8.9 13 0x2CD8 8 8.3 12 0x26D4 7 7.4 11 0x20D1 6 6.3 10 0x1CCE 5 4.8 10 0x16CD 4 4.2 9 0x14CB 3 2.8 8 0x12CA 2 1.9 8 0x12C9 1 1.0 8 1 Boost mode enabled. VDDR regulated to 1.95 V. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 37 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.3 TX Current (continued) Table 7-1. Typical TX Current and Output Power (continued) CC1352P7 at 868 MHz, VDDS = 3.6 V (1) (Measured on CC1352P-7EM-XD7793-XD24-PA9093) (1) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x10C8 0 -0.1 7 0x0AC4 -5 -6.8 6 0x0AC2 -10 -13.3 5 0x06C1 -15 -18.5 5 0x04C0 -20 -22.0 4 Internal regulated voltage powers the PA, therefore the output power is not affected by variation in VDDS voltage. Table 7-2. Typical TX Current and Output Power CC1352P7 at 915 MHz, VDDS = 3.3 V (1) (Measured on CC1352P-7EM-XD7793-XD24-PA9093) (1) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x1B8ED2 20 20.4 65 0x448CF 19 19.3 55 0x48022 18 17.8 45 0x2661C 17 16.8 41 0x5618 16 15.9 37 0x4812 15 14.9 33 0x380D 14 13.7 30 VDDS powers the PA, therefore the output power is affected by variation in VDDS voltage. Table 7-3. Typical TX Current and Output Power CC1352P7 at 2.4 GHz, VDDS = 3.3 V (1) (Measured on CC1352-7PEM-XD7793-XD24-PA24) (1) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x3F75F5 20 19.6 102 0x3F61E2 19 18.3 86 0x3047E0 18 17.4 79 0x1B4FE5 17 16.3 71 0x1B39DE 16 15.2 63 0x1B2FDA 15 14.3 58 0x1B27D6 14 13.2 52 VDDS powers the PA, therefore the output power is affected by variation in VDDS voltage. Table 7-4. Typical TX Current and Output Power CC1352P7 at 2.4 GHz, VDDS = 3.0 V (1) (Measured on CC1352-7PEM-XD7793-XD24-PA24_10dBm) (1) 38 txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x103F5F 10 10.7 21 0x10335A 9 9.6 19 0x143661 8 8.5 19 0x144F2A 7 7.6 17 0x144F26 6 6.6 16 0x144722 5 5.4 15 Internal regulated voltage powers the PA, therefore the output power is not affected by variation in VDDS voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.3 TX Current (continued) Table 7-5. Typical TX Current and Output Power CC1352P7 at 2.4 GHz, VDDS = 3.0 V (1) (Measured on CC1352-7PEM-XD7793-XD24-PA24) (1) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x762E 5 4.7 10 0x8220 4 3.7 9 0x5617 3 2.8 8 0x3E66 2 1.9 8 0x3261 1 0.9 8 0x2C5D 0 0.0 7 0x1899 -3 -3.1 6 0x1695 -5 -4.9 6 0x1693 -6 -6.0 6 0x0CD4 -9 -9.1 5 0x0AD3 -10 -9.8 5 0x0AD0 -12 -11.9 5 0x06CD -15 -14.6 5 0x04CA -18 -17.8 5 0x04C8 -20 -20.4 4 Internal regulated voltage powers the PA, therefore the output power is not affected by variation in VDDS voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 39 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.4 RX Performance Sensitivity vs. Frequency Sensitivity vs. Frequency 50 kbps -105 -105 -106 -106 -107 -107 -108 -108 Sensitivity [dBm ] Sensitivity [dBm ] 50 kbps -109 -110 -111 -112 -110 -111 -112 -113 -113 -114 -114 -115 863 864 865 866 867 868 869 -115 900 870 Frequency [MHz] -98 Sensitivity [dBm ] -97 -95 -96 -97 -98 -99 924 D027 -101 -102 -103 -104 2.424 2.432 2.44 2.448 2.456 2.464 2.472 -105 2.4 2.48 2.408 -94 -108 -95 Sensitivity [dBm] -93 -107 -109 -110 -111 -112 2.472 2.48 D029 -98 -99 -114 -101 50 2.464 -97 -100 40 2.456 -96 -113 30 2.448 Bluetooth Low Energy 1 Mbps, 2.44 GHz -106 20 2.44 Sensitivity vs. Temperature -92 Temperature [°C] 2.432 Figure 7-23. Sensitivity vs. Frequency (250 kbps, 2.44 GHz) -105 10 2.424 Frequency [GHz] 50 kbps, 868.3 MHz 0 2.416 D028 Sensitivity vs. Temperature -10 930 -100 -101 2.416 927 -99 -100 Figure 7-22. Sensitivity vs. Frequency (Bluetooth Low Energy 1 Mbps, 2.44 GHz) Sensitivity [dBm] 921 Sensitivity vs. Frequency Frequency [GHz] 60 70 80 90 -102 -40 100 -30 -20 -10 0 10 20 30 40 50 Temperature [°C] D030 Figure 7-24. Sensitivity vs. Temperature (50 kbps, 868.3 MHz) 40 918 IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps) -96 -20 915 Sensitivity vs. Frequency -94 -30 912 Bluetooth Low Energy 1 Mbps, 2.44 GHz -95 -115 -40 909 Figure 7-21. Sensitivity vs. Frequency (50 kbps, 915 MHz) -93 2.408 906 Frequency [MHz] -92 -102 2.4 903 D026 Figure 7-20. Sensitivity vs. Frequency (50 kbps, 868 MHz) Sensitivity [dBm] -109 60 70 80 90 100 D031 Figure 7-25. Sensitivity vs. Temperature (Bluetooth Low Energy 1 Mbps, 2.44 GHz) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.4 RX Performance (continued) Sensitivity vs. VDDS Sensitivity vs. Temperature 50 kbps, 868.3 MHz -95 -105 -96 -106 -97 -107 -98 -108 Sensitivity [dBm ] Sensitivity [dBm] IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz -99 -100 -101 -102 -110 -111 -112 -103 -113 -104 -114 -105 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] -115 1.8 100 2.4 2.6 2.8 3 3.2 3.4 3.6 D033 Sensitivity vs. VDDS Sensitivity vs. VDDS Bluetooth Low Energy 1 Mbps, 2.44 Ghz Bluetooth Low Energy 1 Mbps, 2.44 GHz, DCDC Off -93 -94 -94 -95 -95 Sensitivity [dBm] -92 -96 -97 -98 -99 -96 -97 -98 -99 -100 -100 -101 -101 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage [V] -102 1.8 3.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage [V] D034 Figure 7-28. Sensitivity vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz) 3.8 Figure 7-27. Sensitivity vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz) -93 2 2.2 Voltage [V] -92 -102 1.8 2 D032 Figure 7-26. Sensitivity vs. Temperature (250 kbps, 2.44 GHz) Sensitivity [dBm] -109 3.8 D035 Figure 7-29. Sensitivity vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz, DCDC Off) Sensitivity vs. VDDS Selectivity vs. Frequency Offset IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz 50 kbps, 868.3 MHz -95 80 -96 60 -98 Selectivity [dB] Sensitivity [dBm ] -97 -99 -100 -101 40 20 -102 0 -103 -104 -105 1.8 2 2.2 2.4 2.6 2.8 3 Voltage [V] 3.2 3.4 3.6 3.8 -20 -10 -8 Figure 7-30. Sensitivity vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz) -6 -4 -2 0 2 Frequency [MHz] D036 4 6 8 10 D038 Figure 7-31. Selectivity vs. Frequency Offset (50 kbps, 868.3 MHz) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 41 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.4 RX Performance (continued) Packet error rate vs level and frequency offset for SLR 5 kbps. 0 100 90 -20 80 70 Level [dBm] -40 60 -60 50 40 -80 30 -100 20 10 -120 0 -30 -20 -10 0 10 20 30 Offset frequency [ppm] Figure 7-32. PER vs. Level vs. Frequency (SimpleLink™ Long Range 5 kbps, 868 MHz) Figure 7-33. PER vs. Level vs. Frequency (SimpleLink™ Long Range 5 kbps, 868 MHz) Figure 7-34. Narrowband, 9.6 kbps ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX Bandwidth 42 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.5 TX Performance Output Power vs. Temperature Output Power vs. Temperature 50 kbps, 915 MHz, +20 dBm PA, VDDS = 3.3 V 50 kbps, 868.3 MHz, +14 dBm 26 14 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 13.8 24 Output Power [dBm] Output Power [dBm] 13.6 13.4 13.2 13 12.8 12.6 22 20 18 16 12.4 14 12.2 12 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 12 -40 100 Temperature [°C] -30 -10 0 10 20 30 40 50 60 70 80 90 D040 Output Power vs. Temperature Output Power vs. Temperature Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm -20 -10 0 10 20 30 40 50 60 70 80 90 100 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] D041 Figure 7-37. Output Power vs. Temperature (Bluetooth Low Energy 1 Mbps, 2.44 GHz) 100 Figure 7-36. Output Power vs. Temperature (50 kbps, 915 MHz) Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm Temperature [°C] D042 Figure 7-38. Output Power vs. Temperature (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm) TX Output Power vs. Temperature Output Power vs. Temperature Bluetooth Low Energy 1 Mbps, 2.44 GHz, +10 dBm Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA, VDDS = 3.3 V 15 26 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 22 + + + + + 14 13 Output Power [dBm] 24 Output Power [dBm ] -20 Temperature [°C] Output Power [dBm] Output Power [dBm] Figure 7-35. Output Power vs. Temperature (50 kbps, 868.3 MHz) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -40 -30 D039 20 18 16 12 10 dBm 9 dBm 8 dBm 7 dBm 6 dBm 11 10 9 8 7 6 5 4 3 14 2 -40 12 -40 -30 -20 -10 0 10 20 30 40 50 Temperature [°C] 60 70 80 90 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [C] 100 D043 Figure 7-39. Output Power vs. Temperature (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA) Figure 7-40. Output Power vs. Temperature (2.44 GHz, +10 dBm PA) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 43 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.5 TX Performance (continued) Output Power vs. VDDS Output Power vs. VDDS 14 13.9 13.8 13.7 13.6 13.5 13.4 13.3 13.2 13.1 13 12.9 12.8 12.7 12.6 12.5 12.4 12.3 12.2 12.1 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 50 kbps, 915 MHz, +20 dBm PA 22 3 14 2.4 2.6 2.8 3 3.2 3.4 D045 Output Power vs. VDDS Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Figure 7-42. Output Power vs. Supply Voltage (VDDS) (50 kbps, 915 MHz) Output Power vs. VDDS 2.2 3.6 Voltage [V] 3.8 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage [V] D046 Figure 7-43. Output Power vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz) 3.8 D048 Figure 7-44. Output Power vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm) TX Output Power vs. VDDS Output Power vs. VDDS Bluetooth Low Energy 1 Mbps, 2.44 GHz, +10 dBm PA Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA 14 22 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 18 + + + + + 13 12 Output Power [dBm] 20 Output Power [dBm] 2.2 Bluetooth Low Energy 1 Mbps, 2.44 GHz, 0 dBm Voltage [V] 16 14 10 dBm 9 dBm 8 dBm 7 dBm 6 dBm 11 10 9 8 7 6 5 12 4 1.8 10 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Voltage [V] 2 2.2 2.4 2.6 2.8 Voltage [V] 3 3.2 3.4 3.6 3.8 D050 Figure 7-45. Output Power vs. Supply Voltage (VDDS) (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA) 44 2 D044 Output Power [dBm] Output Power [dBm] 16 10 1.8 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Figure 7-41. Output Power vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz) 2 18 12 Voltage [V] 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 1.8 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 20 Output Power [dBm] Output Power [dBm] 50 kbps, 868.3 MHz, +14 dBm Figure 7-46. Output Power vs. Supply Voltage (VDDS) (2.44 GHz, +10 dBm PA) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.5 TX Performance (continued) Output Power vs. Frequency Output Power vs. Frequency 14 13.9 13.8 13.7 13.6 13.5 13.4 13.3 13.2 13.1 13 12.9 12.8 12.7 12.6 12.5 12.4 12.3 12.2 12.1 12 863 50 kbps, +14 dBm Output Power [dBm] Output Power [dBm] 50 kbps, +14 dBm 864 865 866 867 868 869 870 Frequency [MHz] 914 916 918 920 922 924 Output Power vs. Frequency 20.4 20 19.6 19.2 18.8 18.4 18 17.6 17.2 16.8 16.4 906 908 910 912 914 916 918 920 922 924 926 Frequency [MHz] 928 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 2.4 2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 Frequency [GHz] D056 Figure 7-49. Output Power vs. Frequency (50 kbps, 915 MHz, VDDS = 3.3 V) 926 928 D053 Bluetooth Low Energy 1 Mbps, 2.44 Ghz, 0 dBm Output Power [dBm] Output Power [dBm] 912 50 kbps, +20 dBm PA, VDDS = 3.3 V 20.8 2.48 D058 Figure 7-50. Output Power vs. Frequency (Bluetooth Low Energy 1 Mbps, 2.44 GHz) Output Power vs. Frequency Output Power vs. Frequency Bluetooth Low Energy 1 Mbps, 2.44 Ghz, +5 dBm Bluetooth Low Energy 1 Mbps, +20 dBm PA, VDDS = 3.3 V 25 24 23 Output Power [dBm] Output Power [dBm] 910 Output Power vs. Frequency 21.2 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.4 908 Figure 7-48. Output Power vs. Frequency (50 kbps, 915 MHz) +20 dBm +17 dBm 904 906 Frequency [MHz] 22 16 902 904 D052 Figure 7-47. Output Power vs. Frequency (50 kbps, 868 MHz) 21.6 14 13.9 13.8 13.7 13.6 13.5 13.4 13.3 13.2 13.1 13 12.9 12.8 12.7 12.6 12.5 12.4 12.3 12.2 12.1 12 902 22 21 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 20 19 18 17 16 15 14 2.408 2.416 2.424 2.432 2.44 2.448 Frequency [GHz] 2.456 2.464 2.472 2.48 13 2.4 2.408 Figure 7-51. Output Power vs. Frequency (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +5 dBm) 2.416 2.424 2.432 2.44 2.448 Frequency [GHz] D059 2.456 2.464 2.472 2.48 D060 Figure 7-52. Output Power vs. Frequency (Bluetooth Low Energy 1 Mbps, 2.44 GHz, +20 dBm PA) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 45 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.5 TX Performance (continued) Output Power vs. Frequency IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), +10 dBm PA 14 13 Output Power [dBm] 12 +10 dBm +9 dBm + 8dBm +7 dBm +6 dBm 11 10 9 8 7 6 5 2405 2415 2425 2435 2445 2455 2465 2475 2480 Frequency [MHz] Figure 7-53. Output Power vs. Frequency (250 kbps, +10 dBm PA) 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 7.20.6 ADC Performance ENOB vs. Input Frequency ENOB vs. Sampling Frequency Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10 11.4 Internal Reference, No Averaging Internal Unscaled Reference, 14-bit Mode 10.2 11.1 10.15 10.1 ENOB [Bit] ENOB [Bit] 10.8 10.5 10.2 10.05 10 9.95 9.9 9.9 9.85 9.8 9.6 0.2 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10 20 30 40 50 1 70 100 Frequency [kHz] 4 5 6 7 8 10 20 30 40 50 70 100 200 D062 Figure 7-55. ENOB vs. Sampling Frequency INL vs. ADC Code DNL vs. ADC Code Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s 2.5 1 2 0.5 1.5 DNL [LSB] 1.5 0 1 -0.5 0.5 -1 0 -1.5 -0.5 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 ADC Code 0 400 1600 2000 2400 2800 3200 ADC Accuracy vs. VDDS Vin = 1 V, Internal reference, 200 kSamples/s Vin = 1 V, Internal reference, 200 kSamples/s 1.008 1.008 1.007 1.007 Voltage [V] 1.01 1.009 1.006 1.005 1.004 1.006 1.005 1.004 1.003 1.003 1.002 1.002 1.001 1.001 -10 0 10 20 30 40 50 60 70 4000 D065 ADC Accuracy vs. Temperature -20 3600 Figure 7-57. DNL vs. ADC Code 1.01 -30 1200 ADC Code 1.009 1 -40 800 D064 Figure 7-56. INL vs. ADC Code Voltage [V] 3 Frequency [kHz] Figure 7-54. ENOB vs. Input Frequency INL [LSB] 2 D061 80 90 Temperature [°C] 1 1.8 100 2 Figure 7-58. ADC Accuracy vs. Temperature 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage [V] D066 3.8 D067 Figure 7-59. ADC Accuracy vs. Supply Voltage (VDDS) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 47 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8 Detailed Description 8.1 Overview Section 3.1 shows the core modules of the CC1352P7 device. 8.2 System CPU The CC1352P7 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the application and the higher layers of radio protocol stacks. The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Its features include the following: • ARMv7-M architecture optimized for small-footprint embedded applications • Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm core in a compact memory size • Fast code execution permits increased sleep mode time • Deterministic, high-performance interrupt handling for time-critical applications • Single-cycle multiply instruction and hardware divide • Hardware division and fast digital-signal-processing oriented multiply accumulate • Saturating arithmetic for signal processing • IEEE 754-compliant single-precision Floating Point Unit (FPU) • Memory Protection Unit (MPU) for safety-critical applications • Full debug with data matching for watchpoint generation – Data Watchpoint and Trace Unit (DWT) – JTAG Debug Access Port (DAP) – Flash Patch and Breakpoint Unit (FPB) • Trace support reduces the number of pins required for debugging and tracing – Instrumentation Trace Macrocell Unit (ITM) – Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO) • Optimized for single-cycle flash memory access • Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait states • Ultra-low-power consumption with integrated sleep modes • 48 MHz operation • 1.25 DMIPS per MHz 48 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.3 Radio (RF Core) The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and assembles the information bits in a given packet structure. The RF core offers a high level, command-based API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not programmable by customers and is interfaced through the TI-provided RF driver that is included with the SimpleLink Software Development Kit (SDK). The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main CPU, which reduces power and leaves more resources for the user application. Several signals are also available to control external circuitry such as RF switches or range extenders autonomously. Dual-band and multiprotocol solutions are enabled through time-sliced access of the radio, handled transparently for the application through the TI-provided RF driver and dual-mode manager. The various physical layer radio formats are partly built as a software defined radio where the radio behavior is either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards even with over-the-air (OTA) updates while still using the same silicon. Note Not all combinations of features, frequencies, data rates, and modulation formats described in this chapter are supported. Over time, TI can enable new physical radio formats (PHYs) for the device and provides performance numbers for selected PHYs in the data sheet. Supported radio formats for a specific device, including optimized settings to use with the TI RF driver, are included in the SmartRF Studio tool with performance numbers of selected formats found in Section 7. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 49 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.3.1 Proprietary Radio Formats The CC1352P7 radio can support a wide range of physical radio formats through a set of hardware peripherals combined with firmware available in the device ROM, covering various customer needs for optimizing towards parameters such as speed or sensitivity. This allows great flexibility in tuning the radio both to work with legacy protocols as well as customizing the behavior for specific application needs. Table 8-1 gives a simplified overview of features of the various radio formats available in ROM. Other radio formats may be available in the form of radio firmware patches or programs through the Software Development Kit (SDK) and may combine features in a different manner, as well as add other features. Table 8-1. Feature Support Feature Main 2-(G)FSK Mode High Data Rates Low Data Rates SimpleLink™ Long Range Programmable preamble, sync word and CRC Yes Yes Yes No Programmable receive bandwidth Yes Yes Yes (down to 4 kHz) Yes 20 to 1000 kbps ≤ 2 Msps ≤ 100 ksps ≤ 20 ksps 2-(G)FSK 2-(G)FSK 4-(G)FSK 2-(G)FSK 4-(G)FSK 2-(G)FSK Dual Sync Word Yes Yes No No Carrier Sense (1) (2) Yes No No No Data / Symbol rate(3) Modulation format Preamble Detection(2) Yes Yes Yes No Data Whitening Yes Yes Yes Yes Digital RSSI Yes Yes Yes Yes CRC filtering Yes Yes Yes Yes Direct-sequence spread spectrum (DSSS) No No No 1:2 1:4 1:8 Forward error correction (FEC) No No No Yes Link Quality Indicator (LQI) Yes Yes Yes Yes (1) (2) (3) Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API. Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power. Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a smaller range might be supported. 8.3.2 Bluetooth 5.2 Low Energy The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-speed 2-Mbps physical layer and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or through a high-level Bluetooth API. The Bluetooth 5.2 PHY and part of the controller are in radio and system ROM, providing significant savings in memory usage and more space available for applications. The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers significant improvements for energy efficiency and wireless coexistence with reduced radio communication time. Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not previously an option using Bluetooth Low Energy. With high-speed mode, existing applications deliver faster responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates. 50 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.3.3 802.15.4 (Thread, Zigbee, 6LoWPAN) Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread, Zigbee, and 6LoWPAN protocols. The 802.15.4 PHY and MAC are in radio and system ROM. TI also provides royalty-free protocol stacks for Thread and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution. 8.4 Memory The up to 704KB nonvolatile (flash) memory provides storage for code and data. The flash memory is in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done through the ccfg.c source file that is included in all TI provided examples. The ultra-low leakage system static RAM (SRAM) is split into four 32KB and one 16KB blocks and can be used for both storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always initialized to zeroes upon code execution from boot. To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU. The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area (CCFG). There is a 4KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets. The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks, which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that can be used for initial programming of the device. 8.5 Sensor Controller The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby significantly reducing power consumption and offloading the system CPU. The Sensor Controller Engine is user programmable with a simple programming language that has syntax similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable state machines, or event routing. The main advantages are: • Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power • 2 MHz low-power mode enables lowest possible handling of digital sensors • Dynamic reuse of hardware resources • 40-bit accumulator supporting multiplication, addition and shift • Observability and debugging options Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C driver source code, which the System CPU application uses to control and exchange data with the Sensor Controller. Typical use cases may be (but are not limited to) the following: • Read analog sensors using integrated ADC or comparators • Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged) • Capacitive sensing • Waveform generation • Very low-power pulse counting (flow metering) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 51 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 • Key scan The peripherals in the Sensor Controller include the following: • The low-power clocked comparator can be used to wake the system CPU from any state in which the comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator. The output of the comparator can also be used to trigger an interrupt or the ADC. • Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital converter, and a comparator. The continuous time comparator in this block can also be used as a higheraccuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive sensing. • The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be triggered by many different sources including timers, I/O pins, software, and comparators. • The analog modules can connect to up to eight different GPIOs • Dedicated SPI master with up to 6 MHz clock speed The peripherals in the Sensor Controller can also be controlled from the main application processor. 52 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.6 Cryptography The CC1352P7 device comes with a wide set of modern cryptography-related hardware accelerators, drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit of being lower power and improves availability and responsiveness of the system because the cryptography operations runs in a background hardware thread. Together with a large selection of open-source cryptography libraries provided with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The hardware accelerator modules are: • True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit. • Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512 • Advanced Encryption Standard (AES) with 128 and 256 bit key lengths • Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic curves up to 512 bits and RSA key pair generation up to 1024 bits. Through use of these modules and the TI provided cryptography drivers, the following capabilities are available for an application or stack: • Key Agreement Schemes – Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE) – Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE) • Signature Generation – Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA) • Curve Support – Short Weierstrass form (full hardware support), such as: • NIST-P224, NIST-P256, NIST-P384, NIST-P521 • Brainpool-256R1, Brainpool-384R1, Brainpool-512R1 • secp256r1 – Montgomery form (hardware support for multiplication), such as: • Curve25519 • SHA2 based MACs – HMAC with SHA224, SHA256, SHA384, or SHA512 • Block cipher mode of operation – AESCCM – AESGCM – AESECB – AESCBC – AESCBC-MAC • True random number generation Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of the TI SimpleLink SDK for the CC1352P7 device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 53 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.7 Timers A large selection of timers are available as part of the CC1352P7 device. These timers are: • Real-Time Clock (RTC) A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF). This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for frequency drift when using the RCOSC_LF as the low frequency system clock. If an external LF clock with frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this. When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the RTC halts when a debugger halts the device. • General Purpose Timers (GPTIMER) The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48 MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting, pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of the timer are connected to the device event fabric, which allows the timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes. • Sensor Controller Timers The Sensor Controller contains 3 timers: AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each edge of a selected tick source. Both one-shot and periodical timer modes are available. AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as well as for PWM output or waveform generation. • Radio Timer A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is typically used as the timing base in wireless network communication using the 32-bit timing word as the network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in the radio APIs and should only be used when the accurate 48 MHz high frequency crystal is the source of SCLK_HF. • Watchdog timer The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and when a debugger halts the device. 54 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.8 Serial Peripherals and I/O The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI modules support configurable phase and polarity. The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baudrate generation up to a maximum of 3 Mbps. The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation microphones (PDM). The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface can handle 100 kHz and 400 kHz operation, and can serve as both master and slave. The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 6. All digital peripherals can be connected to any digital pin on the device. For more information, see the CC13x2x7, CC26x2x7 SimpleLink™ Wireless MCU Technical Reference Manual. 8.9 Battery and Temperature Monitor A combined temperature and battery voltage monitor is available in the CC1352P7 device. The battery and temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and respond to changes in environmental conditions as needed. The module contains window comparators to interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can also be used to wake up the device from Standby mode through the Always-On (AON) event fabric. 8.10 µDMA The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data. Some features of the µDMA controller include the following (this is not an exhaustive list): • • • • Highly flexible and configurable channel operation of up to 32 channels Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral Data sizes of 8, 16, and 32 bits Ping-pong mode for continuous streaming of data 8.11 Debug The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 55 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 8.12 Power Management To minimize power consumption, the CC1352P7 supports a number of power modes and power management features (see Table 8-2). Table 8-2. Power Modes MODE SOFTWARE CONFIGURABLE POWER MODES ACTIVE IDLE STANDBY SHUTDOWN RESET PIN HELD CPU Active Off Off Off Off Flash On Available Off Off Off SRAM On On Retention Off Off Supply System On On Duty Cycled Off Off Register and CPU retention Full Full Partial No No SRAM retention Full Full Full No No 48 MHz high-speed clock (SCLK_HF) XOSC_HF or RCOSC_HF XOSC_HF or RCOSC_HF Off Off Off 2 MHz medium-speed clock (SCLK_MF) RCOSC_MF RCOSC_MF Available Off Off 32 kHz low-speed clock (SCLK_LF) XOSC_LF or RCOSC_LF XOSC_LF or RCOSC_LF XOSC_LF or RCOSC_LF Off Off Peripherals Available Available Off Off Off Sensor Controller Available Available Available Off Off Wake-up on RTC Available Available Available Off Off Wake-up on pin edge Available Available Available Available Off Wake-up on reset pin On On On On On Brownout detector (BOD) On On Duty Cycled Off Off Power-on reset (POR) On On On Off Off Watchdog timer (WDT) Available Available Paused Off Off In Active mode, the application system CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 8-2). In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event brings the processor back into active mode. In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode. In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in this mode is the latched I/O state and the flash memory contents. 56 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller independently of the system CPU. This means that the system CPU does not have to wake up, for example to perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller, control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be controlled by the system CPU. Note The power, RF and clock management for the CC1352P7 device require specific configuration and handling by software for optimized performance. This configuration and handling is implemented in the TI-provided drivers that are part of the SimpleLink™ CC13xx and CC26xx software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in source code. 8.13 Clock Systems The CC1352P7 device has several internal system clocks. The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation requires an external 48 MHz crystal. SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator (RCOSC_MF). SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digital IO. When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other devices, thereby reducing the overall system cost. 8.14 Network Processor Depending on the product configuration, the CC1352P7 device can function as a wireless network processor (WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the device's system CPU inside the device. In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CC1352P7 57 CC1352P7 www.ti.com SWRS251A – MAY 2021 – REVISED NOVEMBER 2021 9 Application, Implementation, and Layout Note Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware Configuration and PCB Design Considerations Application Report. For optimum RF performance, especially when using the high-power PA, it is important to accurately follow the reference design with respect to component values and layout. Failure to do so may lead to reduced RF performance due to balun mismatch. For the high-power PA, the amplitude- and phase balance through the balun must be