CC2340R5
SWRS272C – APRIL 2023 – REVISED JUNE 2023
CC2340R5 SimpleLink™ Bluetooth ® 5.3 Low Energy Wireless MCU
1 Features
•
Wireless microcontroller
•
•
•
•
•
•
•
•
•
Optimized 48-MHz Arm® Cortex®-M0+ processor
512 KB of in-system programmable flash
12 KB of ROM for bootloader and drivers
36 KB of ultra-low leakage SRAM. Full RAM
retention in standby mode
2.4 GHz RF transceiver compatible with
Bluetooth® 5.3 Low Energy
Integrated balun
Supports over-the-air upgrade (OTA)
Serial Wire Debug (SWD)
Low power consumption
•
•
MCU consumption:
– 2.6 mA active mode, CoreMark®
– 53 μA/MHz running CoreMark®
– < 710 nA standby mode, RTC, 36 KB RAM
– 150 nA shutdown mode, wake-up on pin
Radio Consumption:
– 5.3 mA RX
– 5.1 mA TX at 0 dBm
– < 11.0 mA TX at +8 dBm
Wireless protocol support
•
•
•
•
Bluetooth® 5.3 Low Energy
Zigbee® 1
SimpleLink™ TI 15.4-stack 1
Proprietary systems
High-performance radio
•
•
•
-102 dBm for Bluetooth® Low Energy 125 kbps
-96.5 dBm for Bluetooth® Low Energy 1 Mbps
Output power up to +8 dBm with temperature
compensation
•
•
•
•
•
•
•
3× 16-bit and 1× 24-bit general-purpose timers,
quadrature decode mode support
12-bit ADC, 1.2 Msps with external reference, 267
ksps with internal reference, up to 12 external ADC
inputs
1× low power comparator
1× UART
1× SPI
1× I2C
Real-time clock (RTC)
Integrated temperature and battery monitor
Watchdog timer
Security enablers
•
•
AES 128-bit cryptographic accelerator
Random number generator from on-chip analog
noise
Development tools and software
•
•
•
•
LP-EM-CC2340R5 LaunchPad Development Kit
SimpleLink™ CC23xx Software Development Kit
(SDK)
SmartRF™ Studio for simple radio configuration
SysConfig system configuration tool
Operating range
•
•
•
On-chip buck DC/DC converter
1.71-V to 3.8-V single supply voltage
Tj: -40 to +125°C
RoHS-compliant package
•
•
5-mm × 5-mm RKP QFN40 (26 GPIOs)
4-mm × 4-mm RGE QFN24 (12 GPIOs)
Regulatory compliance
•
Suitable for systems targeting compliance with
these standards:
– EN 300 328 (Europe)
– FCC CFR47 Part 15
– ARIB STD-T66 (Japan)
MCU peripherals
•
Up to 26 I/O Pads
– 2 IO pads SWD, muxed with GPIOs
– 2 IO pads LFXT, muxed with GPIOs
– Up to 22 DIOs (analog or digital IOs)
1
Available in a future SDK
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC2340R5
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SWRS272C – APRIL 2023 – REVISED JUNE 2023
•
2 Applications
•
•
Medical
– Home healthcare – blood glucose monitors,
blood pressure monitor, CPAP machine,
electronic thermometer
– Patient monitoring & diagnostics – medical
sensor patches
– Personal care & Fitness – electric toothbrush,
wearable fitness & activity monitor
Building automation
– Building security systems – motion detector,
electronic smart lock, door and window sensor,
garage door system, gateway
– HVAC – thermostat, wireless environmental
sensor
– Fire safety system – smoke and heat detector
– Video surveillance – IP network camera
•
•
•
•
Lighting
– LED luminaire
– Lighting Control – daylight sensor, lighting
sensor, wireless control
Factory automation and control
Retail automation & payment – Electronic point of
sale
– Electronic shelf label
Communication equipment
– Wired networking
– wireless LAN or Wi-Fi access points, edge
router
Personal electronics
– Connected peripherals – consumer wireless
module, pointing devices, keyboards and
keypads
– Gaming – electronic and robotic toys
– Wearables (non-medical) – smart trackers,
smart clothing
3 Description
The SimpleLink™ CC2340R5 device is a 2.4 GHz wireless microcontroller (MCU) targeting Bluetooth® 5.3 Low
Energy and Proprietary 2.4 GHz applications. The device is optimized for low-power wireless communication
with on-chip dual image Over the Air Download (OAD) support 2 in Building automation (wireless sensors,
lighting control, beacons), asset tracking, medical, retail EPOS (electronic point of sale), ESL (electronic shelf
label), and Personal electronics (toys, HID, stylus pens) markets. highlighted features of this device include:
• Support for Bluetooth ® 5 features: High Speed Mode (2 Mbps PHY), Long Range (LE Coded 125 kbps and
500 kbps PHYs), Privacy 1.2.1 and Channel Selection Algorithm #2, as well as backwards compatibility and
support for key features from the Bluetooth ® 4.2 and earlier Low Energy specifications.
• Fully-qualified Bluetooth ® 5.3 software protocol stack included with the SimpleLink™ CC23xx Software
Development Kit (SDK).
• Zigbee® protocol stack support in the SimpleLink™ CC23xx Software Development Kit (SDK) 2
• Ultra-low standby current less than 0.71 μA with RTC operational and full RAM retention that enables
significant battery life extension especially for applications with longer sleep intervals.
• Integrated balun for reduced Bill-of-Material (BOM) board layout
• Excellent radio sensitivity and robustness (selectivity and blocking) performance for Bluetooth ® Low Energy
(-102 dBm for 125 kbps LE Coded PHY, with integrated balun).
The CC2340R5 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth Low
Energy, Thread, Zigbee, Sub-1 GHz MCUs, and host MCUs that all share a common, easy-to-use development
environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the
SimpleLink™ platform enables you to add any combination of the portfolio’s devices into your design, allowing
100 percent code reuse when your design requirements change. For more information, visit SimpleLink™ MCU
platform.
2
2
Available in a future SDK
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SWRS272C – APRIL 2023 – REVISED JUNE 2023
Device Information
(1)
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
CC2340R52E0RGER
QFN24
4.00 mm × 4.00 mm
CC2340R52E0RKPR
QFN40
5.00 mm × 5.00 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section
12, or see the TI website.
4 Functional Block Diagram
Arm Cortex M0+ Processor
48 MHz
HFXT
48 MHz
HFOSC
DC/DC
POR
32.768 kHz
LFXT
32.768 kHz
LFOSC
Global LDO
BOD
System Buses
µDMA (8 channel)
ADC
Modem Accelerators
SWD
PWR & CLK Mgmt.
12kB System ROM
ADC
B
A
L
U
N
2.4 GHz
50 Ω
System Buses
512kB Flash
36kB SRAM
LNA
RF RAM
PA
Radio Digital
Digital PLL
2.4GHz Radio Transceiver
48 MHz
RTC
Timers
LGPT0-LGPT3
1x UART
12-bit ADC
1.2 Msps
WDT
SYSTIM
System Timer
1x SPI
Low Power
Comparator
Temperature
Sensor
1x I2C
Battery
Monitor
AES-128
IOMUX | up to 26 GPIOs
Figure 4-1. CC2340R5 Block Diagram
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SWRS272C – APRIL 2023 – REVISED JUNE 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Comparison......................................................... 5
7 Pin Configuration and Functions...................................6
7.1 Pin Diagram – RKP Package (Top View)....................6
7.2 Signal Descriptions – RKP Package...........................7
7.3 Connections for Unused Pins and Modules –
RKP Package................................................................ 8
7.4 Pin Diagram – RGE Package (Top View)................... 8
7.5 Signal Descriptions – RGE Package.......................... 9
7.6 Connections for Unused Pins and Modules –
RGE Package..............................................................10
7.7 RKP and RGE Peripheral Pin Mapping.....................11
7.8 RKP and RGE Peripheral Signal Descriptions..........16
8 Specifications................................................................ 21
8.1 Absolute Maximum Ratings...................................... 21
8.2 ESD Ratings............................................................. 21
8.3 Recommended Operating Conditions.......................21
8.4 DCDC........................................................................21
8.5 Global LDO (GLDO)..................................................21
8.6 Power Supply and Modules...................................... 22
8.7 Battery Monitor..........................................................22
8.8 Temperature Sensor................................................. 22
8.9 Power Consumption - Power Modes........................ 23
8.10 Power Consumption - Radio Modes....................... 24
8.11 Nonvolatile (Flash) Memory Characteristics........... 24
8.12 Thermal Resistance Characteristics....................... 24
8.13 RF Frequency Bands.............................................. 25
8.14 Bluetooth Low Energy - Receive (RX).................... 26
8.15 Bluetooth Low Energy - Transmit (TX)....................29
8.16 Proprietary Radio Modes........................................ 30
8.17 2.4 GHz RX/TX CW................................................ 31
8.18 Timing and Switching Characteristics..................... 31
8.19 Peripheral Characteristics.......................................33
9 Detailed Description......................................................42
9.1 Overview................................................................... 42
9.2 System CPU............................................................. 42
9.3 Radio (RF Core)........................................................43
9.4 Memory..................................................................... 43
9.5 Cryptography............................................................ 44
9.6 Timers....................................................................... 44
9.7 Serial Peripherals and I/O.........................................45
9.8 Battery and Temperature Monitor............................. 46
9.9 µDMA........................................................................ 46
9.10 Debug..................................................................... 46
9.11 Power Management................................................ 47
9.12 Clock Systems........................................................ 48
9.13 Network Processor..................................................48
10 Application, Implementation, and Layout................. 49
10.1 Reference Designs................................................. 49
10.2 Junction Temperature Calculation...........................50
11 Device and Documentation Support..........................51
11.1 Device Nomenclature..............................................51
11.2 Tools and Software..................................................51
11.3 Documentation Support.......................................... 54
11.4 Support Resources................................................. 54
11.5 Trademarks............................................................. 54
11.6 Electrostatic Discharge Caution.............................. 55
11.7 Glossary.................................................................. 55
12 Mechanical, Packaging, and Orderable
Information.................................................................... 56
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from April 31, 2023 to June 30, 2023 (from Revision B (April 2023) to Revision C
(June 2023))
Page
• Removed preview status for 4-mm × 4-mm RGE QFN24 package................................................................... 1
• Corrected links for applications.......................................................................................................................... 2
• Corrected pin pitch in pin diagram title............................................................................................................... 6
• Corrected pin pitch in pin diagram title............................................................................................................... 8
• Corrected signal name column for DIO19.........................................................................................................11
• Changed CDM ESD value to +/- 500 V in ESD Ratings................................................................................... 21
• Clarified that HFOSC tracks HFXT in Table 9-2 and is off in Standby.............................................................. 47
• Corrected temperature calculation example..................................................................................................... 50
4
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6 Device Comparison
X
CC1311R3
X
X
CC1311P3
X
X
X
7 X 7 mm VQFN (48)
X
5 X 5 mm VQFN (40)
RAM +
GPIO
Cache (KB)
4 X 4 mm VQFN (24)
+20 dBm PA
Multiprotocol
Thread
ZigBee
Bluetooth® LE
Sidewalk
X
FLASH
(KB)
5 X 5 mm VQFN (32)
X
PACKAGE SIZE
4 X 4 mm VQFN (32)
CC1310
Wi-SUN®
Wireless M-Bus
Device
2.4GHz Prop.
Sub-1 GHz Prop.
RADIO SUPPORT
32-128
16-20 + 8
10-30
X
352
32 + 8
22-30
352
32 + 8
26
X
352
80 + 8
30
X
704
144 + 8
30
X
X
X
CC1312R
X
X
X
CC1312R7
X
X
X
CC1352R
X
X
X
X
X
X
X
X
352
80 + 8
28
X
CC1352P
X
X
X
X
X
X
X
X
X
352
80 + 8
26
X
CC1352P7
X
X
X
X
X
X
X
X
X
704
144 + 8
26
X
X
X
X
512
36
12-26
X
CC2340R5
(1)
X
X
X
X
X
X
CC2640R2F
X
128
20 + 8
10-31
CC2642R
X
352
80 + 8
31
X
CC2642R-Q1
X
352
80 + 8
31
X
352
32 + 8
23-31
X
X
352
32 + 8
22-26
X
X
CC2651R3
X
X
X
CC2651P3
X
X
X
X
X
X
X
CC2652R
X
X
X
X
X
352
80 + 8
31
X
CC2652RB
X
X
X
X
X
352
80 + 8
31
X
CC2652R7
X
X
X
X
X
704
144 + 8
31
X
CC2652P
X
X
X
X
X
X
352
80 + 8
26
X
CC2652P7
X
X
X
X
X
X
704
144 + 8
26
X
CC2662R-Q1
X
352
80 + 8
31
X
(1)
ZigBee and Thread support enabled by future software update
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7 Pin Configuration and Functions
32 DIO6_A1
31 VDDS
34 VDDR
33 DIO7_A0
36 X48N
35 X48P
38 VDDS
37 NC
40 RFGND
39 ANT
7.1 Pin Diagram – RKP Package (Top View)
VDDR
1
30 DCDC
DIO8
2
29 DIO5_A2
DIO9
3
28 VDDD
DIO10
4
27 DIO4_X32N
DIO11
5
26 DIO3_X32P
DIO12
6
25 RSTN
DIO13
7
24 DIO2_A3
VDDS
8
23 DIO1_A4
DIO14
9
22 DIO0_A5
DIO24_A7 20
DIO22_A9 18
DIO23_A8 19
DIO21_A10 16
VDDS 17
DIO19 14
DIO20_A11 15
21 DIO25_A6
DIO16_SWDIO 11
DIO17_SWDCK 12
DIO18 13
DIO15 10
Figure 7-1. RKP (5-mm × 5-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:
•
•
•
•
•
•
Pin 6, DIO12
Pin 11, DIO16_SWDIO
Pin 12, DIO17_SWDCK
Pin 13, DIO18
Pin 14, DIO19
Pin 20, DIO24_A7
The following I/O pins marked in Figure 7-1 in italics have analog capabilities:
•
•
•
•
•
•
•
•
•
•
•
•
6
Pin 15, DIO20_A11
Pin 16, DIO21_A10
Pin 18, DIO22_A9
Pin 19, DIO23_A8
Pin 20, DIO24_A7
Pin 21, DIO25_A6
Pin 22, DIO0_A5
Pin 23, DIO1_A4
Pin 24, DIO2_A3
Pin 29, DIO5_A2
Pin 32, DIO6, A1
Pin 33, DIO7_A0
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7.2 Signal Descriptions – RKP Package
Table 7-1. Signal Descriptions – RKP Package
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
Ground – exposed ground pad(1)
EGP
—
—
GND
VDDR
1
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (3) (4)
DIO8
2
I/O
Digital
GPIO
DIO9
3
I/O
Digital
GPIO
DIO10
4
I/O
Digital
GPIO
DIO11
5
I/O
Digital
GPIO
DIO12
6
I/O
Digital
GPIO, high-drive capability
DIO13
7
I/O
Digital
GPIO
VDDS
8
—
Power
1.71-V to 3.8-V DIO supply(5)
DIO14
9
I/O
Digital
GPIO
DIO15
10
I/O
Digital
GPIO
DIO16_SWDIO
11
I/O
Digital
GPIO, SWD interface: mode select or SWDIO, high-drive capability
DIO17_SWDCK
12
I/O
Digital
GPIO, SWD interface: clock, high-drive capability
DIO18
13
I/O
Digital
GPIO, high-drive capability
DIO19
14
I/O
Digital
GPIO, high-drive capability
DIO20_A11
15
I/O
Digital or Analog
GPIO, analog capability
DIO21_A10
16
I/O
Digital or Analog
GPIO, analog capability
VDDS
17
—
Power
DIO22_A9
18
I/O
Digital or Analog
GPIO, analog capability
DIO23_A8
19
I/O
Digital or Analog
GPIO, analog capability
DIO24_A7
20
I/O
Digital or Analog
GPIO, Analog capability, high-drive capability
DIO25_A6
21
I/O
Digital or Analog
GPIO, analog capability
DIO0_A5
22
I/O
Digital or Analog
GPIO, analog capability
DIO1_A4
23
I/O
Digital or Analog
GPIO, analog capability
DIO2_A3
24
I/O
Digital or Analog
GPIO, analog capability
RSTN
25
I
Digital
DIO3_X32P
26
I/O
Digital or Analog
GPIO, 32-kHz crystal oscillator pin 1, Optional TCXO input
DIO4_X32N
27
I/O
Digital or Analog
GPIO, 32-kHz crystal oscillator pin 2
VDDD
28
—
Power
DIO5_A2
29
I/O
Digital or Analog
DCDC
30
—
Power
Switching node of internal DC/DC converter(5)
VDDS
31
—
Power
1.71-V to 3.8-V analog supply(5)
DIO6_A1
32
I/O
Digital or Analog
GPIO, analog capability
DIO7_A0
33
I/O
Digital or Analog
GPIO, analog capability
VDDR
34
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO. Connect an external 10 μF
decoupling capacitor.(2) (3) (4)
X48P
35
—
Analog
48-MHz crystal oscillator pin 1
X48N
36
—
Analog
48-MHz crystal oscillator pin 2
NC
37
—
—
VDDS
38
—
Power
ANT
39
I/O
RF
1.71-V to 3.8-V DIO supply(5)
Reset, active low. No internal pullup resistor
For decoupling of internal 1.28-V regulated core-supply. Connect
an external 1 μF decoupling capacitor.(2)
GPIO, analog capability
No Connect
1.71-V to 3.8-V analog supply(5)
2.4 GHz TX, RX
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Table 7-1. Signal Descriptions – RKP Package (continued)
PIN
NAME
RFGND
(1)
(2)
(3)
(4)
(5)
NO.
40
I/O
TYPE
DESCRIPTION
—
RFGND
RF Ground
EGP is the only non-RF ground connection for the device. Good electrical connection to PCB ground plane is required for proper
device operation.
Do not supply external circuitry from this pin.
VDDR pins 1 and 34 must be tied together on the PCB.
Output from internal DC/DC and LDO is trimmed to 1.5 V.
For more details, see the technical reference manual listed in Section 11.3.
7.3 Connections for Unused Pins and Modules – RKP Package
Table 7-2. Connections for Unused Pins – RKP Package
FUNCTION
SIGNAL NAME
GPIO (digital)
DIOn
ACCEPTABLE PRACTICE(1)
PREFERRED
PRACTICE(1)
2–7
9–10
13–14
NC, GND, or VDDS
NC
11
NC, GND, or VDDS
GND or VDDS
12
NC, GND, or VDDS
GND or VDDS
15–16
18–24
29
32–33
NC, GND, or VDDS
NC
NC or GND
NC
DIO16_SWDIO
SWD
DIO17_SWDCK
GPIO (digital or analog)
32.768-kHz crystal
DC/DC converter(2)
(1)
(2)
PIN NUMBER
DIOn_Am
DIO3_X32P
26
DIO4_X32N
27
DCDC
30
NC
NC
VDDS
8, 17, 31, 38
VDDS
VDDS
NC = No connect
When the DC/DC converter is not used, the inductor between DCDC and VDDR can be removed. VDDR must still be connected and
the 10 μF DCDC capacitor must be kept on the VDDR net.
20 VDDR
19 DIO6_A1
22 X48N
21 X48P
24 VDDS
23 GND
7.4 Pin Diagram – RGE Package (Top View)
16 VDDD
DIO11
4
15 DIO4_X32N
DIO12
5
14 DIO3_X32P
DIO13
6
13 RSTN
DIO20_A11
DIO24_A7 12
17 DCDC
3
9
DIO21_A10 10
VDDS 11
2
DIO8
8
VDDR
7
18 VDDS
DIO16_SWDIO
1
DIO17_SWDCK
ANT
Figure 7-2. RGE (4-mm × 4-mm) Pinout, 0.5-mm Pitch(Top View)
8
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The following I/O pins marked in Figure 7-2 in bold have high-drive capabilities:
•
•
•
•
Pin 5, DIO12
Pin 7, DIO16_SWDIO
Pin 8, DIO17_SWDCK
Pin 12, DIO24_A7
The following I/O pins marked in Figure 7-2 in italics have analog capabilities:
•
•
•
•
Pin 9, DIO20_A11
Pin 10, DIO21_A10
Pin 12, DIO24_A7
Pin 19, DIO6_A1
7.5 Signal Descriptions – RGE Package
Table 7-3. Signal Descriptions – RGE Package
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
Ground – exposed ground pad(1)
EGP
—
—
GND
ANT
1
I/O
RF
VDDR
2
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (3) (4)
DIO8
3
I/O
Digital
GPIO
DIO11
4
I/O
Digital
GPIO
DIO12
5
I/O
Digital
GPIO, high-drive capability
DIO13
6
I/O
Digital
GPIO
DIO16_SWDIO
7
I/O
Digital
GPIO, SWD interface: mode select or SWDIO, high-drive capability
DIO17_SWDCK
8
I/O
Digital
GPIO, SWD interface: clock, high-drive capability
DIO20_A11
9
I/O
Digital or Analog
GPIO, analog capability
DIO21_A10
10
I/O
Digital or Analog
GPIO, analog capability
VDDS
11
—
Power
DIO24_A7
12
I/O
Digital or Analog
GPIO, Analog capability, high-drive capability
RSTN
13
I
Digital
Reset, active low. No internal pullup resistor
DIO3_X32P
14
I/O
Digital or Analog
GPIO, 32-kHz crystal oscillator pin 1, Optional TCXO input
DIO4_X32N
15
I/O
Digital or Analog
GPIO, 32-kHz crystal oscillator pin 2
VDDD
16
—
Power
For decoupling of internal 1.28-V regulated core-supply. Connect
an external 1 μF decoupling capacitor.(2)
DCDC
17
—
Power
Switching node of internal DC/DC converter(5)
VDDS
18
—
Power
1.71-V to 3.8-V analog supply(5)
DIO6_A1
19
I/O
Digital or Analog
VDDR
20
—
Power
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO. Connect an external 10 μF
decoupling capacitor.(2) (3) (4)
X48P
21
—
Analog
48-MHz crystal oscillator pin 1
X48N
22
—
Analog
48-MHz crystal oscillator pin 2
GND
23
—
GND
VDDS
24
—
Power
(1)
(2)
(3)
(4)
(5)
2.4 GHz TX, RX
1.71-V to 3.8-V DIO supply(5)
GPIO, analog capability
Ground
1.71-V to 3.8-V analog supply(5)
EGP is the only non-RF ground connection for the device. Good electrical connection to PCB ground plane is required for proper
device operation.
Do not supply external circuitry from this pin.
VDDR pins 2 and 20 must be tied together on the PCB.
Output from internal DC/DC and LDO is trimmed to 1.5 V.
For more details, see technical reference manual listed in Section 11.3.
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7.6 Connections for Unused Pins and Modules – RGE Package
Table 7-4. Connections for Unused Pins – RGE Package
PIN NUMBER
ACCEPTABLE PRACTICE(1)
PREFERRED
PRACTICE(1)
3–6
NC, GND, or VDDS
NC
DIO16_SWDIO
7
NC, GND, or VDDS
GND or VDDS
DIO17_SWDCK
8
NC, GND, or VDDS
GND or VDDS
9–10
12
19
NC, GND, or VDDS
NC
NC or GND
NC
FUNCTION
SIGNAL NAME
GPIO (digital)
DIOn
SWD
GPIO (digital or analog)
32.768-kHz crystal
DC/DC converter(2)
(1)
(2)
10
DIOn_Am
DIO3_X32P
14
DIO4_X32N
15
DCDC
17
NC
NC
VDDS
11, 18, 24
VDDS
VDDS
NC = No connect
When the DC/DC converter is not used, the inductor between DCDC and VDDR can be removed. VDDR must still be connected and
the 10 μF DCDC capacitor must be kept on the VDDR net.
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7.7 RKP and RGE Peripheral Pin Mapping
Table 7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping
PIN NO.
QFN24
QFN40
2
1
PIN NAME
SIGNAL NAME
SIGNAL TYPE(1)
PIN MUX ENCODING
SIGNAL DIRECTION
VDDR
VDDR
—
N/A
N/A
GPIO8
0
I/O
SPI0SCLK
1
I/O
2
O
3
O
I2C0SDA
4
I/O
T0C0N
5
O
DTB3
7
O
GPIO9
0
I/O
UART0RTS
3
—
—
2
3
4
DIO8
DIO9
DIO10
T1C0N
T3C0
I/O
1
O
LRFD3
3
O
GPIO10
0
I/O
LPCO
1
O
T2PE
I/O
I/O
2
O
T3C0N
3
O
GPIO11
0
I/O
SPI0CSN
1
I/O
2
O
3
O
T1C2N
4
5
5
6
DIO11
DIO12
T0C0
I/O
LRFD0
4
O
SPI0POCI
5
I/O
DTB9
7
O
GPIO12
0
I/O
SPI0POCI
1
I/O
SPI0PICO
2
I/O
UART0RXD
I/O
3
I
T1C1
4
O
I2C0SDA
5
I/O
DTB13
7
O
GPIO13
0
I/O
SPI0POCI
1
I/O
2
I/O
3
O
T0C0N
4
O
T1F
5
O
DTB4
7
O
N/A
N/A
0
I/O
1
O
2
O
LRFD5
3
O
T1F
4
O
SPI0PICO
6
—
7
8
DIO13
VDDS
UART0TXD
VDDS
I/O
—
GPIO14
T3C2
—
9
DIO14
T1C2N
I/O
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Table 7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)
PIN NO.
QFN24
—
QFN40
10
PIN NAME
DIO15
SIGNAL NAME
SIGNAL TYPE(1)
PIN MUX ENCODING
SIGNAL DIRECTION
GPIO15
0
I/O
UART0RXD
1
I
T2C0N
I/O
2
O
CKMIN
3
I
GPIO16
0
I/O
SPI0PICO
1
I/O
UART0RXD
7
8
—
—
9
12
11
12
13
14
15
DIO16_SWD
IO
DIO17_SWD
CK
DIO18
DIO19
DIO20_A11
I2C0SDA
I/O
2
I
3
I/O
T1C2
4
O
T1C0N
5
O
DTB10
7
O
GPIO17
0
I/O
SPI0SCLK
1
I/O
UART0TXD
2
O
I2C0SCL
3
I/O
T1C1N
I/O
4
O
T0C2
5
O
DTB11
7
O
GPIO18
0
I/O
T3C0
1
O
2
O
3
O
SPI0SCLK
4
I/O
DTB12
7
O
GPIO19
0
I/O
T3C1
1
O
LPCO
UART0TXD
T2PE
I/O
2
O
SPI0PICO
4
I/O
DTB0
7
O
GPIO20
0
I/O
LPCO
1
O
UART0TXD
2
O
UART0RXD
3
I
T1C0
I/O
I/O
4
O
SPI0POCI
5
I/O
ADC11
6
I
DTB14
7
O
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Table 7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)
PIN NO.
QFN24
10
11
—
—
12
—
QFN40
16
17
18
19
20
21
PIN NAME
DIO21_A10
VDDS
DIO22_A9
DIO23_A8
DIO24_A7
DIO25_A6
SIGNAL NAME
SIGNAL TYPE(1)
22
DIO0_A5
GPIO21
0
I/O
1
I
T1C1N
2
O
T0C1
3
O
SPI0POCI
I/O
4
I/O
LRFD1
5
O
ADC10/LPC+
6
I
DTB15
7
O
N/A
N/A
GPIO22
VDDS
0
I/O
T2C0
1
O
UART0RXD
2
I
T3C1N
—
I/O
3
O
ADC9
6
I
DTB1
7
O
GPIO23
0
I/O
1
O
3
O
T2C1
T3C2N
I/O
ADC8/LPC+/LPC-
6
I
GPIO24
0
I/O
SPI0SCLK
1
I/O
T1C0
2
O
3
O
4
O
T3C0
T0PE
I/O
I2C0SCL
5
I/O
ADC7/LPC+/LPC-
6
I
DTB5
7
O
GPIO25
0
I/O
SPI0POCI
1
I/O
I2C0SCL
2
I/O
T2C2N
I/O
3
O
ADC6
6
I
GPIO0
0
I/O
1
I/O
2
I/O
I2C0SDA
I/O
T3C2
3
O
ADC5
6
I
GPIO1
0
I/O
T3C1
1
O
2
O
3
O
UART0RTS
4
O
ADC4
5
I
DTB2
6
O
LRFD7
—
23
DIO1_A4
SIGNAL DIRECTION
UART0CTS
SPI0CSN
—
PIN MUX ENCODING
T1F
I/O
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Table 7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)
PIN NO.
QFN24
—
QFN40
24
PIN NAME
DIO2_A3
SIGNAL NAME
SIGNAL TYPE(1)
PIN MUX ENCODING
SIGNAL DIRECTION
GPIO2
0
I/O
T0PE
1
O
2
O
3
I
T2C1N
I/O
UART0CTS
ADC3
13
14
15
16
25
26
27
28
RTSN
DIO3_X32P
DIO4_X32N
VDDD
6
I
N/A
N/A
GPIO3
0
I/O
LFCI
1
I
T0C1N
2
O
LRFD0
3
O
RSTN
T3C1
—
I/O
4
O
T1C2
5
O
LFXT_P
6
I
DTB7
7
O
GPIO4
0
I/O
T0C2N
1
O
UART0TXD
2
O
LRFD1
3
O
SPI0PICO
4
I/O
T0C2
5
O
LFXT_N
6
I
DTB8
7
O
N/A
N/A
0
I/O
1
O
3
O
VDDD
—
GPIO5
T2C2
—
29
DIO5_A2
6
I
17
30
DCDC
DCDC
—
N/A
N/A
18
31
VDDS
VDDS
—
N/A
N/A
LRFD6
I/O
ADC2
19
—
32
33
DIO6_A1
DIO7_A0
GPIO6
0
I/O
SPI0CSN
1
I/O
I2C0SCL
2
I/O
T1C2
3
O
LRFD2
I/O
4
O
UART0TXD
5
O
ADC1/AREF+
6
I
DTB6
7
O
GPIO7
0
I/O
T3C1
1
O
3
O
6
I
LRFD4
I/O
ADC0/AREF-
14
20
34
VDDR
VDDR
—
N/A
N/A
21
35
X48P
X48P
—
N/A
N/A
22
36
X48N
X48N
—
N/A
N/A
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Table 7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)
PIN NO.
QFN24
QFN40
PIN NAME
SIGNAL NAME
SIGNAL TYPE(1)
PIN MUX ENCODING
SIGNAL DIRECTION
—
37
NC
NC
—
N/A
N/A
24
38
VDDS
VDDS
—
N/A
N/A
1
39
ANT
ANT
—
N/A
N/A
—
40
RFGND
RFGND
—
N/A
N/A
—
N/A
N/A
GND_TAB
(1)
Signal Types: I = Input, O = Output, I/O = Input or Output.
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7.8 RKP and RGE Peripheral Signal Descriptions
Table 7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions
FUNCTION
ADC
ADC Reference
Clock
Comparator
SIGNAL NAME
PIN
QFN24 QFN40 TYPE
SIGNAL
DIRECTION
DESCRIPTION
ADC11
9
15
HP ADC channel 11 input
ADC10
10
16
HP ADC channel 10 input
ADC9
—
18
HP ADC channel 9 input
ADC8
—
19
HP ADC channel 8 input
ADC7
12
20
HP ADC channel 7 input
ADC6
—
21
ADC5
—
22
ADC4
—
23
ADC channel 4 input
ADC3
—
24
ADC channel 3 input
ADC2
—
29
ADC channel 2 input
ADC1
19
32
HP ADC channel 1 input
ADC0
—
33
HP ADC channel 0 input
AREF+
19
32
AREF-
—
33
X32P
14
X32N
X48P
I/O
I
ADC channel 6 input
ADC channel 5 input
ADC external voltage reference, positive terminal
I/O
I
26
I/O
I
32-kHz crystal oscillator pin 1, Optional TCXO input
15
27
I/O
I
32-kHz crystal oscillator pin 2
21
35
—
I
48-MHz crystal oscillator pin 1
X48N
22
36
—
I
48-MHz crystal oscillator pin 2
CKMIN
—
10
I/O
I
TDC or HFOSC tracking loop reference clock input
LFCI
14
26
I/O
I
Low frequency clock input (LFXT bypass clock from
pin)
I/O
O
Low power comparator output
LPCO
LPC+
Comparator
Input
LPC-
16
Pin No.
—
4
—
13
9
15
10
16
—
19
12
20
—
19
12
20
ADC external voltage reference, negative terminal
Low power comparator positive input terminal
I/O
I
Lower power comparator negative input terminal
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Table 7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)
FUNCTION
Digital Test Bus
GPIO
SIGNAL NAME
Pin No.
PIN
QFN24 QFN40 TYPE
SIGNAL
DIRECTION
DESCRIPTION
DTB3
3
2
Digital test bus output 3
DTB9
4
5
Digital test bus output 9
DTB0
—
14
Digital test bus output 0
DTB4
6
7
Digital test bus output 4
DTB10
7
11
Digital test bus output 10
DTB11
8
12
Digital test bus output 11
DTB12
—
13
Digital test bus output 12
DTB13
5
6
DTB1
—
18
DTB2
—
23
Digital test bus output 2
DTB14
9
15
Digital test bus output 14
DTB5
12
20
Digital test bus output 5
DTB15
10
16
Digitial test bus output 15
DTB7
14
26
Digital test bus output 7
DTB8
15
27
Digital test bus output 8
DTB6
19
32
Digital test bus output 6
GPIO8
3
2
GPIO9
—
3
GPIO10
—
4
GPIO11
4
5
GPIO12
5
6
GPIO13
6
7
GPIO14
—
9
GPIO15
—
10
GPIO16
7
11
GPIO17
8
12
GPIO18
—
13
GPIO19
—
14
GPIO20
9
15
GPIO21
10
16
GPIO22
—
18
GPIO23
—
19
GPIO24
12
20
GPIO25
—
21
GPIO0
—
22
GPIO1
—
23
GPIO2
—
24
GPIO3
14
26
GPIO4
15
27
GPIO5
—
29
GPIO6
19
32
GPIO7
—
33
I/O
I/O
O
I/O
Digital test bus output 13
Digital test bus output 1
General-purpose input or output
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Table 7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
SIGNAL
DIRECTION
DESCRIPTION
8
12
12
20
—
21
19
32
3
2
5
6
7
11
—
22
—
3
4
5
14
26
—
9
10
16
15
27
LRFD7
—
23
LRF digital output 7
LRFD6
—
29
LRF digital output 6
LRFD2
19
32
LRF digital output 2
LRFD4
—
33
LRF digital output 4
I2C0SCL
I2C
I2C0SDA
LRFD3
LRFD0
LRFD5
LRF Digital
Output
Pin No.
PIN
QFN24 QFN40 TYPE
LRFD1
VDDR
2
1
20
34
I/O
I/O
I2C clock data
I/O
I/O
I2C data
LRF digital ouptut 3
LRF digital output 0
LRF digital output 5
I/O
O
LRF digital output 1
—
—
Internal supply
—
—
1.71-V to 3.8V DIO supply
—
8
11
17
18
31
24
38
VDDD
16
28
—
—
For decoupling of internal 1.28-V regulated coresupply.
DCDC
17
30
—
—
Switching node of internal DC/DC converter
Reset
RSTN
13
25
—
—
Global main device reset (active low)
RF
ANT
1
39
RF Ground
RFGND
—
40
Power
18
VDDS
50 ohm RF port
—
—
RF Ground reference
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Table 7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
SPI0SCLK
SPI0POCI
SPI
SPI0CSN
SPI0PICO
SWD
3
2
8
12
—
13
12
20
4
5
5
6
6
7
9
15
10
16
—
21
4
5
—
22
19
32
5
6
6
7
7
11
—
14
15
27
SIGNAL
DIRECTION
DESCRIPTION
I/O
I/O
SPI clock
I/O
I/O
SPI POCI
I/O
I/O
SPI chip select
I/O
I/O
SPI PICO
SWDIO
7
11
I/O
I/O
JTAG/SWD TCK. Reset default pinout.
SWDCK
8
12
I/O
I
JTAG/SWD TMS. Reset default pinout.
T0C0
4
5
T0C1
10
16
T0C2
T1C0
T1C1
T1C2
Timers Capture/
Compare
Pin No.
PIN
QFN24 QFN40 TYPE
8
12
15
27
9
15
12
20
5
6
7
11
14
26
19
32
T2C0
—
18
T2C1
—
19
T2C2
—
29
T3C0
T3C1
T3C2
—
3
—
13
12
20
—
14
—
23
14
26
—
33
—
9
—
22
Capture/compare Output-0 from Timer-0
I/O
I/O
Capture/compare Output-1 from Timer-0
Capture/compare Output-2 from Timer-0
Capture/compare Output-0 from Timer-1
I/O
I/O
Capture/compare Output-1 from Timer-1
Capture/compare Output-2 from Timer-1
Capture/compare Output-0 from Timer-2
I/O
I/O
Capture/compare Output-1 from Timer-2
Capture/compare Output-2 from Timer-2
Capture/compare Output-0 from Timer-3
I/O
I/O
Capture/compare Output-1 from Timer-3
Capture/compare Output-2 from Timer-3
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Table 7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
Pin No.
PIN
QFN24 QFN40 TYPE
3
2
6
7
T0C1N
14
26
T0C2N
15
27
T0C0N
T1C0N
T1C1N
3
2
7
11
8
12
10
16
SIGNAL
DIRECTION
DESCRIPTION
Complementary compare/PWM Output-0 from
Timer-0
I/O
O
Complementary compare/PWM Output-1 from
Timer-0
Complementary compare/PWM Output-2 from
Timer-0
Complementary compare/PWM Output-0 from
Timer-1
I/O
O
Complementary compare/PWM Output-1 from
Timer-1
Timers Complementary T1C2N
Capture/
Compare
T2C0N
4
5
—
9
—
10
T2C1N
—
24
T2C2N
—
21
Complementary compare/PWM Output-2 from
Timer-2
T3C0N
—
4
Complementary compare/PWM Output-0 from
Timer-3
T3C1N
—
18
T3C2N
—
19
6
7
T1F
—
9
—
23
—
4
—
14
12
20
—
24
6
7
Timers - Fault
input
T2PE
Timers Prescaler Event
T0PE
UART0TXD
UART
UART0RXD
UART0CTS
UART0RTS
20
8
12
—
13
9
15
15
27
19
32
5
6
—
10
7
11
9
15
—
18
10
16
—
24
3
2
—
23
Complementary compare/PWM Output-2 from
Timer-1
Complementary compare/PWM Output-0 from
Timer-2
I/O
I/O
O
O
Complementary compare/PWM Output-1 from
Timer-2
Complementary compare/PWM Output-1 from
Timer-3
Complementary compare/PWM Output-2 from
Timer-3
I/O
I
Fault input for Timer-1
I/O
O
Prescaler event ouput from Timer-2
I/O
O
Prescaler eveny ouput from Timer-0
I/O
O
UART0 TX data
I/O
I
UART0 RX data
I/O
I
UART0 clear-to-send input (active low)
I/O
O
UART0 request-to-send (active low)
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
VDDS
MIN
MAX
–0.3
4.1
V
pin(3)
–0.3
VDDS + 0.3, max 4.1
V
Voltage on crystal oscillator pins X48P and X48N
–0.3
1.24
V
0
VDDS
Supply voltage
Voltage on any digital
Vin_adc
Voltage on ADC input
Input level, RF pins
Tstg
(1)
(2)
(3)
5
Storage temperature
–40
UNIT
V
dBm
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground, unless otherwise noted.
Including analog capable DIOs.
8.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
All pins
±1000
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
All pins
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Operating ambient temperature(1) (2)
–40
125
°C
Operating junction temperature(1) (2)
–40
125
°C
Operating supply voltage (VDDS)
1.71
3.8
V
Rising supply voltage slew rate
0
100
mV/µs
Falling supply voltage slew rate(3)
0
1
mV/µs
(1)
(2)
(3)
Operation at or near maximum operating temperature for extended durations will result in a reduction in lifetime.
For thermal resistance details, refer to Thermal Resistance Characteristics table in this document.
For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 10-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
8.4 DCDC
When measured on the CC2340R5 reference design with Tc = 25 °C and DCDC enabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
VDDS supply voltage for DCDC operation (1) (2)
(1)
(2)
MIN
TYP
MAX
2.2
3.0
3.8
UNIT
V
When the supply voltage drops below the DCDC operation min voltage, the device automatically transitions to use GLDO regulator
on-chip.
A 10uH and 10uF load capacitor are required on the VDDR voltage rail. They should be placed close to the DCDC output pin.
8.5 Global LDO (GLDO)
When measured on the CC2340R5 reference design with Tc = 25 °C.
PARAMETER
TEST CONDITIONS
VDDS supply voltage for GLDO operation (1)
(1)
MIN
TYP
MAX
1.71
3.0
3.8
UNIT
V
A 10 µF capacitor is recommended at VDDR pin.
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8.6 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDDS_BOD
Untrimmed brownout rising threshold
Before initial boot (1)
1.67
V
Trimmed brownout rising threshold (1)
1.68
V
Trimmed brownout falling threshold (1)
1.67
V
1.5
V
1.45
V
POR
power-on reset power-up level
power-on reset power-down level
(1)
Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RSTN pin.
8.7 Battery Monitor
Measured on the CC2340R5 reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
22
Range
1.7
Accuracy
mV
3.8
VDDS = 3.0 V
UNIT
30
V
mV
8.8 Temperature Sensor
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Accuracy
(1)
22
TEST CONDITIONS
-40 °C to 85 °C
MIN
TYP
±10
(1)
MAX
UNIT
°C
Raw output from register.
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8.9 Power Consumption - Power Modes
When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, DCDC enabled, GLDO disabled, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption with DCDC
Icore
Active
MCU running CoreMark from Flash at 48 MHz
2.6
mA
Icore
Active
MCU running CoreMark from Flash at 48MHz
53
µA / MHz
Icore
Idle
Supply Systems and RAM powered, flash disabled, DMA disabled
780
µA
Icore
Idle
Supply Systems and RAM powered, flash disabled, DMA enabled
810
µA
Icore
Idle
Supply Systems and RAM powered, flash enabled, DMA disabled
1100
µA
Icore
Idle
Supply Systems and RAM powered, flash enabled, DMA enabled
1200
µA
Icore
Standby
RTC running, 36kB RAM retention
LFOSC, DCDC recharge current setting (ipeak = 1)
0.71
µA
Icore
Standby
0.74
µA
RTC running, 36kB RAM retention
LFXT, DCDC recharge current setting (ipeak = 1)
Core Current consumption with GLDO
Icore
Active
MCU running CoreMark from Flash at 48 MHz
4.1
mA
Icore
Idle
Supply Systems and RAM powered, flash disabled, DMA disabled
1170
µA
Icore
Idle
Supply Systems and RAM powered, flash disabled, DMA enabled
1230
µA
Icore
Idle
Supply Systems and RAM powered, flash enabled, DMA disabled
1490
µA
Icore
Idle
Supply Systems and RAM powered, flash enabled, DMA enabled
1665
µA
Icore
Standby
RTC running, 36kB RAM retention
LFOSC, default GLDO recharge current setting
1.1
µA
Icore
Standby
RTC running, 36kB RAM retention
LFXT default GLDO recharge current setting
1.15
µA
Reset, Shutdown Current Consumption
Icore
Reset
Reset. RSTN pin asserted or VDDS below power-on-reset threshold
150
nA
Icore
Shutdown
Shutdown measured in steady state. No clocks running, no retention, IO
wakeup enabled
150
nA
Peripheral Current Consumption
Iperi
RF
Delta current, clock enabled, RF subsystem idle
40
µA
Iperi
Timers
Delta current with clock enabled, module is idle, one LGPT timer
2.4
µA
Iperi
I2C
Delta current with clock enabled, module is idle
10.6
µA
Iperi
SPI
Delta current with clock enabled, module is idle
3.4
µA
Iperi
UART
Delta current with clock enabled, module is idle
24.5
µA
Iperi
CRYPTO (AES)
Delta current with clock enabled, module is idle
3.8
µA
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8.10 Power Consumption - Radio Modes
When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V with DCDC enabled unless otherwise
noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
5.3
mA
9
mA
(1)
IRX
Radio receive current
2440 MHz, 1 Mbps, GFSK, system bus off
IRX
Radio receive current
2440 MHz, 1 Mbps, GFSK, DCDC OFF, system bus off (1)
Radio transmit current
-8 dBm output power setting
2440 MHz system bus off (1)
4.0
mA
Radio transmit current
0 dBm output power setting
2440 MHz system bus off (1)
5.1
mA
Radio transmit current
0 dBm output power setting
2440 MHz DCDC OFF, system bus off (1)
8.8
mA
Radio transmit current
+4 dBm output power setting
2440 MHz system bus off (1)
7.7
mA
Radio transmit current
+6 dBm output power setting
2440 MHz system bus off (1)
8.9
mA
Radio transmit current
+8 dBm output power setting
2440 MHz system bus off (1)
10.7
mA
Radio transmit current
+8 dBm output power setting
2440 MHz DCDC OFF, system bus off (1)
19
mA
ITX
ITX
ITX
ITX
ITX
ITX
ITX
(1)
System bus off refers to device idle mode, DMA disabled, flash disabled
8.11 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Flash sector size
TYP
MAX
2
UNIT
KB
Supported flash erase cycles before failure, full bank(1) (2)
30
k Cycles
Supported flash erase cycles before failure, single sector(3)
60
k Cycles
Maximum number of write operations per row before sector
erase(4)
83
Write
Operations
Flash retention
105 °C
11.4
Flash retention
125 °C
10
Flash sector erase current
Average delta current
1.2
Flash sector erase time(5)
0 erase cycles
2.2
ms
Flash write current
Average delta current, full sector at a time
1.7
mA
Flash write time(5)
full sector at a time, 0 erase cycles
7.7
µs
(1)
(2)
(3)
(4)
(5)
Years
Years
mA
A full bank erase is counted as a single erase cycle on each sector
Aborting flash during erase or program modes is not a safe operation.
Up to 16 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum
per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
This number is dependent on Flash aging and increases over time and erase cycles
8.12 Thermal Resistance Characteristics
PACKAGE
THERMAL
METRIC
THERMAL METRIC
RKP
(VQFN)
RGE
(VQFN)
UNIT (1)
40 PINS
24 PINS
RθJA
Junction-to-ambient thermal resistance
31.8
40.1
℃/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.1
30.5
℃/W
RθJB
Junction-to-board thermal resistance
12.7
17.2
℃/W
ψJT
Junction-to-top characterization parameter
0.3
0.4
℃/W
ψJB
Junction-to-board characterization parameter
12.7
17.1
℃/W
24
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PACKAGE
THERMAL
METRIC
RθJC(bot)
(1)
THERMAL METRIC
RKP
(VQFN)
RGE
(VQFN)
40 PINS
24 PINS
3.3
3.4
Junction-to-case (bottom) thermal resistance
UNIT (1)
℃/W
°C/W = degrees Celsius per watt.
8.13 RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
Frequency bands
2360
TYP
MAX
UNIT
2510
MHz
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8.14 Bluetooth Low Energy - Receive (RX)
When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125 kbps (LE Coded)
Receiver sensitivity
BER = 10–3
Receiver saturation
BER =
10–3
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Data rate error tolerance
–102
dBm
5
dBm
(1)
kHz
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–90 / 90) (1)
ppm
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (255-byte packets)
> (–90 / 90) (1)
ppm
Co-channel rejection(2)
Wanted signal at –79 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±1 MHz(2)
> (–122/ 122)
–6
dB
Wanted signal at –79 dBm, modulated interferer at ±1
MHz, BER = 10–3
9 / 5 (3)
dB
Selectivity, ±2 MHz(2)
Wanted signal at –79 dBm, modulated interferer at ±2
MHz, BER = 10–3
44 / 31 (3)
dB
Selectivity, ±3 MHz(2)
Wanted signal at –79 dBm, modulated interferer at ±3
MHz, BER = 10–3
47 / 42 (3)
dB
Selectivity, ±4 MHz(2)
Wanted signal at –79 dBm, modulated interferer at ±4
MHz, BER = 10–3
49 / 45 (3)
dB
Selectivity, ±6 MHz(2)
Wanted signal at –79 dBm, modulated interferer at ≥ ±6
MHz, BER = 10–3
52 / 48 (3)
dB
Selectivity, ±7 MHz
Wanted signal at –79 dBm, modulated interferer at ≥ ±7
MHz, BER = 10–3
54 / 49 (3)
dB
Selectivity, Image frequency(2)
Wanted signal at –79 dBm, modulated interferer at image
frequency, BER = 10–3
31
dB
Selectivity, Image frequency ±1
MHz(2)
Note that Image frequency + 1 MHz is the Co- channel
–1 MHz. Wanted signal at –79 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
5 / 42 (3)
dB
500 kbps (LE Coded)
Receiver sensitivity
BER = 10–3
–99
dBm
Receiver saturation
BER = 10–3
5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
(1)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–90/ 90) (1)
ppm
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (255-byte packets)
> (–90 / 90) (1)
ppm
Co-channel rejection(2)
Wanted signal at –72 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±1 MHz(2)
> (–122 / 122)
–4.5
dB
Wanted signal at –72 dBm, modulated interferer at ±1
MHz, BER = 10–3
9 / 5 (3)
dB
Selectivity, ±2 MHz(2)
Wanted signal at –72 dBm, modulated interferer at ±2
MHz, BER = 10–3
42 / 31 (3)
dB
Selectivity, ±3 MHz(2)
Wanted signal at –72 dBm, modulated interferer at ±3
MHz, BER = 10–3
45 / 41 (3)
dB
Selectivity, ±4 MHz(2)
Wanted signal at –72 dBm, modulated interferer at ±4
MHz, BER = 10–3
46 / 42 (3)
dB
Selectivity, ±6 MHz(2)
Wanted signal at –72 dBm, modulated interferer at ≥ ±6
MHz, BER = 10–3
50 / 45 (3)
dB
Selectivity, ±7 MHz
Wanted signal at –72 dBm, modulated interferer at ≥ ±7
MHz, BER = 10–3
51 / 46 (3)
dB
Selectivity, Image frequency(2)
Wanted signal at –72 dBm, modulated interferer at image
frequency, BER = 10–3
31
dB
Selectivity, Image frequency ±1
MHz(2)
Note that Image frequency + 1 MHz is the Co- channel
–1 MHz. Wanted signal at –72 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
5 / 41 (3)
dB
26
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When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1 Mbps (LE 1M)
Receiver sensitivity
BER = 10–3
–96.5
dBm
Receiver saturation
BER = 10–3
5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–225 /225) (1)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–750 / 750) (1)
ppm
Co-channel rejection(2)
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10–3
Selectivity, ±1 MHz(2)
–6
dB
Wanted signal at –67 dBm, modulated interferer at ±1
MHz, BER = 10–3
7 / 5 (3)
dB
Selectivity, ±2 MHz(2)
Wanted signal at –67 dBm, modulated interferer at ±2
MHz,BER = 10–3
39 / 28 (3)
dB
Selectivity, ±3 MHz(2)
Wanted signal at –67 dBm, modulated interferer at ±3
MHz, BER = 10–3
44 / 38 (3)
dB
Selectivity, ±4 MHz(2)
Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3
47 / 35 (3)
dB
Selectivity, ±5 MHz or more(2)
Wanted signal at –67 dBm, modulated interferer at ≥ ±5
MHz, BER = 10–3
40
dB
Selectivity, image frequency(2)
Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3
28
dB
Selectivity, image frequency
±1 MHz(2)
Note that Image frequency + 1 MHz is the Co- channel
–1 MHz. Wanted signal at –67 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
5 / 38 (3)
dB
Out-of-band blocking(4)
30 MHz to 2000 MHz
–10
dBm
Out-of-band blocking
2003 MHz to 2399 MHz
–10
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
–10
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz (excluding VCO frequency)
–2
dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2405 and 2408 MHz respectively, at the given power
level
–37
dBm
Spurious emissions,
30 to 1000 MHz(5)
Measurement in a 50-Ω single-ended load.
< –59
dBm
Spurious emissions,
1 to 12.75 GHz(5)
Measurement in a 50-Ω single-ended load.
< –47
dBm
RSSI dynamic range (6)
70
dB
RSSI accuracy
±4
dB
RSSI resolution
1
dB
2 Mbps (LE 2M)
Receiver sensitivity
Measured at SMA connector, BER = 10–3
–92
dBm
Receiver saturation
Measured at SMA connector, BER = 10–3
2
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and
the internally generated carrier frequency
> (–225 / 225) (1)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
> (–1050 / 1050) (1)
ppm
Co-channel rejection(2)
Wanted signal at –67 dBm, modulated interferer in
channel,BER = 10–3
Selectivity, ±2 MHz(2)
–8
dB
Wanted signal at –67 dBm, modulated interferer at ±2
MHz, Image frequency is at –2 MHz, BER = 10–3
9 / 5 (3)
dB
Selectivity, ±4 MHz(2)
Wanted signal at –67 dBm, modulated interferer at ±4
MHz, BER = 10–3
40 / 32 (3)
dB
Selectivity, ±6 MHz(2)
Wanted signal at –67 dBm, modulated interferer at ±6
MHz, BER = 10–3
46 / 40 (3)
dB
Selectivity, image frequency(2)
Wanted signal at –67 dBm, modulated interferer at image
frequency, BER = 10–3
5
dB
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When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Selectivity, image frequency
±2 MHz(2)
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at ±2
MHz from image frequency, BER = 10–3
Out-of-band blocking(4)
30 MHz to 2000 MHz
–10
dBm
Out-of-band blocking
2003 MHz to 2399 MHz
–10
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
–12
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz (excluding VCO frequency)
–10
dBm
Intermodulation
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2408 and 2414 MHz respectively, at the given power
level
–38
dBm
(1)
(2)
(3)
(4)
(5)
(6)
28
–8 / 32 (3)
dB
Exceeding Bluetooth specification
Numbers given as I/C dB
X / Y, where X is +N MHz and Y is –N MHz
Excluding one exception at Fwanted / 2, per Bluetooth Specification
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
The device will saturate at -30dB.
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8.15 Bluetooth Low Energy - Transmit (TX)
When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Max output power
Delivered to a single-ended 50-Ω load through integrated balun
8
dBm
Output power
programmable range
Delivered to a single-ended 50-Ω load through integrated balun
28
dB
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8.16 Proprietary Radio Modes
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DCDC enabled unless
otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements
are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps GFSK (HID), 320 kHz deviation
Receiver sensitivity
30
PER = 30.8%, Payload 37 bytes
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8.17 2.4 GHz RX/TX CW
When measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DCDC enabled
unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All
measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Spurious emissions and harmonics
Spurious emissions(1)
f < 1 GHz, outside restricted bands
< –36
dBm
f < 1 GHz, restricted bands ETSI
< –54
dBm
f < 1 GHz, restricted bands FCC
< –55
dBm
< –42
dBm
Second harmonic
< –42
dBm
Third harmonic
< –42
dBm
+8 dBm setting
f > 1 GHz, including harmonics
Harmonics (1)
(1)
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
8.18 Timing and Switching Characteristics
8.18.1 Reset Timing
PARAMETER
MIN
RSTN low duration
TYP
MAX
UNIT
1
µs
8.18.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include any software overhead (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCU, Reset/Shutdown to Active(1)
GLDO default charge current setting,
VDDR capacitor fully charged (2)
350-450
µs
MCU, Standby to Active
MCU, Standby to Active (ready to execute
code from flash). DCDC ON, default
recharge current configuration
33-43 (3)
µs
MCU, Standby to Active
MCU, Standby to Active (ready to execute
code from flash). GLDO ON, default
recharge current configuration
33-50 (3)
µs
MCU, Idle to Active
Flash enabled in idle mode
3
µs
MCU, Idle to Active
Flash disabled in idle mode
14
µs
(1)
(2)
(3)
Wakeup time includes device ROM bootcode execution time. The wakeup time is dependent on remaining charge on VDDR capacitor
when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again.
This is the best case reset/shutdown to active time (including ROM bootcode operation), for the specified GLDO charge current setting
considering the VDDR capacitor is fully charged and is not discharged during the reset and shutdown events; that is, when the device
is in reset / shutdown modes for only a very short period of time
Depending on VDDR capacitor voltage level.
8.18.3 Clock Specifications
8.18.3.1 48 MHz Crystal Oscillator (HFXT)
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(4)
PARAMETER
MIN
TYP
Crystal frequency
48
ESR
Equivalent series resistance
6 pF < CL ≤ 9 pF
20
ESR
Equivalent series resistance
5 pF < CL ≤ 6 pF
CL
Crystal load capacitance(1)
3
7(2)
MAX
UNIT
MHz
60
Ω
80
Ω
9
pF
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Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(4)
PARAMETER
Start-up
time (3)
(1)
(2)
(3)
(4)
MIN
TYP
Until clock is qualified
MAX
200
UNIT
µs
Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certain regulations.
On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
Tai-Saw TZ3908AAAO43 has been validated for CC2340R5 design.
8.18.3.2 48 MHz RC Oscillator (HFOSC)
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Frequency
48
MHz
Uncalibrated frequency accuracy
±3
%
(1)
±0.25
%
Calibrated frequency accuracy
(1)
Accuracy relative to the calibration source (HFXT)
8.18.3.3 32 kHz Crystal Oscillator (LFXT)
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
Crystal frequency
TYP
MAX
32.768
Supported crystal load capacitance
6
ESR
30
UNIT
kHz
12
pF
100
kΩ
MAX
UNIT
8.18.3.4 32 kHz RC Oscillator (LFOSC)
Measured on the CC2340R5 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
Temperature coefficient.
(1)
32
TYP
32.768 (1)
Calibrated frequency
±600
kHz
ppm/°C
When using LFOSC as source for the low frequency system clock (LFCLK), the accuracy of the LFCLK-derived Real Time Clock
(RTC) can be improved by measuring LFOSC relative to HFXT and compensating for the RTC tick speed. This functionality is available
through the TI-provided Power driver.
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8.19 Peripheral Characteristics
8.19.1 UART
8.19.1.1 UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UART rate
UNIT
3
MBaud
8.19.2 SPI
8.19.2.1 SPI Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
fSCLK
1/tsclk
DCSCK
SPI clock frequency
TEST CONDITIONS
MIN
TYP
MAX
Primary Mode
1.71 < VDDS < 3.8
12
Secondary Mode
2.7 < VDDS < 3.8
8
Secondary Mode
VDDS < 2.7
7
SCK Duty Cycle
45
50
55
MIN
TYP
MAX
(tSPI/2) 1
tSPI/2
(tSPI/2) +
1
UNIT
MHz
%
8.19.2.2 SPI Controller Mode
Over operating free-air temperature range (unless otherwise noted)
PARAMETERS
tSCLK_H/
L
TEST CONDITIONS
SCLK High or Low time
tCS.LEAD CS lead-time, CS active to clock
UNIT
ns
1
SCLK
1
SCLK
tCS.LAG
CS lag time, Last clock to CS
inactive
tCS.ACC
CS access time, CS active to
PICO data out
1
SCLK
tCS.DIS
CS disable time, CS inactive to
PICO high impedance
1
SCLK
tVALID.C
PICO output data valid time(1)
SCLK edge to PICO valid,CL = 20 pF
13
ns
PICO output data hold time(2)
CL = 20 pF
O
tHD.CO
(1)
(2)
0
ns
Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
Specifies how long data on the output is valid after the output changing SCLK clock edge
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8.19.2.3 SPI Timing Diagrams - Controller Mode
CS
(inverted)
tCS, LEAD
CS
1 / fSPI
tCS, LAG
SCLK
(SPO = 0)
tSCLK_H/L
tSCLK_H/L
SCLK
(SPO = 1)
tSU,CI
tHD,CI
POCI
tHD,CO
tVALID,CO
tCS, ACC
tCS, DIS
PICO
Controller Mode, SPH = 0
Figure 8-1. SPI Timing Diagram - Controller Mode, SPH = 0
CS
(inverted)
tCS, LEAD
CS
1 / fSPI
tCS, LAG
SCLK
(SPO = 0)
tSCLK_H/L
tSCLK_H/L
SCLK
(SPO = 1)
tSU,CI
tHD,CI
tCS, ACC
POCI
tHD,CO
tVALID,CO
tCS, DIS
PICO
Controller Mode, SPH = 1
Figure 8-2. SPI Timing Diagram - Controller Mode, SPH = 1
8.19.2.4 SPI Peripheral Mode
Over operating free-air temperature range (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
tCS.LEAD CS lead-time, CS active to clock
34
MIN
1
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TYP
MAX
UNIT
SCLK
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Over operating free-air temperature range (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tCS.LAG
CS lag time, Last clock to CS
inactive
tCS.ACC
CS access time, CS active to
POCI data out
VDDS = 3.3V
56
ns
tCS.ACC
CS access time, CS active to
POCI data out
VDDS = 1.8V
70
ns
tCS.DIS
CS disable time, CS inactive to
POCI high inpedance
VDDS = 3.3V
56
ns
tCS.DIS
CS disable time, CS inactive to
POCI high inpedance
VDDS = 1.8V
70
ns
tSU.PI
PICO input data setup time
30
ns
tHD.PI
PICO input data hold time
0
ns
tVALID.P
POCI output data valid time(1)
SCLK edge to POCI valid,CL = 20 pF, 3.3V (4)
50
ns
POCI output data valid time(1)
SCLK edge to POCI valid,CL = 20 pF, 1.8V (4)
65
ns
POCI output data hold time(2)
CL = 20 pF
O
tVALID.P
O
tHD.PO
(1)
(2)
1
SCLK
0
ns
Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
Specifies how long data on the output is valid after the output changing SCLK clock edge
8.19.2.5 SPI Timing Diagrams - Peripheral Mode
CS
(inverted)
tCS, LEAD
CS
1 / fSPI
tCS, LAG
SCLK
(SPO = 0)
tSCLK_H/L
tSCLK_H/L
SCLK
(SPO = 1)
tSU,PI
tHD,PI
PICO
tCS, ACC
tHD,PO
tVALID,PO
tCS, DIS
POCI
Peripheral Mode, SPH = 0
Figure 8-3. SPI Timing Diagram - Peripheral Mode, SPH = 0
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CS
(inverted)
tCS, LEAD
CS
1 / fSPI
tCS, LAG
SCLK
(SPO = 0)
tSCLK_H/L
tSCLK_H/L
SCLK
(SPO = 1)
tSU,PI
tHD,PI
PICO
tHD,PO
tVALID,PO
tCS, ACC
tCS, DIS
POCI
Peripheral Mode, SPH = 1
Figure 8-4. SPI Timing Diagram - Peripheral Mode, SPH = 1
8.19.3 I2C
8.19.3.1 I2C
Over operating free-air temperature range (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
fSCL = 100kHz
4.0
µs
tHD,STA
Hold time (repeated) START
fSCL > 100kHz
0.6
µs
tSU,STA
Setup time for a repeated
START
fSCL = 100kHz
4.7
µs
tSU,STA
Setup time for a repeated
START
fSCL > 100kHz
0.6
µs
tHD,DAT
Data hold time
tSU,DAT
Data setup time
tSU,STO
Setup time for STOP
tSU,STO
Setup time for STOP
tBUF
0
µs
100
µs
fSCL = 100kHz
4.0
µs
fSCL > 100kHz
0.6
µs
Bus free time between STOP
and START conditions
fSCL = 100kHz
4.7
µs
tBUF
Bus free time between STOP
and START conditions
fSCL > 100kHz
1.3
µs
tSP
Pulse duration of spikes
supressed by input deglitch filter
50
ns
36
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8.19.3.2 I2C Timing Diagram
tSU,STA
tHD,STA
tBUF
tHD,STA
SDA
ttLOWt
ttHIGHt
tSP
SCL
tHD,DAT
tSU,DAT
tSU,STO
Figure 8-5. I2C Timing Diagram
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8.19.4 GPIO
8.19.4.1 GPIO DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
39.08
65.84
108.9
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
9.815
20.71
39.96
µA
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
0.9145
1.105
1.277
V
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
0.5891
0.752
0.9146
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.2559
0.3534
0.4401
V
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 10 mA load
high-drive GPIOs only, max drive setting
GPIO VOL at 10 mA load
high-drive GPIOs only, max drive setting
GPIO VOH at 2 mA load
standard drive GPIOs
GPIO VOL at 2 mA load
standard drive GPIOs
2.466
V
0.2527
2.516
V
V
0.1985
V
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
169.5
261.5
392.7
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
60.08
109.7
171.6
µA
GPIO low-to-high input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
1.757
1.983
2.27
V
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 1 → 0
1.262
1.515
1.791
V
GPIO input hysteresis
IH = 1, difference between 0 → 1
and 1 → 0 points
0.3961
0.4689
0.5405
V
TA = 25 °C
VIH
Lowest GPIO input voltage reliably interpreted as a
High
VIL
Highest GPIO input voltage reliably interpreted as a
Low
0.8*VDDS
V
0.2*VDDS
V
8.19.5 ADC
8.19.5.1 Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(2)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDDS
V
ADC Power Supply and Input Range Conditions
V(Ax)
Analog input voltage range
I(ADC)
singleended
mode
Operating supply current
into VDDS terminal
CI GPIO
Input capacitance into a
single terminal
RI GPIO
Input MUX ON-resistance
All ADC analog input pins Ax
0
RES = 0x0 (12Bit mode), Fs = 1.2MSPS, Internal reference
OFF (ADCREF_EN = 0), VeREF+ = VDDS
480
RES = 0x0 (12Bit mode), Fs = 266ksps, Internal reference ON
(ADCREF_EN = 0), ADCREF = 2.5V
365
μA
5
7
pF
0.5
1
kΩ
ADC Switching Characteristics
FS ADC
REF
ADC sampling frequency
when using the internal ADC
reference voltage
ADCREF_EN = 1, RES = 0x0 (12-bit), VDDS = 1.71V to
VDDSmax
267 (1)
ksps
FS ADC
REF
ADC sampling frequency
when using the internal ADC
reference voltage
ADCREF_EN = 1, RES = 0x1 (10-bit), VDDS = 1.71V to
VDDSmax
308 (1)
ksps
FS ADC
REF
ADC sampling frequency
when using the internal ADC
reference voltage
ADCREF_EN = 1, RES = 0x2 (8-bit), VDDS = 1.71V to
VDDSmax
400 (1)
ksps
1.2 (1)
Msps
ADC sampling frequency
FS EXTR
ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x0 (12-bit), VDDS
when using the external ADC
EF
= 1.71V to VDDSmax
reference voltage
38
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Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(2)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
MAX
UNIT
ADC sampling frequency
FS EXTR
ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x1 (10-bit), VDDS
when using the external ADC
EF
= 1.71V to VDDSmax
reference voltage
PARAMETER
1.33 (1)
Msps
ADC sampling frequency
FS EXTR
ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x2 (8-bit), VDDS
when using the external ADC
EF
= 1.71V to VDDSmax
reference voltage
1.6 (1)
Msps
NCONVER
T
NCONVER
T
NCONVER
T
tSample
tVSUPPLY/
3(sample)
TEST CONDITIONS
MIN
TYP
Clock cycles for conversion
RES = 0x0 (12-bit)
14
cycles
Clock cycles for conversion
RES = 0x1 (10-bit)
12
cycles
Clock cycles for conversion
RES = 0x2 (8-bit)
9
cycles
Sampling time
RES = 0x0 (12-bit), RS = 25 Ω, Cpext = 10 pF. +/- 0.5 LSB
settling
Sample time required
when Vsupply/3 channel is
selected
250
ns
20
µs
ADC Linearity Parameters
EI
Integral linearity error (INL)
for single-ended inputs
12-bit Mode, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8
+/- 2
LSB
ED
Differential linearity error
(DNL)
12-bit Mode, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8
+/- 1
LSB
EO
Offset error
12-bit Mode, External reference, VR+ = VeREF+ =
VDDS, VDDS=1.71-->3.8
1.98
LSB
EO
Offset error
12-bit Mode, Internal reference, VR+ = ADCREF = 2.5V
1.02
LSB
EG
Gain error
External Reference, VR+ = VeREF+ = VDDS , VDD= 1.71-->3.8
+/- 2
LSB
EG
Gain error
Internal reference, VR+ = ADCREF = 2.5V
+/- 40
LSB
ADC Dynamic Parameters
ENOB
Effective number of bits
ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
0x2 (8-bit)
8
bit
ENOB
Effective number of bits
ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
0x1 (10-bit)
9.9
bit
ENOB
Effective number of bits
ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
0x0 (12-bit)
11.2
bit
ENOB
Effective number of bits
ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x2
(8-bit)
8
bit
ENOB
Effective number of bits
ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V} , RES = 0x1
(10-bit)
ENOB
Effective number of bits
ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0
(12-bit)
ENOB
Effective number of bits
VDDS reference, RES = 0x0 (12-bit)
SINAD
Signal-to-noise and distortion ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =
ratio
0x0 (12-bit)
69.18
SINAD
Signal-to-noise and distortion ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0
ratio
(12-bit)
64.37
SINAD
Signal-to-noise and distortion
VDDS reference, RES = 0x0 (12-bit)
ratio
69.18
9.6
bit
10.4
bit
11.2
bit
dB
dB
dB
ADC External Reference
EXTREF
Positive external reference
voltage input
ADCREF_EN=0, ADC reference sourced from external
reference pin (VeREF+)
EXTREF
Negative external reference
voltage input
ADCREF_EN=0, ADC reference sourced from external
reference pin (VeREF-)
1.4
VDDS
V
0
V
ADC Temperature Diode, Supply Monitor
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Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(2)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
ADC
Internal
Input:
Vsupply voltage divider
VSUPPLY / accuracy for supply
3
monitoring
Accurac
y
TEST CONDITIONS
ADC input channel: Vsupply monitor
MIN
TYP
MAX
UNIT
+/- 1
%
10
µA
VDDS
V
ADCREF_EN = 1, ADCREF_VSEL = 0, VDDS = 1.71V VDDSmax
1.4
V
ADCREF_EN = 1, ADCREF_VSEL = 1, VDDS = 2.7V VDDSmax
2.5
V
80
µA
2
µs
ADC
Internal Vsupply voltage divider current
ADC input channel Vsupply monitor. Vsupply=VDDS=3.3V
Input:
consumption
IVsupply / 3
ADC Internal and VDDS Reference
VDDSR
EF
Positive ADC reference
voltage
ADCRE
F
Internal ADC Reference
Voltage
IADCREF
Operating supply current into
ADCREF_EN = 1, VDDA = 1.7V to VDDAmax, ADCREF_VSEL
VDDA terminal with internal
= {0,1}
reference ON
tON
Internal ADC Reference
Voltage power on-time
(1)
(2)
40
ADC reference sourced from VDDS
ADCREF_EN = 1
Measured with 48MHz HFOSC
Using IEEE Std 1241-2010 for terminology and test methods
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8.19.6 Comparators
8.19.6.1 Ultra-low power comparator
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Input voltage range
MIN
TYP
0
Clock frequency
Voltage Divider Accuracy
Input voltage range is between VDDS/4 and VDDS
Offset
Measured at VDDS / 2 (Errors seen when using two external inputs )
Decision time
Step from –50 mV to 50 mV
Comparator enable time
COMP_LP disable → enable, VIN+, VIN- from pins,Overdrive ≥ 20
mV
Current consumption
Including using VDDS/2 as internal reference at VIN- comparator
terminal
MAX
VDDS
UNIT
V
32
KHz
98
%
+/- 27.3
1
mV
3
Clock Cycle
70
µs
270
nA
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9 Detailed Description
9.1 Overview
Section 4 shows the core modules of the CC2340R5 device.
9.2 System CPU
The CC2340R5 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M0+ system CPU, which runs the
application, the protocol stacks, and the radio. The Cortex-M0+ processor is built on a highly area and power
optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers
exceptional energy efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor offers
multiple benefits to developers including:
•
•
•
Ultra-low power, energy efficient operation
Deterministic, high-performance interrupt handling for time-critical applications
Upward compatibility with the Cortex-M processors family
The Cortex-M0+ processor provides the excellent performance expected of a modern 32- bit architecture core,
with higher code density than other 8-bit and 16-bit microcontrollers. Its features include the following:
•
•
•
•
•
•
•
•
•
ARMv6-M architecture optimized for small-footprint embedded applications
Subset of Arm Thumb/Thumb-2 mixed 16- and 32-bit instructions delivers the high performance expected of
a 32-bit Arm
Single-cycle multiply instruction
VTOR supporting offset of the vector table base address
Serial Wire debug with HW break-point comparators
Ultra-low-power consumption with integrated sleep modes
SysTick timer
48 MHz operation
0.99 DMIPS/MHz
Additionally, the CC2340Rx devices are compatible with all ARM tools and software.
42
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9.3 Radio (RF Core)
The low-power RF Core (LRF) implements a high performance and highly flexible RF sub system containing
RF and baseband circuitry in addition to a software defined digital radio (LRFD). LRFD provides a high-level,
command-based API to the main CPU and handles all of the timing critical and low-level details of many
different radio PHYs. Several signals are also available to control external circuitry such as RF switches or range
extenders autonomously.
The software-defined modem is not programmable by customers but is instead loaded with pre-compiled images
provided in the radio driver in the SimpleLink™ CC23xx software development kit (SDK). This mechanism allows
the radio platform to be updated for support of future versions of standards with over-the-air (OTA) updates while
still using the same silicon. LRFD stores the code images in the RF SRAM and does not make use of any ROM
memory, thus image loading from NV memory only occurs once after boot and also, no patching is required
when exiting power modes.
9.3.1 Bluetooth 5.3 Low Energy
The RF Core offers full support for Bluetooth 5.3 Low Energy, including the high-speed 2 Mbps physical layer
and the 500 kbps and 125 kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.3 stack or
through a high-level Bluetooth API.
The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times
the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers
significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.
Bluetooth 5.3 also enables unparalleled flexibility for adjustment of speed and range based on application
needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible
at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not
previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster
responses, richer engagement, and longer battery life. Bluetooth 5.3 enables fast, reliable firmware updates.
9.3.2 802.15.4 (Thread and Zigbee)
Through a dedicated IEEE radio API, the RF sub-system supports the 2.4-GHz IEEE 802.15.4-2011 physical
layer (2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread and Zigbee protocols. TI also provides
royalty-free protocol stacks for Thread and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end
solution.
9.4 Memory
The 512 KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-system
programmable and erasable. A special flash memory sector must contain a Customer Configuration section
(CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done
through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static 36 KB RAM (SRAM) can be used for both storage of data and execution of
code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode
power consumption numbers. System SRAM is always initialized to zeroes upon code execution during boot.
The ROM includes device bootcode firmware handling initial device trimming operations, security configurations
and device lifecycle management. The ROM also contains a serial (SPI and UART) bootloader that can be used
for initial programming of the device.
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9.5 Cryptography
The CC2340R5 device comes with AES-128 cryptography hardware accelerator, reducing code footprint and
execution time for cryptographic operations. It also has the benefit of being lower power and improves availability
and responsiveness of the system because the cryptography operations run in a background hardware thread.
The AES hardware accelerators supports the following block cipher modes and message authentication codes:
• AES ECB encrypt
• AES CBC encrypt
• AES CTR encrypt/decrypt
• AES CBC-MAC
• AES GCM
• AEC CCM (uses a combination of CTR + CBC-MAC hardware via software drivers)
The AES hardware accelerator can be fed with plaintext/ciphertext from either CPU or using DMA. Sustained
throughput of one 16 byte ECB block per 23 cycles is possible corresponding to > 30 Mbps.
The CC2340R5 device supports Random Number Generation (RNG) using on-chip analog noise as the
non-deterministic noise source for the purpose of generating a seed for a cryptographically secure counter
deterministic random bit generator (CTR-DRBG) that in turn is used to generate random numbers for keys,
initialization vectors (IVs), and other random number requirements. Hardware acceleration of AES CTR-DRBG is
supported.
The CC2340R5 device includes a complete SHA 256 library in ROM, reducing the code footprint of the
application. Uses cases may include generating digests for use in digital signature algorithms, data integrity
checks, and password storage.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform.
9.6 Timers
A large selection of timers are available as part of the CC2340R5 device. These timers are:
•
Real-Time Clock (RTC)
The RTC is a 67-bit, 2-channel timer running on the LFCLK system clock. The RTC is active in STANDBY
and ACTIVE power states. When the device enters the RESET or SHUTDOWN state the RTC is reset.
The RTC accumulates time elapsed since reset on each LFCLK. The RTC counter is incremented by LFINC
at a rate of 32.768 kHz. LFINC indicates the period of LFCLK in μs, with an additional granularity of 16
fractional bits.
The counter can be read from two 32-bit registers. RTC.TIME8U has a range of approximately 9.5 hours with
an LSB representing 8 microseconds. RTC.TIME524M has a range of approximately 71.4 years with an LSB
representing 524 milliseconds.
There is hardware synchronization between the system timer (SYSTIM) and the RTC so that the multichannel and higher resolution SYSTIM remain in synchronization with the RTC’s time base.
•
The RTC has two channels: one compare channel and one capture channel and is capable of waking the
device out of the standby power state. The RTC compare channel is typically used only by system software
and only during the standby power state.
System Timer (SYSTIM)
The SYSTIM is a 34-bit, 5-channel wrap-around timer with a per-channel selectable 32b slice with either a 1
us resolution and 1h11m35s range or 250 ns resolution and 17m54s range. All channels support both capture
and single-shot compare (posting an event) operation. One channel is reserved for system software, three
channels are reserved for radio software and one channel is freely available to user applications.
For software convenience a hardware synchronization mechanism automatically ensures that the RTC and
SYSTIM share a common time base (albeit with different resolutions/spans). Another software convenience
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feature is that SYSTIM qualifies any submitted compare values so that the timer channel will immediately
trigger if the submitted event is in the immediate past (4.294s with 1 us resolution and 1.049s with 250 ns
resolution).
General Purpose Timers (LGPT)
The CC2340R5 device provides four LGPTs with 3 × 16 bit timers and 1× 24 bit timer, all running on up to 48
MHz. The LGPTs support a wide range of features such as:
–
–
–
–
–
–
–
3 capture/compare channels
One-shot or periodic counting
Pulse width modulation (PWM)
Time counting between edges and edge counting
Input filter implemented on each of the channels for all timers
IR generation feature available on Timer-0
Dead band feature available on Timer-1
The timer capture/compare and PWM signals are connected to IOs via IO controller module (IOC) and the
internal timer event connections to CPU, DMA and other peripherals are via the event fabric, which allows
the timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. Two LGPTs (2× 16
bit timers) supports quadrature decoder mode to enable buffered decoding of quadrature-encoded sensor
signals. The LGPTs are available in device Active and Idle power modes.
Table 9-1. Timer Comparison
•
Feature
Timer 0
Timer 1
Timer 2
Timer 3
Counter Width
16-bit counter width
24-bit counter width
24-bit counter width
24-bit counter width
Quadrature Decoder
Yes
No
Yes
No
Park Mode on Fault
No
Yes
No
No
Programmable DeadBand Insertion
No
Yes
No
No
Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. Upon
counter expiry, the watchdog timer resets the device when periodic monitoring of the system components
and tasks fails to verify proper functionality. The watchdog timer runs on a 32 kHz clock rate and operates in
device active, idle, and standby modes and cannot be stopped once enabled.
9.7 Serial Peripherals and I/O
The CC2340R5 device provides 1xUART, 1xSPI and 1xI2C serial peripherals
The SPI module supports both SPI controller and peripheral up to 12 MHz with configurable phase and polarity.
The UART module implement universal asynchronous receiver and transmitter functions. They support flexible
baud-rate generation up to a maximum of 3 Mbps and IRDA SIR mode of operation.
The I2C module is used to communicate with devices compatible with the I2C standard. The I2C interface can
handle 100 kHz and 400 kHz operation, and can serve as both controller and target.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a fixed manner over DIOs. All digital I/Os are interrupt and wake-up capable, have
a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull, open-drain, or open source.
Some GPIOs have high-drive capabilities, which are marked in bold in Section 7.
For more information, see the CC23xx SimpleLink™ Wireless MCU Technical Reference Manual.
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9.8 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2340R5 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage
and respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.9 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
•
•
•
•
Channel operation of up to 8 channels, with 6 channels having dedicated peripheral interface and 2 channels
having ability to be triggered via configurable events.
Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
Data sizes of 8, 16, and 32 bits
Ping-pong mode for continuous streaming of data
9.10 Debug
On-chip debug is supported through the serial wire debug (SWD) interface, which is an ARM bi-directional 2-wire
protocol that communicates with the JTAG Test Access Port (TAP) controller and allows for complete debug
functionality. SWD is fully compatible with Texas Instruments' XDS family of debug probes.
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9.11 Power Management
To minimize power consumption, the CC2340R5 supports a number of power modes and power management
features (see Table 9-2).
Table 9-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES (1)
MODE
ACTIVE
IDLE
STANDBY
SHUTDOWN
RESET PIN
HELD
CPU
Active
Off
Off
Off
Off
Flash
On
Available
Off
Off
Off
SRAM
On
On
Retention
Off
Off
Radio
Available
Available
Off
Off
Off
Supply System
On
On
Duty Cycled
Off
Off
CPU register retention
Full
Full
Full (2)
No
No
SRAM retention
Full
Full
Full
Off
Off
HFOSC (tracks HFXT)
HFOSC (tracks HFXT)
Off
Off
Off
LFXT or LFOSC
LFXT or LFOSC
LFXT or LFOSC
Off
Off
Available
Available
IOC, BATMON,
RTC, LPCOMP
Off
Off
Wake-up on RTC
N/A
Available
Available
Off
Off
Wake-up on pin edge
N/A
Available
Available
Available
Off
Wake-up on reset pin
On
On
On
On
On
Brownout detector (BOD)
On
On
Duty Cycled
Off
Off
48 MHz high-speed clock
(HFCLK)
32 kHz low-speed clock (LFCLK)
Peripherals
Power-on reset (POR)
On
On
On
On
On
Watchdog timer (WDT)
Available
Available
Available
Off
Off
(1)
(2)
“Available” indicates that the specific IP or feature can be enabled by user application in the corresponding device operating modes.
“On” indicates that the specific IP or feature is turned on irrespective of the user application configuration of the device in the
corresponding device operating mode. “Off” indicates that the specific IP or feature is turned off and not available for the user
application in the corresponding device operating mode.
Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode
In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power
consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU..
In Idle mode the CPU is in sleep but selected peripherals and subsystems (such as the radio) can be active.
Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on state of the DMA and debug
subsystem.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or
comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the
device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up
again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby
mode.
In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with
the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from
shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset
in this way and reset-by-reset pin or power-on reset, or thermal shutdown reset, by reading the reset status
register. The only state retained in this mode are the latched I/O state, 3V register bank, and the flash memory
contents.
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Note
The power, RF and clock management for the CC2340R5 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in
the TI-provided drivers that are part of the CC2340R5 software development kit (SDK). Therefore,
TI highly recommends using this software framework for all application development on the device.
The complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source
code.
9.12 Clock Systems
The CC2340R5 device has the following internal system clocks.
The 48 MHz HFCLK is used as the main system (MCU and peripherals) clock. This is driven by the internal 48
MHz RC Oscillator (HFOSC), which can track its accuracy against an external 48 MHz crystal (HFXT). Radio
operation requires an external 48 MHz crystal.
The 32.768 kHz LFCLK is used as the internal low-frequency system clock. It is used for the RTC, the watchdog
timer (if enabled in standby power mode), and to synchronize the radio timer before or after Standby power
mode. LFCLK can be driven by the internal 32.8 kHz RC Oscillator (LFOSC), a 32.768 kHz watch-type crystal, or
clock input in LFXT bypass mode. When using a crystal or the internal RC oscillator, the device can output the
32 kHz LFCLK signal to other devices, thereby reducing the overall system cost.
9.13 Network Processor
Depending on the product configuration, the CC2340R5 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC - with the application and protocol stack running on the system CPU inside the device).
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
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10 Application, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC2340R5
device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator
components, as well as ground connections for all of these.
LP-EM-CC2340R5 Design
Files
The CC2340R5 LaunchPad Design Files contain detailed schematics and
layouts to build application specific boards using the CC2340R5 device.
Sub-1 GHz and 2.4 GHz
Antenna Kit for LaunchPad™
Development Kit and
SensorTag
The antenna kit allows real-life testing to identify the optimal antenna for your
application. The antenna kit includes 16 antennas for frequencies from 169 MHz
to 2.4 GHz, including:
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.
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10.2 Junction Temperature Calculation
This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are two recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T J = ψJT × P + Tcase
(1)
T J = ψJB × P + Tboard
(2)
2. From board temperature:
P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in Thermal Resistance Characteristics.
Example:
In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm output
power. Let us assume we want to maintain a junction temperature equal or less than 85 °C and the supply
voltage is 3 V. Using Equation 1, the temperature difference between the top of the case and junction
temperature is calculated. To calculate P, look up the current consumption for Tx at 85 °C. At 85 °C the current
consumption is approximately 5.5 mA. This means that P is 5.5 mA × 3 V = 16.5 mW.
The maximum case temperature to maintain and junction temperature of 85 °C is then calculated as:
Tcase < T j − 0.4°C W × 23.4mW = 84.99°C
(3)
For various application use cases current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, and so on. Typically, the easiest way to find the peak current consumption, and thus
the peak power dissipation in the device, is to measure as described in the Measuring CC13xx and CC26xx
Current Consumption application report.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or
date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, X is in
preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RHB).
For orderable part numbers of devices in the RHB (5-mm x 5-mm) package type, see the Package Option
Addendum of this document, the Device Information in Section 3, the TI website (www.ti.com), or contact your TI
sales representative.
CC2340 R 5 2 E 0 RKP R
R = Large Reel
PREFIX
X = Experimental Device
Blank = Qualified Device
DEVICE
SimpleLink™ Bluetooth® 5.3
Low Energy Wireless MCU
CONFIGURATION
R = Regular (+8 dBm)
FLASH SIZE
5 = 512KB
PACKAGE
RKP = 5 mm x 5 mm QFN
RGE = 4 mm x 4 mm QFN
PRODUCT REVISION
TEMPERATURE
E = 125 °C Ambient
SRAM SIZE
2 = 36KB
Figure 11-1. Device Nomenclature
11.2 Tools and Software
The CC2340R5 device is supported by a variety of software and hardware development tools.
Development Kit
CC2340R5
LaunchPad™
Development Kit
The CC2340R5 LaunchPad™ Development Kit enables development of high-performance
wireless applications that benefit from low-power operation. The kit features the
CC2340R5 SimpleLink Wireless MCU, which allows you to quickly evaluate and prototype
2.4-GHz wireless applications such as Bluetooth 5 Low Energy, Zigbee and Thread, plus
combinations of these. The kit works with the LaunchPad ecosystem, easily enabling
additional functionality like sensors, display and more.
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Software
SimpleLink™
CC23xx software
development kit
(SDK)
The SimpleLink CC23xx software development kit (SDK) provides a complete package
for the development of wireless applications on the CC23xx family of devices. The SDK
includes a comprehensive software package for the CC2340R5 device, including the
following protocol stacks:
• Bluetooth Low Energy 4 and 5.3
The SimpleLink CC23xx SDK is part of TI’s SimpleLink MCU platform, offering a single
development environment that delivers flexible hardware, software and tool options for
customers developing wired and wireless applications. For more information about the
SimpleLink MCU Platform, visit https://www.ti.com/simplelink.
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Code Composer
Studio™ Integrated
Development
Environment (IDE)
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Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse® software framework with advanced embedded debug capabilities from TI resulting
in a compelling feature-rich development environment for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling). A real-time object viewer plugin is available
for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer
Studio™ Cloud
IDE
Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and
build CCS and Energia™ projects. After you have successfully built your project, you can
download and run on your connected LaunchPad. Basic debugging, including features like
setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded
Workbench® for
Arm®
IAR Embedded Workbench® is a set of development tools for building and debugging
embedded system applications using assembler, C and C++. It provides a completely
integrated development environment that includes a project manager, editor, and build
tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™ and Segger J-Link™. A real-time object viewer plugin is
available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box
on most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 KB size-limited version is available through iar.com.
SmartRF™ Studio SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
SimpleLink Wireless MCUs from Texas Instruments. The application will help designers
of RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing
and debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF device.
Features of the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.
UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free
of charge.
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11.2.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of
wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering
flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.
11.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder (CC2340R5). In the upper right corner, click on Alert me to register and receive
a weekly digest of any product information that has changed. For change details, review the revision history
included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
TI Resource Explorer
TI Resource Explorer Software examples, libraries, executables, and documentation are available for your
device and development board.
Errata
CC2340R5 Silicon
Errata
The silicon errata describes the known exceptions to the functional specifications for
each silicon revision of the device and description on how to recognize a device
revision.
Application Reports
All application reports for the CC2340R5 device are found on the device product folder (CC2340R5).
Technical Reference Manual (TRM)
CC23xx SimpleLink™ Wireless MCU
TRM
The TRM provides a detailed description of all modules and peripherals
available in the device family.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
SimpleLink™, LaunchPad™, Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas
Instruments.
I-jet™ is a trademark of IAR Systems AB.
J-Link™ is a trademark of SEGGER Microcontroller Systeme GmbH.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Bluetooth® is a registered trademark of Bluetooth SIG.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Wi-Fi® is a registered trademark of Wi-Fi Alliance.
Eclipse® is a registered trademark of Eclipse Foundation.
IAR Embedded Workbench® is a registered trademark of IAR Systems AB.
Windows® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CC2340R52E0RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
Call TI | NIPDAU
Level-3-260C-168 HR
-40 to 125
CC2340
R52
Samples
CC2340R52E0RKPR
ACTIVE
VQFN
RKP
40
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
CC2340
R52
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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