CC2420
2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver
Applications
2.4 GHz IEEE 802.15.4 systems
ZigBee systems
Home/building automation
Industrial Control
Wireless sensor networks
PC peripherals
Consumer Electronics
Product Description
The CC2420 is a true single-chip 2.4 GHz
IEEE 802.15.4 compliant RF transceiver
designed for low power and low voltage
wireless applications. CC2420 includes a
digital direct sequence spread spectrum
baseband modem providing a spreading
gain of 9 dB and an effective data rate of
250 kbps.
The CC2420 is a low-cost, highly integrated
solution for robust wireless communication
in the 2.4 GHz unlicensed ISM band. It
complies with worldwide regulations
covered by ETSI EN 300 328 and EN 300
440 class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan).
features reduce the load on the host
controller and allow CC2420 to interface
low-cost microcontrollers.
The configuration interface and transmit /
receive FIFOs of CC2420 are accessed via
an SPI interface. In a typical application
CC2420 will be used together with a
microcontroller and a few external passive
components.
CC2420 is based on Chipcon’s SmartRF03 technology in 0.18 m CMOS.
The CC2420 provides extensive hardware
support for packet handling, data
buffering, burst transmissions, data
encryption, data authentication, clear
channel assessment, link quality indication
and packet timing information. These
Key Features
True single-chip 2.4 GHz IEEE
802.15.4 compliant RF transceiver
with baseband modem and MAC
support
DSSS baseband modem with 2
MChips/s and 250 kbps effective data
rate.
Suitable for both RFD and FFD
operation
Low current consumption (RX: 18.8
mA, TX: 17.4 mA)
Low supply voltage (2.1 – 3.6 V) with
integrated voltage regulator
Low supply voltage (1.6 – 2.0 V) with
external voltage regulator
SWRS041c
Programmable output power
No external RF switch / filter needed
I/Q low-IF receiver
I/Q direct upconversion transmitter
Very few external components
128(RX) + 128(TX) byte data buffering
Digital RSSI / LQI support
Hardware MAC encryption (AES-128)
Battery monitor
QLP-48 package, 7x7 mm
Complies with ETSI EN 300 328, EN
300 440 class 2, FCC CFR-47 part 15
and ARIB STD-T66
Powerful and flexible development
tools available
Page 1 of 85
CC2420
Table of contents
1
Abbreviations _________________________________________________________________ 5
2
References ___________________________________________________________________ 6
3
Features _____________________________________________________________________ 7
4
Absolute Maximum Ratings _____________________________________________________ 8
5
Operating Conditions __________________________________________________________ 8
6
Electrical Specifications ________________________________________________________ 9
6.1
Overall ___________________________________________________________________ 9
6.2
Transmit Section ___________________________________________________________ 9
6.3
Receive Section ___________________________________________________________ 10
6.4
RSSI / Carrier Sense _______________________________________________________ 11
6.5
IF Section ________________________________________________________________ 11
6.6
Frequency Synthesizer Section _______________________________________________ 11
6.7
Digital Inputs/Outputs ______________________________________________________ 12
6.8
Voltage Regulator _________________________________________________________ 13
6.9
Battery Monitor ___________________________________________________________ 13
6.10 Power Supply _____________________________________________________________ 13
7
Pin Assignment ______________________________________________________________ 15
8
Circuit Description ___________________________________________________________ 17
9
Application Circuit ___________________________________________________________ 19
9.1
Input / output matching _____________________________________________________ 19
9.2
Bias resistor ______________________________________________________________ 19
9.3
Crystal __________________________________________________________________ 19
9.4
Voltage regulator __________________________________________________________ 19
9.5
Power supply decoupling and filtering _________________________________________ 19
10
IEEE 802.15.4 Modulation Format ____________________________________________ 24
11
Configuration Overview _____________________________________________________ 25
12
Evaluation Software ________________________________________________________ 26
13
4-wire Serial Configuration and Data Interface __________________________________ 27
13.1 Pin configuration __________________________________________________________ 27
13.2 Register access ____________________________________________________________ 27
13.3 Status byte _______________________________________________________________ 28
13.4 Command strobes _________________________________________________________ 29
13.5 RAM access ______________________________________________________________ 29
13.6 FIFO access ______________________________________________________________ 31
13.7 Multiple SPI access ________________________________________________________ 31
14
Microcontroller Interface and Pin Description ___________________________________ 32
14.1 Configuration interface _____________________________________________________ 32
14.2 Receive mode_____________________________________________________________ 33
14.3 RXFIFO overflow _________________________________________________________ 33
14.4 Transmit mode ____________________________________________________________ 34
14.5 General control and status pins _______________________________________________ 35
15
Demodulator, Symbol Synchroniser and Data Decision ___________________________ 35
16
Frame Format _____________________________________________________________ 36
16.1 Synchronisation header _____________________________________________________ 36
16.2 Length field ______________________________________________________________ 37
16.3 MAC protocol data unit _____________________________________________________ 37
16.4 Frame check sequence ______________________________________________________ 38
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Page 2 of 85
CC2420
17
RF Data Buffering __________________________________________________________ 39
17.1 Buffered transmit mode _____________________________________________________ 39
17.2 Buffered receive mode ______________________________________________________ 39
17.3 Unbuffered, serial mode ____________________________________________________ 40
18
Address Recognition ________________________________________________________ 41
19
Acknowledge Frames _______________________________________________________ 41
20
Radio control state machine __________________________________________________ 43
21
MAC Security Operations (Encryption and Authentication) _______________________ 45
21.1 Keys ____________________________________________________________________ 45
21.2 Nonce / counter ___________________________________________________________ 45
21.3 Stand-alone encryption _____________________________________________________ 46
21.4 In-line security operations ___________________________________________________ 46
21.5 CTR mode encryption / decryption ____________________________________________ 47
21.6 CBC-MAC_______________________________________________________________ 47
21.7 CCM ___________________________________________________________________ 47
21.8 Timing __________________________________________________________________ 48
22
Linear IF and AGC Settings __________________________________________________ 48
23
RSSI / Energy Detection _____________________________________________________ 48
24
Link Quality Indication______________________________________________________ 49
25
Clear Channel Assessment ___________________________________________________ 50
26
Frequency and Channel Programming _________________________________________ 50
27
VCO and PLL Self-Calibration _______________________________________________ 51
27.1 VCO____________________________________________________________________ 51
27.2 PLL self-calibration ________________________________________________________ 51
28
Output Power Programming _________________________________________________ 51
29
Voltage Regulator __________________________________________________________ 51
30
Battery Monitor ____________________________________________________________ 52
31
Crystal Oscillator___________________________________________________________ 53
32
Input / Output Matching _____________________________________________________ 54
33
Transmitter Test Modes _____________________________________________________ 55
33.1 Unmodulated carrier _______________________________________________________ 55
33.2 Modulated spectrum _______________________________________________________ 56
34
System Considerations and Guidelines _________________________________________ 57
34.1 Frequency hopping and multi-channel systems ___________________________________ 57
34.2 Data burst transmissions ____________________________________________________ 57
34.3 Crystal accuracy and drift ___________________________________________________ 57
34.4 Communication robustness __________________________________________________ 57
34.5 Communication security ____________________________________________________ 57
34.6 Low-cost systems __________________________________________________________ 58
34.7 Battery operated systems ____________________________________________________ 58
34.8 BER / PER measurements ___________________________________________________ 58
35
PCB Layout Recommendations _______________________________________________ 59
36
Antenna Considerations _____________________________________________________ 59
37
Configuration Registers _____________________________________________________ 61
38
Test Output Signals _________________________________________________________ 81
39
Package Description (QLP 48) __________________________ Error! Bookmark not defined.
40
Recommended layout for package (QLP 48) ______________ Error! Bookmark not defined.
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Page 3 of 85
CC2420
40.1
40.2
40.3
40.4
41
Package thermal properties __________________________ Error! Bookmark not defined.
Soldering information ______________________________________________________ 83
Plastic tube specification ____________________________ Error! Bookmark not defined.
Carrier tape and reel specification _____________________ Error! Bookmark not defined.
Ordering Information _________________________________ Error! Bookmark not defined.
42
General Information ________________________________________________________ 84
42.1 Document History _________________________________________________________ 84
42.2 Product Status Definitions ___________________________ Error! Bookmark not defined.
43
Address Information __________________________________ Error! Bookmark not defined.
44
TI Worldwide Technical Support _______________________ Error! Bookmark not defined.
Important Notice ___________________________________________ Error! Bookmark not defined.
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Page 4 of 85
CC2420
1
Abbreviations
ADC
AES
AGC
ARIB
BER
CBC-MAC
CCA
CCM
CFR
CSMA-CA
CTR
CW
DAC
DSSS
ESD
ESR
EVM
FCC
FCF
FIFO
FFCTRL
HSSD
IEEE
IF
ISM
ITU-T
-
I/O
I/Q
kbps
LNA
LO
LQI
LSB
MAC
MFR
MHR
MIC
MPDU
MSDU
NA
NC
O-QPSK
PA
PCB
PER
PHY
PHR
PLL
PSDU
QLP
RAM
RBW
RF
RSSI
-
Analog to Digital Converter
Advanced Encryption Standard
Automatic Gain Control
Association of Radio Industries and Businesses
Bit Error Rate
Cipher Block Chaining Message Authentication Code
Clear Channel Assessment
Counter mode + CBC-MAC
Code of Federal Regulations
Carrier Sense Multiple Access with Collision Avoidance
Counter mode (encryption)
Continuous Wave
Digital to Analog Converter
Direct Sequence Spread Spectrum
Electro Static Discharge
Equivalent Series Resistance
Error Vector Magnitude
Federal Communications Commission
Frame Control Field
First In First Out
FIFO and Frame Control
High Speed Serial Debug
Institute of Electrical and Electronics Engineers
Intermediate Frequency
Industrial, Scientific and Medical
International Telecommunication Union – Telecommunication
Standardization Sector
Input / Output
In-phase / Quadrature-phase
kilo bits per second
Low-Noise Amplifier
Local Oscillator
Link Quality Indication
Least Significant Bit / Byte
Medium Access Control
MAC Footer
MAC Header
Message Integrity Code
MAC Protocol Data Unit
MAC Service Data Unit
Not Available
Not Connected
Offset - Quadrature Phase Shift Keying
Power Amplifier
Printed Circuit Board
Packet Error Rate
Physical Layer
PHY Header
Phase Locked Loop
PHY Service Data Unit
Quad Leadless Package
Random Access Memory
Resolution BandWidth
Radio Frequency
Receive Signal Strength Indicator
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Page 5 of 85
CC2420
RX
SHR
SPI
TBD
T/R
TX
VCO
VGA
2
[1]
-
Receive
Synchronisation Header
Serial Peripheral Interface
To Be Decided / To Be Defined
Transmit / Receive
Transmit
Voltage Controlled Oscillator
Variable Gain Amplifier
References
IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) specifications for Low Rate Wireless Personal Area
Networks (LR-WPANs)
http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf
[2]
NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department of
Commerce/N.I.S.T., November 26, 2001. Available from the NIST website.
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
[3]
R. Housley, D. Whiting, N. Ferguson, Counter with CBC-MAC (CCM),
submitted to NIST, June 3, 2002. Available from the NIST website.
http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/ProposedModesPag
e.html
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Page 6 of 85
CC2420
3
Features
2400 – 2483.5 MHz RF Transceiver
Direct
Sequence
Spread
Spectrum (DSSS) transceiver
250 kbps data rate, 2 MChip/s
chip rate
O-QPSK with half sine pulse
shaping modulation
Very low current consumption
(RX: 18.8 mA, TX: 17.4 mA)
High sensitivity (-95 dBm)
High adjacent channel rejection
(30/45 dB)
High alternate channel rejection
(53/54 dB)
On-chip VCO, LNA and PA
Low supply voltage (2.1 – 3.6 V)
with on-chip voltage regulator
Programmable output power
I/Q low-IF soft decision receiver
I/Q
direct
up-conversion
transmitter
Separate transmit and receive FIFOs
128 byte transmit data FIFO
128 byte receive data FIFO
Very few external components
Only reference crystal and a
minimised number of passives
No external filters needed
Easy configuration interface
4-wire SPI interface
Serial clock up to 10 MHz
802.15.4 MAC hardware support:
Automatic preamble generator
Synchronisation
word
insertion/detection
CRC-16
computation
and
checking over the MAC payload
Clear Channel Assessment
Energy detection / digital RSSI
Link Quality Indication
Full automatic MAC security (CTR,
CBC-MAC, CCM)
802.15.4 MAC hardware security:
Automated security operations
within the receive and transmit
FIFOs.
CTR mode encryption / decryption
CBC-MAC authentication
CCM encryption / decryption and
authentication
Stand-alone AES encryption
Development tools available
Fully equipped development kit
Demonstration board reference
design with microcontroller code
Easy-to-use
software
for
generating the CC2420 configuration data
Small size QLP-48 package, 7 x 7 mm
Complies with EN 300 328, EN 300
440 class 2, FCC CFR47 part 15 and
ARIB STD-T66
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Page 7 of 85
CC2420
4
Absolute Maximum Ratings
Parameter
Min.
Max.
Units
Supply voltage for on-chip voltage regulator,
VREG_IN pin 43.
-0.3
3.6
V
Supply voltage (VDDIO) for digital I/Os, DVDD3.3,
pin 25.
-0.3
3.6
V
Supply voltage (VDD) on AVDD_VCO, DVDD1.8,
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)
−0.3
2.0
V
Voltage on any digital I/O pin, (pin no. 21, 27-34
and 41)
-0.3
VDDIO+0.3, max 3.6
V
Voltage on any other pin, (pin no. 6, 7, 8, 11, 12,
13, 16, 36, 38, 39, 40, 45, 46 and 47)
-0.3
VDD+0.3, max 2.0
V
10
dBm
150
C
260
C
Input RF level
Storage temperature range
−50
Reflow solder temperature
The absolute maximum ratings given
above should under no circumstances be
violated. Stress exceeding one or more of
Condition
T = 10 s
the limiting values may cause permanent
damage to the device.
Caution!
ESD
sensitive
device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
5
Operating Conditions
Parameter
Min.
Supply voltage for on-chip voltage regulator,
VREG_IN pin 43.
Typ.
Max.
Units
2.1
3.6
V
Supply voltage (VDDIO) for digital I/Os, DVDD3.3,
pin 25 .
1.6
3.6
V
The digital I/O voltage (DVDD3.3 pin)
must match the external interfacing
circuit (e.g. microcontroller).
Supply voltage (VDD) on AVDD_VCO, DVDD1.8,
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)
1.6
2.0
V
The typical application uses regulated
1.8 V supply generated by the on-chip
voltage regulator.
Operating ambient temperature range, T A
−40
85
C
1.8
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Condition
Page 8 of 85
CC2420
6
Electrical Specifications
Measured on CC2420 EM with transmission line balun, T A = 25 C,
voltage regulator used if nothing else stated.
6.1
Overall
Parameter
Min.
RF Frequency Range
2400
6.2
DVDD3.3 and VREG_IN = 3.3 V, internal
Typ.
Max.
Unit
Condition / Note
2483.5
MHz
Programmable in 1 MHz steps, 5
MHz steps for compliance with
[1]
Max.
Unit
Condition / Note
Transmit Section
Parameter
Min.
Typ.
Transmit bit rate
250
250
kbps
As defined by [1]
Transmit chip rate
2000
2000
kChips/s
As defined by [1]
Nominal output power
-3
dBm
Delivered to a single ended 50
load through a balun.
0
[1] requires minimum –3 dBm
Programmable output power range
24
dB
The output power is
programmable in 8 steps from
approximately –24 to 0 dBm.
-44
dBm
-64
dBm
Measured conducted with 1 MHz
resolution bandwidth on
spectrum analyser. At max output
power delivered to a single
ended 50 load through a balun.
See page 54.
30 - 1000 MHz
1– 12.75 GHz
1.8 – 1.9 GHz
5.15 – 5.3 GHz
-56
-44
-56
-51
dBm
dBm
dBm
dBm
Complies with EN 300 328, EN
300 440, FCC CFR47 Part 15
and ARIB STD-T-66
Error Vector Magnitude (EVM)
11
%
Measured as defined by [1]
Harmonics
2nd harmonic
rd
3 harmonic
Spurious emission
Maximum output power.
[1] requires max. 35 %
Optimum load impedance
95
+ j187
SWRS041c
Differential impedance as seen
from the RF-port (RF_P and
RF_N) towards the antenna. For
matching details see the Input /
Output Matching section on page
54.
Page 9 of 85
CC2420
6.3
Receive Section
Parameter
Min.
Typ.
-90
-95
Max.
Unit
Condition / Note
dBm
PER = 1%, as specified by [1]
Receiver Sensitivity
Measured in a 50 single-ended
load through a balun.
[1] requires –85 dBm
Saturation (maximum input level)
0
10
dBm
PER = 1%, as specified by [1]
Measured in a 50 single–ended
load through a balun.
[1] requires –20 dBm
Adjacent channel rejection
+ 5 MHz channel spacing
45
dB
Wanted signal @ -82 dBm,
adjacent modulated channel at
+5 MHz, PER = 1 %, as specified
by [1].
[1] requires 0 dB
Adjacent channel rejection
- 5 MHz channel spacing
30
dB
Wanted signal @ -82 dBm,
adjacent modulated channel at
-5 MHz, PER = 1 %, as specified
by [1].
[1] requires 0 dB
Alternate channel rejection
+ 10 MHz channel spacing
54
dB
Wanted signal @ -82 dBm,
adjacent modulated channel at
+10 MHz, PER = 1 %, as
specified by [1]
[1] requires 30 dB
Alternate channel rejection
- 10 MHz channel spacing
53
dB
Wanted signal @ -82 dBm,
adjacent modulated channel at
-10 MHz, PER = 1 %, as
specified by [1]
[1] requires 30 dB
Channel rejection
≥ + 15 MHz
62
dB
≤ - 15 MHz
62
dB
Co-channel rejection
Wanted signal @ -82 dBm.
Undesired signal is an IEEE
802.15.4 modulated channel,
stepped through all channels
from 2405 to 2480 MHz. Signal
level for PER = 1%.
-3
dB
Wanted signal @ -82 dBm.
Undesired signal is an IEEE
802.15.4 modulated at the same
frequency as the desired signal.
Signal level for PER = 1%.
-28
-28
-27
-28
dBm
dBm
dBm
dBm
Wanted signal 3 dB above the
sensitivity level, CW jammer,
PER = 1%. Complies with EN
300 440 class 2.
-73
-58
dBm
dBm
Conducted measurement in a 50
single ended load. Measured
according to EN 300 328, EN
300 440 class 2, FCC CFR47,
Part 15 and ARIB STD-T-66
Blocking / Desensitisation
+/- 5 MHz from band edge
+/- 20 MHz from band edge
+/- 30 MHz from band edge
+/- 50 MHz from band edge
Spurious emission
30 – 1000 MHz
1 – 12.75 GHz
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Page 10 of 85
CC2420
Parameter
Min.
Frequency error tolerance
-300
Typ.
Max.
Unit
Condition / Note
300
kHz
Difference between centre
frequency of the received RF
signal and local oscillator
frequency
[1] requires 200 kHz
Symbol rate error tolerance
120
ppm
Difference between incoming
symbol rate and the internally
generated symbol rate
[1] requires 80 ppm
Data latency
6.4
3
s
Processing delay in receiver.
Time from complete transmission
of SFD until complete reception
of SFD, i.e. from SFD goes
active on transmitter until active
on receiver.
Unit
Condition / Note
RSSI / Carrier Sense
Parameter
Min.
Typ.
Max.
Carrier sense level
− 77
dBm
Programmable in
RSSI.CCA_THR
RSSI dynamic range
100
dB
The range is approximately from
–100 dBm to 0 dBm
RSSI accuracy
6
dB
See page 48 for details
RSSI linearity
3
dB
RSSI average time
128
s
8 symbol periods, as specified by
[1]
Unit
Condition / Note
6.5
IF Section
Parameter
Min.
Intermediate frequency (IF)
6.6
Typ.
Max.
2
MHz
Frequency Synthesizer Section
Parameter
Min.
Crystal oscillator frequency
Crystal frequency accuracy
requirement
Crystal operation
Typ.
Max.
16
- 40
40
Parallel
SWRS041c
Unit
Condition / Note
MHz
See page 53 for details.
ppm
Including aging and temperature
dependency, as specified by [1]
C381 and C391 are loading
capacitors, see page 53
Page 11 of 85
CC2420
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Crystal load capacitance
12
16
20
pF
16 pF recommended
60
Crystal ESR
Crystal oscillator start-up time
1.0
ms
−109
−117
−117
−117
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100
kHz
Phase noise
Unmodulated carrier
PLL loop bandwidth
PLL lock time
6.7
16 pF load
At ±1 MHz offset from carrier
At ±2 MHz offset from carrier
At ±3 MHz offset from carrier
At ±5 MHz offset from carrier
192
s
The startup time from the crystal
oscillator is running and RX / TX
turnaround time
Max.
Unit
Condition / Note
Digital Inputs/Outputs
Parameter
Min.
Typ.
General
Signal levels are referred to the
voltage level at pin DVDD3.3
Logic "0" input voltage
0
0.3*
DVDD
V
Logic "1" input voltage
0.7*
DVDD
DVDD
V
Logic "0" output voltage
0
0.4
V
Output current −8 mA,
3.3 V supply voltage
Logic "1" output voltage
2.5
VDD
V
Output current 8 mA,
3.3 V supply voltage
Logic "0" input current
NA
−1
A
Input signal equals GND
Logic "1" input current
NA
1
A
Input signal equals VDD
FIFO setup time
20
ns
TX unbuffered mode, minimum
time FIFO must be ready before
the positive edge of FIFOP
FIFO hold time
10
ns
TX unbuffered mode, minimum
time FIFO must be held after the
positive edge of FIFOP
Serial interface pins (SCLK, SI, SO
and CSn) timing specification
See Table 4 on page 28
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Page 12 of 85
CC2420
6.8
Voltage Regulator
Parameter
Min.
Typ.
Max.
Unit
General
Condition / Note
Note that the internal voltage
regulator
can
only
supply
CC2420 and no external circuitry.
Input Voltage
2.1
3.0
3.6
V
On the VREG_IN pin
Output Voltage
1.7
1.8
1.9
V
On the VREG_OUT pin
Quiescent current
13
20
29
A
No current drawn from the
VREG_OUT pin. Min and max
numbers include 2.1 through 3.6
V input voltage
0.3
0.6
ms
Start-up time
6.9
Battery Monitor
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Current consumption
6
30
90
A
When enabled
Start-up time
100
s
Voltage regulator already
enabled
Settling time
2
s
New toggle voltage programmed
Step size
50
mV
Hysteresis
10
mV
Absolute accuracy
-80
80
mV
Relative accuracy
-50
50
mV
Max.
Unit
May be software calibrated for
known reference voltage
6.10 Power Supply
Parameter
Min.
Typ.
Condition / Note
Current drawn from VREG_IN,
through voltage regulator
Current consumption in different
modes (see Figure 25, page 44)
Voltage regulator off (OFF)
Power Down mode (PD)
Idle mode (IDLE)
0.02
20
426
Current Consumption,
receive mode
18.8
1
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A
A
A
Voltage regulator off
Voltage regulator on
Including crystal oscillator and
voltage regulator
mA
Page 13 of 85
CC2420
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
mA
mA
mA
mA
mA
The output power is delivered
differentially to a 50 singled
ended load through a balun, see
also page 54.
Current Consumption,
transmit mode:
P = -25 dBm
P = -15 dBm
P = -10 dBm
P = −5 dBm
P = 0 dBm
8.5
9.9
11
14
17.4
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Page 14 of 85
CC2420
AVDD_CHP
ATEST1
ATEST2
R_BIAS
AVDD_IF1
VREG_IN
VREG_OUT
VREG_EN
NC
XOSC16_Q1
XOSC16_Q2
AVDD_XOSC16
47
46
45
44
43
42
41
40
39
38
37
Pin Assignment
48
7
VCO_GUARD
1
36
NC
AVDD_VCO
2
35
DVDD_RAM
AVDD_PRE
3
34
SO
AVDD_RF1
4
33
SI
GND
5
32
SCLK
RF_P
6
31
CSn
TXRX_SWITCH
7
30
FIFO
RF_N
8
29
FIFOP
GND
9
28
CCA
AVDD_SW
10
27
SFD
NC
11
26
DVDD1.8
NC
12
25
DVDD3.3
CC2420
QLP48
7x7
DGND_GUARD
DGUARD
DSUB_CORE
20
DSUB_PADS
19
DVDD_ADC
24
18
AVDD_ADC
23
17
NC
RESETn
16
AVDD_IF2
DGND
15
AVDD_RF2
22
14
NC
21
13
AGND
Exposed die
attach pad
Figure 1. CC2420 Pinout – Top View
Pin
Pin Name
Pin type
Pin Description
-
AGND
Ground (analog)
1
2
3
4
5
6
VCO_GUARD
AVDD_VCO
AVDD_PRE
AVDD_RF1
GND
RF_P
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Ground (analog)
RF I/O
7
TXRX_SWITCH
Power (analog)
8
RF_N
RF I/O
9
10
11
12
13
14
GND
AVDD_SW
NC
NC
NC
AVDD_RF2
Ground (analog)
Power (analog)
Power (analog)
Exposed die attach pad. Must be connected to solid ground
plane
Connection of guard ring for VCO (to AVDD) shielding
1.8 V Power supply for VCO
1.8 V Power supply for Prescaler
1.8 V Power supply for RF front-end
Grounded pin for RF shielding
Positive RF input/output signal to LNA/from PA in
receive/transmit mode
Common supply connection for integrated RF front-end. Must
be connected to RF_P and RF_N externally through a DC
path
Negative RF input/output signal to LNA/from PA in
receive/transmit mode
Grounded pin for RF shielding
1.8 V Power supply for LNA / PA switch
Not Connected
Not Connected
Not Connected
1.8 V Power supply for receive and transmit mixers
SWRS041c
Page 15 of 85
CC2420
Pin
Pin Name
Pin type
Pin Description
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AVDD_IF2
NC
AVDD_ADC
DVDD_ADC
DGND_GUARD
DGUARD
RESETn
DGND
DSUB_PADS
DSUB_CORE
DVDD3.3
DVDD1.8
SFD
CCA
FIFOP
Power (analog)
Power (analog)
Power (digital)
Ground (digital)
Power (digital)
Digital Input
Ground (digital)
Ground (digital)
Ground (digital)
Power (digital)
Power (digital)
Digital output
Digital output
Digital output
30
FIFO
Digital I/O
31
32
33
34
CSn
SCLK
SI
SO
35
36
37
38
39
40
41
DVDD_RAM
NC
AVDD_XOSC16
XOSC16_Q2
XOSC16_Q1
NC
VREG_EN
Digital input
Digital input
Digital input
Digital output
(tristate)
Power (digital)
Power (analog)
Analog I/O
Analog I/O
Digital input
42
43
44
45
46
47
48
VREG_OUT
VREG_IN
AVDD_IF1
R_BIAS
ATEST2
ATEST1
AVDD_CHP
Power output
Power (analog)
Power (analog)
Analog output
Analog I/O
Analog I/O
Power (analog)
1.8 V Power supply for transmit / receive IF chain
Not Connected
1.8 V Power supply for analog parts of ADCs and DACs
1.8 V Power supply for digital parts of receive ADCs
Ground connection for digital noise isolation
1.8 V Power supply connection for digital noise isolation
Asynchronous, active low digital reset
Ground connection for digital core and pads
Substrate connection for digital pads
Substrate connection for digital modules
3.3 V Power supply for digital I/Os
1.8 V Power supply for digital core
SFD (Start of Frame Delimiter) / digital mux output
CCA (Clear Channel Assessment) / digital mux output
Active when number of bytes in FIFO exceeds threshold /
serial RF clock output in test mode
Active when data in FIFO /
serial RF data input / output in test mode
SPI Chip select, active low
SPI Clock input, up to 10 MHz
SPI Slave Input. Sampled on the positive edge of SCLK
SPI Slave Output. Updated on the negative edge of SCLK.
Tristate when CSn high.
1.8 V Power supply for digital RAM
Not Connected
1.8 V crystal oscillator power supply
16 MHz Crystal oscillator pin 2
16 MHz Crystal oscillator pin 1 or external clock input
Not Connected
Voltage regulator enable, active high, held at VREG_IN
voltage level when active. Note that VREG_EN is relative
VREG_IN, not DVDD3.3.
Voltage regulator 1.8 V power supply output
Voltage regulator 2.1 to 3.6 V power supply input
1.8 V Power supply for transmit / receive IF chain
External precision resistor, 43 k, 1 %
Analog test I/O for prototype and production testing
Analog test I/O for prototype and production testing
1.8 V Power supply for phase detector and charge pump
NOTES:
The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the
chip.
SWRS041c
Page 16 of 85
CC2420
8
Circuit Description
AUTOMATIC GAIN CONTROL
ADC
DIGITAL
DEMODULATOR
ADC
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
- Frame
synchronization
LNA
Serial
voltage
regulator
CC2420
FREQ
SYNTH
0
90
Serial
microcontroller
interface
SmartRF
CONTROL LOGIC
TX/RX CONTROL
DIGITAL
INTERFACE
WITH FIFO
BUFFERS,
CRC AND
ENCRYPTION
TX POWER CONTROL
DAC
Power
Control
PA
DIGITAL
MODULATOR
- Data spreading
- Modulation
Digital and
Analog test
interface
DAC
XOSC
On-chip
BIAS
R
16 MHz
Figure 2. CC2420 simplified block diagram
A simplified block diagram of CC2420 is
shown in Figure 2.
CC2420 features a low-IF receiver. The
received RF signal is amplified by the lownoise amplifier (LNA) and down-converted
in quadrature (I and Q) to the intermediate
frequency (IF). At IF (2 MHz), the complex
I/Q signal is filtered and amplified, and
then digitized by the ADCs. Automatic
gain control, final channel filtering, despreading, symbol correlation and byte
synchronisation are performed digitally.
When the SFD pin goes active, this
indicates that a start of frame delimiter has
been detected. CC2420 buffers the
received data in a 128 byte receive FIFO.
The user may read the FIFO through an
SPI interface. CRC is verified in hardware.
RSSI and correlation values are appended
to the frame. CCA is available on a pin in
receive mode. Serial (unbuffered) data
modes are also available for test
purposes.
The CC2420 transmitter is based on direct
up-conversion. The data is buffered in a
128 byte transmit FIFO (separate from the
receive FIFO). The preamble and start of
frame delimiter are generated by
hardware. Each symbol (4 bits) is spread
using the IEEE 802.15.4 spreading
sequence to 32 chips and output to the
digital-to-analog converters (DACs).
An analog low pass filter passes the signal
to the quadrature (I and Q) upconversion
mixers. The RF signal is amplified in the
power amplifier (PA) and fed to the
antenna.
The internal T/R switch circuitry makes the
antenna interface and matching easy. The
RF connection is differential. A balun may
be used for single-ended antennas. The
biasing of the PA and LNA is done by
connecting TXRX_SWITCH to RF_P and
RF_N through an external DC path.
The frequency synthesizer includes a
completely on-chip LC VCO and a 90
SWRS041c
Page 17 of 85
CC2420
degrees phase splitter for generating the I
and Q LO signals to the down-conversion
mixers in receive mode and up-conversion
mixers in transmit mode. The VCO
operates in the frequency range 4800 –
4966 MHz, and the frequency is divided by
two when split in I and Q.
A crystal must be connected to
XOSC16_Q1
and
XOSC16_Q2
and
provides the reference frequency for the
synthesizer. A digital lock signal is
available from the PLL.
The digital baseband includes support for
frame handling, address recognition, data
buffering and MAC security.
The 4-wire SPI serial interface is used for
configuration and data buffering.
An on-chip voltage regulator delivers the
regulated 1.8 V supply voltage. The
voltage regulator may be enabled /
disabled through a separate pin.
A battery monitor may optionally be used
to monitor the unregulated power supply
voltage.
The
battery
monitor
is
configurable through the SPI interface.
SWRS041c
Page 18 of 85
CC2420
9
Application Circuit
Few external components are required for
the operation of CC2420. A typical
application circuit is shown in Figure 4.
The external components shown are
described in Table 1 and typical values are
given in Table 2. Note that most
decoupling capacitors are not shown on
the application circuits. For the complete
reference design please refer to Texas
Instrument’s web site: http://www.ti.com.
9.1
Input / output matching
The RF input/output is high impedance
and differential. The optimum differential
load for the RF port is 95+j187 .
When using an unbalanced antenna such
as a monopole, a balun should be used in
order to optimise performance. The balun
can be implemented using low-cost
discrete inductors and capacitors only or in
combination with transmission lines.
Figure 3 shows the balun implemented in a
two-layer reference design. It consists of a
half wave transmission line, C81, L61, L71
and L81. The circuit will present the
optimum RF termination to CC2420 with a
50 load on the antenna connection. This
circuit has improved EVM performance,
sensitivity and harmonic suppression
compared to the design in Figure 4.
Please refer to the input/output matching
section on page 54 for more details.
The balun in Figure 4 consists of C61,
C62, C71, C81, L61, L62 and L81, and will
present the optimum RF termination to
CC2420 with a 50 load on the antenna
connection. A low pass filter may be added
to add margin to the FCC requirement on
second harmonic level.
If a balanced antenna such as a folded
dipole is used, the balun can be omitted. If
the antenna also provides a DC path from
the TXRX_SWITCH pin to the RF pins,
inductors are not needed for DC bias.
Figure 5 shows a suggested application
circuit using a differential antenna. The
antenna type is a standard folded dipole.
The dipole has a virtual ground point;
hence bias is provided without degradation
in antenna performance.
9.2
Bias resistor
The bias resistor R451 is used to set an
accurate bias current.
9.3
Crystal
An external crystal with two loading
capacitors (C381 and C391) is used for
the crystal oscillator. See page 53 for
details.
9.4
Voltage regulator
The on chip voltage regulator supplies all
1.8 V power supply inputs. C42 is required
for stability of the regulator. A series
resistor may be used to comply with the
ESR requirement.
9.5
Power supply decoupling and
filtering
Proper power supply decoupling must be
used for optimum performance. The
placement and size of the decoupling
capacitors and the power supply filtering
are very important to achieve the best
performance in an application. Texas
Instruments provides a compact reference
design that should be followed very
closely..
SWRS041c
Page 19 of 85
CC2420
Ref
Description
C42
Voltage regulator load capacitance
C61
Balun and match
C62
DC block to antenna and match
C71
Front-end bias decoupling and match
C81
Balun and match
C381
16MHz crystal load capacitor, see page 53
C391
16MHz crystal load capacitor, see page 53
L61
DC bias and match
L62
DC bias and match
L71
DC bias and match
L81
Balun and match
R451
Precision resistor for current reference generator
XTAL
16MHz crystal, see page 53
Table 1. Overview of external components
3.3 V
Power
supply
C391
C381
C42
R451
C81
L81
L71
XOSC16_Q2 38
AVDD_XOSC16 37
NC 40
VREG_EN 41
VREG_IN 43
XOSC16_Q1 39
NC 36
2 AVDD_VCO
DVDD_RAM 35
3
AVDD_PRE
SO 34
4
AVDD_RF1
5
GND
6
RF_P
7
TXRX_SWITCH
8
RF_N
9
GND
SI 33
CC2420
SCLK 32
QLP48
RF
7x7
L61
CSn 31
FIFO 30
Transceiver
FIFOP 29
CCA 28
10 AVDD_SW
SFD 27
11 NC
DVDD1.8 26
DSUB_CORE 24
DSUB_PADS 23
DGND 22
RESETn 21
DGUARD 20
DGND_GUARD 19
DVDD_ADC 18
NC 16
AVDD_ADC 17
AVDD_IF2 15
NC 13
AVDD_RF2 14
12 NC
Digital Interface
Antenna
(50 Ohm)
VREG_OUT 42
1 VCO_GUARD
AVDD_IF1 44
ATEST2 46
R_BIAS 45
ATEST1 47
AVDD_CHP 48
XTAL
DVDD3.3 25
Figure 3. Typical application circuit with transmission line balun for single-ended
operation
SWRS041c
Page 20 of 85
CC2420
3.3 V
Power
supply
C391
C381
R451
C62
C71
L81
C81
L61
XOSC16_Q2 38
AVDD_XOSC16 37
XOSC16_Q1 39
NC 40
VREG_EN 41
VREG_OUT 42
NC 36
2 AVDD_VCO
DVDD_RAM 35
3
AVDD_PRE
SO 34
4
AVDD_RF1
SI 33
5
GND
6
RF_P
C61
L62
XTAL
CC2420
7
TXRX_SWITCH
8
RF_N
9
GND
SCLK 32
QLP48
RF
7x7
CSn 31
FIFO 30
Transceiver
Digital Interface
Antenna
(50 Ohm)
VREG_IN 43
R_BIAS 45
1 VCO_GUARD
AVDD_IF1 44
ATEST2 46
ATEST1 47
AVDD_CHP 48
C42
FIFOP 29
CCA 28
10 AVDD_SW
SFD 27
11 NC
DVDD1.8 26
DSUB_CORE 24
DGND 22
DSUB_PADS 23
RESETn 21
DGUARD 20
DVDD_ADC 18
DGND_GUARD 19
NC 16
AVDD_ADC 17
AVDD_IF2 15
NC 13
AVDD_RF2 14
12 NC
DVDD3.3 25
Figure 4. Typical application circuit with discrete balun for single-ended operation
SWRS041c
Page 21 of 85
CC2420
3.3 V
Power
supply
C391
C381
R451
L61
AVDD_XOSC16 37
XOSC16_Q2 38
XOSC16_Q1 39
NC 40
VREG_EN 41
VREG_IN 43
XTAL
NC 36
2 AVDD_VCO
DVDD_RAM 35
3
AVDD_PRE
SO 34
4
AVDD_RF1
5
GND
6
RF_P
CC2420
7
TXRX_SWITCH
8
RF_N
9
GND
L71
SI 33
SCLK 32
QLP48
RF
7x7
CSn 31
FIFO 30
Transceiver
Digital Interface
Folded
dipole
antenna
VREG_OUT 42
1 VCO_GUARD
AVDD_IF1 44
R_BIAS 45
ATEST2 46
ATEST1 47
AVDD_CHP 48
C42
FIFOP 29
CCA 28
10 AVDD_SW
SFD 27
11 NC
DVDD1.8 26
DSUB_CORE 24
DGND 22
DSUB_PADS 23
DGUARD 20
RESETn 21
DGND_GUARD 19
DVDD_ADC 18
AVDD_ADC 17
NC 16
AVDD_IF2 15
NC 13
AVDD_RF2 14
12 NC
DVDD3.3 25
Figure 5. Suggested application circuit with differential antenna (folded dipole)
SWRS041c
Page 22 of 85
CC2420
Item
Single
ended
output,
transmission line balun
Single
ended
discrete balun
output,
Differential antenna
C42
10 μF, 0.5 < ESR < 5
10 μF, 0.5 < ESR < 5
10 μF, 0.5 < ESR < 5
C61
Not used
0.5 pF, +/- 0.25pF, NP0, 0402
Not used
C62
Not used
5.6 pF, +/- 0.25pF, NP0, 0402
Not used
C71
Not used
5.6 pF, 10%, X5R, 0402
Not used
C81
5.6 pF, +/- 0.25pF, NP0, 0402
0.5 pF, +/- 0.25pF, NP0, 0402
Not used
C381
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
C391
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
L61
8.2 nH, 5%,
Monolithic/multilayer, 0402
7.5 nH, 5%,
Monolithic/multilayer, 0402
27 nH, 5%, Monolithic/multilayer,
0402
L62
Not used
5.6 nH, 5%,
Monolithic/multilayer, 0402
Not used
L71
22 nH, 5%,
Monolithic/multilayer, 0402
Not used
12 nH, 5%, Monolithic/multilayer,
0402
L81
1.8 nH, +/- 0.3nH,
Monolithic/multilayer, 0402
7.5 nH, 5%,
Monolithic/multilayer, 0402
Not used
R451
43 k, 1%, 0402
43 k, 1%, 0402
43 k, 1%, 0402
XTAL
16 MHz crystal, 16 pF load
(CL),
ESR < 60
16 MHz crystal, 16 pF load
(CL),
ESR < 60
16 MHz crystal, 16 pF load (CL),
ESR < 60
Table 2. Bill of materials for the application circuits
SWRS041c
Page 23 of 85
CC2420
10 IEEE 802.15.4 Modulation Format
least significant byte is transmitted first,
except for security related fields where the
most significant byte it transmitted first.
This section is meant as an introduction to
the 2.4 GHz direct sequence spread
spectrum (DSSS) RF modulation format
defined in IEEE 802.15.4. For a complete
description, please refer to [1].
Each symbol is mapped to one out of 16
pseudo-random sequences, 32 chips
each. The symbol to chip mapping is
shown in Table 3. The chip sequence is
then transmitted at 2 MChips/s, with the
least significant chip (C0) transmitted first
for each symbol.
The modulation and spreading functions
are illustrated at block level in Figure 6 [1].
Each byte is divided into two symbols, 4
bits each. The least significant symbol is
transmitted first. For multi-byte fields, the
Transmitted
bit-stream
(LSB first)
Bit-toSymbol
Symbolto-Chip
O-QPSK
Modulator
Modulated
Signal
Figure 6. Modulation and spreading functions [1]
Symbol
Chip sequence (C0, C1, C2, … , C31)
0
11011001110000110101001000101110
1
11101101100111000011010100100010
2
00101110110110011100001101010010
3
00100010111011011001110000110101
4
01010010001011101101100111000011
5
00110101001000101110110110011100
6
11000011010100100010111011011001
7
10011100001101010010001011101101
8
10001100100101100000011101111011
9
10111000110010010110000001110111
10
01111011100011001001011000000111
11
01110111101110001100100101100000
12
00000111011110111000110010010110
13
01100000011101111011100011001001
14
10010110000001110111101110001100
15
11001001011000000111011110111000
Table 3. IEEE 802.15.4 symbol-to-chip mapping [1]
The modulation format is Offset –
Quadrature Phase Shift Keying (O-QPSK)
with half-sine chip shaping. This is
equivalent to MSK modulation. Each chip
is shaped as a half-sine, transmitted
alternately in the I and Q channels with
one half chip period offset. This is
illustrated for the zero-symbol in Figure 7.
SWRS041c
Page 24 of 85
CC2420
TC
I-phase
1
Q-phase
0
1
0
1
1
0
1
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
1
1
0
1
0
2TC
Figure 7. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 μs
11 Configuration Overview
CC2420 can be configured to achieve the
best performance for different applications.
Through the programmable configuration
registers the following key parameters can
be programmed:
Power-down / power-up mode
Crystal oscillator power-up / power
down
Clear Channel Assessment mode
Packet handling hardware support
Encryption / Authentication modes
SWRS041c
Page 25 of 85
Receive / transmit mode
RF channel selection
RF output power
CC2420
12 Evaluation Software
Texas Instruments (TI) provides users of
CC2420 with a software program,
®
SmartRF
Studio (Windows interface)
which may be used for radio performance
and functionality evaluation. SmartRF®
Studio can be downloaded from TI’s web
page: http://www.ti.com. Figure 8 shows
the user interface of the CC2420
configuration software.
Figure 8. SmartRF Studio user interface
SWRS041c
Page 26 of 85
CC2420
13 4-wire Serial Configuration and Data Interface
CC2420 is configured via a simple 4-wire
SPI-compatible interface (pins SI, SO,
SCLK and CSn) where CC2420 is the slave.
This interface is also used to read and
write buffered data (see page 39). All
address and data transfer on the SPI
interface is done most significant bit first.
13.1 Pin configuration
The digital inputs SCLK, SI and CSn are
high-impedance inputs (no internal pull-up)
and should have external pull-ups if not
driven. SO is high-impedance when CSn is
high. An external pull-up should be used at
SO to prevent floating input at
microcontroller. Unused I/O pins on the
MCU can be set to outputs with a fixed ‘0’
level to avoid leakage currents.
13.2 Register access
There are 33 16-bit configuration and
status registers, 15 command strobe
registers, and two 8-bit registers to access
the separate transmit and receive FIFOs.
Each of the 50 registers is addressed by a
6-bit address. The RAM/Register bit (bit 7)
must be cleared for register access. The
Read/Write bit (bit 6) selects a read or a
write operation and makes up the 8-bit
address field together with the 6-bit
address.
In each register read or write cycle, 24 bits
are sent on the SI-line. The CSn pin (Chip
Select, active low) must be kept low during
this transfer. The bit to be sent first is the
RAM/Register bit (set to 0 for register
access), followed by the R/W bit (0 for
write, 1 for read). The following 6 bits are
the address-bits (A5:0). A5 is the most
significant bit of the address and is sent
first. The 16 data-bits are then transferred
(D15:0), also MSB first. See Figure 9 for
an illustration.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The R/W bit must
be set high to initiate the data read-back.
CC2420 then returns the data from the
addressed register on the 16 clock cycles
following the register address. The SO pin
is used as the data output and must be
configured
as
an
input
by the
microcontroller.
The timing for the programming is also
shown in Figure 9 with reference to Table
4. The clocking of the data on SI into the
CC2420 is done on the positive edge of
SCLK. When the last bit, D0, of the 16
data-bits has been written, the data word
is loaded in the internal configuration
register.
Multiple registers may be written without
releasing CSn, as described in the Multiple
SPI access section on page 31.
The register data will be retained during
power down mode, but not when the
power-supply is turned off (e.g. by
disabling the voltage regulator using the
VREG_EN pin). The registers can be
programmed in any order.
SWRS041c
Page 27 of 85
CC2420
tsp
tch
tcl
thd
tsd
tns
SCLK
CSn
Write to register / RXFIFO:
SI
0
0
A5
A4
A3
A2
A1
A0
SO
S7
S6
S5
S4
S3
S2
S1
S0
X
DW15 DW14 DW13 DW12 DW11 DW10
DW9
DW8
X
DW7
DW6
DW5
DW4
DW3
DW2
DW1
DW0
X
DW7
DW6
DW5
DW4
DW3
DW2
DW1
DW0
X
S6
S5
S4
S3
S2
S1
S0
DR6
DR5
DR4
DR3
DR2
DR1
DR0
X
Write to TXFIFO:
SI
0
0
A5
A4
A3
A2
A1
A0
SO
S7
S6
S5
S4
S3
S2
S1
S0
X
DW7
S7
DW6
DW5
DW4
DW3
DW2
DW1
DW0
S6
S5
S4
S3
S2
S1
S0
X
S7
DR9
DR8
DR7
X
X
S7
Read from register / RXFIFO:
SI
0
1
A5
A4
A3
A2
A1
A0
SO
S7
S6
S5
S4
S3
S2
S1
S0
X
DR15
DR14 DR13 DR12 DR11 DR10
DR15
Read and write one byte to RAM: (multiple read / writes also possible)
SI
1
A6
A5
A4
A3
A2
A1
A0
SO
S7
S6
S5
S4
S3
S2
S1
S0
X
B1
B0
0
X
X
X
X
X
DW6
DW5
DW4
DW3
DW2
DW1
DW0
X
DR7
DW7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR7
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR7
Read one byte from RAM: (multiple reads also possible)
SI
1
A6
A5
A4
A3
A2
A1
A0
SO
S7
S6
S5
S4
S3
S2
S1
S0
X
B1
B0
1
X
X
X
X
X
X
X
Figure 9. SPI timing diagram
Parameter
Symbol
Min
Max
Units
10
MHz
Conditions
SCLK, clock
frequency
FSCLK
SCLK low
pulse
duration
tcl
25
ns
The minimum time SCLK must be low.
SCLK high
pulse
duration
tch
25
ns
The minimum time SCLK must be high.
CSn setup
time
tsp
25
ns
The minimum time CSn must be low before the
first positive edge of SCLK.
CSn hold time
tns
25
ns
The minimum time CSn must be held low after the
last negative edge of SCLK.
SI setup time
tsd
25
ns
The minimum time data on SI must be ready
before the positive edge of SCLK.
SI hold time
thd
25
ns
The minimum time data must be held at SI, after
the positive edge of SCLK.
Rise time
trise
100
ns
The maximum rise time for SCLK and CSn
Fall time
tfall
100
ns
The maximum fall time for SCLK and CSn
Note: The set-up- and hold-times refer to 50% of VDD.
Table 4. SPI timing specification
13.3 Status byte
pin. The status byte contains 6 status bits
which are described in Table 5.
During transfer of the register access byte,
command strobes, the first RAM address
byte and data transfer to the TXFIFO, the
CC2420 status byte is returned on the SO
Issuing a SNOP (no operation) command
strobe may be used to read the status
byte. It may also be read during access to
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CC2420
chip functions such as register or FIFO
access.
Bit #
Name
Description
7
-
Reserved, ignore value
6
XOSC16M_STABLE
Indicates whether the 16 MHz oscillator is running or not
0 : The 16 MHz crystal oscillator is not running
1 : The 16 MHz crystal oscillator is running
5
TX_UNDERFLOW
Indicates whether an FIFO underflow has occurred during
transmission. Must be cleared manually with a SFLUSHTX
command strobe.
0 : No underflow has occurred
1 : An underflow has occurred
4
ENC_BUSY
Indicates whether the encryption module is busy
0 : Encryption module is idle
1 : Encryption module is busy
3
TX_ACTIVE
Indicates whether RF transmission is active
0 : RF Transmission is idle
1 : RF Transmission is active
2
LOCK
Indicates whether the frequency synthesizer PLL is in lock or not
0 : The PLL is out of lock
1 : The PLL is in lock
1
RSSI_VALID
Indicates whether the RSSI value is valid or not.
0 : The RSSI value is not valid
1 : The RSSI value is valid, always true when reception has been
enabled at least 8 symbol periods (128 us)
0
-
Reserved, ignore value
Table 5. Status byte returned during address transfer and TXFIFO writing
13.4 Command strobes
Command strobes may be viewed as
single byte instructions to CC2420. By
addressing a command strobe register
internal sequences will be started. These
commands must be used to enable the
crystal oscillator, enable receive mode,
start decryption etc. All 15 command
strobes are listed in Table 11 on page 62.
When the crystal oscillator is disabled
(Power Down state in Figure 25 on page
44), only the SXOSCON command strobe
may be used. All other command strobes
will be ignored and will have no effect. The
crystal oscillator must stabilise (see the
XOSC16M_STABLE status bit in Table 5)
before other command strobes are
accepted.
The command strobe register is accessed
in the same way as for a register write
operation, but no data is transferred. That
is, only the RAM/Register bit (set to 0),
R/W bit (set to 0) and the 6 address bits
(in the range 0x00 through 0x0E) are
written. A command strobe may be
followed by any other SPI access without
pulling CSn high, and is executed on the
last falling edge on SCLK.
13.5 RAM access
The internal 368 byte RAM may be
accessed through the SPI interface. Single
or multiple bytes may be read or written
sending the address part (2 bytes) only
once. The address is then automatically
incremented by the CC2420 hardware for
each new byte. Data is read and written
one byte at a time, unlike register access
where 2 bytes are always required after
each address byte.
The crystal oscillator must be running
when accessing the RAM.
The RAM/Register bit must be set high to
enable RAM access. The 9 bit RAM
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CC2420
address consists of two parts, B1:0 (MSB)
selecting one of the three memory banks
and A6:0 (LSB) selecting the address
within the selected bank. The RAM is
divided into three memory banks: TXFIFO
(bank 0), RXFIFO (bank 1) and security
(bank 2). The FIFO banks are 128 bytes
each, while the security bank is 112 bytes.
For RAM read, the selected byte(s) are
output on the SO pin directly after the
second address byte.
See Figure 10 for an illustration on how
multiple RAM bytes may be read or written
in one operation.
The RAM memory space is shown in
Table 6. The lower 256 bytes are used to
store FIFO data. Note that RAM access
should never be used for FIFO write
operations because the FIFO counter will
not be updated. Use RXFIFO and TXFIFO
access instead as described in section
FIFO access.
A6:0 is transmitted directly after the
RAM/Register bit as shown in Figure 9.
For RAM access, a second byte is also
required before the data transfer. This byte
contains B1:0 in bits 7 and 6, followed by
the R/W bit (0 for read+write, 1 for read).
Bits 4 through 0 are don’t care as shown in
Figure 9.
As with register data, data stored in RAM
will be retained during power down mode,
but not when the power-supply is turned
off (e.g. by disabling the voltage regulator
using the VREG_EN pin).
For RAM write, data to be written must be
input on the SI pin directly after the
second address byte. RAM data read is
output on the SO pin simultaneously, but
may be ignored by the user if only writing
is of interest.
CSn:
Command strobe:
ADDR
Multiple command strobes:
ADDR
ADDR
ADDR
Read or write a whole register (16 bit):
ADDR
DATA8MSB
DATA8LSB
Read 8 MSB of a register:
ADDR
DATA8MSB
ADDR
DATA8MSB
DATA8LSB
ADDR
DATA8MSB
...
ADDRFIFO
DATAbyte0
DATAbyte1
DATAbyte2
DATAbyte3
...
DATAbyte n-3 DATAbyte n-2 DATAbyte n-1
ADDRLRAM ADDRHRAM DATAADDR DATAADDR+1 DATAADDR+2 ...
DATAADDR+n
Multiple register read or write
Read or write n bytes from/to RF FIFO:
Read or write n bytes from/to RAM:
Note:
...
...
ADDR
ADDR
ADDR
DATA8MSB
DATA8LSB
FIFO and RAM access must be terminated with setting the CSn pin high.
Command strobes and register access may be followed by any other access,
since they are completed on the last negative edge on SCLK. They may however also be
terminated with setting CSn high, if desirable, e.g. for reading only 8 bits from a configuration
register.
Figure 10. Configuration registers write and read operations via SPI
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CC2420
Address
Byte Ordering
Name
Description
0x16F –
0x16C
-
-
Not used
0x16B –
0x16A
MSB
LSB
SHORTADR
16-bit Short address, used for address recognition.
0x169 –
0x168
MSB
LSB
PANID
16-bit PAN identifier, used for address recognition.
0x167 –
0x160
MSB
LSB
IEEEADR
64-bit IEEE address of current node, used for address
recognition.
0x15F –
0x150
MSB
LSB
CBCSTATE
Temporary storage for CBC-MAC calculations
0x14F –
0x140
MSB (Flags)
LSB
TXNONCE / TXCTR
Transmitter nonce for in-line authentication and
transmitter counter for in-line encryption.
0x13F –
0x130
MSB
LSB
KEY1
Encryption key 1
0x12F –
0x120
MSB
LSB
SABUF
Stand-alone encryption buffer, for plaintext input and
ciphertext output
0x11F –
0x110
MSB (Flags)
LSB
RXNONCE / RXCTR
Receiver nonce for in-line authentication or
receiver counter for in-line decryption.
0x10F –
0x100
MSB
LSB
KEY0
Encryption key 0
0x0FF –
0x080
MSB
LSB
RXFIFO
128 bytes receive FIFO
0x07F –
0x000
MSB
LSB
TXFIFO
128 bytes transmit FIFO
Table 6. CC2420 RAM Memory Space
13.6 FIFO access
The TXFIFO and RXFIFO may be
accessed through the TXFIFO (0x3E) and
RXFIFO (0x3F) registers.
The TXFIFO is write only, but may be read
back using RAM access as described in
the previous section. Data is read and
written one byte at a time, as with RAM
access. The RXFIFO is both writeable and
readable. Writing to the RXFIFO should
however only be done for debugging or for
using the RXFIFO for security operations
(decryption / authentication).
The crystal oscillator must be running
when accessing the FIFOs.
When writing to the TXFIFO, the status
byte (see Table 5) is output for each new
data byte on SO, as shown in Figure 9.
This could be used to detect TXFIFO
underflow (see section RF Data Buffering
section on page 39) while writing data to
the TXFIFO.
Multiple FIFO bytes may be accessed in
one operation, as with the RAM access.
FIFO access can only be terminated by
setting the CSn pin high once it has been
started.
The FIFO and FIFOP pins also provide
additional information on the data in the
receive FIFO, as will be described in the
Microcontroller
Interface
and
Pin
Description section on page 32. Note that
the FIFO and FIFOP pins only apply to the
RXFIFO. The TXFIFO has its underflow
flag in the status byte.
The TXFIFO may be flushed by issuing a
SFLUSHTX command strobe. Similarly, a
SFLUSHRX command strobe will flush the
receive FIFO.
13.7 Multiple SPI access
Register access, command strobes, FIFO
access and RAM access may be issued
continuously without setting CSn high.
E.g. the user may issue a command
strobe, a register write and writing 3 bytes
to the TXFIFO in one operation, as
illustrated in Figure 11. The only exception
is that FIFO and RAM access must be
terminated by setting CSn high.
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CC2420
CSn
SI
ADDR
ADDR
-
-
SO
Status
Status
DATA8MSB
DATA8LSB
Command
Strobe
ADDRTXFIFO DATAADDR DATAADDR+1 DATAADDR+2
Status
Status
Register
Read
Status
Status
TXFIFO
Write
Figure 11. Multiple SPI Access Example
14 Microcontroller Interface and Pin Description
When used in a typical system, CC2420 will
interface to a microcontroller. This
microcontroller must be able to:
Program CC2420 into different modes,
read and write buffered data, and read
back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLK and CSn).
Interface to the receive and transmit
FIFOs using the FIFO and FIFOP
status pins.
Interface to the CCA pin for clear
channel assessment.
Interface to the SFD pin for timing
information (particularly for beaconing
networks).
microcontroller uses 4 I/O pins for the SPI
configuration interface (SI, SO, SCLK and
CSn). SO should be connected to an input
at the microcontroller. SI, SCLK and CSn
must
be
microcontroller
outputs.
Preferably the microcontroller should have
a hardware SPI interface.
The microcontroller pins connected to SI,
SO and SCLK can be shared with other
SPI-interface devices. SO is a high
impedance output as long as CSn is not
activated (active low).
CSn should have an external pull-up
resistor or be set to a high level when the
voltage regulator is turned off in order to
prevent the input from floating. SI and
SCLK should be set to a defined level to
prevent the inputs from floating.
14.1 Configuration interface
A CC2420 to microcontroller interface
example is shown in Figure 12. The
C
CC2420
FIFO
GIO0
FIFOP
Interrupt
CCA
GIO1
SFD
Timer Capture
CSn
SI
SO
SCLK
GIO2
MOSI
MISO
SCLK
Figure 12. Microcontroller interface example
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CC2420
14.2 Receive mode
In receive mode, the SFD pin goes active
after the start of frame delimiter (SFD) field
has been completely received. If address
recognition is disabled or is successful, the
SFD pin goes inactive again only after the
last byte of the MPDU has been received.
If the received frame fails address
recognition, the SFD pin goes inactive
immediately. This is illustrated in Figure
13.
The FIFO pin is active when there are one
or more data bytes in the RXFIFO. The
first byte to be stored in the RXFIFO is the
length field of the received frame, i.e. the
FIFO pin goes active when the length field
is written to the RXFIFO. The FIFO pin
then remains active until the RXFIFO is
empty.
If a previously received frame is
completely or partially inside the RXFIFO,
the FIFO pin will remain active until the
RXFIFO is empty.
The FIFOP pin is active when the number
of unread bytes in the RXFIFO exceeds
the
threshold
programmed
into
IOCFG0.FIFOP_THR. When address
recognition is enabled the FIFOP pin will
remain inactive until the incoming frame
passes address recognition, even if the
number of bytes in the RXFIFO exceeds
the programmed threshold.
The FIFOP pin will also go active when
the last byte of a new packet is received,
even if the threshold is not exceeded. If
so, the FIFOP pin will go inactive once
one byte has been read out of the
RXFIFO.
When address recognition is enabled, data
should not be read out of the RXFIFO
before the address is completely received,
since the frame may be automatically
flushed by CC2420 if it fails address
recognition. This may be handled by using
the FIFOP pin, since this pin does not go
active until the frame passes address
recognition.
Figure 14 shows an example of pin activity
when reading a packet from the RXFIFO.
In this example, the packet size is 8 bytes,
IOCFG0.FIFOP_THR
=
3
and
MODEMCTRL0.AUTOCRC is set. The length
will be 8 bytes, RSSI will contain the
average RSSI level during reception of the
packet and FCS/corr contains information
of FCS check result and the correlation
levels.
14.3 RXFIFO overflow
The RXFIFO can only contain a maximum
of 128 bytes at a given time. This may be
divided between multiple frames, as long
as the total number of bytes is 128 or less.
If an overflow occurs in the RXFIFO, this is
signalled to the microcontroller by making
the FIFO pin go inactive while the FIFOP
pin is active. Data already in the RXFIFO
will not be affected by the overflow, i.e.
frames already received may be read out.
A SFLUSHRX command strobe is required
after an RXFIFO overflow to enable
reception of new data. Note that the
SFLUSHRX command strobe should be
issued twice to ensure that the SFD pin
goes back to its inactive state.
For security enabled frames, the MAC
layer must read the source address of the
received frame before it can decide which
key to use to decrypt or authenticate. This
data must therefore not be overwritten
even if it has been read out of the RXFIFO
by
the
microcontroller.
If
the
SECCTRL0.RXFIFO_PROTECTION control
bit is set, CC2420 also protects the frame
header of security enabled frames until
decryption has been performed. If no MAC
security is used or if it is implemented
outside the CC2420, this bit may be cleared
to achieve optimal use of the RXFIFO.
SWRS041c
Page 33 of 85
CC2420
on
ed
iv
ce
re
d
e
te
ct
by
te
th
de
D
ng
e
F
L
S
Data received over RF
Address
recognition OK
iti
gn
co
re
s d
es te
dr le
Ad omp
c
U d
PD eive
t M rec
s
La yte
b
Preamble
SFD Length
MAC Protocol Data Unit (MPDU) with correct address
Preamble
SFD Length
MAC Protocol Data Unit (MPDU) with wrong address
SFD Pin
FIFO Pin
FIFOP Pin, if threshold
higher than frame length
FIFOP Pin, if threshold
lower than frame length
Data received over RF
Address
recognition fails
SFD Pin
FIFO Pin
FIFOP Pin
Figure 13. Pin activity examples during receive
n
he
w te
w by
o
l st
es la
go t of
FO ou
FI ad s
re tart
s
gh f
hi r o
ns be HR
i
a
m um _T
re n P
P as IFO
FO ng F
FI s lo s >
a yte
b
SCLK
SFD
CSn
SI
ADDRTXFIFO
-
-
-
-
-
-
-
-
-
SO
Status
Length
PSDU0
PSDU1
PSDU2
PSDU3
PSDU4
PSDU5
RSSI
FCS/Corr
FIFOP
FIFO
Figure 14. Example of pin activity when reading RXFIFO.
14.4 Transmit mode
During transmit the FIFO and FIFOP pins
are still only related to the RXFIFO. The
SFD pin is however active during
transmission of a data frame, as shown in
Figure 15.
The SFD pin goes active when the SFD
field has been completely transmitted. It
goes inactive again when the complete
MPDU (as defined by the length field) has
been transmitted or if an underflow is
detected. See the RF Data Buffering
section on page 39 for more information
on TXFIFO underflow.
As can be seen from comparing Figure 13
and Figure 15, the SFD pin behaves very
similarly during reception and transmission
of a data frame. If the SFD pins of the
transmitter and the receiver are compared
during the transmission of a data frame, a
small delay of approximately 2 μs can be
seen because of bandwidth limitations in
both the transmitter and the receiver.
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CC2420
d
m
m
co
an
N
XO e
ST trob
s
Data transmitted
over RF
d
U itte
PD sm w
o
M
n
l
f
st tra er
La yte nd
b Xu
T
ed
D
tra
itt
m
ns
SF
Preamble
SFD
Length
MAC Protocol Data Unit (MPDU)
SFD Pin
12 symbol periods
Automatically generated
preamble and SFD
Data fetched
from TXFIFO
CRC generated
by CC2420
Figure 15. Pin activity example during transmit
14.5 General control and status pins
In receive mode, the FIFOP pin can be
used to interrupt the microcontroller when
a threshold has been exceeded or a
complete frame has been received. This
pin should then be connected to a
microcontroller interrupt pin.
In receive mode, the FIFO pin can be
used to detect if there is data at all in the
receive FIFO.
The SFD pin can be used to extract the
timing information of transmitted and
received data frames. The SFD pin will go
active when a start of frame delimiter has
been completely detected / transmitted.
The SFD pin should preferably be
connected to a timer capture pin on the
microcontroller.
For debug purposes, the SFD and CCA
pins can be used to monitor several status
signals as selected by the IOCFG1
register. See Table 12 and Table 13 for
available signals.
The polarity of FIFO, FIFOP, SFD and CCA
can be controlled by the IOCFG0 register
(address 0x1C).
15 Demodulator, Symbol Synchroniser and Data Decision
The block diagram for the CC2420
demodulator is shown in Figure 16.
Channel filtering and frequency offset
compensation is performed digitally. The
signal level in the channel is estimated to
generate the RSSI level (see the RSSI /
Energy Detection section on page 48 for
more information). Data filtering is also
included for enhanced performance.
With the ±40 ppm frequency accuracy
requirement from [1], a compliant receiver
must be able to compensate for up to 80
ppm or 200 kHz. The CC2420 demodulator
tolerates up to 300 kHz offset without
significant degradation of the receiver
performance.
Soft decision is used at the chip level, i.e.
the demodulator does not make a decision
for each chip, only for each received
symbol. De-spreading is performed using
over sampled symbol correlators. Symbol
synchronisation is achieved by a
continuous start of frame delimiter (SFD)
search.
When a SFD is detected, data is written to
the RXFIFO and may be read out by the
microcontroller at a lower bit rate than the
250 kbps generated by the receiver.
The CC2420 demodulator also handles
symbol rate errors in excess of 120 ppm
without
performance
degradation.
Resynchronisation
is
performed
continuously to adjust for error in the
incoming symbol rate.
The RXCTRL1.RXBPF_LOCUR control bit
should be written to 1.
The MDMCTRL1.CORR_THR control bits
are by default set to 20 defining the
threshold for detecting IEEE 802.15.4 start
of frame delimiters.
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or
CC2420
I / Q Analog
IF signal
Digital
IF Channel
Filtering
ADC
Frequency
Offset
Compensation
RSSI
Generator
Digital
Data
Filtering
Symbol
Correlators and
Synchronisation
Data
Symbol
Output
Average
Correlation
Value (may be
used for LQI)
RSSI
Figure 16. Demodulator Simplified Block Diagram
16 Frame Format
CC2420 has hardware support for parts of
the IEEE 802.15.4 frame format. This
section gives a brief summary to the IEEE
802.15.4 frame format, and describes how
CC2420 is set up to comply with this.
Figure 17 [1] shows a schematic view of
the IEEE 802.15.4 frame format. Similar
figures describing specific frame formats
(data
frames,
beacon
frames,
acknowledgment
frames
and
MAC
command frames) are included in [1].
Bytes:
1
0 to 20
2
Frame
Data
Address
Control Field
Sequence
Information
(FCF)
Number
MAC Header (MHR)
MAC
Layer
Bytes:
PHY
Layer
1
1
Start of frame
Frame
Delimiter
Length
(SFD)
Synchronisation Header
PHY Header
(SHR)
(PHR)
n
Frame payload
MAC Payload
2
Frame Check
Sequence
(FCS)
MAC Footer
(MFR)
5 + (0 to 20) + n
MAC Protocol
Data Unit
(MPDU)
PHY Service Data Unit
(PSDU)
4
Preamble
Sequence
11 + (0 to 20) + n
PHY Protocol Data Unit
(PPDU)
Figure 17. Schematic view of the IEEE 802.15.4 Frame Format [1]
16.1 Synchronisation header
The synchronisation header (SHR)
consists of the preamble sequence
followed by the start of frame delimiter
(SFD). In [1], the preamble sequence is
defined to be 4 bytes of 0x00. The SFD is
one byte, set to 0xA7.
In CC2420, the preamble length and SFD is
configurable. The default values are
compliant with [1]. Changing these values
will make the system non-compliant to
IEEE 802.15.4.
A synchronisation header is always
transmitted first in all transmit modes.
The preamble sequence length can be set
by MDMCTRL0.PREAMBLE_LENGTH, while
the SFD is programmed in the SYNCWORD
register. SYNCWORD is 2 bytes long, which
gives the user some extra flexibility as
described below. Figure 18 shows how the
CC2420 synchronisation header relates to
the IEEE 802.15.4 specification.
The programmable preamble length only
applies to transmission, it does not affect
receive mode. The preamble length should
not be set shorter than the default value.
Note that 2 of the 8 zero-symbols in the
preamble sequence required by [1] are
included in the SYNCWORD register so that
the CC2420 preamble sequence is only 6
symbols long for compliance with [1]. Two
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CC2420
A. If SYNCWORD = 0xA70F, CC2420 will
require the incoming symbol sequence of
(from left to right) 0 0 7 A. If SYNCWORD =
0xA700, CC2420 will require the incoming
symbol sequence of (from left to right) 0 0
0 7 A.
additional zero symbols in SYNCWORD
make CC2420 compliant with [1].
In reception, CC2420 synchronises to
received zero-symbols and searches for
the SFD sequence defined by the
SYNCWORD register. The least significant
symbols in SYNCWORD set to 0xF will be
ignored, while symbols different from 0xF
will be required for synchronisation. The
default setting of 0xA70F thereby requires
one
additional
zero-symbol
for
synchronisation. This will reduce the
number of false frames detected due to
noise.
In receive mode CC2420 uses the
preamble
sequence
for
symbol
synchronisation and frequency offset
adjustments. The SFD is used for byte
synchronisation, and is not part of the data
stored in the receive buffer (RXFIFO).
The following illustrates how the
programmed synch word is interpreted
during reception by CC2420: If SYNCWORD =
0xA7FF, CC2420 will require the incoming
symbol sequence of (from left to right) 0 7
Synchronisation Header
Preamble
IEEE 802.15.4
CC2420
0
0
0
0
SFD
0
0
2·(PREAMBLE_LENGTH + 1) zero symbols
0
0
7
A
SW0
SW1
SW2
SW3
Each box corresponds to 4 bits. Hence the preamble corresponds to 8 x 4 ''0' s or 4 bytes with the value 0.
SW0 = SYNCWORD[3:0]
if different from 'F', else '0'
SW1 = SYNCWORD[7:4]
if different from 'F', else '0'
SW2 = SYNCWORD[11:8] if different from 'F', else '0'
SW3 = SYNCWORD[15:12] if different from 'F', else '0'
Figure 18. Transmitted Synchronisation Header
16.2 Length field
The frame length field shown in Figure 17
defines the number of bytes in the MPDU.
Note that the length field does not include
the length field itself. It does however
include
the
FCS
(Frame
Check
Sequence), even if this is inserted
automatically by CC2420 hardware. It also
includes the MIC if authentication is used.
The length field is 7 bits and has a
maximum value of 127. The most
significant bit in the length field is reserved
[1], and should be set to zero.
CC2420 uses the length field both for
transmission and reception, so this field
must always be included. In transmit
mode, the length field is used for
underflow detection, as described in the
FIFO access section on page 31.
16.3 MAC protocol data unit
The FCF, data sequence number and
address information follows the length field
as shown in Figure 17. Together with the
MAC data payload and Frame Check
Sequence, they form the MAC Protocol
Data Unit (MPDU).
The format of the FCF is shown in Figure
19. Please refer to [1] for details.
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CC2420
CC2420 includes hardware address
recognition, as described in the Address
Recognition section on page 41.
There is no hardware support for the data
sequence number, this field must be
inserted and verified by software.
Bits: 0-2
3
4
5
6
7-9
10-11
12-13
14-15
Frame
Type
Security
Enabled
Frame
Pending
Acknowledge
request
Intra
PAN
Reserved
Destination
addressing
mode
Reserved
Source
addressing
mode
Figure 19. Format of the Frame Control Field (FCF) [1]
interested in the correctness of the FCS,
not the FCS sequence itself. The FCS
sequence itself is therefore not written to
the RXFIFO during receive.
16.4 Frame check sequence
A 2-byte frame check sequence (FCS)
follows the last MAC payload byte as
shown in Figure 17. The FCS is calculated
over the MPDU, i.e. the length field is not
part of the FCS. This field is automatically
generated and verified by hardware when
the MODEMCTRL0.AUTOCRC control bit is
set. It is recommended to always have this
enabled, except possibly for debug
purposes. If cleared, CRC generation and
verification must be performed by
software.
Instead, when MODEMCTRL0.AUTOCRC is
set the two FCS bytes are replaced by the
RSSI value, average correlation value
(used for LQI) and CRC OK/not OK. This
is illustrated in Figure 21.
The first FCS byte is replaced by the 8-bit
RSSI value. This RSSI value is measured
over the first 8 symbols following the SFD.
See the RSSI section on page 48 for
details.
The FCS polynomial is [1]:
16
12
5
The 7 least significant bits in the last FCS
byte are replaced by the average
correlation value of the 8 first symbols of
the received PHY header (length field) and
PHY Service Data Unit (PSDU). This
correlation value may be used as a basis
for calculating the LQI. See the Link
Quality Indication section on page 49 for
details.
x +x +x +1
The CC2420 hardware implementation is
shown in Figure 20. Please refer to [1] for
further details.
In transmit mode the FCS is appended at
the correct position defined by the length
field. The FCS is not written to the
TXFIFO, but stored in a separate 16-bit
register.
The most significant bit in the last byte of
each frame is set high if the CRC of the
received frame is correct and low
otherwise.
In receive mode the FCS is verified by
hardware. The user is normally only
Data
input
(LSB
first)
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
Figure 20. CC2420 Frame Check Sequence (FCS) hardware implementation [1]
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CC2420
Length byte
Data in RXFIFO
n
MPDU
MPDU1
MPDU2
MPDUn-2
Bit number
RSSI
(signed)
CRC / Corr
7
6
5
4
3
2
1
0
CRC
Correlation value (unsigned)
OK
Figure 21. Data in RXFIFO when MDMCTRL0.AUTOCRC is set
17 RF Data Buffering
CC2420 can be configured for different
transmit and receive modes, as set in the
MDMCTRL1.TX_MODE
and
MDMCTRL1.RX_MODE
control
bits.
Buffered mode (mode 0) will be used for
normal operation of CC2420, while other
modes are available for test purposes.
17.1 Buffered transmit mode
A TXFIFO underflow is issued if too few
bytes are written to the TXFIFO.
Transmission
is
then
automatically
stopped. The underflow is indicated in the
TX_UNDERFLOW status bit, which is
returned during each address byte and
each byte written to the TXFIFO. The
underflow bit is only cleared by issuing a
SFLUSHTX command strobe.
In buffered transmit mode (TX_MODE 0),
the 128 byte TXFIFO, located in CC2420
RAM, is used to buffer data before
transmission. A preamble sequence
(defined in the Frame Format section
below) is automatically inserted before the
length field during transmission. The
length field must always be the first byte
written to the transmit buffer for all frames.
The TXFIFO can only contain one data
frame at a given time.
Writing one or multiple bytes to the
TXFIFO is described in the FIFO access
section on page 31. Reading data from the
TXFIFO is possible with RAM access, but
this does not remove the byte from the
FIFO.
Writing to the TXFIFO after a frame has
been transmitted will cause the TXFIFO to
be automatically flushed before the new
byte is written. The only exception is if a
TXFIFO underflow has occurred, then a
SFLUSHTX command strobe is required.
Transmission is enabled by issuing a
STXON or STXONCCA command strobe.
See the Radio control state machine
section on page 43 for an illustration of
how the transmit command strobes affect
the state of CC2420. The STXONCCA strobe
is ignored if the channel is busy. See the
Clear Channel Assessment section on
page 50 for details on CCA.
The preamble sequence is started 12
symbol periods after the command strobe.
After the programmable start of frame
delimiter has been transmitted, data is
fetched from the TXFIFO.
After complete transmission of a data
frame, the TXFIFO is automatically refilled
with the last transmitted frame. Issuing a
new STXON or STXONCCA command
strobe will then cause CC2420 to retransmit
the last frame.
17.2 Buffered receive mode
In buffered receive mode (RX_MODE 0),
the 128 byte RXFIFO, located in CC2420
RAM, is used to buffer data received by
the demodulator. Accessing data in the
RXFIFO is described in the FIFO access
section on page 31.
The FIFO and FIFOP pins are used to
assist the microcontroller in supervising
the RXFIFO. Please note that the FIFO
and FIFOP pins are only related to the
RXFIFO, even if CC2420 is in transmit
mode.
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CC2420
Multiple data frames may be in the
RXFIFO simultaneously, as long as the
total number of bytes does not exceed
128.
See the RXFIFO overflow section on page
33 for details on how a RXFIFO overflow is
detected and signalled.
17.3 Unbuffered, serial mode
Unbuffered mode should be used for
evaluation / debugging purposes only.
Buffered mode is recommended for all
applications.
In unbuffered mode, the FIFO and FIFOP
pins are reconfigured as data and data
clock pins. The TXFIFO and RXFIFO
buffers are not used in this mode. A
synchronous data clock is provided by
CC2420 at the FIFOP pin, and the FIFO pin
is used as data input/output. The FIFOP
clock frequency is 250 kHz when active.
This is illustrated in Figure 22.
Incoming / outgoing
RF data
Transmit mode:
Preamble
In
serial
transmit
mode
(MDMCTRL1.TX_MODE=1),
a
synchronisation sequence is inserted at
the start of each frame by hardware, as in
buffered mode. Data is sampled by CC2420
on the positive edge of FIFOP and should
be updated by the microcontroller on the
negative edge of FIFOP. See Figure 22 for
an illustration of the timing in serial
transmit mode. The SFD and CCA pins
retain their normal operation also in serial
mode. CC2420 will remain in serial transmit
mode until transmission is turned off
manually.
In
serial
receive
mode
(MDMCTRL1.RX_MODE=1)
byte
synchronisation is still performed by
CC2420. This means that the FIFOP clock
pin will remain inactive until a start of
frame delimiter has been detected.
SFD
s0
s1
s2
4 us
FIFOP
FIFO (from uC)
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10 b11 b8
b9
b10 b11
b0
b1
Receive mode:
FIFOP
FIFO (from CC2420)
b2
b3
b4
Figure 22. Unbuffered test mode, pin activity
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CC2420
18 Address Recognition
CC2420 includes hardware support for
address recognition, as specified in [1].
Hardware address recognition may be
enabled
/
disabled
using
the
MDMCTRL0.ADR_DECODE control bit.
Address recognition is based on the
following requirements, listed from section
7.5.6.2 in [1]:
The frame type subfield shall not
contain an illegal frame type
If the frame type indicates that the
frame is a beacon frame, the
source PAN identifier shall match
macPANId unless macPANId is
equal to 0xFFFF, in which case
the beacon frame shall be
accepted regardless of the source
PAN identifier.
If a destination PAN identifier is
included in the frame, it shall
match macPANId or shall be the
broadcast
PAN
identifier
(0xFFFF).
If a short destination address is
included in the frame, it shall
match either macShortAddress or
the broadcast address (0xFFFF).
Otherwise
if
an
extended
destination address is included in
the frame, it shall match
aExtendedAddress.
If only source addressing fields
are included in a data or MAC
command frame, the frame shall
only be accepted if the device is a
PAN coordinator and the source
PAN
identifier
macPANId.
matches
If any of the above requirements are not
satisfied and address recognition is
enabled, CC2420 will disregard the
incoming frame and flush the data from the
RXFIFO. Only data from the rejected
frame is flushed, data from previously
accepted frames may still be in the
RXFIFO.
The IOCFG0.BCN_ACCEPT control bit
must be set when the PAN identifier
programmed into CC2420 RAM is equal to
0xFFFF and cleared otherwise. This
particularly applies to active and passive
scans as defined by [1], which requires all
received beacons to be processed by the
MAC sublayer.
Incoming frames with reserved frame
types (FCF frame type subfield is 4, 5, 6 or
7)
is
however
accepted
if
the
RESERVED_FRAME_MODE control bit in
MDMCTRL0 is set. In this case, no further
address recognition is performed on these
frames. This option is included for future
expansions of the IEEE 802.15.4 standard.
If a frame is rejected, CC2420 will only start
searching for a new frame after the
rejected frame has been completely
received (as defined by the length field) to
avoid detecting false SFDs within the
frame.
The
MDMCTRL0.PAN_COORDINATOR
control bit must be correctly set, since
parts of the address recognition procedure
requires knowledge about whether the
current device is a PAN coordinator or not.
19 Acknowledge Frames
CC2420 includes hardware support for
transmitting acknowledge frames, as
specified in [1]. Figure 23 shows the
format of the acknowledge frame.
If MDMCTRL0.AUTOACK is enabled, an
acknowledge frame is transmitted for all
incoming frames accepted by the address
recognition with the acknowledge request
flag set and a valid CRC. AUTOACK
therefore does not make sense unless
also ADR_DECODE and AUTOCRC are
enabled. The sequence number is copied
from the incoming frame.
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CC2420
AUTOACK may be used for non-beacon
systems as long as the frame pending field
(see Figure 19) is cleared. The
acknowledge frame is then transmitted 12
Bytes:
symbol periods after the last symbol of the
incoming frame. This is as specified by [1]
for non-beacon networks.
1
1
Start of Frame
Preamble
Frame
Delimiter
Sequence
Length
(SFD)
Synchronisation Header
PHY Header
(SHR)
(PHR)
1
2
Frame
Data
Control Field
Sequence
(FCF)
Number
MAC Header (MHR)
4
2
Frame Check
Sequence
(FCS)
MAC Footer
(MFR)
Figure 23. Acknowledge frame format [1]
Two command strobes, SACK and
SACKPEND are defined to transmit
acknowledge frames with the frame
pending field cleared or set, respectively.
The acknowledge frame is only transmitted
if the CRC is valid.
For systems using beacons, there is an
additional timing requirement that the
acknowledge frame transmission should
be started on the first backoff-slot
boundary (20 symbol periods) at least 12
symbol periods after the last symbol of the
incoming frame. This timing must be
controlled by the microcontroller by issuing
the SACK and SACKPEND command strobe
12 symbol periods before the following
backoff-slot boundary, as illustrated in
Figure 24.
If a SACK or SACKPEND command strobe
is issued while receiving an incoming
frame, the acknowledge frame is
transmitted 12 symbol periods after the
last symbol of the incoming frame. This
should be used to transmit acknowledge
frames in non-beacon networks. This
timing is also illustrated in Figure 24.
Using SACKPEND will set the pending data
flag
for
automatically
transmitted
acknowledge frames using AUTOACK. The
pending flag will then be set also for future
acknowledge frames, until a SACK
command strobe is issued.
Acknowledge frames may be manually
transmitted
using
normal
data
transmission if desired.
y
D
ar
l
nd
b o PEN
u
m
K
bo
sy AC
ot
U
S
l
D
fs
/
of
PP K
k
t
c
C
s
La
Ba
SA
Beacon
network
PPDU
12
symbol
periods
12 symbol periods
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